Display device and electronic device including the same

Abstract

The present application relates to a display device and an electronic device including the same, the display device including: a first pixel circuit including a first-1 pixel circuit and a first-2 pixel circuit arranged along a first direction on a substrate; a first-1 gate line extending in the first direction and electrically connected to the first-1 pixel circuit; a first-2 gate line extending in the first direction and electrically connected to the first-2 pixel circuit; and reference voltage lines including a horizontal reference voltage line extending in a first direction and a vertical reference voltage line protruding from the horizontal reference voltage line in a second direction intersecting the first direction, and the first-1 pixel circuit and the first-2 pixel circuit are arranged such that a vertical reference voltage line is interposed between the first-1 pixel circuit and the first-2 pixel circuit.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0110014, filed on August 16, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more implementations relate to display devices. Background Technology

[0004] Display devices visually display image data. Display devices can use light-emitting diodes (LEDs) to provide images. Display devices are becoming increasingly diverse in use, and various designs have been explored to improve their quality. Summary of the Invention

[0005] One or more implementations include a display device.

[0006] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing embodiments of the present disclosure.

[0007] According to one or more embodiments, a display device includes: a first pixel circuit including a first-1 pixel circuit and a first-2 pixel circuit disposed on a substrate along a first direction; a first-1 gate line extending in the first direction and electrically connected to the first-1 pixel circuit; a first-2 gate line extending in the first direction and electrically connected to the first-2 pixel circuit; and a reference voltage line including a horizontal reference voltage line extending in the first direction and a vertical reference voltage line protruding from the horizontal reference voltage line in a second direction intersecting the first direction, wherein the first-1 pixel circuit and the first-2 pixel circuit are arranged such that the vertical reference voltage line is interposed between the first-1 pixel circuit and the first-2 pixel circuit.

[0008] According to one or more embodiments, the first pixel circuit may further include a first light-emitting diode electrically connected to the first pixel circuit.

[0009] According to one or more embodiments, the first light-emitting diode may include a first-1 light-emitting diode electrically connected to a first-1 pixel circuit and a first-2 light-emitting diode electrically connected to a first-2 pixel circuit, wherein the first-1 light-emitting diode and the first-2 light-emitting diode are arranged along a first direction.

[0010] According to one or more embodiments, the first-1 light-emitting diode and the first-2 light-emitting diode can be configured to emit light of the same color.

[0011] According to one or more embodiments, the display device may further include a first data line that extends on a substrate in a second direction and overlaps with a vertical reference voltage line.

[0012] According to one or more embodiments, the first-1 pixel circuit and the first-2 pixel circuit can be arranged such that a first data line is inserted between the first-1 pixel circuit and the first-2 pixel circuit.

[0013] According to one or more embodiments, the display device may further include a second pixel circuit arranged adjacent to the first pixel circuit in a first direction, and including a second-1 pixel circuit and a second-2 pixel circuit arranged along the first direction, wherein the second-1 pixel circuit and the second-2 pixel circuit are arranged such that a vertical reference voltage line is inserted between the second-1 pixel circuit and the second-2 pixel circuit.

[0014] According to one or more embodiments, the first-1 gate line can be electrically connected to the second-1 pixel circuit, and the first-2 gate line can be electrically connected to the second-2 pixel circuit.

[0015] According to one or more embodiments, the display device may further include a second light-emitting diode electrically connected to the second pixel circuit.

[0016] According to one or more embodiments, the first light-emitting diode and the second light-emitting diode can be configured to emit light of different colors.

[0017] According to one or more embodiments, the second light-emitting diode may include a second-1 light-emitting diode electrically connected to a second-1 pixel circuit and a second-2 light-emitting diode electrically connected to a second-2 pixel circuit, wherein the second-1 light-emitting diode and the second-2 light-emitting diode are arranged along a first direction.

[0018] According to one or more embodiments, the second-1 light-emitting diode and the second-2 light-emitting diode can be configured to emit light of the same color.

[0019] According to one or more embodiments, the display device may further include a second data line that extends on a substrate in a second direction and overlaps with a vertical reference voltage line.

[0020] According to one or more embodiments, the second-1 pixel circuit and the second-2 pixel circuit can be arranged such that the second data line is between the second-1 pixel circuit and the second-2 pixel circuit.

[0021] According to one or more embodiments, the display device may further include a third pixel circuit arranged adjacent to the second pixel circuit in a first direction, and including a third-1 pixel circuit and a third-2 pixel circuit arranged along the first direction, wherein the third-1 pixel circuit and the third-2 pixel circuit may be arranged such that a vertical reference voltage line is inserted between the third-1 pixel circuit and the third-2 pixel circuit.

[0022] According to one or more embodiments, the first-1 gate line can be electrically connected to the third-2 pixel circuit, and the first-2 gate line can be electrically connected to the third-1 pixel circuit.

[0023] According to one or more embodiments, the display device may further include a third light-emitting diode electrically connected to a third pixel circuit, wherein the third light-emitting diode may include a third-1 light-emitting diode electrically connected to the third pixel circuit and a third-2 light-emitting diode electrically connected to the third pixel circuit, the third-1 light-emitting diode and the third-2 light-emitting diode being arranged along a first direction.

[0024] According to one or more embodiments, the third-1 light-emitting diode and the third-2 light-emitting diode can be configured to emit light of the same color.

[0025] According to one or more embodiments, the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode can be configured to emit light of different colors.

[0026] According to one or more embodiments, the display device may further include a third data line that extends on the substrate in a second direction and overlaps with a vertical reference voltage line.

[0027] According to one or more embodiments, the third-1 pixel circuit and the third-2 pixel circuit can be arranged such that a third data line is inserted between the third-1 pixel circuit and the third-2 pixel circuit.

[0028] According to one or more embodiments, an electronic device includes a display device, the display device comprising: a first pixel circuit including a first-1 pixel circuit and a first-2 pixel circuit disposed on a substrate along a first direction; a first-1 gate line extending in the first direction and electrically connected to the first-1 pixel circuit; a first-2 gate line extending in the first direction and electrically connected to the first-2 pixel circuit; and a reference voltage line including a horizontal reference voltage line extending in the first direction and a vertical reference voltage line protruding from the horizontal reference voltage line in a second direction intersecting the first direction, wherein the first-1 pixel circuit and the first-2 pixel circuit are arranged such that the vertical reference voltage line is interposed between the first-1 pixel circuit and the first-2 pixel circuit. Attached Figure Description

[0029] The above and other aspects and features of the embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 It is a schematic plan view of a display device according to one or more embodiments; Figure 2 It is a schematic block diagram of a display device according to one or more embodiments; Figure 3 It is a schematic equivalent circuit diagram of a light-emitting diode and a pixel circuit electrically connected to the light-emitting diode according to one or more embodiments, wherein the light-emitting diode is a light-emitting element corresponding to a pixel of a display device; Figure 4 This is a schematic cross-sectional view of a part of a display device according to one or more embodiments; Figure 5 It is a schematic plan view of a portion of wiring arranged in the display area of ​​a display device according to one or more embodiments; and Figures 6 to 12 This is a plan view illustrating the process of forming pixel circuits included in a display device according to one or more embodiments. Detailed Implementation

[0030] Because this disclosure allows for various modifications and numerous implementations, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. A full understanding of this disclosure, its advantages, and the objectives achieved by practicing this disclosure will be obtained by referring to the accompanying drawings, which illustrate embodiments of this disclosure. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0031] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Similar reference numerals in the drawings denote similar elements, and therefore their descriptions will be omitted.

[0032] In the following embodiments, although terms such as "first" and "second" may be used to describe various elements, such elements are not necessarily limited to the above terms.

[0033] In the following implementation, singular expressions cover plural expressions unless they have a distinctly different meaning in the context.

[0034] In the following implementation, it should be understood that terms such as “comprising” and “having” are intended to indicate the presence of a feature or element disclosed in this disclosure and are not intended to exclude the possibility that one or more other features or elements may be present or added.

[0035] It will be understood that when a layer, region, or element is said to be formed on another layer, region, or element, it can be formed directly or indirectly on the other layer, region, or element. That is, for example, there can be intermediate layers, regions, or elements.

[0036] For ease of explanation, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, because the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0037] When a particular implementation can be carried out differently, a specific process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of their description.

[0038] In this disclosure, "A and / or B" can include "A", "B", or "A and B". Furthermore, "at least one of A and B" can mean A, B, or A and B.

[0039] It will be understood that when a layer, region, or component is referred to as being connected to another layer, region, or component, it can be directly or indirectly connected to that other layer, region, or component. That is, for example, there can be intermediary layers, regions, or components. For example, it will be understood that when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, it can be directly or indirectly electrically connected to that other layer, region, or component. That is, for example, there can be intermediary layers, regions, or components.

[0040] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0041] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting the portion of the object from the side. The terms "overlap" or "overlapped" mean that the first object may be above or below the second object, or to one side of the second object, and vice versa. Additionally, the term "overlap" can include layering, stacking, facing, extending over, covering, or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "separated from," or "offset from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "face" and "facing" can mean that the first object may be directly opposite or indirectly opposite the second object. Where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, but still facing each other.

[0042] For ease of description, the spatial relative terms “below,” “below,” “down,” “above,” “up,” etc., may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned “below” or “below” another device may be placed “above” the other device. Thus, the exemplary term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0043] When an element is referred to as being “connected” or “linked” to another element, the element may be “directly connected” or “directly linked” to the other element, or “electrically connected” or “electrically linked” to the other element with one or more intervening elements inserted between them. It will also be understood that when the terms “comprises,” “comprising,” “has,” “have,” “having,” “includes,” and / or “including” are used, they may specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0044] Given the measurements discussed and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the terms “about” or “approximately” as used herein include the value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5% of the value.

[0045] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formalized sense unless explicitly defined in the specification.

[0046] In view of the whole of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0047] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 This is a schematic plan view of a display device 1 according to one or more embodiments.

[0049] refer to Figure 1 The display device 1 may include a display area DA for displaying an image and a non-display area NDA outside the display area DA. The display area DA may be completely surrounded by the non-display area NDA along the edge or periphery of the display area DA.

[0050] In a plan view, the display area DA can be rectangular. In one or more other embodiments, the display area DA can be a polygonal shape such as a triangle, pentagon, or hexagon, a circle, an ellipse, or an atypical shape. The corners of the edges of the display area DA can be rounded.

[0051] Figure 1The display device 1 can be a device for displaying moving or still images, and can be used in portable electronic devices such as mobile phones, laptops, tablet PCs, smartphones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices, or ultra-mobile PCs (UMPCs). Optionally, the display device 1 can be used in televisions, monitors, billboards, and electronic devices for the Internet of Things (IoT), or in wearable electronic devices such as smartwatches, watch phones, glasses displays, and head-mounted displays (HMDs). Furthermore, the display device 1 according to one or more embodiments can be applied to a central information display (CID) arranged on the instrument panel or central dashboard of a vehicle, an interior mirror display replacing the side mirrors of a vehicle, or a display electronic device arranged behind the front seats of a vehicle as an entertainment device for passengers in the rear seats of the vehicle.

[0052] Figure 2 This is a block diagram schematically showing a display device 1 according to one or more embodiments.

[0053] refer to Figure 1 and Figure 2 The display device 1 according to one or more embodiments may include a pixel unit 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0054] Pixel unit 11 may include a pixel arranged in the display area DA (see [reference]). Figure 1 Multiple pixels (PX) in a ) can be arranged in a pattern such as stripes, pentiles, etc. ® Various arrangements of layout (diamond layout) and mosaic layout to achieve the desired image. (PENTILE) ® The pixel arrangement structure can be called an RGBG matrix structure (e.g., PENTILE). ® Matrix structure or RGBG structure (e.g., Pentium) ® Structure). PENTILE ® "[Image Name]" is a registered trademark of Samsung Display Inc. of South Korea. Each of the plurality of pixels (PX) may include a display element (e.g., a light-emitting diode), and the display element may be electrically connected to pixel circuitry. The plurality of pixels (PX) can represent an image by using light emitted from the display element corresponding to each of the plurality of pixels (PX). The pixel circuitry may be electrically connected to gate line GL and data line DL, and may include a plurality of transistors and at least one capacitor.

[0055] Used for transmitting DA to be applied to the display area (see...) Figure 1The various wires of the electrical signals, the peripheral circuitry electrically connected to the pixel circuitry, and / or the pads to which the printed circuit board (PCB) or driver IC chip is attached may be located in the non-display area NDA (see NDA). Figure 1 In, for example, the gate drive circuit 13, the data drive circuit 15, the power supply circuit 17, and the controller 19 can be located in the non-display area NDA (see...). Figure 1 )middle.

[0056] The gate drive circuit 13 can be electrically connected to multiple gate lines GL, can generate gate signals in response to the control signal GCS from the controller 19, and can sequentially provide gate signals to the gate lines GL. The gate signals can be gate control signals used to control the on and off states of transistors electrically connected to the gate lines GL. The gate signals can be square wave signals, including an on-state voltage that can turn on the transistors and an off-state voltage that can turn off the transistors. In one or more embodiments, the on-state voltage can be a high-level voltage (first-level voltage) or a low-level voltage (second-level voltage).

[0057] Figure 2 The pixel circuit corresponding to pixel PX is shown connected to gate line GL. However, this is only an example, and the pixel circuit corresponding to pixel PX can be connected to two or more gate lines, and when an on-state voltage is applied, the gate drive circuit 13 can provide two or more gate signals with different timings to the respective gate lines. For example, the pixel circuit can be connected to the first to the fifth gate lines, and the gate drive circuit 13 can apply a first gate signal GW, a second gate signal GR, a third gate signal EM, a fourth gate signal GI, and a fifth gate signal EMB to the first, second, third, fourth, and fifth gate lines, respectively. The third gate signal EM can be an emitter control signal used to control the on and off states of a transistor whose gate is connected to the third gate line.

[0058] The data drive circuit 15 can be connected to multiple data lines DL and can provide data signals DATA to the data lines DL in response to control signals DCS from the controller 19. The data signals DATA provided to the data lines DL can be provided to the pixel circuit. The data drive circuit 15 can convert input image data with grayscale values ​​input from the controller 19 into data signals DATA in the form of voltage or current.

[0059] The power supply circuit 17 can generate the voltage required to drive the pixel PX in response to the control signal PCS from the controller 19. The power supply circuit 17 can generate a driving voltage ELVDD and a common voltage ELVSS, and provide them to the pixel PX. The driving voltage ELVDD can be a high-level voltage provided to a first electrode (pixel electrode or anode) of the display element included in the pixel PX. The common voltage ELVSS can be a low-level voltage provided to a second electrode (opposite electrode or cathode) of the display element included in the pixel PX. The power supply circuit 17 can generate a reference voltage Vref and a first initialization voltage Vaint, and provide them to the pixel PX.

[0060] The driving voltage ELVDD can be higher than the common voltage ELVSS. The reference voltage Vref can be lower than the driving voltage ELVDD. The initialization voltage Vaint can be equal to or higher than the common voltage ELVSS.

[0061] The controller 19 can generate control signals GCS, DCS, and PCS based on signals input from an external source and provide them to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The control signal GCS output to the gate drive circuit 13 may include multiple clock signals and a gate start signal. The control signal DCS output to the data drive circuit 15 may include a source start signal and a clock signal.

[0062] Figure 3 This is a schematic equivalent circuit diagram of a light-emitting diode (LED) and a pixel circuit PC electrically connected to the LED. The LED is a light-emitting element corresponding to a pixel of the display device 1 according to one or more embodiments.

[0063] The pixel circuit PC can be electrically connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GRL configured to transmit a second gate signal GR, a third gate line EML configured to transmit a third gate signal EM, a fourth gate line GIL configured to transmit a fourth gate signal GI, a fifth gate line EMBL configured to transmit a fifth gate signal EMB, and a data line DL configured to transmit a data signal DATA. Because the light emission of the light-emitting diode (LED) is controlled by the third gate signal EM and the fifth gate signal EMB, the third gate signal EM and the fifth gate signal EMB can be referred to as emission control signals, and the third gate line EML and the fifth gate line EMBL can be referred to as emission control lines. The pixel circuit PC can also be electrically connected to a drive voltage line PL configured to transmit a drive voltage ELVDD, a reference voltage line VRL configured to transmit a reference voltage Vref, and a first initialization voltage line VAL configured to transmit a first initialization voltage Vaint.

[0064] In one or more embodiments, some of the multiple transistors included in the pixel circuit PC may be N-type transistors, and the others may be P-type transistors. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be N-type transistors, and the fifth transistor T5 and the sixth transistor T6 may be P-type transistors. The semiconductor layers of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may comprise a different material than the semiconductor layers of the fifth transistor T5 and the sixth transistor T6. In one or more embodiments, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may comprise a semiconductor layer comprising an oxide, and the fifth transistor T5 and the sixth transistor T6 may comprise amorphous silicon, polycrystalline silicon, and / or organic semiconductors.

[0065] The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, a first capacitor C1, a second capacitor C2, and an auxiliary capacitor Ca. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to the data signal DATA, and the second transistors T2, T3, T4, T5, and T6 may be switching transistors configured to transmit signals. The first terminal (or first electrode) and the second terminal (or second electrode) of each of the first transistors T1, T2, T3, T4, T5, and T6 may be a source (or source electrode) or a drain (or drain electrode) depending on the voltage between the first and second terminals. For example, depending on the voltage between the first and second terminals, the first terminal may be a drain and the second terminal may be a source, or vice versa. In the following text, the node to which the first -1 gate electrode (e.g., or first -1 gate) of the first transistor T1 is connected can be defined as the first node N1, and the node to which the second terminal of the first transistor T1 is connected can be defined as the second node N2.

[0066] The first transistor T1 can be connected to the driving voltage line PL and the light-emitting diode (LED). The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a first gate (or a first gate electrode including a first-1 gate and a first-2 gate), a first terminal, and a second terminal connected to the second node N2. The first transistor T1 may include a first-1 gate connected to the first node N1. The first transistor T1 may also include a first-2 gate connected to its second terminal (or the second node N2). The first-1 gate and the first-2 gate may be arranged on different layers facing each other. For example, the first-1 gate and the first-2 gate of the first transistor T1 may face each other, with a semiconductor layer between them. Here, the first gate (or first gate electrode) of the first transistor T1 can direct the turning on and off of the first-1 gate (or first-1 gate electrode) involved in the first transistor T1.

[0067] The gate (or first-1 gate) of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The first-2 gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the drive voltage line PL via the fifth transistor T5, and its second terminal can be connected to the pixel electrode of the light-emitting diode (LED) via the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can receive the data signal DATA according to the switching operation of the second transistor T2 to control the amount of drive current flowing through the LED.

[0068] The second transistor T2 can be connected to the data line DL and the gate (first-1 gate) of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 can be connected to the gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 can be turned on by a first gate signal GW received through the first gate line GWL to electrically connect the data line DL to the first node N1 and transmit the data signal DATA received through the data line DL to the first node N1.

[0069] A third transistor T3 can be connected to the gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the second gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be connected to the gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 can be turned on by a second gate signal GR received through the second gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1.

[0070] A fourth transistor T4 can be connected to a sixth transistor T6 and a first initialization voltage line VAL. The fourth transistor T4 can also be connected to a light-emitting diode (LED) and the first initialization voltage line VAL. The fourth transistor T4 may include a gate connected to a fourth gate line GIL, a first terminal connected to a third node N3, and a second terminal connected to the first initialization voltage line VAL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the LED. The fourth transistor T4 can be turned on by a fourth gate signal GI received through the fourth gate line GIL to transmit a first initialization voltage Vaint received through the first initialization voltage line VAL to the third node N3 and initialize the pixel electrode (e.g., the anode) of the LED.

[0071] The fifth transistor T5 can be connected to the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the third gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to the third gate signal EM received through the third gate line EML.

[0072] The sixth transistor T6 can be connected to the first transistor T1 and the light-emitting diode (LED). The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the LED. The sixth transistor T6 can be turned on or off according to the fifth gate signal EMB received through the fifth gate line EMBL.

[0073] A first capacitor C1 can be connected between the gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 can be connected to the first node N1, and its second electrode can be connected to the second node N2. The first electrode of the first capacitor C1 can be connected to the gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 can be connected to the second terminal of the first transistor T1, the gate of the first-second transistor, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1 can be a storage capacitor, and can store the threshold voltage of the first transistor T1 and the voltage corresponding to the data signal DATA.

[0074] When the third transistor T3 and the fifth transistor T5 are turned on, the first transistor T1 can be turned on. When the voltage at the second terminal of the first transistor T1 drops to the difference (Vref-Vth1) between the reference voltage Vref and the threshold voltage (Vth1) of the first transistor T1, the first transistor T1 can be turned off, and the voltage corresponding to the threshold voltage (Vth1) of the first transistor T1 can be stored in the first capacitor C1, and thus the threshold voltage (Vth1) of the first transistor T1 can be compensated.

[0075] The second capacitor C2 can be connected between the drive voltage line PL and the second node N2. The first electrode of the second capacitor C2 can be connected to the drive voltage line PL. The second electrode of the second capacitor C2 can be connected to the second terminal and the first-2 gate of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6.

[0076] The capacitance of each of the first capacitor C1 and the second capacitor C2 can vary according to the color of the light emitted from the light-emitting diode (LED).

[0077] The auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the sustaining voltage line VSSL, and the pixel electrode of the light-emitting diode (LED). The auxiliary capacitor Ca can store and maintain the voltage corresponding to the voltage difference between the pixel electrode of the LED and the sustaining voltage line VSSL, thereby preventing the problem of increased black brightness when the sixth transistor T6 is turned off.

[0078] A light-emitting diode (LED) can be connected to a first transistor T1 via a sixth transistor T6. The LED may include a pixel electrode (e.g., anode) connected to a third node N3 and a counter electrode (e.g., cathode) facing the pixel electrode, and the counter electrode may receive a common voltage ELVSS. In one or more embodiments, the counter electrode (e.g., cathode) may extend into the display area DA and thus be electrically connected to a sustaining voltage line VSSL configured to provide the common voltage ELVSS. Due to the conduction of a fifth transistor T5 and a sixth transistor T6, a drive current output from the first transistor T1 can flow through the LED, and the LED can emit light with a brightness corresponding to the drive current.

[0079] although Figure 3 The pixel circuit PC shown includes six transistors, but this disclosure is not limited thereto. In one or more other embodiments, the number of transistors in the pixel circuit PC may be five or fewer, or seven or more.

[0080] Figure 4 This is a schematic cross-sectional view showing a portion of a display device 1 according to one or more embodiments.

[0081] refer to Figure 4 The display device 1 may include light-emitting diodes (LEDs) disposed in the display area DA. The LEDs may be disposed on the substrate 100, and pixel circuitry PC may be disposed between the substrate 100 and the LEDs. In one or more embodiments, Figure 4 The first transistor T1, the first capacitor C1, and the second capacitor C2 are shown as some components of the pixel circuit PC.

[0082] Substrate 100 may include glass materials and / or polymer resins. In one or more embodiments, substrate 100 may have an alternating stacked structure comprising a base layer of polymer resin and barrier layers comprising inorganic insulating materials such as silicon oxides and / or silicon nitrides. The polymer resin may include polymer resins such as polyethersulfone, polyarylates, polyetherimides, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimides, polycarbonates, cellulose triacetate, and / or cellulose acetate propionate.

[0083] A bottom metal layer (BML) can be disposed on the substrate 100. The bottom metal layer (BML) can serve as the first electrode C11 of the first capacitor C1 and the first electrode C21 of the second capacitor C2. That is, the bottom metal layer (BML) may include the first electrode C11 of the first capacitor C1 and the first electrode C21 of the second capacitor C2. The first electrode C11 of the first capacitor C1 and the first electrode C21 of the second capacitor C2 can be disposed on the substrate 100.

[0084] In one or more embodiments, the first-11 gate line GWL1-1 (see...) Figure 6 ), First-21 gate line GWL2-1 (see Figure 6 ), reference voltage line VRL, drive voltage line PL, horizontal sustaining voltage line HVSSL (see Figure 5 ), First -11 Initialization Horizontal Voltage Line HVAL(R)1 (see Figure 6 ) and the first-2 initialization level voltage line HVAL (GB) (see Figure 5 It can be additionally disposed on the substrate 100.

[0085] The bottom metal layer (BML) may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In one or more embodiments, the bottom metal layer (BML) may be a single layer of molybdenum, have a bilayer structure in which a molybdenum layer and a titanium layer are laminated, or have a trilayer structure in which a titanium layer, an aluminum layer, and a titanium layer are laminated.

[0086] The first-11 gate line GWL1-1, the first-21 gate line GWL2-1, the reference voltage line VRL, the drive voltage line PL, the horizontal sustaining voltage line HVSSL, the first-11 initialization horizontal voltage line HVAL(R)1, and the first-2 initialization horizontal voltage line HVAL(GB) may contain the same material as the bottom metal layer BML.

[0087] A first insulating layer 111 may be disposed on the substrate 100 to cover the bottom metal layer BML. The first insulating layer 111 may be disposed on the first electrode C11 of the first capacitor C1 and the first electrode C21 of the second capacitor C2. The first insulating layer 111 may comprise an inorganic insulating material such as silicon oxide, silicon nitride, or silicon nitride, and may comprise a single-layer or multi-layer structure containing the inorganic insulating material. A semiconductor layer and a first conductive layer CL1 may be disposed on the first insulating layer 111.

[0088] A semiconductor layer can be disposed on top of the first insulating layer 111. In this respect, Figure 4 A first semiconductor layer A1 is shown disposed on a first insulating layer 111 of a first transistor T1. The first semiconductor layer A1 may include a channel region CH1 and doped regions disposed on both sides of the channel region CH1, and at this point, Figure 4 The first region B1 is shown as one of the doped regions arranged on one side of the channel region CH1.

[0089] The first semiconductor layer A1 may include oxides of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and / or zinc (Zn). For example, the first semiconductor layer A1 may include an InSnZnO (ITZO) semiconductor layer and / or an InGaZnO (IGZO) semiconductor layer. Conductive (or conductive) processes based on, for example, plasma processing may be performed on at least a portion of the first semiconductor layer A1.

[0090] A first conductive layer CL1 may be disposed on top of a first insulating layer 111. The first conductive layer CL1 may serve as the second electrode C22 of the second capacitor C2. That is, the first conductive layer CL1 may include the second electrode C22 of the second capacitor C2. The second electrode C22 of the second capacitor C2 may be disposed on top of the first insulating layer 111.

[0091] The first conductive layer CL1 may comprise one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In one or more embodiments, the first conductive layer CL1 may be a single layer of molybdenum, may have a bilayer structure in which molybdenum and titanium layers are stacked, or may have a trilayer structure in which titanium, aluminum, and titanium layers are stacked.

[0092] The second insulating layer 112 may be disposed above the first insulating layer 111 to cover the first semiconductor layer A1 and the first conductive layer CL1. The second insulating layer 112 may be disposed above the first semiconductor layer A1 of the first transistor T1 and the second electrode C22 of the second capacitor C2. The second insulating layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon nitride, and may include a single-layer or multi-layer structure containing the inorganic insulating material.

[0093] The second conductive layer CL2 can be disposed on the second insulating layer 112. The second conductive layer CL2 can serve as the first gate electrode G1 of the first transistor T1 and the second electrode C12 of the first capacitor C1. That is, the second conductive layer CL2 may include the first gate electrode G1 of the first transistor T1 and the second electrode C12 of the first capacitor C1. The first gate electrode G1 of the first transistor T1 and the second electrode C12 of the first capacitor C1 can be disposed on the second insulating layer 112. The first gate electrode G1 of the first transistor T1 may overlap with the channel region CH1 of the first semiconductor layer A1 of the first transistor T1, and the second insulating layer 112 is located between them.

[0094] In one or more embodiments, the first-12 gate line GWL1-2 (see...) Figure 8 ), first-22 gate line GWL2-2 (see Figure 8 ), second gate line GRL, third gate line EML, fourth gate line GIL, fifth gate line EMBL and first -12 initialization level voltage line HVAL(R)2 (see Figure 8 It can be additionally disposed on the second insulating layer 112.

[0095] The second conductive layer CL2 may comprise one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In one or more embodiments, the second conductive layer CL2 may be a single layer of molybdenum, may have a bilayer structure in which molybdenum and titanium layers are stacked, or may have a trilayer structure in which titanium, aluminum, and titanium layers are stacked.

[0096] The first-12 gate line GWL1-2, the first-22 gate line GWL2-2, the second gate line GRL, the third gate line EML, the fourth gate line GIL, the fifth gate line EMBL, and the first-12 initialization horizontal voltage line HVAL(R)2 may contain the same material as the second conductive layer CL2.

[0097] The third insulating layer 113 may be disposed above the second insulating layer 112 to cover the second conductive layer CL2. The third insulating layer 113 may be disposed above the first gate electrode G1 of the first transistor T1 and the second electrode C12 of the first capacitor C1. The third insulating layer 113 may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon nitride, and may include a single-layer or multi-layer structure containing the inorganic insulating material.

[0098] The data line DL and the 94th connection electrode CM94 can be disposed on the third insulating layer 113. The 94th connection electrode CM94 can be connected to the first semiconductor layer A1 of the first transistor T1 through the 98th contact hole CNT98. The 94th connection electrode CM94 can be connected to the bottom metal layer BML through the 99th contact hole CNT99. That is, the 94th connection electrode CM94 can be connected to each of the first transistor T1 and the bottom metal layer BML.

[0099] In one or more embodiments, in addition to the 94th connecting electrode CM94, a plurality of connecting electrodes may be disposed on the third insulating layer 113.

[0100] The data line DL and the 94th connection electrode CM94 may comprise one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In one or more embodiments, the data line DL and the 94th connection electrode CM94 may be a single layer of molybdenum, may have a double-layer structure in which molybdenum and titanium layers are stacked, or may have a triple-layer structure in which titanium, aluminum, and titanium layers are stacked.

[0101] Figure 4 The multiple connection electrodes not shown may be made of the same material as the data line DL and the 94th connection electrode CM94.

[0102] A fourth insulating layer 114 may be disposed above the third insulating layer 113 to cover the data line DL and the 94th connection electrode CM94. The fourth insulating layer 114 may comprise an organic insulating material such as acrylic acid, benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO).

[0103] The vertical sustaining voltage line VVSSL can be set on the fourth insulating layer 114.

[0104] In one or more embodiments, the first-1 initialization of the vertical voltage line VVAL(R) (see...) Figure 5 ) and the first-2 initialization vertical voltage line VVAL (GB) (see Figure 5 It can be additionally disposed on the fourth insulating layer 114.

[0105] The vertical sustaining voltage line (VVSSL) may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In one or more embodiments, the VVSSL may be a single layer of molybdenum, may have a double-layer structure in which molybdenum and titanium layers are stacked, or may have a triple-layer structure in which titanium, aluminum, and titanium layers are stacked.

[0106] The first-1 initialization vertical voltage line VVAL(R) and the first-2 initialization vertical voltage line VVAL(GB) may contain the same material as the vertical sustaining voltage line VVSSL.

[0107] A fifth insulating layer 115 may be disposed above the fourth insulating layer 114 to cover the vertical sustaining voltage line VVSSL. The fifth insulating layer 115 may comprise an organic insulating material such as acrylic acid, benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO).

[0108] The light-emitting diode (LED) can be disposed on the fifth insulating layer 115 and can include a pixel electrode 210, an emitting layer 222 and a counter electrode 230.

[0109] Pixel electrode 210 may be disposed on the fifth insulating layer 115. Pixel electrode 210 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or any compound thereof. In one or more embodiments, pixel electrode 210 may also include a conductive oxide layer above and / or below the reflective layer. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one or more embodiments, pixel electrode 210 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0110] A dam layer 123 may be disposed on the fifth insulating layer 115 to partially cover the end of the pixel electrode 210. The dam layer 123 may include an opening 123OP overlapping the pixel electrode 210 and may cover the edge of the pixel electrode 210. The dam layer 123 may include an organic insulating material. In one or more embodiments, the dam layer 123 may include a light-transmitting organic insulator. In one or more other embodiments, the dam layer 123 may include an organic insulating material comprising a light-blocking material. In one or more embodiments, the dam layer 123 may include a polyimide (PI)-based binder and therein mixed red, green, and blue pigments. Optionally, the dam layer 123 may include a carbon-based binder resin and a mixture of lactam-based black and / or blue pigments. Optionally, the dam layer 123 may include carbon black. The dam layer 123 may improve the contrast of the display panel.

[0111] Spacers 125 may be disposed on top of the dam layer 123. Spacers 125 may comprise different materials than the dam layer 123. For example, the dam layer 123 and spacers 125 may comprise different materials (e.g., the dam layer 123 may comprise a negative photosensitive material, and the spacers 125 may comprise a positive photosensitive material), and may be formed separately by individual masking processes. In one or more embodiments, spacers 125 may comprise the same material as the dam layer 123 and may be formed together in the same masking process (e.g., a halftone masking process).

[0112] The emitting layer 222 may include high-molecular-weight or low-molecular-weight organic materials for emitting light of a specific color. The emitting layer 222 may include materials for emitting red, green, or blue light, depending on the light-emitting diode (LED).

[0113] Functional layers may also be included below and / or above the emitter layer 222. For example, a first functional layer 221 may be included between the pixel electrode 210 and the emitter layer 222, and a second functional layer 223 may be included between the emitter layer 222 and the opposing electrode 230 described below. The first functional layer 221 may include a hole transport layer and / or a hole injection layer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer.

[0114] The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and / or any alloy thereof. Optionally, the counter electrode 230 may also include a layer such as ITO, IZO, ZnO, and / or In2O3 on top of the (semi-)transparent layer comprising the above materials.

[0115] Unlike the pixel electrodes 210, which are respectively formed to correspond to the light-emitting diodes (LEDs), the relative electrode 230 can extend to correspond to the pixel electrode 210. For example, the pixel electrode 210 of one LED and the pixel electrode 210 of another LED can be separated from each other (e.g., spaced apart), but the relative electrode 230 that overlaps with the pixel electrode 210 can extend to cover the aforementioned pixel electrode 210.

[0116] The encapsulation layer 300 can be disposed on the light-emitting diode (LED) and can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one or more embodiments, such as Figure 4 As shown, the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0117] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise one or more inorganic insulating materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon nitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise a single layer or multiple layers containing the above materials. The organic encapsulation layer 320 may comprise a polymer-based material. Polymer-based materials may include acrylic resins, epoxy resins, polyimide, polyethylene, etc. In one or more embodiments, the organic encapsulation layer 320 may comprise acrylates. In one or more embodiments, the organic encapsulation layer 320 may comprise acrylates.

[0118] Figure 4 This is a schematic cross-sectional view showing a portion of display device 1, therefore details are omitted. Figure 3 Some of the components shown. See later. Figures 5 to 12 This describes a detailed description of the components of display device 1.

[0119] Figure 5 It is a plan view schematically showing a portion of the wiring arranged in the display area DA of the display device 1 according to one or more embodiments.

[0120] The pixel circuitry PC can be arranged in the display area DA along a first direction (e.g., the +x-axis direction and / or the -x-axis direction) and a second direction (e.g., the +y-axis direction and / or the -y-axis direction), and Figure 5 The pixel circuit PC is shown arranged in the same row (e.g., the i-th row).

[0121] Each pixel circuit PC can be electrically connected to a light-emitting diode. In the following text, for ease of explanation, the pixel circuit PC electrically connected to each of the first to third light-emitting diodes that emit different colors of light is described as the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0122] The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 can be arranged sequentially along a first direction (e.g., the +x axis direction). Furthermore, the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode can be arranged sequentially along the first direction (e.g., the +x axis direction).

[0123] The first pixel circuit PC1 can be electrically connected to a first light-emitting diode (LED) that emits light of a first color. The first pixel circuit PC1 may include a first-1 pixel circuit PC1-1 and a first-2 pixel circuit PC1-2 arranged sequentially along a first direction (e.g., the +x-axis direction). The first LED may include a first-1 LED and a first-2 LED arranged sequentially along the first direction (e.g., the +x-axis direction). The first-1 pixel circuit PC1-1 can be electrically connected to the first-1 LED, and the first-2 pixel circuit PC1-2 can be electrically connected to the first-2 LED. The first-1 LED and the first-2 LED can each emit light of the first color. That is, the first-1 LED and the first-2 LED can emit light of the same color.

[0124] The second pixel circuit PC2 can be electrically connected to a second light-emitting diode (LED) that emits light of a second color. The second pixel circuit PC2 can include a second-1 pixel circuit PC2-1 and a second-2 pixel circuit PC2-2 arranged sequentially along a first direction (e.g., the +x-axis direction). The second LED can include a second-1 LED and a second-2 LED arranged sequentially along the first direction (e.g., the +x-axis direction). The second-1 pixel circuit PC2-1 can be electrically connected to the second-1 LED, and the second-2 pixel circuit PC2-2 can be electrically connected to the second-2 LED. The second-1 LED and the second-2 LED can each emit light of a second color. That is, the second-1 LED and the second-2 LED can emit light of the same color.

[0125] The third pixel circuit PC3 can be electrically connected to a third light-emitting diode (LED) that emits light of a third color. The third pixel circuit PC3 can include a third-1 pixel circuit PC3-1 and a third-2 pixel circuit PC3-2 arranged sequentially along a first direction (e.g., the +x-axis direction). The third LED can include a third-1 LED and a third-2 LED arranged sequentially along the first direction (e.g., the +x-axis direction). The third-1 pixel circuit PC3-1 can be electrically connected to the third-1 LED, and the third-2 pixel circuit PC3-2 can be electrically connected to the third-2 LED. The third-1 LED and the third-2 LED can each emit light of a third color. That is, the third-1 LED and the third-2 LED can emit light of the same color.

[0126] In one or more embodiments, the first color, the second color, and the third color are different colors of light, and can be selected from red, green, and blue. The first light-emitting diode, the second light-emitting diode, and the third light-emitting diode can emit different colors of light. For example, the first color can be red, the second color can be green, and the third color can be blue.

[0127] The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 can be arranged repeatedly along a first direction (e.g., the +x-axis direction and / or the -x-axis direction). The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 can be arranged sequentially along the first direction (e.g., the +x-axis direction and / or the -x-axis direction).

[0128] In the display area DA, lines electrically connected to the pixel circuit PC can be arranged, such as a first wire (hereinafter referred to as a horizontal wire) extending along a first direction (e.g., the +x-axis direction and / or the -x-axis direction) and a second wire (hereinafter referred to as a vertical wire) extending along a second direction (e.g., the +y-axis direction and / or the -y-axis direction).

[0129] Horizontal conductors extending along a first direction (e.g., the +x-axis direction and / or the -x-axis direction) may include a first -1 gate line GWL1, a first -2 gate line GWL2, a reference voltage line VRL, a drive voltage line PL, a horizontal sustaining voltage line HVSSL, and a first initialization horizontal voltage line HVAL. Specifically, the first gate line GWL may include the first -1 gate line GWL1 and the first -2 gate line GWL2. Additionally, the first initialization horizontal voltage line HVAL may include the first -1 initialization horizontal voltage line HVAL(R) and the first -2 initialization horizontal voltage line HVAL(GB).

[0130] The vertical conductor extending along a second direction (e.g., the +y-axis direction and / or the -y-axis direction) may include a first initial vertical voltage line VVAL and a vertical sustaining voltage line VVSSL. Specifically, the first initial vertical voltage line VVAL may include a first-1 initial vertical voltage line VVAL(R) and a first-2 initial vertical voltage line VVAL(GB).

[0131] The first-1 initialization vertical voltage line VVAL(R) and the first-1 initialization horizontal voltage line HVAL(R) that provide the first-1 initialization voltage Vaint(R) to the first-1 pixel circuit PC1-1 can be electrically connected in the display area DA.

[0132] The first-2 initialization vertical voltage line VVAL (GB) and the first-2 initialization horizontal voltage line HVAL (GB) that provide the first-3 initialization voltage Vaint (GB) to the second pixel circuit PC2 and the third pixel circuit PC3 can be electrically connected in the display area DA.

[0133] The vertical sustaining voltage line VVSSL and the horizontal sustaining voltage line HVSSL can be electrically connected in the display area DA. At this time, the vertical sustaining voltage line VVSSL can be electrically connected to the common voltage ELVSS.

[0134] Figure 5 The second pixel circuit PC2 and the third pixel circuit PC3 are shown to be electrically connected to the same voltage lines, such as the first-2 initialization vertical voltage line VVAL(GB) and / or the first-2 initialization horizontal voltage line HVAL(GB), but this disclosure is not limited thereto. As one or more other embodiments, the horizontal and vertical voltage lines for applying the first initialization voltage to the second pixel circuit PC2 and the horizontal and vertical voltage lines for applying the first initialization voltage to the third pixel circuit PC3 may each exist independently.

[0135] Figures 6 to 12 This is a plan view illustrating the process of forming a pixel circuit PC included in a display device 1 according to one or more embodiments.

[0136] Specifically, Figure 10 yes Figure 9 A magnified view of part of AA, and Figure 11 yes Figure 9 A magnified view of part of BB. Figure 12 It can correspond to the reference. Figure 4 The display device 1 described has a planar structure of a pixel circuit PC.

[0137] refer to Figure 4 and Figure 6The first-11 gate line GWL1-1, the first-21 gate line GWL2-1, the reference voltage line VRL, the bottom metal layer BML, the drive voltage line PL, the horizontal sustaining voltage line HVSSL, the first-11 initialization horizontal voltage line HVAL(R)1 and the first-2 initialization horizontal voltage line HVAL(GB) can be arranged on the substrate 100.

[0138] The first-11 gate line GWL1-1, the first-21 gate line GWL2-1, the reference voltage line VRL, the drive voltage line PL, the horizontal sustaining voltage line HVSSL, the first-11 initialization horizontal voltage line HVAL(R)1, and the first-2 initialization horizontal voltage line HVAL(GB) may extend in a first direction (e.g., in the +x-axis direction and / or the -x-axis direction) to cross the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0139] The first-11 initialization horizontal voltage line HVAL(R)1, the first-2 initialization horizontal voltage line HVAL(GB), the horizontal sustaining voltage line HVSSL, the drive voltage line PL, the bottom metal layer BML, the reference voltage line VRL, the first-21 gate line GWL2-1, and the first-11 gate line GWL1-1 can be arranged in the same layer (or at the same location), but can be arranged sequentially to be spaced apart from each other along a second direction (e.g., the +y axis direction).

[0140] The bottom metal layer (BML) can be configured in multiple quantities to correspond to the number of pixel circuits (PCs). For example, as... Figure 6 As shown, the six bottom metal layers BML can correspond to the first-1 pixel circuit PC1-1, the first-2 pixel circuit PC1-2, the second-1 pixel circuit PC2-1, the second-2 pixel circuit PC2-2, the third-1 pixel circuit PC3-1, and the third-2 pixel circuit PC3-2, respectively. The multiple bottom metal layers BML can be arranged in an island shape to be spaced apart from each other (e.g., spaced apart). The bottom metal layers BML can have isolated shapes.

[0141] The reference voltage line VRL may include a horizontal reference voltage line VRL_H extending in a first direction (e.g., in the +x-axis direction and / or -x-axis direction) and a vertical reference voltage line VRL_V protruding from the horizontal reference voltage line VRL_H in a second direction (e.g., in the +y-axis direction and / or -y-axis direction). The vertical reference voltage line VRL_V may be placed at the boundary between the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2. In other words, the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2 may have the vertical reference voltage line VRL_V arranged between them, and may have a symmetrical structure with respect to the vertical reference voltage line VRL_V. The vertical reference voltage line VRL_V may also be placed at the boundary between the second-1 pixel circuit PC2-1 and the second-2 pixel circuit PC2-2. In other words, the second-1 pixel circuit PC2-1 and the second-2 pixel circuit PC2-2 may have the vertical reference voltage line VRL_V arranged between them, and may have a symmetrical structure with respect to the vertical reference voltage line VRL_V. The vertical reference voltage line VRL_V can be placed at the boundary between the third-1 pixel circuit PC3-1 and the third-2 pixel circuit PC3-2. In other words, the third-1 pixel circuit PC3-1 and the third-2 pixel circuit PC3-2 can have the vertical reference voltage line VRL_V arranged between them, and can have a symmetrical structure with respect to the vertical reference voltage line VRL_V.

[0142] exist Figure 6 In the structure shown, for example, the first insulating layer 111 may be disposed on the first-11 gate line GWL1-1, the first-21 gate line GWL2-1, the reference voltage line VRL, the bottom metal layer BML, the drive voltage line PL, the first-11 initialization level voltage line HVAL(R)1, and the first-2 initialization level voltage line HVAL(GB). In one or more embodiments, in Figure 6 In the structure shown, for example, the first insulating layer 111 can also be arranged on the horizontal sustaining voltage line HVSSL.

[0143] refer to Figure 4 and Figure 7 The first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, the fourth semiconductor layer A4, the fifth semiconductor layer A5, and the sixth semiconductor layer A6, as well as the first conductive layer CL1, can be disposed on the first insulating layer 111. The first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, the fourth semiconductor layer A4, the fifth semiconductor layer A5, and the sixth semiconductor layer A6 can contain the same material.

[0144] The first semiconductor layer A1 and the fifth semiconductor layer A5 can be integrally connected. The second semiconductor layer A2 and the third semiconductor layer A3 can be integrally connected. The fourth semiconductor layer A4 and the sixth semiconductor layer A6 can be integrally connected. The first semiconductor layer A1 is arranged adjacent to the second semiconductor layer A2 and the third semiconductor layer A3, but can be separated from each other (e.g., spaced apart). The fifth semiconductor layer A5 and the sixth semiconductor layer A6 are arranged adjacent to each other, but can be separated from each other (e.g., spaced apart).

[0145] The first conductive layer CL1 may be arranged to overlap with the bottom metal layer BML. At least a portion of the bottom metal layer BML that overlaps with the first conductive layer CL1 may be the first electrode C21 of the second capacitor C2. Additionally, at least a portion of the first conductive layer CL1 that overlaps with the bottom metal layer BML may be the second electrode C22 of the second capacitor C2. That is, the bottom metal layer BML may include the first electrode C21 of the second capacitor C2, and the first conductive layer CL1 may include the second electrode C22 of the second capacitor C2.

[0146] The first conductive layer CL1 can be configured in multiple quantities to correspond to the number of pixel circuits PC. For example, as Figure 7 As shown, the six first conductive layers CL1 can correspond to the first-1 pixel circuit PC1-1, the first-2 pixel circuit PC1-2, the second-1 pixel circuit PC2-1, the second-2 pixel circuit PC2-2, the third-1 pixel circuit PC3-1, and the third-2 pixel circuit PC3-2, respectively. The first conductive layers CL1 can be configured in an island shape to be spaced apart (e.g., spaced apart) from the first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, the fourth semiconductor layer A4, the fifth semiconductor layer A5, and the sixth semiconductor layer A6. The first conductive layers CL1 can have an isolated shape.

[0147] Therefore, the second capacitor C2 can be configured in multiple quantities to correspond to the number of pixel circuits PC. For example, as Figure 7 As shown, the second capacitor C2 is configured with six units and can correspond to the first-1 pixel circuit PC1-1, the first-2 pixel circuit PC1-2, the second-1 pixel circuit PC2-1, the second-2 pixel circuit PC2-2, the third-1 pixel circuit PC3-1, and the third-2 pixel circuit PC3-2.

[0148] The first conductive layer CL1 disposed in two adjacent pixel circuits PC can be integrally connected. For example, the first conductive layer CL1 disposed in the first pixel circuit PC1 and the second pixel circuit PC2 can be integrally connected, and the first conductive layer CL1 disposed in the second pixel circuit PC2 and the third pixel circuit PC3 can be integrally connected.

[0149] exist Figure 7 In the structure shown, for example, the second insulating layer 112 may be placed on the first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, the fourth semiconductor layer A4, the fifth semiconductor layer A5, the sixth semiconductor layer A6, and the first conductive layer CL1.

[0150] refer to Figure 4 and Figure 8 The first-12 gate line GWL1-2, the first-22 gate line GWL2-2, the second gate line GRL, the third gate line EML, the fourth gate line GIL, the fifth gate line EMBL, the first-12 initialization horizontal voltage line HVAL(R)2, the second gate electrode G2, and the second conductive layer CL2 can be arranged on the second insulating layer 112.

[0151] The first -12 gate line GWL1-2, the first -22 gate line GWL2-2, the second gate line GRL, the third gate line EML, the fourth gate line GIL, the fifth gate line EMBL, and the first -12 initialization horizontal voltage line HVAL(R)2 may extend in a first direction (e.g., in the +x-axis direction and / or the -x-axis direction) to cross the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3. The first -12 gate line GWL1-2, the first -22 gate line GWL2-2, the second gate line GRL, the second gate electrode G2, the second conductive layer CL2, the third gate line EML, the fifth gate line EMBL, the fourth gate line GIL, and the first -12 initialization horizontal voltage line HVAL(R)2 may be arranged sequentially to be spaced apart from each other along a second direction (e.g., in the -y-axis direction).

[0152] The second gate electrode G2 can be configured in multiple numbers to correspond to the number of pixel circuits PC. For example, as Figure 8 As shown, the six second gate electrodes G2 can correspond to the first-1 pixel circuit PC1-1, the first-2 pixel circuit PC1-2, the second-1 pixel circuit PC2-1, the second-2 pixel circuit PC2-2, the third-1 pixel circuit PC3-1, and the third-2 pixel circuit PC3-2, respectively. The multiple second gate electrodes G2 can be arranged in an island shape to be spaced apart from each other (e.g., spaced apart). The multiple second gate electrodes G2 can have isolated shapes.

[0153] The second conductive layer CL2 can be configured in multiple quantities to correspond to the number of pixel circuits PC. For example, as Figure 8As shown, the six second conductive layers CL2 can correspond to the first-1 pixel circuit PC1-1, the first-2 pixel circuit PC1-2, the second-1 pixel circuit PC2-1, the second-2 pixel circuit PC2-2, the third-1 pixel circuit PC3-1, and the third-2 pixel circuit PC3-2, respectively. The multiple second conductive layers CL2 can be arranged in an island shape to be spaced apart from each other (e.g., spaced apart). The multiple second conductive layers CL2 can have isolated shapes.

[0154] Gate line GWL1-2 of the first-12 gate line can be connected to gate line GWL1-1 of the first-11 gate line (see...). Figure 6 (overlap). The first-12 gate line GWL1-2 can be electrically connected to the first-11 gate line GWL1-1 (see...) Figure 6 For example, in one or more embodiments, the first-12 gate line GWL1-2 and the first-11 gate line GWL1-1 (see...) Figure 6 () can be connected at specified intervals via contact holes. First-11 gate line GWL1-1 (see...) Figure 6 The first-12 gate line GWL1-2 is referred to as the first-1 gate line GWL1 (see [link]). Figure 5 ).

[0155] Gate line GWL2-2 of the first-22 can be connected to gate line GWL2-1 of the first-21 (see...) Figure 6 The first-22 gate line GWL2-2 can be electrically connected to the first-21 gate line GWL2-1 (see [link]). Figure 6 For example, in one or more embodiments, the first-22 gate line GWL2-2 and the first-21 gate line GWL2-1 (see...) Figure 6 () can be connected at specified intervals via contact holes. First-21 gate line GWL2-1 (see...) Figure 6 ) and the first-22 gate line GWL2-2 are referred to as the first-2 gate line GWL2 (see Figure 5 ).

[0156] At least a portion of the second gate line GRL may overlap with the third semiconductor layer A3. The portion of the second gate line GRL that overlaps with the third semiconductor layer A3 may be the third gate electrode G3. That is, the second gate line GRL may include the third gate electrode G3. The third semiconductor layer A3 and the third gate electrode G3 may form a third transistor T3. That is, the third transistor T3 may include the third semiconductor layer A3 and the third gate electrode G3.

[0157] The second gate electrode G2 may overlap with the second semiconductor layer A2. The second semiconductor layer A2 and the second gate electrode G2 may form the second transistor T2. That is, the second transistor T2 may include the second semiconductor layer A2 and the second gate electrode G2.

[0158] At least a portion of the second conductive layer CL2 may overlap with the first semiconductor layer A1. The portion of the second conductive layer CL2 that overlaps with the first semiconductor layer A1 may be the first gate electrode G1. That is, the second conductive layer CL2 may include the first gate electrode G1. The first semiconductor layer A1 and the first gate electrode G1 may form a first transistor T1. That is, the first transistor T1 may include the first semiconductor layer A1 and the first gate electrode G1.

[0159] At least a portion of the third gate line EML may overlap with the fifth semiconductor layer A5. The portion of the third gate line EML that overlaps with the fifth semiconductor layer A5 may be the fifth gate electrode G5. That is, the third gate line EML may include the fifth gate electrode G5. The fifth semiconductor layer A5 and the fifth gate electrode G5 may form a fifth transistor T5. That is, the fifth transistor T5 may include the fifth semiconductor layer A5 and the fifth gate electrode G5.

[0160] At least a portion of the fifth gate line EMBL may overlap with the sixth semiconductor layer A6. The portion of the fifth gate line EMBL that overlaps with the sixth semiconductor layer A6 may be the sixth gate electrode G6. That is, the fifth gate line EMBL may include the sixth gate electrode G6. The sixth semiconductor layer A6 and the sixth gate electrode G6 may form the sixth transistor T6. That is, the sixth transistor T6 may include the sixth semiconductor layer A6 and the sixth gate electrode G6.

[0161] At least a portion of the fourth gate line GIL may overlap with the fourth semiconductor layer A4. The portion of the fourth gate line GIL overlapping with the fourth semiconductor layer A4 may be the fourth gate electrode G4. That is, the fourth gate line GIL may include the fourth gate electrode G4. The fourth semiconductor layer A4 and the fourth gate electrode G4 may form a fourth transistor T4. That is, the fourth transistor T4 may include the fourth semiconductor layer A4 and the fourth gate electrode G4.

[0162] The first-12 initialization level voltage line HVAL(R)2 can be the same as the first-11 initialization level voltage line HVAL(R)1 (see...). Figure 6 Overlap. The first-12 initialization level voltage line HVAL(R)2 can be electrically connected to the first-11 initialization level voltage line HVAL(R)1 (see...). Figure 6 For example, in one or more embodiments, the first-12 initializes the horizontal voltage line HVAL(R)2 and the first-11 initializes the horizontal voltage line HVAL(R)1 (see...). Figure 6 ) can be accessed through the non-display area NDA (see Figure 1 The contact hole connection in ) . First-11 Initialize the horizontal voltage line HVAL(R)1 (see Figure 6 ) and the first -12 initialization horizontal voltage line HVAL(R)2 (see Figure 5 The first-1 initialization horizontal voltage line HVAL(R) is referred to as the first-1 initialization horizontal voltage line (see [link]). Figure 5 ).

[0163] The second conductive layer CL2 can be arranged to overlap with the bottom metal layer BML. At least a portion of the bottom metal layer BML overlapping the second conductive layer CL2 can be the first electrode C11 of the first capacitor C1. Additionally, at least a portion of the second conductive layer CL2 overlapping the bottom metal layer BML can be the first capacitor C1 (e.g., see...). Figure 4 The second electrode C12 of the first capacitor C1. That is, the bottom metal layer BML may include the first electrode C11 of the first capacitor C1, and the second conductive layer CL2 may include the second electrode C12 of the first capacitor C1.

[0164] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, as well as the first capacitor C1, can be configured in multiple quantities to correspond to the number of pixel circuits PC. For example, as Figure 6 As shown, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, as well as the first capacitor C1, are each set to a quantity of six, and can correspond to the first-1 pixel circuit PC1-1, the first-2 pixel circuit PC1-2, the second-1 pixel circuit PC2-1, the second-2 pixel circuit PC2-2, the third-1 pixel circuit PC3-1, and the third-2 pixel circuit PC3-2.

[0165] The third insulating layer 113 can be set in Figure 8 On the structure shown (e.g., first-12 gate line GWL1-2, first-22 gate line GWL2-2, second gate line GRL, third gate line EML, fourth gate line GIL, fifth gate line EMBL, first-12 initialization horizontal voltage line HVAL(R)2, second gate electrode G2 and second conductive layer CL2).

[0166] refer to Figures 4 to 9 Multiple connecting electrodes and data lines DL can be arranged on the third insulating layer 113.

[0167] The 93rd connecting electrode CM93 can contact the fifth semiconductor layer A5 of the fifth transistor T5 through the 94th contact hole CNT94. The 93rd connecting electrode CM93 can contact the driving voltage line PL through the 95th contact hole CNT95. The 93rd connecting electrode CM93 can contact the first conductive layer CL1 through the 96th contact hole CNT96. Therefore, the 93rd connecting electrode CM93 can electrically connect the fifth transistor T5 of the second capacitor C2, the driving voltage line PL, and the second electrode C22.

[0168] The 94th connecting electrode CM94 can contact the sixth semiconductor layer A6 of the sixth transistor T6 through the 97th contact hole CNT97. The 94th connecting electrode CM94 can contact the first semiconductor layer A1 of the first transistor T1 through the 98th contact hole CNT98. The 94th connecting electrode CM94 can contact the bottom metal layer BML through the 99th contact hole CNT99. Therefore, the 94th connecting electrode CM94 can electrically connect the sixth transistor T6, the first transistor T1, the first electrode C11 of the first capacitor C1, and the first electrode C21 of the second capacitor C2.

[0169] The 95th connecting electrode CM95 can contact the second conductive layer CL2 through the 101 contact hole CNT101. The 95th connecting electrode CM95 can contact the second semiconductor layer A2 of the second transistor T2 and the third semiconductor layer A3 of the third transistor T3 through the 102 contact hole CNT102. Therefore, the 95th connecting electrode CM95 can electrically connect the first gate electrode G1 of the first transistor T1, the second electrode C12 of the first capacitor C1, the second transistor T2, and the third transistor T3.

[0170] The 96th connecting electrode CM96 can contact the second gate electrode G2 of the second transistor T2 through the 103rd contact hole CNT103. The 96th connecting electrode CM96 can contact the first-1 gate line GWL1 or the first-2 gate line GWL2 through the 104th contact hole CNT104. Therefore, the 96th connecting electrode CM96 can electrically connect the second transistor T2 and the first gate line GWL.

[0171] Specifically, when the first-1 gate line GWL1 is electrically connected to the first-1 pixel circuit PC1-1 to provide a signal, the first-2 gate line GWL2 can be electrically connected to the first-2 pixel circuit PC1-2 to provide a signal. Similarly, when the first-1 gate line GWL1 is electrically connected to the second-1 pixel circuit PC2-1 to provide a signal, the first-2 gate line GWL2 can be electrically connected to the second-2 pixel circuit PC2-2 to provide a signal. Furthermore, when the first-1 gate line GWL1 is electrically connected to the third-2 pixel circuit PC3-2 to provide a signal, the first-2 gate line GWL2 can be electrically connected to the third-1 pixel circuit PC3-1 to provide a signal.

[0172] When a signal is applied from the first-1 gate line GWL1 to the first-1 pixel circuit PC1-1, a coupling capacitance may be generated primarily between the 94th connection electrode CM94 of the first semiconductor layer A1 electrically connected to the first transistor T1 of the first-1 pixel circuit PC1-1 and the 96th connection electrode CM96 electrically connected to the first-1 gate line GWL1 and disposed in the region of the first-1 pixel circuit PC1-1. Furthermore, even when a signal is subsequently applied sequentially from the first-2 gate line GWL2 to the first-2 pixel circuit PC1-2 adjacent to the first-1 pixel circuit PC1-1, a secondary coupling capacitance may be generated between the 94th connection electrode CM94 of the first semiconductor layer A1 electrically connected to the first transistor T1 of the first-1 pixel circuit PC1-1 and the 96th connection electrode CM96 electrically connected to the first-2 gate line GWL2 and disposed in the region of the first-2 pixel circuit PC1-2. The 94th connection electrode CM94 of the first transistor T1 connected to the first-1 pixel circuit PC1-1 is connected to the first-1 gate line GWL1, and a coupling capacitance is generated between the 96th connection electrode CM96 arranged in the region of the first-1 pixel circuit PC1-1 and the 96th connection electrode CM96 connected to the first-2 gate line GWL2 and arranged in the region of the first-2 pixel circuit PC1-2, which may cause the node of the source of the first transistor T1 of the first-1 pixel circuit PC1-1 to jitter, resulting in brightness deviation.

[0173] In one or more embodiments, a vertical reference voltage line VRL_V, protruding from the horizontal reference voltage line VRL_H extending in the first direction (e.g., in the +y-axis direction and / or in the -y-axis direction), can be arranged at the boundary between the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2 in a second direction (e.g., in the +y-axis direction and / or in the -y-axis direction). In other words, the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2 can have the vertical reference voltage line VRL_V arranged between them. The vertical reference voltage line VRL_V is arranged between the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2 and is connected to the 94th connection electrode CM94 and the first-2 gate line GWL2 connected to the first transistor T1 of the first-1 pixel circuit PC1-1, and can shield the 96th connection electrode CM96 arranged in the region of the first-2 pixel circuit PC1-2.

[0174] Therefore, when the first-2 gate line GWL2 is connected to the first-2 pixel circuit PC1-2 and a signal is applied, secondary coupling capacitance is prevented between the 94th connection electrode CM94 of the first transistor T1 connected to the first-1 pixel circuit PC1-1 and the 96th connection electrode CM96 connected to the first-2 gate line GWL2 and arranged in the region of the first-2 pixel circuit PC1-2, thereby preventing node jitter at the source of the first transistor T1 of the first-1 pixel circuit PC1-1, and thus improving the quality and brightness of the display device.

[0175] The secondary coupling capacitance generated between the 94th connection electrode CM94 of the first transistor T1 connected to the first-1 pixel circuit PC1-1 and the 96th connection electrode CM96 connected to the first-2 gate line GWL2 and arranged in the region of the first-2 pixel circuit PC1-2 has a greater impact than the primary coupling capacitance generated between the 94th connection electrode CM94 of the first semiconductor layer electrically connected to the first transistor T1 of the first-1 pixel circuit PC1-1 and the 96th connection electrode CM96 electrically connected to the first-1 gate line GWL1 and arranged in the region of the first-1 pixel circuit PC1-1. Therefore, by arranging the vertical reference voltage line VRL_V, the impact of the secondary coupling capacitance is reduced, thereby reducing the impact of the coupling capacitance. By preventing node jitter at the source of the first transistor T1 of the first-1 pixel circuit PC1-1, the quality and brightness of the display device can be improved.

[0176] When a signal is applied from the first-1 gate line GWL1 to the second-1 pixel circuit PC2-1, a coupling capacitance may be generated primarily between the 94th connection electrode CM94 of the first semiconductor layer A1 electrically connected to the first transistor T1 of the second-1 pixel circuit PC2-1 and the 96th connection electrode CM96 electrically connected to the first-1 gate line GWL1 and disposed in the region of the second-1 pixel circuit PC2-1. Furthermore, even when a signal is subsequently applied sequentially from the first-2 gate line GWL2 to the second-2 pixel circuit PC2-2 adjacent to the second-1 pixel circuit PC2-1, a secondary coupling capacitance may be generated between the 94th connection electrode CM94 of the first semiconductor layer A1 electrically connected to the first transistor T1 of the second-1 pixel circuit PC2-1 and the 96th connection electrode CM96 electrically connected to the first-2 gate line GWL2 and disposed in the region of the second-2 pixel circuit PC2-2. The 94th connection electrode CM94 of the first transistor T1 connected to the second-1 pixel circuit PC2-1 is connected to the first-1 gate line GWL1, and a coupling capacitance is generated between the 96th connection electrode CM96 arranged in the region of the second-1 pixel circuit PC2-1 and the 96th connection electrode CM96 connected to the first-2 gate line GWL2 and arranged in the region of the second-2 pixel circuit PC2-2, which may cause the node of the source of the first transistor T1 of the second-1 pixel circuit PC2-1 to jitter, resulting in brightness deviation.

[0177] In one or more embodiments, a horizontal reference voltage line VRL_H extending in a first direction (e.g., in the +x-axis direction and / or in the -x-axis direction) and a vertical reference voltage line VRL_V protruding in a second direction (e.g., in the +y-axis direction and / or in the -y-axis direction) can be arranged at the boundary between the second-1 pixel circuit PC2-1 and the second-2 pixel circuit PC2-2. In other words, the second-1 pixel circuit PC2-1 and the second-2 pixel circuit PC2-2 can have a vertical reference voltage line VRL_V arranged between them. The vertical reference voltage line VRL_V is arranged between the second-1 pixel circuit PC2-1 and the second-2 pixel circuit PC2-2 and is connected to the 94th connection electrode CM94 and the first-2 gate line GWL2 connected to the first transistor T1 of the second-1 pixel circuit PC2-1, and can shield the 96th connection electrode CM96 arranged in the region of the second-2 pixel circuit PC2-2.

[0178] Therefore, when the first-2 gate line GWL2 is connected to the second-2 pixel circuit PC2-2 and a signal is applied, secondary coupling capacitance is prevented between the 94th connection electrode CM94 of the first transistor T1 connected to the second-1 pixel circuit PC2-1 and the 96th connection electrode CM96 connected to the first-2 gate line GWL2 and arranged in the region of the second-2 pixel circuit PC2-2, thereby preventing node jitter at the source of the first transistor T1 of the second-1 pixel circuit PC2-1, and thus improving the quality and brightness of the display device.

[0179] The secondary coupling capacitance generated between the 94th connection electrode CM94 of the first transistor T1 connected to the second-1 pixel circuit PC2-1 and the 96th connection electrode CM96 connected to the first-2 gate line GWL2 and arranged in the region of the second-2 pixel circuit PC2-2 has a greater impact than the first coupling capacitance generated between the 94th connection electrode CM94 of the first semiconductor layer A1 electrically connected to the first transistor T1 of the second-1 pixel circuit PC2-1 and the 96th connection electrode CM96 electrically connected to the first-1 gate line GWL1 and arranged in the region of the second-1 pixel circuit PC2-1. Therefore, by arranging the vertical reference voltage line VRL_V, the impact of the secondary coupling capacitance is reduced, thereby preventing node jitter at the source of the first transistor T1 of the second-1 pixel circuit PC2-1, and improving the quality and brightness of the display device.

[0180] When a signal is applied from the first-2 gate line GWL2 to the third-1 pixel circuit PC3-1, a coupling capacitance may be generated primarily between the 94th connection electrode CM94 of the first semiconductor layer A1 electrically connected to the first transistor T1 of the third-1 pixel circuit PC3-1 and the 96th connection electrode CM96 electrically connected to the first-2 gate line GWL2 and disposed in the region of the third-1 pixel circuit PC3-1. Furthermore, even when a signal is subsequently applied sequentially from the first-1 gate line GWL1 to the third-2 pixel circuit PC3-2 adjacent to the third-1 pixel circuit PC3-1, a secondary coupling capacitance may be generated between the 94th connection electrode CM94 of the first semiconductor layer A1 electrically connected to the first transistor T1 of the third-1 pixel circuit PC3-1 and the 96th connection electrode CM96 electrically connected to the first-1 gate line GWL1 and disposed in the region of the third-2 pixel circuit PC3-2. The 94th connection electrode CM94 of the first transistor T1 connected to the third-1 pixel circuit PC3-1 is connected to the first-2 gate line GWL2, and a coupling capacitance is generated between the 96th connection electrode CM96 arranged in the region of the third-1 pixel circuit PC3-1 and the 96th connection electrode CM96 connected to the first-1 gate line GWL1 and arranged in the region of the third-2 pixel circuit PC3-2, so that the node of the source of the first transistor T1 of the third-1 pixel circuit PC3-1 can jitter, resulting in brightness deviation.

[0181] In one or more embodiments, a horizontal reference voltage line VRL_H extending in a first direction (e.g., in the +x-axis direction and / or in the -x-axis direction) and a vertical reference voltage line VRL_V protruding in a second direction (e.g., in the +y-axis direction and / or in the -y-axis direction) can be arranged at the boundary between the third-1 pixel circuit PC3-1 and the third-2 pixel circuit PC3-2. In other words, the third-1 pixel circuit PC3-1 and the third-2 pixel circuit PC3-2 can have a vertical reference voltage line VRL_V arranged between them. The vertical reference voltage line VRL_V is arranged between the third-1 pixel circuit PC3-1 and the third-2 pixel circuit PC3-2 and is capable of shielding the 94th connection electrode CM94 connected to the first transistor T1 of the third-1 pixel circuit PC3-1 and the 96th connection electrode CM96 connected to the first gate line GWL1 and arranged in the region of the third-2 pixel circuit PC3-2.

[0182] Therefore, when the first-1 gate line GWL1 is connected to the third-2 pixel circuit PC3-2 and a signal is applied, secondary coupling capacitance is prevented between the 94th connection electrode CM94 of the first transistor T1 connected to the third-1 pixel circuit PC3-1 and the 96th connection electrode CM96 connected to the first-1 gate line GWL1 and arranged in the region of the third-2 pixel circuit PC3-2, thereby preventing node jitter at the source of the first transistor T1 of the third-1 pixel circuit PC3-1, thereby improving the quality and brightness of the display device.

[0183] The secondary coupling capacitance generated between the 94th connection electrode CM94 of the first transistor T1 connected to the third-1 pixel circuit PC3-1 and the 96th connection electrode CM96 connected to the first-1 gate line GWL1 and arranged in the region of the third-2 pixel circuit PC3-2 has a greater impact than the primary coupling capacitance generated between the 94th connection electrode CM94 of the first semiconductor layer A1 electrically connected to the first transistor T1 of the third-1 pixel circuit PC3-1 and the 96th connection electrode CM96 electrically connected to the first-2 gate line GWL2 and arranged in the region of the third-1 pixel circuit PC3-1. Therefore, by arranging the vertical reference voltage line VRL_V, the impact of the secondary coupling capacitance is reduced, thereby reducing the impact of the coupling capacitance of the third-1 pixel circuit PC3-1. By preventing node jitter at the source of the first transistor T1, the quality and brightness of the display device can be improved.

[0184] The 97th connecting electrode CM97 can contact the reference voltage line VRL through the 105th contact hole CNT105. The 97th connecting electrode CM97 can contact the semiconductor layer of the third transistor T3 through the 106th contact hole CNT106. Therefore, the 97th connecting electrode CM97 can electrically connect the reference voltage line VRL and the third transistor T3.

[0185] refer to Figure 9 and Figure 10The first connecting electrode CM911 can contact the fourth semiconductor layer A4 of the fourth transistor T4 of the first pixel circuit PC1 (e.g., the first-2 pixel circuit PC1-2) through the first-1 contact hole CNT911. The first-1 contact hole CNT911 can penetrate the second insulating layer 112 and the third insulating layer 113. The first connecting electrode CM911 can contact the first-1 initialization horizontal voltage line HVAL(R) through the first-2 contact hole CNT912. The first-2 contact hole CNT912 can penetrate the third insulating layer 113. Therefore, through the first connecting electrode CM911, the first-1 initialization horizontal voltage line HVAL(R) can be electrically connected to the fourth transistor T4 of the first pixel circuit PC1 (e.g., the first-2 pixel circuit PC1-2). The first connecting electrode CM911 can be configured in an island shape to be separated (e.g., spaced apart) from other connecting electrodes arranged on the same layer. The first connecting electrode CM911 can have an isolated shape.

[0186] The first connecting electrode CM911 may include a first-1 connecting electrode portion CM9111 and a first-2 connecting electrode portion CM9112. The first-1 connecting electrode portion CM9111 extends in a first direction (e.g., in the +x-axis direction and / or the -x-axis direction) and may be electrically connected to each of the fourth transistor T4 of the first pixel circuit PC1 (e.g., the first-2 pixel circuit PC1-2) and the first-1 initialization horizontal voltage line HVAL(R). The first-2 connecting electrode portion CM9112 may extend from an end of the first-1 connecting electrode portion CM9111 in a second direction (e.g., in the +y-axis direction). At least a portion of the first-2 connecting electrode portion CM9112 may be disposed at the boundary between the first pixel circuit PC1 (e.g., the first-2 pixel circuit PC1-2) and the second pixel circuit PC2 (e.g., the second-1 pixel circuit PC2-1).

[0187] refer to Figure 9 and Figure 11The second connecting electrode CM912 can contact the fourth semiconductor layer A4 of the fourth transistor T4 of the third pixel circuit PC3 (e.g., the third-1 pixel circuit PC3-1) through the second-1 contact hole CNT913. The second-1 contact hole CNT913 can penetrate the second insulating layer 112 and the third insulating layer 113. The second connecting electrode CM912 can contact the first-2 initialization horizontal voltage line HVAL(GB) through the second-2 contact hole CNT914. The second-2 contact hole CNT914 can penetrate the third insulating layer 113. Therefore, through the second connecting electrode CM912, the first-2 initialization horizontal voltage line HVAL(GB) can be electrically connected to the fourth transistor T4 of the third pixel circuit PC3 (e.g., the third-1 pixel circuit PC3-1). The second connecting electrode CM912 can be configured in an island shape to be separated (e.g., spaced apart) from other connecting electrodes arranged on the same layer. The second connecting electrode CM912 can have an isolated shape.

[0188] The second connection electrode CM912 may include a second-1 connection electrode portion CM9121 and a second-2 connection electrode portion CM9122. The second-1 connection electrode portion CM9121 extends in a first direction (e.g., in the +x-axis direction and / or the -x-axis direction) and may be electrically connected to each of the fourth transistor T4 of the third pixel circuit PC3 (e.g., the third-1 pixel circuit PC3-1) and the first-2 initialization horizontal voltage line HVAL(GB). The second-2 connection electrode portion CM9122 may extend from an end of the second-1 connection electrode portion CM9121 in a second direction (e.g., in the +y-axis direction). At least a portion of the second-2 connection electrode portion CM9122 may be disposed at the boundary between the second pixel circuit PC2 (e.g., the second-2 pixel circuit PC2-2) and the third pixel circuit PC3 (e.g., the third-1 pixel circuit PC3-1).

[0189] Refer again Figure 9 The third connecting electrode CM913 can contact the horizontal sustaining voltage line HVSSL through the third contact hole CNT915. At least a portion of the second connecting electrode CM912 can overlap with the horizontal sustaining voltage line HVSSL. The third contact hole CNT915 can penetrate the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The third connecting electrode CM913 can be configured in an island shape to be spaced apart (e.g., spaced apart) from other connecting electrodes arranged in the same layer (e.g., at). The third connecting electrode CM913 can have an isolated shape.

[0190] The data line DL extends in a second direction (e.g., in the +y-axis direction and / or the -y-axis direction) and may be electrically connected to the second semiconductor layer A2 of the second transistor T2. The data line DL may include a first data line DL(R), a second data line DL(G), and a third data line DL(B). The first data line DL(R), the second data line DL(G), and the third data line DL(B) may be arranged to overlap with the vertical reference voltage line VRL_V.

[0191] The first data line DL(R) can be placed in the first pixel circuit PC1. Specifically, the first data line DL(R) can be placed at the boundary between the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2. In other words, the first data line DL(R) can be arranged between the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2. The first data line DL(R) can be electrically connected to the semiconductor layer of the second transistor T2 of the first pixel circuit PC1 through the contact hole CNT107. Specifically, the first data line DL(R) can be electrically connected to the semiconductor layer of the second transistor T2 of each of the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2 through the contact hole CNT107.

[0192] The second data line DL(G) can be placed in the second pixel circuit PC2. Specifically, the second data line DL(G) can be placed at the boundary between the second-1 pixel circuit PC2-1 and the second-2 pixel circuit PC2-2. In other words, the second-1 pixel circuit PC2-1 and the second-2 pixel circuit PC2-2 can be arranged such that the second data line DL(G) is inserted between them. The second data line DL(G) can be electrically connected to the semiconductor layer of the second transistor T2 of the second pixel circuit PC2 through the contact hole CNT108. Specifically, the second data line DL(G) can be electrically connected to the semiconductor layer of the second transistor T2 of each of the second-1 pixel circuit PC2-1 and the second-2 pixel circuit PC2-2 through the contact hole CNT108.

[0193] The third data line DL(B) can be placed in the third pixel circuit PC3. Specifically, the third data line DL(B) can be placed at the boundary between the third-1 pixel circuit PC3-1 and the third-2 pixel circuit PC3-2. In other words, the third data line DL(B) can be arranged between the third-1 pixel circuit PC3-1 and the third-2 pixel circuit PC3-2. The third data line DL(B) can be electrically connected to the semiconductor layer of the second transistor T2 of the third pixel circuit PC3 through the contact hole CNT109. Specifically, the third data line DL(B) can be electrically connected to the semiconductor layer of the second transistor T2 of each of the third-1 pixel circuit PC3-1 and the third-2 pixel circuit PC3-2 through the contact hole CNT109.

[0194] exist Figure 9 In the structure shown, for example, the fourth insulating layer 114 can be placed on multiple connection electrodes and data lines DL.

[0195] refer to Figure 4 as well as Figures 9 to 12 The first-1 initial vertical voltage line VVAL(R), the first-2 initial vertical voltage line VVAL(GB), and the vertical sustaining voltage line VVSSL can be arranged on the fourth insulating layer 114.

[0196] The first-1 initialization vertical voltage line VVAL(R), the first-2 initialization vertical voltage line VVAL(GB), and the vertical sustaining voltage line VVSSL may extend in a second direction (e.g., in the +y-axis direction and / or the -y-axis direction). The first-1 initialization vertical voltage line VVAL(R), the first-2 initialization vertical voltage line VVAL(GB), and the vertical sustaining voltage line VVSSL may be arranged sequentially on the same layer (e.g., at), but spaced apart from each other along a first direction (e.g., in the +x-axis direction).

[0197] The first-1 initialized vertical voltage line VVAL(R) can be electrically connected to the first-1 initialized horizontal voltage line HVAL(R). The first-1 initialized vertical voltage line VVAL(R) can be connected to the first connecting electrode CM911 through the 111 contact hole CNT111. The 111 contact hole CNT111 can penetrate the fourth insulating layer 114. The first connecting electrode CM911 can be electrically connected to the first-1 initialized horizontal voltage line HVAL(R) and the first-1 initialized vertical voltage line VVAL(R). The first-1 initialized horizontal voltage line HVAL(R), the first-1 initialized vertical voltage line VVAL(R), and the first connecting electrode CM911 can be arranged in different layers.

[0198] Specifically, the first-2 connecting electrode portion CM9112 can be electrically connected to the first-1 initialization vertical voltage line VVAL(R). The first-1 initialization vertical voltage line VVAL(R) can be arranged at the boundary between the first pixel circuit PC1 (e.g., the first-2 pixel circuit PC1-2) and the second pixel circuit PC2 (e.g., the second-1 pixel circuit PC2-1). At least a portion of the first-2 connecting electrode portion CM9112 can overlap with the first-1 initialization vertical voltage line VVAL(R).

[0199] The first-2 initialized vertical voltage line VVAL(GB) can be electrically connected to the first-2 initialized horizontal voltage line HVAL(GB). The first-2 initialized vertical voltage line VVAL(GB) can be connected to the second connecting electrode CM912 through the 112 contact hole CNT112. The 112 contact hole CNT112 can penetrate the fourth insulating layer 114. The second connecting electrode CM912 can be electrically connected to the first-2 initialized horizontal voltage line HVAL(GB) and the first-2 initialized vertical voltage line VVAL(GB). The first-2 initialized horizontal voltage line HVAL(GB), the first-2 initialized vertical voltage line VVAL(GB), and the second connecting electrode CM912 can be arranged in different layers.

[0200] Specifically, the second-2 connecting electrode portion CM9122 can be electrically connected to the first-2 initialization vertical voltage line VVAL(GB). The first-2 initialization vertical voltage line VVAL(GB) can be arranged at the boundary between the second pixel circuit PC2 (e.g., the second-2 pixel circuit PC2-2) and the third pixel circuit PC3 (e.g., the third-1 pixel circuit PC3-1). At least a portion of the second-2 connecting electrode portion CM9122 can overlap with the first-2 initialization vertical voltage line VVAL(GB).

[0201] The vertical sustaining voltage line VVSSL can be electrically connected to the horizontal sustaining voltage line HVSSL. The vertical sustaining voltage line VVSSL can be connected to the third connecting electrode CM913 through contact hole CNT113. Contact hole CNT113 can penetrate the fourth insulating layer 114. The third connecting electrode CM913 can be electrically connected to both the vertical sustaining voltage line VVSSL and the horizontal sustaining voltage line HVSSL. At least a portion of the third connecting electrode CM913 can overlap with the vertical sustaining voltage line VVSSL. The horizontal sustaining voltage line HVSSL, the vertical sustaining voltage line VVSSL, and the third connecting electrode CM913 can be arranged in different layers.

[0202] In one or more embodiments, a horizontal reference voltage line VRL_H extending in a first direction (e.g., in the +x-axis direction and / or -x-axis direction) and a vertical reference voltage line VRL_V protruding in a second direction (e.g., in the +y-axis direction and / or -y-axis direction) are disposed between the first-1 pixel circuit PC1-1 and the first-2 pixel circuit PC1-2 to shield the 94th connection electrode CM94 of the first transistor T1 connected to the first-1 pixel circuit PC1-1 and the 96th connection electrode CM96 connected to the first-2 gate line GWL2 and disposed in the region of the first-2 pixel circuit PC1-2. Therefore, when the first-2 gate line GWL2 is connected to the second-2 pixel circuit PC2-2 and a signal is applied, coupling capacitance can be prevented from being generated between the 94th connection electrode CM94 of the first transistor T1 connected to the first-1 pixel circuit PC1-1 and the 96th connection electrode CM96 connected to the first-2 gate line GWL2 and arranged in the region of the first-2 pixel circuit PC1-2, thereby preventing node jitter at the source of the first transistor T1 of the first-1 pixel circuit PC1-1, thereby improving the quality and brightness of the display device.

[0203] According to one or more of the above embodiments, a display device with improved reliability and quality can be realized. Of course, the scope of this disclosure is not limited to these embodiments.

[0204] Although this disclosure has been described with reference to embodiments shown in the accompanying drawings, these are merely examples and will be understood by those skilled in the art that various modifications and equivalent embodiments are possible. Therefore, the technical scope of this disclosure can be determined by the technical concept of the claims and their equivalents.

Claims

1. A display device, comprising: The first pixel circuit includes a first-1 pixel circuit and a first-2 pixel circuit arranged on a substrate along a first direction; A first-1 gate line extends in the first direction and is electrically connected to the first-1 pixel circuit; First-2 gate lines extend in the first direction and are electrically connected to the first-2 pixel circuits; as well as The reference voltage line includes a horizontal reference voltage line extending in the first direction and a vertical reference voltage line protruding from the horizontal reference voltage line in a second direction intersecting the first direction. The first-1 pixel circuit and the first-2 pixel circuit are arranged such that the vertical reference voltage line is inserted between the first-1 pixel circuit and the first-2 pixel circuit.

2. The display device according to claim 1 further includes a first light-emitting diode, the first light-emitting diode being electrically connected to the first pixel circuit.

3. The display device according to claim 2, wherein, The first light-emitting diode includes a first-1 light-emitting diode electrically connected to the first-1 pixel circuit and a first-2 light-emitting diode electrically connected to the first-2 pixel circuit, wherein the first-1 light-emitting diode and the first-2 light-emitting diode are arranged along the first direction.

4. The display device according to claim 3, wherein, The first-1 light-emitting diode and the first-2 light-emitting diode are configured to emit light of the same color.

5. The display device of claim 1, further comprising a first data line extending on the substrate in the second direction and overlapping the vertical reference voltage line.

6. The display device according to claim 5, wherein, The first -1 pixel circuit and the first -2 pixel circuit are arranged such that the first data line is inserted between the first -1 pixel circuit and the first -2 pixel circuit.

7. The display device according to claim 2, further comprising a second pixel circuit, the second pixel circuit being arranged adjacent to the first pixel circuit in the first direction, and including a second-1 pixel circuit and a second-2 pixel circuit arranged along the first direction. in, The second-1 pixel circuit and the second-2 pixel circuit are arranged such that the vertical reference voltage line is inserted between the second-1 pixel circuit and the second-2 pixel circuit.

8. The display device according to claim 7, wherein: The first-1 gate line is electrically connected to the second-1 pixel circuit, and The first-2 gate line is electrically connected to the second-2 pixel circuit.

9. The display device according to claim 7 further includes a second light-emitting diode, the second light-emitting diode being electrically connected to the second pixel circuit.

10. The display device according to claim 9, wherein, The first light-emitting diode and the second light-emitting diode are configured to emit light of different colors.

11. The display device according to claim 9, wherein, The second light-emitting diode includes a second-1 light-emitting diode electrically connected to the second-1 pixel circuit and a second-2 light-emitting diode electrically connected to the second-2 pixel circuit, wherein the second-1 light-emitting diode and the second-2 light-emitting diode are arranged along the first direction.

12. The display device according to claim 11, wherein, The second-1 light-emitting diode and the second-2 light-emitting diode are configured to emit light of the same color.

13. The display device of claim 7, further comprising a second data line extending on the substrate in the second direction and overlapping the vertical reference voltage line.

14. The display device according to claim 13, wherein, The second-1 pixel circuit and the second-2 pixel circuit are arranged such that the second data line is between the second-1 pixel circuit and the second-2 pixel circuit.

15. The display device of claim 9, further comprising a third pixel circuit, the third pixel circuit being arranged adjacent to the second pixel circuit in the first direction, and including a third-1 pixel circuit and a third-2 pixel circuit arranged along the first direction. in, The third-1 pixel circuit and the third-2 pixel circuit are arranged such that the vertical reference voltage line is inserted between the third-1 pixel circuit and the third-2 pixel circuit.

16. The display device according to claim 15, wherein: The first-1 gate line is electrically connected to the third-2 pixel circuit, and The first-2 gate line is electrically connected to the third-1 pixel circuit.

17. The display device according to claim 15, further comprising a third light-emitting diode, the third light-emitting diode being electrically connected to the third pixel circuit. in, The third light-emitting diode includes a third-1 light-emitting diode electrically connected to the third-1 pixel circuit and a third-2 light-emitting diode electrically connected to the third-2 pixel circuit, wherein the third-1 light-emitting diode and the third-2 light-emitting diode are arranged along the first direction.

18. The display device according to claim 17, wherein, The third-1 light-emitting diode and the third-2 light-emitting diode are configured to emit light of the same color.

19. The display device according to claim 17, wherein, The first light-emitting diode, the second light-emitting diode, and the third light-emitting diode are configured to emit light of different colors.

20. The display device of claim 15, further comprising a third data line extending on the substrate in the second direction and overlapping the vertical reference voltage line. in, The third-1 pixel circuit and the third-2 pixel circuit are arranged such that the third data line is inserted between the third-1 pixel circuit and the third-2 pixel circuit.

21. An electronic device including a display device, the display device comprising: The first pixel circuit includes a first-1 pixel circuit and a first-2 pixel circuit arranged on a substrate along a first direction; A first-1 gate line extends in the first direction and is electrically connected to the first-1 pixel circuit; First-2 gate lines extend in the first direction and are electrically connected to the first-2 pixel circuits; as well as The reference voltage line includes a horizontal reference voltage line extending in the first direction and a vertical reference voltage line protruding from the horizontal reference voltage line in a second direction intersecting the first direction. The first-1 pixel circuit and the first-2 pixel circuit are arranged such that the vertical reference voltage line is inserted between the first-1 pixel circuit and the first-2 pixel circuit.

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