Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes a substrate including a display area and a peripheral area surrounding the display area; a pixel circuit disposed in the display area; and a scan driver disposed in the peripheral area, the scan driver electrically connected to the pixel circuit, and the scan driver including: a sensing transistor; a first wiring electrically connected to a source electrode of the sensing transistor; and a first capacitor electrically connected to a source electrode of the sensing transistor and a gate electrode of the sensing transistor. The peripheral area includes a wiring arrangement area in which a wiring is disposed, and a circuit arrangement area in which at least one transistor is disposed, where the circuit arrangement area is between the display area and the wiring arrangement area. The first capacitor is provided in the wiring arrangement area. The sensing transistor is disposed in the circuit arrangement region. The first capacitor includes: a first electrode electrically connected to the first wiring; and a second electrode electrically connected to the gate electrode of the sensing transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0113090, filed on August 22, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device and an electronic device including the display device, and more specifically, to a display device for implementing a thin bezel and an electronic device including the display device. Background Technology

[0004] The display device is configured to receive information about an image and display the image. The display device is used as a display unit in miniaturized products such as mobile phones, and as a display unit in large products such as televisions.

[0005] A display device includes a plurality of pixels that receive electrical signals and emit light to display an image to the outside. Each pixel includes a light-emitting element. As an example, an organic light-emitting display device includes an organic light-emitting diode (OLED) as the light-emitting element. Typically, an organic light-emitting display device may include a thin-film transistor and an OLED on a substrate, and the organic light-emitting display device may operate while the OLED emits light spontaneously.

[0006] Electronic devices can provide users with a visual interface through display devices.

[0007] Various studies have been conducted to achieve display devices with thinner bezels. Summary of the Invention

[0008] One or more embodiments include a display device for achieving a thin bezel. However, such technical objectives are merely illustrative, and this disclosure is not limited thereto.

[0009] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of the embodiments of this disclosure.

[0010] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area surrounding the display area; a pixel circuit disposed in the display area; and a scan driver disposed in the peripheral area, the scan driver being electrically connected to the pixel circuit, and the scan driver including: a sensing transistor; a first wiring electrically connected to a source electrode of the sensing transistor; and a first capacitor electrically connected to the source electrode and the gate electrode of the sensing transistor, wherein the peripheral area includes a wiring arrangement area and a circuit arrangement area, the wiring being disposed in the wiring arrangement area, and at least one transistor being disposed in the circuit arrangement area, wherein the circuit arrangement area is between the display area and the wiring arrangement area, the first capacitor being disposed in the wiring arrangement area, the sensing transistor being disposed in the circuit arrangement area, and the first capacitor including: a first electrode electrically connected to the first wiring; and a second electrode electrically connected to the gate electrode of the sensing transistor.

[0011] In an embodiment, the first electrode may be the first wiring.

[0012] In an embodiment, in a plan view, a portion of the first wiring may overlap with the second electrode.

[0013] In one embodiment, a portion of the first wiring may be perpendicularly separated from the second electrode.

[0014] In an embodiment, the first electrode may be the lower electrode, and the second electrode may be the upper electrode.

[0015] In one embodiment, an insulating material may be disposed between the first electrode and the second electrode.

[0016] In an embodiment, in a plan view, the first capacitor may be separated from the sensing transistor in a first direction.

[0017] In one embodiment, the first wiring may extend in a second direction that intersects the first direction.

[0018] In one embodiment, the second electrode may include a first portion that overlaps with the first wiring in the plan view and a second portion that electrically connects the first portion to the gate electrode of the sensing transistor.

[0019] In an embodiment, the first portion may extend in the direction of the first wiring extension, and the second portion may extend in the first direction.

[0020] In an embodiment, the width of the first portion in the first direction may be greater than the width of the second portion in the second direction, and the second direction may intersect the first direction.

[0021] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area surrounding the display area; a pixel circuit disposed in the display area; a scan driver disposed in the peripheral area, the scan driver being electrically connected to the pixel circuit, and the scan driver including: a sensing transistor; a first wiring electrically connected to a source electrode of the sensing transistor; and a first capacitor electrically connected to the source electrode and the gate electrode of the sensing transistor, wherein the first capacitor includes: a first electrode configured to receive a control signal from a controller; and a second electrode electrically connected to the gate electrode of the sensing transistor, wherein the first electrode is the first wiring.

[0022] In an embodiment, the peripheral area includes: a wiring arrangement area in which wiring is arranged; and a circuit arrangement area in which at least one transistor is arranged, the circuit arrangement area being located between the display area and the wiring arrangement area, the first capacitor being disposed in the wiring arrangement area, and the sensing transistor being disposed in the circuit arrangement area.

[0023] In one embodiment, a portion of the first wiring may overlap with the second electrode in a plan view.

[0024] In one embodiment, a portion of the first wiring may be perpendicularly separated from the second electrode.

[0025] In an embodiment, in a plan view, the sensing capacitor may be separated from the sensing transistor in a first direction.

[0026] In one embodiment, the first wiring may extend in a second direction that intersects the first direction.

[0027] According to one or more embodiments, an electronic device includes: a controller for generating a scan input signal; a power module for generating a scan input voltage; and a display module including a display panel and a scan driver, wherein the display panel is divided into: a display area in which pixel circuitry is disposed; and a peripheral area surrounding the display area, and the scan driver is disposed in the peripheral area, the scan driver receiving the scan input signal and the scan input voltage, and the scan driver outputting a scan signal to the pixel circuitry. The scan driver may include at least one capacitor, the at least one capacitor including one electrode and another electrode, wherein the one electrode is a signal line transmitting at least one of the scan input signal and the scan input voltage, and the other electrode overlaps at least a portion of the signal line in a planar view.

[0028] In an embodiment, the peripheral area may include: a wiring arrangement area in which wiring is arranged; and a circuit arrangement area in which at least one transistor is arranged, wherein the circuit arrangement area is located between the display area and the wiring arrangement area, and the at least one capacitor may be located in the wiring arrangement area. Attached Figure Description

[0029] The above and other aspects, features and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a schematic plan view of a display device according to an embodiment;

[0031] Figure 2 This is a schematic conceptual diagram of a display device according to an embodiment;

[0032] Figure 3 yes Figure 2 A block diagram of the scanning driver hierarchy;

[0033] Figure 4 yes Figure 2 Circuit diagrams of the Nth and (N+1)th stages of the scan driver;

[0034] Figure 5 It is shown Figure 2 Timing diagrams of the input and output signals of the Nth and (N+1)th stages of the scan driver;

[0035] Figure 6 This is a diagram. Figure 2 A view of an example circuit diagram of some components in the Nth stage of a scan driver used to output the scan signal;

[0036] Figure 7 It is shown Figure 1 A schematic plan view of an example of area A;

[0037] Figure 8 It is shown Figure 1 A schematic plan view of an example of area A;

[0038] Figure 9 yes Figure 8 A schematic floor plan of a specific example;

[0039] Figure 10 It is a schematic plan view of an example of the circuit layout area of ​​a display device based on a comparative example;

[0040] Figure 11 yes Figure 1 A schematic equivalent circuit diagram of the pixels of a display device;

[0041] Figure 12 yes Figure 1 A schematic cross-sectional view of a portion of the display device; and

[0042] Figure 13 This is a block diagram of an electronic device according to an embodiment. Detailed Implementation

[0043] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in the written description. The effects and features of this disclosure, as well as methods for implementing them, will be illustrated with reference to the embodiments described in detail herein with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below and may be embodied in various forms.

[0044] In the following description, embodiments will be referenced to the accompanying drawings, in which the same reference numerals refer to the same elements and repeated descriptions are omitted.

[0045] As used herein, when various elements such as layers, regions, and plates are disposed "on" another element, not only can the element be disposed "directly" on the other element, but the other element can also be disposed between them. As used herein, when various elements such as layers, regions, and plates are disposed "below" another element, not only can the element be disposed "directly" below the other element, but the other element can also be disposed between them.

[0046] For ease of illustration, the dimensions of elements in the accompanying drawings may be exaggerated or reduced. As an example, for ease of description, the dimensions and thicknesses of each element shown in the drawings are arbitrarily represented, and therefore, this disclosure is not necessarily limited thereto. That is, for ease of description and for clarity, the dimensions, thicknesses, and scales of elements shown in the drawings may be exaggerated and / or simplified. Therefore, spatially relative terms such as “below,” “under,” “below,” “down,” “above,” and “above” can be used herein to readily describe the relationship of one element or feature to other elements or features.

[0047] The terms used in this specification to describe space and direction are those used to describe the space and direction shown in the accompanying drawings, but can be understood as terms used to describe various other directions or various perspectives. As an example, when a device or element shown in the accompanying drawings is flipped, a device or element described as "below" can be interpreted in different orientations (e.g., rotated 90 degrees and in the opposite direction, etc.). As an example, when a device or element shown in the accompanying drawings is flipped, a device or element described as "above" can be interpreted in different orientations (e.g., rotated 90 degrees and in the opposite direction, etc.). Therefore, "below" and "above" can include both upward and downward directions. Devices or elements may be oriented differently from those in the accompanying drawings, and the descriptions of space or direction described herein can be interpreted in various ways.

[0048] The order of processes or methods understood in the descriptions of the technological processes and manufacturing methods in this specification may differ from the order described. For example, two consecutively described processes or methods may be performed simultaneously or substantially simultaneously, or in the reverse order of their description.

[0049] The x-axis, y-axis, and z-axis are not limited to the directions of the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0050] In this document, the terms "first," "second," and "third," etc., may be used to describe specific elements. The terms "first," "second," and "third," etc., may be used to distinguish one element from another.

[0051] When an element is referred to as being “connected to” or “coupled to” another element, it will be understood that the element may be directly or indirectly connected to or coupled to the other element.

[0052] Similarly, when one element is referred to as "electrically" connected to another element, the one element can be directly electrically connected to the other element, or indirectly electrically connected to the other element through a conductive element.

[0053] When an element is referred to as being “between” two elements, it can be understood that the element is a single element arranged between the two elements, or another element other than the element arranged between the two elements.

[0054] The terminology used in this specification is for describing particular embodiments and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0055] It will be understood that the expressions “have,” “possess,” “include,” and “comprise” used herein indicate the presence of a feature, whole, operation, factor, and / or element of the statement, but do not preclude the presence or addition of one or more other features, wholes, operations, factors, and / or elements.

[0056] For example, the term "and / or" includes any and all combinations of one or more of the related listed items. For example, "A and / or B" means A or B or A and B. Expressions such as "at least one" can be used to refer to one or more elements among a plurality of elements. For example, the expressions "at least one of a, b and c" and "at least one selected from the group consisting of a, b and c" are "a", "b", "c", "a, b", "b, c", "a, c" or "a, b, c".

[0057] For example, terms such as “substantially,” “approximately,” and similar terms are used as approximate terms rather than terms of degree, and can be terms that describe inherent variations in measured or calculated values ​​that would be recognized by a person skilled in the art. For example, the use of terms such as “able to” and “may” can be used to mean “one or more embodiments disclosed herein.”

[0058] For example, in this specification, when a layer is referred to as having the “same layer structure” as another layer, it may mean that multiple layers included in one layer can be included in the other layer in the same order. For example, multiple layers included in one layer and multiple layers included in another layer may each comprise the same material and be formed in the same order.

[0059] Electronic or electrical devices and / or any other related devices or components (e.g., some of the various modules) according to embodiments of the present disclosure described herein can be configured using any suitable hardware, firmware (e.g., which may be implemented using a combination of application-specific integrated circuits), software, or a combination of firmware and hardware. For example, the various components of these devices may be formed in a single integrated circuit (IC) chip or in separate IC chips. Furthermore, the various components of these devices may be formed on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or a single substrate. The various components of these devices may be processes or threads that run on one or more processors, execute computer program instructions in one or more computing devices, and interact with other system components to perform the various functions described herein.

[0060] Computer program instructions are stored in memory, which can be implemented in a computing device using standard memory devices, such as random access memory (RAM). Computer program instructions can also be stored on other non-transitory computer-readable media, such as read-only optical disc storage (CD-ROM) and flash memory drives. Those skilled in the art will recognize that, without departing from the spirit and scope of the exemplary embodiments of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0061] In the following, a display device and an electronic device including the display device according to embodiments are described in detail based on the above description.

[0062] Figure 1 This is a schematic plan view of a display device according to an embodiment.

[0063] like Figure 1 As shown, the display device according to an embodiment may include a display panel 10. Any display device can be used, as long as it includes a display panel 10. As an example, the display device may include various devices, such as smartphones, tablet computers, laptop computers, televisions, or billboards. Because the display device according to an embodiment includes thin-film transistors and capacitors, the thin-film transistors and capacitors can be implemented using conductive layers and insulating layers.

[0064] The display panel 10 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of display panel 10 is not particularly limited. The display panel 10 may be a rigid type or a flexible type that can be rolled up or folded. The display module 1400 may also include a support, bracket, or heat dissipation component that supports the display panel 10.

[0065] Display panel 10 includes a display area DA and a peripheral area PA outside the display area DA. Although in Figure 1 The illustration shows a display area DA with a rectangular shape, but this disclosure is not limited thereto. The display area DA can have various shapes, such as circular, elliptical, polygonal shapes other than rectangular, or shapes of specific graphics.

[0066] The display area DA is the area for displaying an image, and multiple pixels PX can be disposed within the display area DA. Each pixel PX may include a display element, such as an organic light-emitting element. Each pixel PX can be configured to emit, for example, red, green, or blue light. The pixel PX can be connected to pixel circuitry including thin-film transistors (TFTs) and storage capacitors. The pixel circuitry can be connected to a scan line SL, a data line DL, and a drive voltage line PL, wherein the scan line SL is configured to transmit a scan signal, the data line DL intersects the scan line SL and is configured to transmit a data signal, and the drive voltage line PL is configured to supply a drive voltage. The data line DL and the drive voltage line PL can extend in the y-axis direction (hereinafter referred to as the second direction), and the scan line SL can extend in the x-axis direction (hereinafter referred to as the first direction).

[0067] Pixel PX can be configured to emit light with a brightness corresponding to an electrical signal from a pixel circuit electrically connected thereto. Display area DA can be configured to display a preset image using the light emitted from pixel PX. For reference, pixel PX can be defined as an emitting area configured to emit red, green, or blue light.

[0068] The peripheral area PA is the region where pixels PX are not disposed and can be configured not to display images. Power lines for driving pixels PX, etc., can be provided in the peripheral area PA. In some aspects, pads can be provided in the peripheral area PA. Printed circuit boards including driving circuitry, integrated circuit components (such as driver integrated circuits (ICs) for example), and pads can be electrically connected to each other in the peripheral area PA.

[0069] For reference, since the display panel 10 includes a substrate 100, it is understood that the substrate 100 includes a display area DA and a peripheral area PA. The substrate 100 is described in detail herein.

[0070] In some aspects, multiple transistors can be arranged in the display area DA. Among the multiple transistors, depending on the type of transistor (N-type or P-type) and / or operating conditions, the first terminal of the transistor can be the source electrode or the drain electrode, and the second terminal can be an electrode different from the first terminal. As an example, if the first terminal is the source electrode, the second terminal can be the drain electrode.

[0071] As an example, multiple transistors may include a driving transistor, a data writing transistor, a compensation transistor, an initialization transistor, and an emission control transistor, etc. The driving transistor can be connected to the driving voltage line PL and the organic light-emitting element OLED (see [link to OLED diagram]). Figure 11 Between ), and the data writing transistor can be connected to the data line DL and the drive transistor, and can perform a switching operation to transmit the data signal received through the data line DL.

[0072] The compensation transistor can be turned on according to the scan signal transmitted through the scan line SL, and is configured to compensate the threshold voltage of the driving transistor by connecting the driving transistor to the organic light-emitting element OLED.

[0073] The initialization transistor can be turned on according to the scan signal transmitted via scan line SL, and is configured to initialize the gate electrode of the driving transistor by transmitting an initialization voltage to the gate electrode of the driving transistor. The scan line connected to the initialization transistor can be a separate scan line different from the scan line connected to the compensation transistor.

[0074] The emitter control transistor can be turned on according to the emitter control signal transmitted through the emitter control line, and therefore, the drive current can flow through the organic light-emitting element OLED.

[0075] An organic light-emitting element (OLED) may include a pixel electrode (anode) and a counter electrode (cathode), and receives a target voltage from both the pixel electrode (anode) and the counter electrode (cathode). The OLED can be configured to display an image by receiving a drive current from a driving transistor and emitting light.

[0076] In the following description, although an organic light-emitting display device is described as an example of a display device according to an embodiment, the display device according to this disclosure is not limited thereto. In another embodiment, the display device according to the embodiment may be an inorganic light-emitting display device or a quantum dot light-emitting display device. As an example, the emitting layer of the display element of the display device may include an organic material or an inorganic material. In some aspects, the display device may include an emitting layer and quantum dots disposed in the path of light emitted from the emitting layer.

[0077] Figure 2 This is a schematic concept diagram of a display device according to an embodiment.

[0078] like Figure 2 As shown, the display device may include a pixel portion PP, a scan driver GP, a data driver DP, and a controller CP.

[0079] The pixel portion PP, which sets multiple pixels PX, can be set in the display area DA (see...). Figure 1In the peripheral area PA (see...), the scan driver GP, data driver DP, and controller CP can be set. Figure 1 )middle.

[0080] Each of the multiple pixels PX can be connected to a corresponding scan line among multiple scan lines SL1, SL2, SL3... and SLn, and a corresponding data line among multiple data lines DL1, DL2,..., DL1, DL1+1, DL1+2,..., DL2i,..., DLm-i+1, DLm-i+2,... and DLm. Here, n is a positive integer, m is a positive integer, and i is a positive integer less than or equal to m / 2. Each of the multiple scan lines SL1 to SLn can extend in a first direction (e.g., the x-axis direction, the row direction) and connect to a pixel PX located in the same row. Each of the multiple scan lines SL1 to SLn can transmit a scan signal to a pixel PX located in the same row. Each of the multiple data lines DL1 to DLm can extend in a second direction (e.g., the y-axis direction, the column direction) and connect to a pixel PX located in the same column.

[0081] The scan driver GP can be connected to multiple scan lines SL1 to SLn, and can generate scan signals in response to the gate drive control signal GCS from the controller CP, and sequentially supply scan signals to the multiple scan lines SL1 to SLn. In the example of sequentially supplying scan signals to scan lines SL1 to SLn, pixels PX can be selected on a row-by-row basis. Each of the data lines DL1 to DLm can transmit data signals to the pixel PX in the selected row. The scan lines can be connected to the gates of transistors included in the pixels PX. The scan signal can be a gate control signal that controls the on and off states of the transistors connected to the scan lines. The scan signal can be a square wave signal in which an on-state voltage that turns the transistor on and an off-state voltage that turns the transistor off are repeated.

[0082] The scan driver GP is a driver chip and can be mounted on the display panel 10. In some aspects, the scan driver GP can be integrated into the display panel 10. As an example, the scan driver GP may include an amorphous silicon TFT gate driver circuit (ASG), a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) embedded in the display panel 10.

[0083] The data driver DP can convert image signals into data signals in the form of voltage or current based on the data drive control signal DCS input from the controller CP.

[0084] The controller CP can generate a data drive control signal DCS and a gate drive control signal GCS in response to a synchronization signal or clock signal supplied from an external source. As an example, the controller CP can be as described herein. Figure 13 The controller 1120-1, or an element including the controller 1120-1, can output a data drive control signal DCS to the data driver DP and a gate drive control signal GCS to the scan driver GP.

[0085] The scan driver GP can be directly formed on the substrate 100 (see...) Figure 1 The data driver DP can be disposed on a flexible printed circuit board (FPCB) electrically connected to pads disposed on one side of the substrate 100. In another embodiment, the data driver DP can be directly disposed on the substrate 100 using a glass-on-chip (COG) method or a plastic-on-chip (COP) method.

[0086] Figure 3 yes Figure 2 A block diagram of the GP level of the scan driver.

[0087] refer to Figure 3 The scan driver GP can include multiple stages ST1 to ST10. Although ten stages are shown for ease of description, each stage can output a scan signal, and the number of stages can correspond to the number of gate lines.

[0088] Within a level, two adjacent levels can form a level pair. For example, a first level pair may include level 1 (ST1) and level 2 (ST2). For example, a second level pair may include level 3 (ST3) and level 4 (ST4). For example, a third level pair may include level 5 (ST5) and level 6 (ST6). For example, a fourth level pair may include level 7 (ST7) and level 8 (ST8). For example, a fifth level pair may include level 9 (ST9) and level 10 (ST10).

[0089] The two stages in a stage pair may include switching elements that are directly connected to each other. In some respects, the two stages in a stage pair may share at least one input signal.

[0090] Figure 4 yes Figure 2 The circuit diagrams for the Nth stage ST_N and the (N+1)th stage ST_N+1 of the scan driver GP are shown. Figure 5 It is shown Figure 2 Timing diagrams of the input and output signals of the Nth stage ST_N and (N+1)th stage ST_N+1 of the scan driver GP.

[0091] For reference only. Figure 4 The circuit diagram is an example for ease of description and can be used in addition to... Figure 4 Various circuit diagrams other than the circuit diagram shown. The construction of transistors used to control the scanning signals of pixels or scan lines can be based on the display panel 10 (see...). Figure 1 Various changes are made to the specifications, user requirements, and supplier environment.

[0092] like Figure 4 As shown, stage N ST_N and stage (N+1) ST_N+1 can form a stage pair. Stage N ST_N and stage (N+1) ST_N+1 can include switching elements directly connected to each other. In some aspects, stage N ST_N and stage (N+1) ST_N+1 can share at least one input signal.

[0093] The first input signal S1 to the sixth input signal S6 can be applied to the Nth stage ST_N, the Nth clock signal can be applied, and the first to third low voltages VSS1, VSS2, and VSS3 can be applied. Figure 5 The diagram shows the Nth scan signal SC_N generated by the Nth stage ST_N and the (N+1)th scan signal SC_N+1 generated by the (N+1)th stage ST_N+1. For ease of description, the scan signal mentioned in this specification can be the Nth scan signal SC_N.

[0094] The Nth clock signal may include the gate clock signal SC-CK_N, the sense clock signal SS-CK_N, and the carry clock signal CR-CK_N. The (N+1)th clock signal may include the gate clock signal SC-CK_N+1, the sense clock signal SS-CK_N+1, and the carry clock signal CR-CK_N+1.

[0095] like Figure 4 As shown, the Nth stage ST_N may include a first sensor 310, a second sensor 320, a Q-node charger 330, a Q-node stabilizer 340, an inverter 350, a carry signal output unit 360, a sensing signal output unit 370, a scan signal output unit 380, and a switching element stabilizer 390.

[0096] The first sensor 310 and the second sensor 320 can operate based on the first input signal S1, the second input signal S2, the sixth input signal S6 and the Q node QN signal (i.e., the signal or voltage of the Q node QN), and can sense the characteristics of the switching elements within the pixels PX of the display panel 10.

[0097] In the following text, an example of a sensing switch element mentioned in this specification may be disposed on substrate 100 (see [reference]). Figure 1 Transistors or thin-film transistors on a transistor.

[0098] The first sensor 310 includes a first sensing switch element T24A, a second sensing switch element T25A, and a sensing capacitor C3A.

[0099] The sensing capacitor C3A may include a first electrode and a second electrode, wherein a sixth input signal S6 is applied to the first electrode and the second electrode is connected to the gate electrode of the first sensing switch element T24A.

[0100] The first sensing switch element T24A may include a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode is connected to the second electrode of the sensing capacitor C3A, the sixth input signal S6 is applied to the source electrode, and the drain electrode is connected to the source electrode of the second sensing switch element T25A.

[0101] The second sensing switch element T25A may include a gate electrode, a source electrode, and a drain electrode, wherein the second input signal S2 is applied to the gate electrode, the source electrode is connected to the drain electrode of the first sensing switch element T24A, and the drain electrode is connected to the Q node QN.

[0102] The second sensor 320 may include a third sensing switch element T21A, a fourth sensing switch element T22A, a fifth sensing switch element T23A, a sixth sensing switch element T26A, and a seventh switch element T27A.

[0103] The third sensing switch element T21A may include a gate electrode, a source electrode, and a drain electrode, wherein a first input signal S1 is applied to the gate electrode, one of the previous carry signals (e.g., the (N-2)th carry signal IN_N-2) is applied to the source electrode, and the drain electrode is connected to the source electrode of the fourth sensing switch element T22A.

[0104] The fourth sensing switch element T22A may include a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode is connected to the drain electrode of the fifth sensing switch element T23A, the source electrode is connected to the drain electrode of the third sensing switch element T21A, and the drain electrode is connected to the drain electrode of the fourth sensing switch element T22B of the (N+1)th stage ST_N+1.

[0105] The fifth sensing switch element T23A may include a gate electrode, a source electrode, and a drain electrode, wherein a first input signal S1 is applied to the gate electrode, the source electrode is connected to the drain electrode of the third sensing switch element T21A, and the drain electrode is connected to the gate electrode of the fourth sensing switch element T22A.

[0106] The sixth sensing switch element T26A may include a gate electrode, a source electrode, and a drain electrode, wherein the second input signal S2 is applied to the gate electrode, the source electrode is connected to the drain electrode of the seventh switch element T27A, and the drain electrode is connected to the drain electrode of the tenth inverting switch element T18A.

[0107] The seventh switching element T27A may include a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode is connected to the drain electrode of the fifth sensing switching element T23A, a first low voltage VSS1 is applied to the source electrode, and the drain electrode is connected to the source electrode of the sixth sensing switching element T26A.

[0108] Q-node charger 330 charges Q-node QN based on one of the previous carry signals. Here, one of the previous carry signals may be the carry signal of the third previous stage from the current stage (e.g., the (N-3)th carry signal IN_N-3).

[0109] The Q-node charger 330 may include a first charging switch element T4-1A and a second charging switch element T4-2A.

[0110] The first charging switch element T4-1A may include a gate electrode, a source electrode, and a drain electrode, wherein one of the previous carry signals (e.g., the (N-3)th carry signal IN_N-3) is applied to the gate electrode, one of the previous carry signals (the (N-3)th carry signal IN_N-3) is applied to the source electrode, and the drain electrode is connected to the source electrode of the second charging switch element T4-2A.

[0111] The second charging switch element T4-2A may include a gate electrode, a source electrode, and a drain electrode, wherein one of the previous carry signals (e.g., the (N-3)th carry signal IN_N-3) is applied to the gate electrode, the source electrode is connected to the drain electrode of the first charging switch element T4-1A, and the drain electrode is connected to the Q node QN.

[0112] Q-node stabilizer 340 stabilizes Q-node QN based on one of the subsequent carry signals and the fifth input signal S5. Here, one of the subsequent carry signals can be the carry signal of the fourth subsequent stage from the current stage (e.g., the (N+4)th carry signal IN_N+4). As an example, Q-node stabilizer 340 for the first stage of a stage pair (e.g., stage N ST_N) can receive the carry signal of the fourth subsequent stage from the current stage (e.g., the (N+4)th carry signal IN_N+4). As an example, Q-node stabilizer 340 for the second stage of a stage pair (e.g., stage (N+1) ST_N+1) can receive the carry signal of the third subsequent stage from the current stage (e.g., the (N+3)th carry signal IN_N+3). Here, the fifth input signal S5 can be a vertical start signal.

[0113] The Q-node stabilizer 340 may include a first stabilizing switch element T1-1A, a second stabilizing switch element T1-2A, a third stabilizing switch element T2-1A, and a fourth stabilizing switch element T2-2A.

[0114] The first stable switching element T1-1A may include a gate electrode, a source electrode, and a drain electrode, wherein a fifth input signal S5 is applied to the gate electrode, the source electrode is connected to the drain electrode of the second stable switching element T1-2A, and a first low voltage VSS1 is applied to the drain electrode.

[0115] The second stable switching element T1-2A may include a gate electrode, a source electrode, and a drain electrode, wherein a fifth input signal S5 is applied to the gate electrode, the source electrode is connected to the Q node QN, and the drain electrode is connected to the source electrode of the first stable switching element T1-1A.

[0116] The third stable switching element T2-1A may include a gate electrode, a source electrode, and a drain electrode, wherein one of the subsequent carry signals (e.g., the (N+4)th carry signal IN_N+4) is applied to the gate electrode, the source electrode is connected to the drain electrode of the fourth stable switching element T2-2A, and a first low voltage VSS1 is applied to the drain electrode.

[0117] The fourth stable switching element T2-2A may include a gate electrode, a source electrode, and a drain electrode, wherein one of the subsequent carry signals (e.g., the (N+4)th carry signal IN_N+4) is applied to the gate electrode, the source electrode is connected to the Q node QN, and the drain electrode is connected to the source electrode of the third stable switching element T2-1A.

[0118] Inverter 350 can generate an inverted signal INV_N based on the third input signal S3 and the Q node QN signal. Inverter 350 can receive the Q node QN+1 signal of the (N+1)th stage ST_N+1 and the inverted signal INV_N+1 of the (N+1)th stage ST_N+1.

[0119] The inverter 350 may include a first inverting switch element T3-1A, a second inverting switch element T3-2A, a third inverting switch element T19A, a fourth inverting switch element T5-1A, a fifth inverting switch element T5-2A, a sixth inverting switch element T20A, a seventh inverting switch element T15A, an eighth inverting switch element T16A, a ninth inverting switch element T17A, and a tenth inverting switch element T18A.

[0120] The carry signal output unit 360 can output the carry signal CR_N based on the Q node QN signal and the inverted signals INV_N and INV_N+1. The carry signal output unit 360 of the (N+1)th stage ST_N+1 can output the carry signal CR_N+1.

[0121] The carry signal output unit 360 may include a first carry switch element T12A, a second carry switch element T13A, and a third carry switch element T14A.

[0122] The first carry switching element T12A may include a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode is connected to the Q node QN, the carry clock signal CR-CK_N is applied to the source electrode, and the drain electrode is connected to the carry signal output terminal.

[0123] The second carry switch element T13A may include a gate electrode, a source electrode, and a drain electrode, wherein the inverted signal INV_N+1 of the (N+1)th stage ST_N+1 is applied to the gate electrode, the source electrode is connected to the carry signal output terminal, and a first low voltage VSS1 is applied to the drain electrode.

[0124] The third carry switch element T14A may include a gate electrode, a source electrode, and a drain electrode, wherein an inverted signal INV_N is applied to the gate electrode, the source electrode is connected to the carry signal output terminal, and a first low voltage VSS1 is applied to the drain electrode.

[0125] The sensing signal output unit 370 can output the sensing signal SS_N based on the Q-node QN signal and the inverted signals INV_N and INV_N+1. The sensing signal output unit 370 of the (N+1)th stage ST_N+1 can output the sensing signal SS_N+1.

[0126] The sensing signal output unit 370 may include a first sensing output switch element T9A, a second sensing output switch element T10A, and a third sensing output switch element T11A.

[0127] The first sensing output switching element T9A may include a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode is connected to the Q node QN, the sensing clock signal SS-CK_N is applied to the source electrode, and the drain electrode is connected to the sensing signal output terminal.

[0128] The second sensing output switching element T10A may include a gate electrode, a source electrode, and a drain electrode, wherein the inverted signal INV_N+1 of the (N+1)th stage ST_N+1 is applied to the gate electrode, the source electrode is connected to the sensing signal output terminal, and a third low voltage VSS3 is applied to the drain electrode.

[0129] The third sensing output switching element T11A may include a gate electrode, a source electrode, and a drain electrode, wherein an inverted signal INV_N is applied to the gate electrode, the source electrode is connected to the sensing signal output terminal, and a third low voltage VSS3 is applied to the drain electrode.

[0130] The sensing signal output unit 370 may further include a sensing output capacitor C2A connected between the gate electrode and the drain electrode of the first sensing output switching element T9A.

[0131] The scan signal output unit 380 can output the scan signal SC_N based on the Q node QN signal and the inverted signals INV_N and INV_N+1.

[0132] The scan signal output unit 380 may include a first gate switch element T6A, a second gate switch element T7A, and a third gate switch element T8A.

[0133] The first gate switching element T6A may include a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode is connected to the Q node QN, the gate clock signal SC-CK_N is applied to the source electrode, and the drain electrode is connected to the scan signal output terminal.

[0134] The second gate switching element T7A may include a gate electrode, a source electrode, and a drain electrode, wherein the inverted signal INV_N+1 of the (N+1)th stage ST_N+1 is applied to the gate electrode, the source electrode is connected to the scan signal output terminal, and a third low voltage VSS3 is applied to the drain electrode.

[0135] The third gate switching element T8A may include a gate electrode, a source electrode, and a drain electrode, wherein an inverted signal INV_N is applied to the gate electrode, the source electrode is connected to the scan signal output terminal, and a third low voltage VSS3 is applied to the drain electrode.

[0136] The scan signal output unit 380 may further include a gate capacitor C1A connected between the gate electrode and the drain electrode of the first gate switching element T6A.

[0137] The switching element stabilizer 390 responds to the Q node QN by transmitting the sixth input signal S6 to the intermediate node of the series-connected switching elements to stabilize the operation of the series-connected switching elements.

[0138] The switching element stabilizer 390 may include a switching element stabilizer switching element T28A.

[0139] The stabilizing switch element T28A may include a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to a Q node QN, a sixth input signal S6 is applied to the source electrode, and the drain electrode is connected to the drain electrode of the first charging switch element T4-1A. The drain electrode of the stabilizing switch element T28A may be commonly connected to the nodes to which the first charging switch element T4-1A and the second charging switch element T4-2A are connected, the nodes to which the first stabilizing switch element T1-1A and the second stabilizing switch element T1-2A are connected, the nodes to which the third stabilizing switch element T2-1A and the fourth stabilizing switch element T2-2A are connected, the nodes to which the first inverting switch element T3-1A and the second inverting switch element T3-2A are connected, and the nodes to which the fourth inverting switch element T5-1A and the fifth inverting switch element T5-2A are connected.

[0140] Figure 4 The Nth stage ST_N and the (N+1)th stage ST_N+1 shown can form a stage pair, and as shown, the (N+1)th stage ST_N+1 can include a circuit that is a mirror image of the Nth stage ST_N. Figure 4 In this document, reference numerals ending with "B" are used to denote elements in level (N+1) ST_N+1 that correspond to elements in level N ST_N, and repeated descriptions thereof will be omitted herein.

[0141] When the third input signal S3 is input to the Nth level ST_N, the fourth input signal S4 can be input to the structure corresponding to the (N+1)th level ST_N+1.

[0142] In some respects, the carry signal of the fourth subsequent stage (e.g., the (N+4)th carry signal IN_N+4) from the current stage (e.g., the Nth stage ST_N) can be applied to the third stabilizing switch element T2-1A and the fourth stabilizing switch element T2-2A of the Q-node stabilizer 240 of the Nth stage ST_N, while the carry signal of the third subsequent stage (e.g., the (N+1)th stage ST_N+1) (e.g., the (N+3)th carry signal IN_N+3) from the current stage can be applied to the third stabilizing switch element T2-1B and the fourth stabilizing switch element T2-2B of the Q-node stabilizer 240 of the (N+1)th stage ST_N+1.

[0143] like Figure 5 As shown, the third input signal S3 can be high and the fourth input signal S4 can be low. However, depending on the situation, the third input signal S3 and the fourth input signal S4 can be inverted on a frame-by-frame basis. When the third input signal S3 and the fourth input signal S4 are inverted, in the next frame, the third input signal S3 can be low and the fourth input signal S4 can be high.

[0144] refer to Figure 3 and Figure 5 Six clock signals CK1 to CK6 with different phases can be sequentially applied to the stage of the scan driver GP.

[0145] As an example, the first clock signal CK1 can be applied to the first stage ST1, the second clock signal CK2 can be applied to the second stage ST2, the third clock signal CK3 can be applied to the third stage ST3, the fourth clock signal CK4 can be applied to the fourth stage ST4, the fifth clock signal CK5 can be applied to the fifth stage ST5, the sixth clock signal CK6 can be applied to the sixth stage ST6, the first clock signal CK1 can be applied to the seventh stage ST7, the second clock signal CK2 can be applied to the eighth stage ST8, the third clock signal CK3 can be applied to the ninth stage ST9, the fourth clock signal CK4 can be applied to the tenth stage ST10, the fifth clock signal CK5 can be applied to the eleventh stage (not shown), and the sixth clock signal CK6 can be applied to the twelfth stage (not shown).

[0146] refer to Figure 4 and Figure 5The Nth level ST_N can operate based on the first clock signal CK1. The first horizontal period t1 to the third horizontal period t3 is the start segment, the fourth horizontal period t4 to the tenth horizontal period t10 is the Q-node high segment where the Q-node QN signal has a high level, the seventh horizontal period t7 is the gate output segment of the output scan signal SC_N, and the eleventh blanking period t11 to the vertical blanking period VBLANK is the hold segment. The vertical blanking period VBLANK starts from the point where the second input signal S2 has a high level, and during the vertical blanking period VBLANK, the first sensor 310 and the second sensor 320 can sense data including data in pixel PX (see [link to relevant documentation]). Figure 1 The characteristics of the switching elements in ).

[0147] Figure 6 This is a diagram. Figure 2 This is an example view of a circuit diagram of some components in the Nth stage ST_N of the scan driver GP used to output the scan signal SC_N.

[0148] For reference only. Figure 6 The circuit diagram is for illustrative purposes only, and Figure 6 The circuit diagram may be a simplified representation of some components associated with the output scan signal SC_N, used for ease of description. Figure 6 In the description, the part with can be omitted. Figure 4 and Figure 5 Identical or repeated content.

[0149] For reference only. Figure 6 The components of the circuit diagram can be... Figure 4 The circuit diagram contains components corresponding to the components, and may include components related to... Figure 4 The circuit diagram contains components that are partially different from or related to the components. Figure 4 The circuit diagram shows the coupling between components, specifically the coupling between different components. However, Figure 6 The circuit diagram is for illustrative purposes only, and Figure 6 The components of the circuit diagram can be based on the display panel 10 (see...). Figure 1 Various changes are made to the specifications, user requirements, and supplier environment.

[0150] Figure 6 The circuit diagram is part of the configuration of the components of the Nth stage ST_N, and may include a first capacitor C1, a second capacitor C2, and a transistor section CCP.

[0151] The first capacitor C1 is... Figure 4 The component corresponding to the sensing capacitor C3A, and the description of the first capacitor C1 can be used... Figure 4 The description of the sensing capacitor C3A is used instead.

[0152] The second capacitor C2 is related to Figure 4 The element corresponding to the gate capacitor C1A, and the description of the second capacitor C2 can be used... Figure 4 The description of the gate capacitor C1A is used instead.

[0153] The transistor portion of the CCP may include Figure 6 The components of the circuit, excluding the first capacitor C1 and the second capacitor C2. As an example, the transistor portion CCP can be defined as some of the components in the Nth stage ST_N of the scan driver GP used to output the scan signal SC_N, including switching elements (e.g., thin-film transistors).

[0154] Figure 6 The circuit may include a first sensor 310, and the first sensor 310 may include a first capacitor C1 and a first sensing transistor Ts1.

[0155] The first sensing transistor Ts1 can be related to Figure 4 The first sensing switch element T24A corresponds to the element. The first sensing transistor Ts1 can be described using... Figure 4 The description of the first sensing switch element T24A is used instead.

[0156] As an example, the first electrode of the first capacitor C1 can be electrically connected to the terminal receiving the sixth input signal S6. The second electrode of the first capacitor C1 can be electrically connected to the gate electrode of the first sensing transistor Ts1. The terminal receiving the sixth input signal S6 can be electrically connected to the source electrode of the first sensing transistor Ts1.

[0157] As an example, Figure 6 The circuit may include a second sensor 320, and the second sensor 320 may include a second-1 sensing transistor Ts2-1 electrically connected to a terminal receiving the second input signal S2. The gate electrode of the second-1 sensing transistor Ts2-1 may be electrically connected to the terminal receiving the second input signal S2. The drain electrode of the second-1 sensing transistor Ts2-1 may be electrically connected to the terminal to which the first low voltage VSS1 is applied.

[0158] As an example, the second sensor 320 may include a second sensing transistor Ts2-2 electrically connected to the second-1 sensing transistor Ts2-1. The source electrode of the second-1 sensing transistor Ts2-1 may be electrically connected to the drain electrode of the second-2 sensing transistor Ts2-2. The gate electrode of the second-2 sensing transistor Ts2-2 may be electrically connected to the second electrode of the first capacitor C1, and may also be electrically connected to the gate electrode of the first sensing transistor Ts1.

[0159] As an example, Figure 6 The circuit may include a scan signal output unit 380, and the scan signal output unit 380 may include a second capacitor C2, a first output transistor Tsc1, and a second output transistor Tsc2.

[0160] The first electrode of the second capacitor C2 can be electrically connected to the gate electrode of the first output transistor Tsc1. The first electrode of the second capacitor C2 can also be electrically connected to the Q node QN. The second electrode of the second capacitor C2 can be electrically connected to the drain electrode of the first output transistor Tsc1. The drain electrode of the first output transistor Tsc1 can also be electrically connected to the output terminal from which the scan signal SC_N is output. The drain electrode of the first output transistor Tsc1 can also be electrically connected to the source electrode of the second output transistor Tsc2. The drain electrode of the second output transistor Tsc2 can be electrically connected to the terminal to which the first low voltage VSS1 is transmitted. As an example, the first low voltage VSS1 can be ground. Depending on the situation, the first low voltage VSS1 can be replaced by a second low voltage VSS2.

[0161] Figure 6 The circuit may also include multiple switching elements (transistors). As an example, Figure 6 The circuit may also include first-1 node transistor Tq1-1 to third-5 node transistor Tq3-5. Figure 6 The circuit may include and Figure 4 The switching elements included in the Q-node charger 330 and Q-node stabilizer 340 correspond to the node transistors.

[0162] As an example, the terminal transmitting the fifth input signal S5 can be electrically connected to the gate electrode of the first-1 node transistor Tq1-1 and the gate electrode of the first-2 node transistor Tq1-2. The drain electrode of the first-1 node transistor Tq1-1 can be electrically connected to the terminal to which the second low voltage VSS2 is transmitted, and the source electrode of the first-1 node transistor Tq1-1 can be electrically connected to the drain electrode of the first-2 node transistor Tq1-2. The source electrode of the first-2 node transistor Tq1-2 can be electrically connected to the Q node QN. As an example, the first-1 node transistor Tq1-1 and the first-2 node transistor Tq1-2 can correspond to those included in... Figure 4 The switching element in the Q-node stabilizer 340.

[0163] As an example, the second-node-1 transistor Tq2-1 can be electrically connected to the second-node-2 transistor Tq2-2, and the source and gate electrodes of the second-node-1 transistor Tq2-1 can be electrically connected to the terminal to which the carry clock signal CR-CK_N is transmitted. The gate electrode of the second-node-1 transistor Tq2-1 can be electrically connected to the gate electrode of the second-node-2 transistor Tq2-2. The drain electrode of the second-node-1 transistor Tq2-1 can be electrically connected to the source electrode of the second-node-2 transistor Tq2-2. As an example, the second-node-1 transistor Tq2-1 and the second-node-2 transistor Tq2-2 can correspond to those included in... Figure 4 The switching element in the Q-node stabilizer 340.

[0164] As an example, the third-1 node transistor Tq3-1 can be electrically connected to the Q node QN. The source electrode of the third-1 node transistor Tq3-1 can be electrically connected to the Q node QN, and the gate electrode of the third-1 node transistor Tq3-1 can be electrically connected to the source electrode of the second-2 sensing transistor. The drain electrode of the third-1 node transistor Tq3-1 can be electrically connected to the terminal to which the second low voltage VSS2 is transmitted.

[0165] As an example, the third-2 node transistor Tq3-2 can be electrically connected to the Q node QN. The source electrode of the third-2 node transistor Tq3-2 can be electrically connected to the drain electrode of the third-5 node transistor Tq3-5, and the drain electrode of the third-2 node transistor Tq3-2 can be electrically connected to the terminal to which the second low voltage VSS2 is delivered. The gate electrode of the third-2 node transistor Tq3-2 can be electrically connected to the third-3 node transistor Tq3-3 and the Q node QN.

[0166] As an example, the third-3 node transistor Tq3-3 can be electrically connected to the Q node QN, the third-2 node transistor Tq3-2, and the third-4 node transistor Tq3-4. The source electrode of the third-3 node transistor Tq3-3 can be electrically connected to the drain electrode of the third-4 node transistor Tq3-4, and the gate electrode of the third-3 node transistor Tq3-3 can be electrically connected to the gate electrode of the third-2 node transistor Tq3-2 and the Q node QN.

[0167] As an example, the third-4 node transistor Tq3-4 can be electrically connected to the third-2 node transistor Tq3-2, the third-3 node transistor Tq3-3, and the third-5 node transistor Tq3-5. The source electrode of the third-4 node transistor Tq3-4 can be electrically connected to the source electrode and the gate electrode of the third-5 node transistor Tq3-5. The source electrode of the third-4 node transistor Tq3-4 can be electrically connected to the terminal to which the sixth input signal S6 is transmitted. The gate electrode of the third-4 node transistor Tq3-4 can be electrically connected to the drain electrode of the third-5 node transistor Tq3-5 and the source electrode of the third-2 node transistor Tq3-2. The drain electrode of the third-4 node transistor Tq3-4 can be electrically connected to the source electrode of the third-3 node transistor Tq3-3.

[0168] As an example, the third-5 node transistor Tq3-5 can be electrically connected to the terminal to which the sixth input signal S6 is transmitted, the third-2 node transistor Tq3-2, and the third-4 node transistor Tq3-4. The source electrode of the third-5 node transistor Tq3-5 can be electrically connected to the gate electrode of the third-5 node transistor Tq3-5 and the Q node QN, and can also be electrically connected to the source electrode of the third-4 node transistor Tq3-4. The drain electrode of the third-5 node transistor Tq3-5 can be electrically connected to the gate electrode of the third-4 node transistor Tq3-4 and the source electrode of the third-2 node transistor Tq3-2.

[0169] Figure 7 It is shown Figure 1 A schematic plan view of an example of region A.

[0170] For reference, region A may include a portion of display area DA and a portion of peripheral area PA. For ease of description, this specification primarily describes display panel 10 (see [link to documentation]). Figure 1 This is an example of a portion of region A, and it can describe only a portion of region A.

[0171] like Figure 7 As shown, the display device according to an embodiment may include a display area DA and a peripheral area PA. To describe the display area DA and the peripheral area PA, a substrate 100 included in the display device (see [reference]) may be described in this specification. Figure 1 It includes the display area DA and the peripheral area PA surrounding the display area DA.

[0172] Pixel PX (see Figure 1The wiring can be located in the display area DA. The peripheral area PA may include a wiring layout area BA and a circuit layout area CA in which a transistor portion CCP is located, wherein the wiring is located in the wiring layout area BA and the transistor portion CCP includes at least one transistor.

[0173] In a plan view, the circuit layout area CA can be located between the display area DA and the wiring layout area BA. As an example, the wiring layout area BA can be located along the edge of the display area DA, and the wiring layout area BA can be located along the outer edge of the circuit layout area CA.

[0174] As an example, the circuit disposed in the circuit layout area CA can be an oxide thin-film transistor (TFT) gate driver circuit for generating or controlling the scan signal transmitted to the pixel. As an example, the circuit disposed in the circuit layout area CA can be a circuit with… Figure 4 Circuit diagram or Figure 6 The circuit diagram.

[0175] As an example, the wiring ML1 to ML3 set in the wiring layout area BA can extend in one direction. In area A, the wiring can extend in the y-axis direction. The wiring set in the wiring layout area BA can extend in the direction of the edge of the display area DA or in the y-axis direction.

[0176] Therefore, in the peripheral area PA, excluding area A, the wiring can extend in a direction intersecting the edge extension direction of the display area DA, or in the x-axis direction. Wiring arranged in the wiring layout area BA can include a sixth input signal S6 (see...). Figure 5 The wiring ML1 (hereinafter referred to as the first wiring) is transmitted to.

[0177] Figure 7 The first capacitor C1 can be Figure 6 The first capacitor C1 or Figure 4 The sensing capacitor C3A. Because Figure 6 The first capacitor C1 is with Figure 4 The concept corresponding to the sensing capacitor C3A is used here for ease of description. Figure 7 The first capacitor C1 is described as equal to Figure 6 The first capacitor C1, and it will be readily understood by those skilled in the art that, Figure 7 The first capacitor C1 is Figure 4 The sensing capacitor C3A.

[0178] Figure 7 The second capacitor C2 can be Figure 6 The second capacitor C2 or Figure 4 The gate capacitor C1A. Because Figure 6 The second capacitor C2 is with Figure 4 The concept corresponding to the gate capacitor C1A, therefore, for ease of description, Figure 7 The second capacitor C2 is described as equal to Figure 6 The second capacitor C2, and it will be readily understood by those skilled in the art that, Figure 7 The second capacitor C2 is Figure 4 The gate capacitor C1A.

[0179] The transistor section CCP can be located within the circuit layout area CA. In a plan view, the transistor section CCP can be positioned between the first capacitor C1 and the second capacitor C2. The transistor section CCP may include multiple transistors, and these multiple transistors can be configured for the scan driver GP (see...). Figure 2 The circuit consists of multiple transistors, which can be configured in various ways depending on their function and role. Although examples of transistor configurations for the CCP section can be derived from... Figure 4 Circuit diagram or Figure 6 The circuit diagram is used for setup, but this is only an example to help understand, and the implementation is not limited to this.

[0180] like Figure 7 As shown, the first capacitor C1 can be disposed in the wiring layout area BA instead of the circuit layout area CA, and the transistor portion CCP can be disposed in the circuit layout area CA. Therefore, it is readily understood that the transistor portion CCP is included in... Figure 4 The first sensing switch element T24A or Figure 6 The first sensing transistor Ts1 is located in the circuit layout area CA.

[0181] The transistor portion CCP and the first capacitor C1 can be separated from each other in a plan view. The transistor portion CCP and the first capacitor C1 can be located at physically separate positions. Therefore, included in the transistor portion CCP... Figure 4 The first sensing switch element T24A or Figure 6 The first sensing transistor Ts1 can be separated from the first capacitor C1 in the planar diagram.

[0182] The first capacitor C1 may include a first upper electrode and a first lower electrode that is perpendicularly separated from the first upper electrode (e.g., separated from the first upper electrode in a third direction (z-axis direction)). A first insulating layer (not shown) may be disposed between the first upper electrode and the first lower electrode. The first insulating layer (not shown) may include a dielectric that insulates between the first upper electrode and the first lower electrode.

[0183] The first upper electrode of the first capacitor C1 can be the second electrode of the sensing capacitor C3A. The first lower electrode of the first capacitor C1 can be the first electrode of the sensing capacitor C3A. That is, the first electrode and the second electrode of the sensing capacitor C3A can overlap each other perpendicularly, and the first electrode can be disposed below the second electrode.

[0184] As an example, a portion of the first wiring ML1 can be separated perpendicularly from the second electrode.

[0185] like Figure 7 As shown, one electrode of the first capacitor C1 may be the first wiring ML1 or a portion of the first wiring ML1 that transmits the sixth input signal S6. The other electrode of the first capacitor C1 may be a metal electrode that overlaps with the first wiring ML1 in the plan view.

[0186] As an example, the first upper electrode of the first capacitor C1 may be a metal electrode that overlaps with the first wiring ML1 in the plan view, and the first lower electrode of the first capacitor C1 may be the first wiring ML1 or a part of the first wiring ML1 that transmits the sixth input signal S6.

[0187] As an example, the second electrode of the first capacitor C1 may include a first portion (e.g., a metal electrode) that overlaps with the first wiring ML1 in a plan view. The second electrode of the first capacitor C1 may also include a second portion that connects the first portion to the gate electrode of the sensing transistor, and the second portion may be connected to the first cover sub-wiring MSLc1.

[0188] As an example, the first portion may extend in the direction in which the first wiring ML1 extends, and the second portion may extend in a direction that intersects the direction in which the first wiring ML1 extends.

[0189] As an example, the width of the first part (e.g., the width in the direction in which the second part extends or the width in the x-axis direction) can be greater than the width of the second part (e.g., the width in the direction in which the first part extends or the width in the y-axis direction).

[0190] As an example, depending on the situation, one electrode of the first capacitor C1 (e.g., the first electrode) may be at least a portion of the wiring that transmits the scan input voltage. The other electrode of the first capacitor C1 (e.g., the second electrode) may be a metal electrode configured to overlap with the wiring that transmits the scan input voltage in a planar diagram. The scan input voltage may refer to the voltage that drives the scan driver. The scan input voltage may be supplied by the power module 1500 described herein (see [link to document]). Figure 13 The controller 1120-1, generated and described herein (see [link to controller 1120-1]), is also described herein. Figure 13It is applied under the control of ).

[0191] The first cover sub-wiring MSLc1 may include a conductive material. The first cover sub-wiring MSLc1 may be electrically connected to a first upper electrode or a second electrode of a first capacitor C1. The first cover sub-wiring MSLc1 may also electrically connect a transistor portion CCP to the first upper electrode or a second electrode of the first capacitor C1.

[0192] The first cover sub-routing MSLc1 may intersect with the first wiring ML1 to the third wiring ML3 in the plan view. The first cover sub-routing MSLc1 may be located on the first wiring ML1 to the third wiring ML3. The first cover sub-routing MSLc1 may extend in a direction that intersects the extension direction of the first wiring ML1. As an example, in region A, the first cover sub-routing MSLc1 may extend in the x-axis direction.

[0193] The second capacitor C2 can be disposed in the peripheral area PA, and specifically, in the circuit layout area CA. In the plan view, the transistor portion CCP can be disposed between the second capacitor C2 and the first capacitor C1. In the plan view, the second capacitor C2 and the transistor portion CCP can be disposed between the first capacitor C1 and the display area DA. In the plan view, the first capacitor C1 can be disposed further away from the display area DA than the second capacitor C2 and the transistor portion CCP.

[0194] The second capacitor C2 may include a second upper electrode and a second lower electrode perpendicularly separated from the second upper electrode. A second insulating layer (not shown) may be disposed between the second upper electrode and the second lower electrode. The second insulating layer (not shown) may include a dielectric that insulates between the second upper electrode and the second lower electrode.

[0195] The second cover sub-wiring MSLc2 may include conductive material. The second cover sub-wiring MSLc2 may be electrically connected to the second capacitor C2. The second cover sub-wiring MSLc2 may also electrically connect the transistor portion CCP to the second capacitor C2.

[0196] The second cover sub-routing MSLc2 can extend in a direction that intersects the direction in which the first routing ML1 extends. As an example, in region A, the second cover sub-routing MSLc2 can extend in the x-axis direction.

[0197] The first wiring ML1 may include a conductive material. The first wiring ML1 may be disposed below the first sub-wiring MSL1 described herein. In a plan view, the direction in which the first wiring ML1 extends may intersect the direction in which the first sub-wiring MSL1 extends. As an example, in region A, the first wiring ML1 may extend in the y-axis direction. In a cross-sectional view, at least one distinct layer may be disposed between the first wiring ML1 and the first sub-wiring MSL1.

[0198] A first via TH1 may be formed in at least one different layer between the first wiring ML1 and the first sub-wiring MSL1. The first wiring ML1 may be electrically connected to the first sub-wiring MSL1 through the first via TH1.

[0199] The first sub-wiring MSL1 may include conductive material. The first sub-wiring MSL1 can electrically connect the first wiring ML1 to the transistor portion CCP.

[0200] The first sub-routing MSL1 can extend in a direction intersecting the direction of the first routing ML1. As an example, in region A, the first sub-routing MSL1 can extend in the x-axis direction. The first sub-routing MSL1 and the first covering sub-routing MSLc1 can be arranged approximately parallel to each other in a plan view.

[0201] In the plan view, the second wiring ML2 can be positioned around the first wiring ML1 (adjacent to and parallel to the first wiring ML1). The second wiring ML2 can transmit another input signal besides the sixth input signal S6 (e.g., the first input signal S1 (see...)). Figure 5 ) to the fifth input signal S5 (see Figure 5 (One of them). To transmit different input signals, the second wiring ML2 can be electrically connected to... Figure 2 The controller CP.

[0202] The second wiring ML2 may include a conductive material. The second wiring ML2 may be disposed below the second sub-wiring MSL2 described herein. In a plan view, the direction in which the second wiring ML2 extends may intersect the direction in which the second sub-wiring MSL2 extends. As an example, in region A, the second wiring ML2 may extend in the y-axis direction. In a cross-sectional view, at least one distinct layer may be disposed between the second wiring ML2 and the second sub-wiring MSL2.

[0203] The second via TH2 can be formed in at least one different layer between the second wiring ML2 and the second sub-wiring MSL2. The second wiring ML2 can be electrically connected to the second sub-wiring MSL2 through the second via TH2. The second wiring ML2 can be in direct contact with the second sub-wiring MSL2 in a direction perpendicular to the substrate 100 (or in a third direction (z-axis direction)) through the second via TH2.

[0204] The second sub-wiring MSL2 may include conductive material. The second sub-wiring MSL2 can be electrically connected to the second wiring ML2 through the second via TH2. The second sub-wiring MSL2 can electrically connect the second wiring ML2 to the transistor portion CCP.

[0205] The second sub-routing MSL2 can extend in a direction intersecting the direction in which the second sub-routing ML2 extends. As an example, in region A, the second sub-routing MSL2 can extend in the x-axis direction. The second sub-routing MSL2 and the second covering sub-routing MSLc2 can be positioned approximately parallel to each other in a plan view.

[0206] In the plan view, the third wiring ML3 can be positioned around the second wiring ML2 (adjacent to and parallel to the second wiring ML2). In the plan view, the second wiring ML2 can be positioned between the first wiring ML1 and the third wiring ML3. The third wiring ML3 can transmit an input signal other than the sixth input signal S6 (e.g., one of the first input signals S1 to the fifth input signal S5). To transmit different input signals, the third wiring ML3 can be electrically connected to... Figure 2 The controller CP.

[0207] The third wiring ML3 may include a conductive material. The third wiring ML3 may be disposed below the third sub-wiring MSL3 described herein. In a plan view, the direction in which the third wiring ML3 extends may intersect the direction in which the third sub-wiring MSL3 extends. As an example, in region A, the third wiring ML3 may extend in the y-axis direction. As an example, the first wiring ML1 to the third wiring ML3 may be disposed parallel to each other in a plan view of region A. In a cross-sectional view, at least one distinct layer may be disposed between the third wiring ML3 and the third sub-wiring MSL3.

[0208] A third via TH3 may be formed in at least one different layer between the third wiring ML3 and the third sub-wiring MSL3. The third wiring ML3 may be electrically connected to the third sub-wiring MSL3 through the third via TH3. The third wiring ML3 may be in direct contact with the third sub-wiring MSL3 in a direction perpendicular to the substrate 100 through the third via TH3.

[0209] Although first wiring ML1 to third wiring ML3 and first sub-wiring MSL1 to third sub-wiring MSL3 are described for ease of description, additional wiring may be provided where applicable or suitable in relation to the function of the display device.

[0210] refer to Figure 1 , Figure 2 , Figure 4 , Figure 6and Figure 7 The scan driver GP can be disposed in the peripheral region PA and electrically connected to the pixel PX (or pixel circuitry including elements forming the pixel PX) of the pixel portion PP. The scan driver GP may include a sensing transistor Ts1, a first wiring ML1 electrically connected to the source electrode of the sensing transistor Ts1 (or an input terminal (e.g., an input terminal for transmitting a sixth input signal S6)), and wiring electrically connected to the source electrode and gate electrode of the sensing transistor Ts1. Figure 4 The sensing capacitor C3A (or Figure 6 The first capacitor C1).

[0211] The controller CP can transmit control signals to the pixel PX (or pixel circuit) and the scan driver GP, respectively. The control signals transmitted by the controller CP can refer to the aforementioned input signals (e.g., Figure 2 The gate drive control signal GCS and Figure 4 (Input signals S1 to S6, etc.)

[0212] Figure 4 The sensing capacitor C3A or Figure 6 The first capacitor C1 can be placed in the wiring layout area BA, and the sensing transistor Ts1 can be placed in the circuit layout area CA. Since the sensing transistor Ts1 is a component included in the transistor section CCP, it is obvious that the sensing transistor Ts1 is placed in the circuit layout area CA.

[0213] As an example, the first wiring ML1 can be electrically connected to the controller CP and can receive control signals from the controller CP to transmit the control signals to the sensing transistor Ts1.

[0214] As an example, a portion of the first wiring ML1 may overlap with the second electrode of the first capacitor C1 in a plan view. As an example, an insulating layer (not shown) may be disposed between the first and second electrodes of the first capacitor C1, and the insulating layer (not shown) may include an insulating material.

[0215] As an example, in a plan view, the first capacitor C1 can be in a first direction (e.g., Figure 7 The first wiring ML1 is separated from the sensing transistor Ts1 in the x-axis direction. As an example, the first wiring ML1 can be in a second direction (e.g., intersecting the first direction) in the x-axis direction. Figure 7 It extends along the y-axis (in the diagram). The intersection of the two directions can refer to the intersection observed in a plan view.

[0216] Figure 8 It is shown Figure 1 A schematic plan view of an example of region A.

[0217] like Figure 8 As shown, the diagram discloses a first transistor portion CCP1 corresponding to the Nth stage ST_N, a first -1 capacitor C1-1, a second -1 capacitor C2-1, a first -1 cover sub-wiring MSLc1-1, a first -1 sub-wiring MSL1-1, a second -1 sub-wiring MSL2-1, and a third -1 sub-wiring MSL3-1. For ease of description, only some components are shown, and additional components may be further provided where applicable or suitable in relation to the function of the display device.

[0218] The first transistor part CCP1 can be related to... Figure 7 The transistor section CCP corresponds to the component. The first transistor section CCP1 of the Nth stage ST_N can be used to perform operations related to... Figure 7 The transistor part of the CCP has the same function as the component.

[0219] The first capacitor C1-1 can be connected to... Figure 7 The component corresponding to the first capacitor C1. The first-1 capacitor C1-1 of the Nth stage ST_N can be used to perform the operation with Figure 7 The first capacitor C1 has the same function as the component.

[0220] The second capacitor C2-1 can be connected to... Figure 7 The component corresponding to the second capacitor C2. The second-1 capacitor C2-1 of the Nth stage ST_N can be used to perform the operation with Figure 7 The second capacitor C2 has the same function as the component.

[0221] The first-1 cover sub-routing MSLc1-1, the first-1 sub-routing MSL1-1, the second-1 sub-routing MSL2-1, and the third-1 sub-routing MSL3-1 can be respectively connected to... Figure 7 The components corresponding to the first cover sub-routing MSLc1, the first sub-routing MSL1, the second sub-routing MSL2, and the third sub-routing MSL3. The first-1 cover sub-routing MSLc1-1, the first-1 sub-routing MSL1-1, the second-1 sub-routing MSL2-1, and the third-1 sub-routing MSL3-1 of the Nth level ST_N can respectively execute with... Figure 7 The first sub-coverage wiring MSLc1, the first sub-wiring MSL1, the second sub-wiring MSL2, and the third sub-wiring MSL3 are components that have the same function.

[0222] Therefore, the description of the first transistor portion CCP1, the first -1 capacitor C1-1, the second -1 capacitor C2-1, the first -1 cover sub-wiring MSLc1-1, the first -1 sub-wiring MSL1-1, the second -1 sub-wiring MSL2-1, and the third -1 sub-wiring MSL3-1 corresponding to the Nth stage ST_N can be used as follows: Figure 7 The description is replaced with [the description].

[0223] like Figure 8 As shown, the second transistor portion CCP2 corresponding to the (N+1)th stage ST_N+1, the first -2 capacitor C1-2, the second -2 capacitor C2-2, the first -2 cover sub-wiring MSLc1-2, the first -2 sub-wiring MSL1-2, the second -2 sub-wiring MSL2-2, and the third -2 sub-wiring MSL3-2 are disclosed. For ease of description, only some components are shown, and additional components may be further provided where applicable or suitable in relation to the function of the display device.

[0224] The second transistor part CCP2 can be related to... Figure 7 The transistor section CCP corresponds to the component. The second transistor section CCP2 of stage (N+1) ST_N+1 can be used to perform operations related to... Figure 7 The transistor part of the CCP has the same function as the component.

[0225] The first capacitor C1-2 can be connected to... Figure 7 The component corresponding to the first capacitor C1. The first -2 capacitor C1-2 of the (N+1)th stage ST_N+1 can be used to perform the operation with Figure 7 The first capacitor C1 has the same function as the component.

[0226] The second capacitor C2-2 can be... Figure 7 The component corresponding to the second capacitor C2. The second capacitor C2-2 of the (N+1)th stage ST_N+1 can be used to perform the function of... Figure 7 The second capacitor C2 has the same function as the component.

[0227] The first-2 cover sub-routing MSLc1-2, the first-2 sub-routing MSL1-2, the second-2 sub-routing MSL2-2, and the third-2 sub-routing MSL3-2 can be respectively connected with... Figure 7 The components corresponding to the first sub-coverage routing MSLc1, the first sub-routing MSL1, the second sub-routing MSL2, and the third sub-routing MSL3.

[0228] The first -2 cover sub-routing MSLc1-2, the first -2 sub-routing MSL1-2, the second -2 sub-routing MSL2-2, and the third -2 sub-routing MSL3-2 of the (N+1)th level ST_N+1 can respectively execute and Figure 7 The first sub-coverage wiring MSLc1, the first sub-wiring MSL1, the second sub-wiring MSL2, and the third sub-wiring MSL3 are components that have the same function.

[0229] Therefore, the description of the second transistor portion CCP2, the first -2 capacitor C1-2, the second -2 capacitor C2-2, the first -2 cover sub-wiring MSLc1-2, the first -2 sub-wiring MSL1-2, the second -2 sub-wiring MSL2-2, and the third -2 sub-wiring MSL3-2 corresponding to the (N+1)th stage ST_N+1 can be used as follows: Figure 7 The description is replaced with [the description].

[0230] Figure 9 yes Figure 8 A schematic floor plan of a specific example.

[0231] For reference, the display area DA (see...) Figure 8 ) can be set Figure 9 The x-axis (rightward direction) is shown in the diagram. For ease of description, the illustration of the display area DA is omitted. Although not shown in the accompanying drawings, the circuit layout area CA can be positioned in the plan view between the wiring layout area BA and the display area DA.

[0232] like Figure 9 As shown, each of the first transistor portion CCP1 and the second transistor portion CCP2 may include a plurality of switching elements (e.g., a plurality of transistors). The plurality of switching elements included in each of the first transistor portion CCP1 and the second transistor portion CCP2 may be based on... Figure 4 or Figure 6 The circuit diagram shows transistors. For ease of description, Figure 9 The description of multiple switching elements can be used as follows: Figure 4 or Figure 6 The circuit diagram description is used instead.

[0233] like Figure 9 As shown, in the circuit layout area CA, a first blank space EA1 is observed formed in the first transistor portion CCP1 (or around the first transistor portion CCP1), and a second blank space EA2 is formed in the second transistor portion CCP2 (or around the second transistor portion CCP2). The first blank space EA1 and the second blank space EA2 may refer to the blank spaces formed when the first-1 capacitor C1-1 moves to the wiring layout area BA.

[0234] For ease of description and in accordance with the description herein Figure 10 In comparison, Figure 9 The first blank space EA1 is shown. It will be apparent that when the first blank space EA1 is utilized, the area occupied by the first transistor portion CCP1 can be reduced. In other words, multiple switching elements included in the first transistor portion CCP1 can be rearranged by utilizing the first blank space EA1, and therefore, the display panel 10 (see [reference]) can be reduced in size. Figure 1 The area of ​​the peripheral area PA (or circuit layout area CA) of the display panel 10 is reduced. Because the area of ​​the peripheral area PA (or circuit layout area CA) of the display panel 10 is reduced, the area of ​​the bezel of the display panel 10 can be reduced.

[0235] For ease of description and comparison Figure 10 In comparison, Figure 9 The second blank space EA2 is shown. It will be apparent that when the second blank space EA2 is utilized, the area occupied by the second transistor portion CCP2 can be reduced. In other words, multiple switching elements included in the second transistor portion CCP2 can be rearranged by utilizing the second blank space EA2, and therefore, the area of ​​the peripheral area PA (or circuit arrangement area CA) of the display panel 10 can be reduced. Because the area of ​​the peripheral area PA (or circuit arrangement area CA) of the display panel 10 is reduced, the area of ​​the bezel of the display panel 10 can be reduced.

[0236] Figure 10 This is a schematic plan view of an example of the circuit layout area of ​​a display device based on a comparative example.

[0237] like Figure 10 As shown, when capacitors 1-1 (C1-1) and 1-2 (C1-2) are located in the circuit layout area CA, no generation occurs. Figure 9 The first blank space EA1 and the second blank space EA2. Therefore, it is revealed that, with Figure 9 Compared to the example, Figure 10 The example does not make efficient use of space.

[0238] Figure 11 yes Figure 1 A schematic equivalent circuit diagram of the pixel PX of the display device.

[0239] like Figure 11 As shown, each pixel PX includes a pixel circuit PC and an organic light-emitting element OLED connected to the pixel circuit PC, wherein the pixel circuit PC is connected to the scan line SL and the data line DL.

[0240] As an example, the pixel circuit PC includes a driving thin-film transistor Td, a switching thin-film transistor Ts, and a storage capacitor Cst. The switching thin-film transistor Ts is connected to the scan line SL and the data line DL, and is configured to transmit a data signal Dm to the driving thin-film transistor Td according to the scan signal Sn, wherein the data signal Dm is input through the data line DL and the scan signal Sn is input through the scan line SL.

[0241] For reference, the scan signal Sn can be Figure 4 and Figure 6 The scan signal SC_N. The scan signal Sn can be composed of... Figure 4 or Figure 6 The signal generated by the circuit. The scan signal Sn can be generated by... Figure 2 The scan signal Sn is generated by the scan driver GP. Figure 4 or Figure 6 The circuit is based on Figure 2 The signal is generated by the input signal generated by the controller CP.

[0242] As an example, the storage capacitor Cst is connected to the switching thin-film transistor Ts and the drive voltage line PL, and is configured to store a voltage corresponding to the difference between the voltage delivered from the switching thin-film transistor Ts and the first power voltage ELVDD (or drive voltage) supplied to the drive voltage line PL.

[0243] As an example, the driving thin-film transistor Td can be connected to the driving voltage line PL and the storage capacitor Cst, and is configured to control the driving current according to the voltage stored in the storage capacitor Cst, the driving current flowing from the driving voltage line PL to the organic light-emitting element OLED. The organic light-emitting element OLED can be configured to emit light with a preset brightness corresponding to the driving current.

[0244] An organic light-emitting element (OLED) can receive a second electrical voltage ELVSS (or a common voltage). As an example, an OLED can receive the second electrical voltage ELVSS (or common voltage) through a counter electrode (cathode) and emit light with a preset brightness based on the driving current corresponding to the voltage difference between the first electrical voltage ELVDD (or driving voltage) and the second electrical voltage ELVSS (or common voltage).

[0245] Although reference Figure 11 The pixel circuit PC is described as including two thin-film transistors and one storage capacitor, but this disclosure is not limited thereto. As an example, the pixel circuit PC may include not only two or more storage capacitors, but also three or more thin-film transistors.

[0246] Figure 12 yes Figure 1 A schematic cross-sectional view of a portion of a display device.

[0247] As described herein, the substrate 100 may include a display area DA (see [link to document]). Figure 1 ) and the peripheral area PA outside the display area DA (see Figure 1 The corresponding region. The substrate 100 may include various flexible or bendable materials. As an example, the substrate 100 may include glass, metal, or polymer resin. In some aspects, the substrate 100 may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyaryl compounds, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may have a multilayer structure comprising two layers each containing a polymer resin and a barrier layer between the two layers containing an inorganic material (such as silicon oxide, silicon nitride, and silicon oxynitride). However, various modifications can be made.

[0248] A buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 can prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and serve as a barrier layer and / or shielding layer for surface planarization. The buffer layer 101 may comprise silicon oxide, silicon nitride, or silicon oxynitride. In some aspects, the buffer layer 101 can support uniform crystallization of the semiconductor layer 110 by adjusting the rate at which heat is provided during the crystallization process of forming the semiconductor layer 110.

[0249] Semiconductor layer 110 may be disposed on buffer layer 101. Semiconductor layer 110 may include polysilicon and includes a channel region, a source region, and a drain region, wherein the channel region is undoped, and the source and drain regions are located on opposite sides of the channel region and are doped with impurities. Here, the impurities may vary depending on the type of thin-film transistor and may be N-type or P-type impurities. Although not shown in the figures, the display device according to the embodiment may further include another semiconductor layer disposed on a different layer.

[0250] A gate insulating layer 102 may be disposed on the semiconductor layer 110. The gate insulating layer 102 may be an element for ensuring insulation between the semiconductor layer 110 and the gate layer 120. The gate insulating layer 102 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and is disposed between the semiconductor layer 110 and the gate layer 120. In some aspects, the gate insulating layer 102 may have a shape corresponding to the entire surface of the substrate 100 and a structure in which contact holes are formed in predetermined portions of the gate insulating layer 102. As used herein, insulating layers comprising inorganic materials can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This also applies to the embodiments and modifications thereof described below.

[0251] Gate layer 120 may be disposed on gate insulating layer 102. Gate layer 120 may be disposed at a position perpendicular to semiconductor layer 110, and may include at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu). Gate layer 120 is described in detail herein. Although not shown in the accompanying drawings, the display device according to embodiments may also include another gate layer disposed on a different layer.

[0252] An interlayer insulating layer 103 may be disposed on the gate layer 120. The interlayer insulating layer 103 may cover the gate layer 120. The interlayer insulating layer 103 may include an inorganic material. As an example, the interlayer insulating layer 103 may include an oxide (such as a metal oxide) or a nitride (such as a metal nitride), and the inorganic material may specifically include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x (It can be ZnO or ZnO2, etc.). In this embodiment, the interlayer insulating layer 103 may include SiO2. x / SiN y or SiN x / SiO y The dual structure.

[0253] The conductive layer 130 may be disposed on the interlayer insulating layer 103. The conductive layer 130 may be used as an electrode connected to the source / drain region of the semiconductor layer 110 through vias included in the interlayer insulating layer 103.

[0254] The conductive layer 130 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As an example, the conductive layer 130 may include a Ti layer, an Al layer, and / or a Cu layer. As an example, the conductive layer 130 may include a three-layer structure of Ti layer / Al layer / Ti layer.

[0255] Although not shown in the accompanying drawings, the display device according to an embodiment may further include another conductive layer disposed on another layer. For example, the other conductive layer may serve as a wiring layer including wiring. The other conductive layer may comprise the same material as conductive layer 130 and have the same layer structure as conductive layer 130.

[0256] An organic insulating layer 104 may be disposed on the conductive layer 130. The organic insulating layer 104 may cover the upper surface of the conductive layer 130 and may be an organic insulating layer having a generally flat upper surface to serve as a planarization layer. The organic insulating layer 104 may include organic materials, such as, for example, acrylic resins, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The organic insulating layer 104 may comprise a single layer or multiple layers. However, various modifications can be made.

[0257] Although not shown in the accompanying drawings, the display device according to an embodiment may further include another organic insulating layer disposed on a different layer. This other organic insulating layer may be disposed on another conductive layer and may cover the upper surface of the other conductive layer to serve as a planarization layer. The other organic insulating layer may comprise the same material as organic insulating layer 104 and have the same layer structure as organic insulating layer 104.

[0258] The pixel electrode 140 may be disposed on the organic insulating layer 104. Alternatively, the pixel electrode 140 may be disposed on another organic insulating layer. However, for ease of description, it will be assumed that the pixel electrode 140 is disposed on the organic insulating layer 104.

[0259] The pixel electrode 140 can be connected to the conductive layer 130 through contact holes formed in the organic insulating layer 104. A display element can be disposed on the pixel electrode 140. An organic light-emitting element (OLED) can be used as the display element (see [link]). Figure 11That is, the organic light-emitting element (OLED) can be disposed on, for example, a pixel electrode 140. The pixel electrode 140 may include a light-transmitting conductive layer and / or a reflective layer, wherein the light-transmitting conductive layer includes a light-transmitting conductive oxide such as In₂O₃ or IZO, and the reflective layer includes a metal such as Al or Ag. As an example, the pixel electrode 140 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0260] A pixel defining layer 105 may be disposed on the organic insulating layer 104 and configured such that the pixel defining layer 105 covers the edge of the pixel electrode 140. As an example, the pixel defining layer 105 may cover the edge of the pixel electrode 140. The pixel defining layer 105 includes an opening corresponding to a pixel, and the opening may be formed to at least expose the central portion of the pixel electrode 140. The opening may be defined by the pixel defining layer 105.

[0261] The pixel defining layer 105 may include organic materials, such as polyimide or hexamethyldisiloxane (HMDSO). In some aspects, spacers (not shown) may be disposed on the pixel defining layer 105. The spacers (not shown) may be arranged in the peripheral region PA, or the spacers (not shown) may be arranged in the display region DA. The spacers (not shown) may be configured to prevent damage to the organic light-emitting element OLED due to mask sagging during the mask manufacturing process. The spacers (not shown) may include organic insulating materials and may comprise a single layer or multiple layers.

[0262] Intermediate layer 150 and opposite electrode 160 may be disposed in the opening. Intermediate layer 150 may comprise a low molecular weight material or a high molecular weight material. When intermediate layer 150 comprises a low molecular weight material, intermediate layer 150 may comprise a hole injection layer, a hole transport layer, an emitter layer, an electron transport layer, and / or an electron injection layer. When intermediate layer 150 comprises a high molecular weight material, intermediate layer 150 may typically have a structure including a hole transport layer and an emitter layer.

[0263] The structure of the intermediate layer 150 is not limited to this and can have various structures. As an example, at least one of the layers constituting the intermediate layer 150 can be integrally formed like the opposing electrode 160. In another embodiment, the intermediate layer 150 may include layers patterned to correspond to each of the plurality of pixel electrodes 140.

[0264] The opposing electrode 160 may include a light-transmitting conductive layer, which may include a light-transmitting conductive oxide, such as ITO, In₂O₃, or IZO. The pixel electrode 140 serves as the anode, and the opposing electrode 160 serves as the cathode. The polarity of the electrodes can be reversed.

[0265] The relative electrode 160 can be disposed on the upper part of the display area DA and cover the entire surface of the display area DA. That is, the relative electrode 160 can be integrally formed such that the relative electrode 160 covers multiple pixels. The relative electrode 160 can be in electrical contact with a common power line disposed in the peripheral area PA. As an example, the relative electrode 160 can extend to a partition wall (not shown).

[0266] The thin-film encapsulation layer (TFE) can completely cover the display area (DA). The TFE can extend to the peripheral area (PA), such that the TFE covers at least a portion of the peripheral area (PA). The TFE can extend outside the common power line.

[0267] The thin-film encapsulation layer TFE may include a first inorganic encapsulation layer 311, a second inorganic encapsulation layer 331, and an organic encapsulation layer 321 between the first inorganic encapsulation layer 311 and the second inorganic encapsulation layer 331. The first inorganic encapsulation layer 311 and the second inorganic encapsulation layer 331 may include at least one inorganic material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 311 and the second inorganic encapsulation layer 331 may include a single layer or multiple layers comprising the above materials. The first inorganic encapsulation layer 311 and the second inorganic encapsulation layer 331 may include the same material or different materials.

[0268] The thickness of the first inorganic encapsulation layer 311 may be different from the thickness of the second inorganic encapsulation layer 331. The thickness of the first inorganic encapsulation layer 311 may be greater than the thickness of the second inorganic encapsulation layer 331. Optionally, the thickness of the second inorganic encapsulation layer 331 may be greater than the thickness of the first inorganic encapsulation layer 311, or the thickness of the first inorganic encapsulation layer 311 may be the same as the thickness of the second inorganic encapsulation layer 331.

[0269] The organic encapsulation layer 321 may include monomeric or polymeric materials. Polymeric materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. As an example, the organic encapsulation layer 321 may include acrylates.

[0270] A partition wall (not shown) may be provided in the peripheral region PA of the substrate 100. As an example, the partition wall (not shown) may be configured to surround the display region DA and may prevent the organic encapsulation layer 321 of the thin-film encapsulation layer TFE from overflowing to the outside of the substrate 100.

[0271] In another embodiment, the thin-film encapsulation layer TFE can be replaced by a cover member that completely covers the display area DA. The cover member can be configured to cover not only the display area DA but also at least a portion of the peripheral area PA. The cover member may include a rigid member (e.g., glass). When the thin-film encapsulation layer TFE is replaced by a cover member, the separator wall (not shown) can be omitted. Depending on the circumstances, a transparent filler may be disposed between the cover member and the opposing electrode 160.

[0272] Figure 13 This is a block diagram of an electronic device 1010 according to an embodiment.

[0273] Electronic device 1010 can output various information through display module 1400 within the operating system. In an example where processor 1100 executes an application stored in memory 1200, display module 1400 provides application information to the user through display panel 10.

[0274] Processor 1100 receives external input via input module 1300 or sensor module 1610 and executes the application corresponding to the external input. For example, if the user selects a camera icon displayed on display panel 10, processor 1100 receives user input via input sensor 1610-2 and activates camera module 1710. Processor 1100 then transmits image data corresponding to the captured image obtained by camera module 1710 to display module 1400. Display module 1400 can display the image corresponding to the captured image via display panel 10.

[0275] In another example, when personal information authentication is performed by the display module 1400, the fingerprint sensor 1610-1 obtains the input fingerprint information as input data. The processor 1100 compares the input data obtained by the fingerprint sensor 1610-1 with the authentication data stored in the memory 1200, and executes the application based on the comparison result. The display module 1400 can display the executed information through the display panel 10 according to the application logic.

[0276] As another example, when a music stream icon is selected to be displayed in display module 1400, processor 1100 obtains user input via input sensor 1610-2 and activates the music stream application stored in memory 1200. In the example where a music execution command is entered in the music stream application, processor 1100 activates sound output module 1630 and provides the user with sound information matching the music execution command.

[0277] The operation of electronic device 1010 has been briefly described above. The construction of electronic device 1010 is described in detail below. Some components of electronic device 1010 described herein may be integrated and provided as a single construction, or a single construction may be divided into two or more constructions and provided.

[0278] refer to Figure 13 Electronic device 1010 can communicate with external electronic device 1020 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In an embodiment, electronic device 1010 may include processor 1100, memory 1200, input module 1300, display module 1400, power module 1500, built-in module 1600, and external module 1700. In an embodiment, at least one of the above-mentioned components may be omitted from electronic device 1010, or one or more other components may be added. In an embodiment, some components (e.g., sensor module 1610, antenna module 1620, or sound output module 1630) may be integrated into another component (e.g., display module 1400).

[0279] Processor 1100 may run software to control at least one other element (e.g., hardware or software element) connected to electronic device 1010 and perform various data processing or operations. In an embodiment, as at least part of the data processing or operation, processor 1100 may store commands or data received from another element (e.g., input module 1300, sensor module 1610, or communication module 1730) in volatile memory 1210 and process the commands and data stored in volatile memory 1210, and the resulting data may be stored in non-volatile memory 1220.

[0280] Processor 1100 may include a main processor 1110 and an auxiliary processor 1120. Main processor 1110 may include at least one of a central processing unit (CPU) 1111 and an application processor (AP). Main processor 1110 may also include at least one of a graphics processing unit (GPU) 1112, a communication processor (CP), and an image signal processor (ISP). Main processor 1110 may also include a neural processing unit (NPU) 1113. NPU 1113 is a processor specifically designed to process artificial intelligence models, which can be created through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks (artificial neural networks). The artificial neural network may be one or a combination of two or more of deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), and deep Q-networks, but is not limited to the examples described herein. In addition to hardware architecture, the artificial intelligence model may additionally or optionally include software architecture. At least two of the processing units and processors described herein can be implemented as a single integrated configuration (e.g., a single chip), or each can be implemented as an independent configuration (e.g., multiple chips).

[0281] The auxiliary processor 1120 may include a controller 1120-1. The controller 1120-1 may include interface conversion circuitry and timing control circuitry. The controller 1120-1 receives image signals from the main processor 1110, converts the data format of the image signals to match the interface specifications of the display module 1400, and outputs the image data. The controller 1120-1 may output various control signals that support driving the display module 1400.

[0282] The auxiliary processor 1120 may also include a controller 1120-1, a data conversion circuit 1120-2, a gamma correction circuit 1120-3, and a rendering circuit 1120-4. The data conversion circuit 1120-2 can receive image data from the controller 1120-1, compensate the image data according to the characteristics of the electronic device 1010 or user settings to display the image at the desired brightness, or convert the image data to reduce power consumption or compensate for image retention. The gamma correction circuit 1120-3 can convert image data or gamma reference voltage, etc., so that the image displayed by the electronic device 1010 has the desired gamma characteristics. The rendering circuit 1120-4 can receive image data from the controller 1120-1 and render the image data by taking into account the pixel arrangement of the display panel 10 applied to the electronic device 1010. At least one of the data conversion circuit 1120-2, the gamma correction circuit 1120-3, and the rendering circuit 1120-4 can be integrated into another component (e.g., the main processor 1110 or the controller 1120-1). At least one of the data conversion circuit 1120-2, the gamma correction circuit 1120-3, and the rendering circuit 1120-4 can be integrated into the data driver DP described herein.

[0283] The memory 1200 may store various data used by at least one element of the electronic device 1010 (e.g., processor 1100 or sensor module 1610), as well as input or output data regarding commands associated therewith. The memory 1200 may include at least one of volatile memory 1210 and non-volatile memory 1220.

[0284] The input module 1300 can receive commands or data from outside the electronic device 1010 (e.g., from a user or external electronic device 1020) that will be used in components of the electronic device 1010 (e.g., processor 1100, sensor module 1610, or sound output module 1630).

[0285] Input module 1300 may include a first input module 1310 for receiving commands or data from a user and a second input module 1320 for receiving commands or data from an external electronic device 1020. The first input module 1310 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 1320 may support a specified protocol that can be connected to the external electronic device 1020 via a wired or wireless connection. In embodiments, the second input module 1320 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 1320 may include a connector that can be physically connected to the external electronic device 1020, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0286] Display module 1400 can provide visual information to the user. Display module 1400 may include display panel 10, scan driver GP, and data driver DP. Display module 1400 may also include a window, a base frame, and a bracket to protect display panel 10.

[0287] exist Figure 13 The display module 1400, display panel 10, and scan driver GP mentioned in the text refer to... Figures 1 to 12 The description of the display module 1400, display panel 10, and scan driver GP, etc., is mentioned above. Therefore, content that is the same as or repeats the above can be omitted in the description of the display module 1400, display panel 10, and scan driver GP, etc.

[0288] The display panel 10 may also include a light-emitting driver. The light-emitting driver outputs a transmission control signal to the display panel 10 in response to a control signal received from the controller 1120-1. The light-emitting driver may be formed separately from the scan driver GP, or it may be integrated into the scan driver GP.

[0289] The scan driver GP receives a control signal from the controller 1120-1 and outputs a scan signal to the display panel 10 in response to the control signal. As an example, the control signal generated by the controller 1120-1 and transmitted to the scan driver GP can be a scan input signal for controlling the scan driver GP. The scan input signal can be an input signal applied to a switching element included in a stage of the scan driver GP. As an example, the input signal can be a first input signal S1 as described herein (see...). Figure 5 ) to the sixth input signal S6 (see Figure 5 In another example, the input signal could be the inverted signal INV_N applied to the inverting element (see [link]). Figure 4 ).

[0290] The data driver DP receives a control signal from the controller 1120-1, converts image data into an analog voltage (e.g., a data voltage) in response to the control signal, and outputs the data voltage to the display panel 10. As an example, the control signal generated by the controller 1120-1 and transmitted to the data driver DP can be a data input signal used to control the data driver DP.

[0291] The data driver DP can be integrated into another component (e.g., controller 1120-1). The functions of the interface conversion circuitry and timing control circuitry of controller 1120-1 can be integrated into the data driver DP.

[0292] The controller 1120-1 can generate clock signals that support the driving of the scan driver GP. As an example, the clock signal could be the first clock signal CK1 transmitted to each stage of the scan driver GP (see [link to controller 1]). Figure 5 ) to the sixth clock signal CK6 (see Figure 5 Each stage of the scan driver GP can operate based on the clock signal corresponding to each stage.

[0293] The scan driver GP can generate a scan signal based on the scan input signal, clock signal, and scan input voltage. The scan signal can be transmitted to the pixel circuitry, and the thin-film transistors included in the pixel circuitry can be driven based on the scan signal. The scan signal can also be transmitted to the gates included in the pixel circuitry.

[0294] The display module 1400 may also include a light-emitting driver and a voltage generation circuit. The voltage generation circuit can output various voltages that support driving the display panel 10.

[0295] The power module 1500 supplies power to the components of the electronic device 1010. As an example, the power module 1500 can generate a first power voltage ELVDD (see [link to example]). Figure 2 ) and second power voltage ELVSS (see Figure 2 The power module 1500 can generate gate drive voltages (e.g., gate high voltage and gate low voltage) that support the drive of the scan driver GP.

[0296] As an example, power module 1500 can refer to a power generator and a power supply, etc. As an example, power module 1500 may include a battery that is charged by a power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0297] As an example, power module 1500 may include a power management integrated circuit (PMIC). The PMIC supplies power optimized for each of the modules described above and those described herein.

[0298] As an example, the power module 1500 may include a wireless power transmitting / receiving component electrically connected to a battery. The wireless power transmitting / receiving component may include multiple coil-shaped antenna radiators.

[0299] The electronic device 1010 may also include a built-in module 1600 and an external module 1700. The built-in module 1600 may include a sensor module 1610, an antenna module 1620, and a sound output module 1630. The external module 1700 may include a camera module 1710, an optical module 1720, and a communication module 1730.

[0300] The sensor module 1610 can sense input caused by the user's body or by the pen of the first input module 1310, and generate an electrical signal or data value corresponding to the input. The sensor module 1610 may include at least one of a fingerprint sensor 1610-1, an input sensor 1610-2, and a digitizer 1610-3.

[0301] The fingerprint sensor 1610-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 1610-1 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0302] The input sensor 1610-2 can generate data values ​​corresponding to the coordinate information of input caused by the user's body or by a pen. The input sensor 1610-2 can generate data values ​​based on changes in electrostatic capacitance caused by the input. The input sensor 1610-2 can sense input caused by a passive pen or send / receive data to / from an active pen.

[0303] The input sensor 1610-2 can measure biosignals, such as blood pressure, water content, or body fat. As an example, when a user touches a part of his or her body to the sensor layer or sensing panel and does not move it within a preset time period, the input sensor 1610-2 can detect the biosignal based on the change in the electric field caused by the part of his or her body and output the information desired by the user to the display module 1400.

[0304] The digitizer 1610-3 can generate data values ​​corresponding to the coordinate information of input caused by a pen. The digitizer 1610-3 can generate data values ​​based on electromagnetic changes caused by the input. The digitizer 1610-3 can sense input caused by a passive pen or send / receive data to / from an active pen.

[0305] At least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be implemented as a sensor layer formed on the display panel 10 by a continuous process. The fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be arranged on the upper side of the display panel 10, and one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 (e.g., the digitizer) can be arranged on the lower side of the display panel 10.

[0306] At least two of the fingerprint sensor 1610-1, input sensor 1610-2, and digitizer 1610-3 can be integrated into a single sensing panel using the same process. When at least two of the fingerprint sensor 1610-1, input sensor 1610-2, and digitizer 1610-3 are integrated into a single sensing panel, the sensing panel can be positioned between the display panel 10 and a window located on the upper side of the display panel 10. In an embodiment, the sensing panel can be positioned on the window. The position of the sensing panel is not particularly limited.

[0307] At least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be built into the display panel 10. That is, at least one of the fingerprint sensor 1610-1, the input sensor 1610-2, and the digitizer 1610-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements and transistors) included in the display panel 10.

[0308] Furthermore, sensor module 1610 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 1010. Sensor module 1610 may also include, for example, gesture sensors, gyroscope sensors, pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, IR (infrared) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0309] Antenna module 1620 may include at least one antenna for transmitting or receiving signals or power to or from an external source. In an embodiment, communication module 1730 may transmit or receive signals to or from external electronic device 1020 via an antenna suitable for a communication method. The antenna pattern of antenna module 1620 may be integrated into a configuration of display module 1400 (e.g., display panel 10) or input sensor 1610-2, etc.

[0310] The sound output module 1630 is a device for outputting sound signals to the external device 1010. The sound output module 1630 may include, for example, a speaker for general purposes (such as multimedia playback or recording playback) and a receiver specifically for telephone reception. In embodiments, the receiver may be integrally formed with the speaker or separate from the speaker. The sound output pattern of the sound output module 1630 may be integrated into the display module 1400.

[0311] Camera module 1710 can capture still images and moving images. In embodiments, camera module 1710 may include one or more lenses, an image sensor, or an image signal processor. Camera module 1710 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight, etc.

[0312] The optical module 1720 can provide light. The optical module 1720 may include a light-emitting diode or a xenon lamp. The optical module 1720 can operate in conjunction with the camera module 1710 or independently.

[0313] Communication module 1730 can support the establishment of a wired or wireless communication channel between electronic device 1010 and external electronic device 1020, and supports communication through the established communication channel. Communication module 1730 may include one or both of the following: a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module; and a wired communication module such as a local area network (LAN) communication module or a power line communication module. Communication module 1730 can communicate with external electronic device 1020 via a short-range communication network such as Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or WAN). The various types of communication modules 1730 described herein can be implemented as a single chip or a separate chip.

[0314] Input module 1300, sensor module 1610, and camera module 1710, etc., can be used to control the operation of display module 1400 in association with processor 1100.

[0315] The processor 1100 outputs commands or data to the display module 1400, sound output module 1630, camera module 1710, or optical module 1720 based on input data received from the input module 1300. As an example, the processor 1100 may generate image data and output it to the display module 1400 in response to input data applied via a mouse or active pen, or generate command data and output it to the camera module 1710 or optical module 1720 in response to input data. In an example where no input data is received from the input module 1300 within a preset time period, the processor 1100 may reduce the power consumed by the electronic device 1010 by switching its operating mode to a low-power mode or sleep mode.

[0316] The processor 1100 outputs commands or data to the display module 1400, the sound output module 1630, the camera module 1710, or the optical module 1720 based on the sensing data received from the sensor module 1610. As an example, the processor 1100 compares the authentication data applied by the fingerprint sensor 1610-1 with the authentication data stored in the memory 1200, and can then execute an application based on the comparison result. The processor 1100 can execute commands and output corresponding image data to the display module 1400 based on sensing data sensed by the input sensor 1610-2 or the digitizer 1610-3. If the sensor module 1610 includes a temperature sensor, the processor 1100 can receive temperature data related to the temperature measured by the sensor module 1610, and also perform brightness correction, etc., on the image data based on the temperature data.

[0317] The processor 1100 can receive measurement data from the camera module 1710 regarding the presence or absence of a user, the user's position, and the user's line of sight. The processor 1100 can also perform brightness correction and other functions on the image data based on the measurement data. As an example, the processor 1100, having determined the presence or absence of a user through input from the camera module 1710, can output image data whose brightness has been corrected by the data conversion circuit 1120-2 or the gamma correction circuit 1120-3 to the display module 1400.

[0318] Some of the components described above can be connected to each other via peripheral communication methods (such as bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or ultrapath interconnect (UPI) links) to exchange signals (e.g., commands or data). For example, processor 1100 can communicate with display module 1400 using a specified interface and one of the above communication methods. Communication methods are not limited to those described above.

[0319] The electronic device 1010 according to various embodiments can be a variety of devices. The electronic device 1010 may include at least one of, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance device. The electronic device 1010 according to embodiments is not limited to the devices described above.

[0320] In this embodiment, the electronic device 1010 may include a controller 1120-1, a power module 1500, and a display module 1400. The display module 1400 may include a display panel 10 and a scan driver GP. The controller 1120-1 may generate a scan input signal that supports driving the scan driver GP. The power module 1500 may generate a scan input voltage that supports driving the scan driver GP under the control of the processor 1100 or the controller 1120-1. As an example, the scan input voltage may be a gate drive voltage.

[0321] The display panel 10 can be divided into a display area DA in which pixel circuits are disposed (see...). Figure 1 ) and the peripheral area PA outside the display area (see Figure 1 As described herein, the area where an image is displayed may be the display area DA, and the area other than the display area DA where no image is displayed may be the peripheral area PA.

[0322] The scan driver GP can be located in the peripheral area PA, and can receive scan input signals from the controller 1120-1 and scan input voltages from the power module 1500. The scan driver GP can generate or output scan signals based on the scan input signals and / or scan input voltages. The scan signals can be transmitted from the scan driver GP to the pixel circuit PC (see [link to relevant documentation]). Figure 11 ).

[0323] In an embodiment, the scan driver GP may include at least one capacitor. The at least one capacitor may include one electrode and another electrode. As an example, one electrode may be a signal line transmitting at least one of a scan input signal and a scan input voltage. As an example, one electrode may be at least a portion of the signal line transmitting at least one of the scan input signal and the scan input voltage.

[0324] The signal line can be the wiring to which the sixth input signal S6 is transmitted (e.g., the first wiring ML1 (see...)). Figure 7 Alternatively, the signal line can be the wiring to which the scan input voltage is transmitted.

[0325] As an example, the other electrode may overlap with one electrode. The other electrode may overlap with a signal line that transmits at least one of the scan input signal and the scan input voltage. As an example, the other electrode may overlap with at least a portion of a signal line that transmits at least one of the scan input signal and the scan input voltage.

[0326] In an embodiment, the peripheral area PA may include a wiring layout area BA in which wiring is disposed (see [link to example]). Figure 7 ) and the circuit layout area CA between the display area DA and the wiring layout area BA, wherein at least one transistor is disposed (see Figure 7 As an example, at least one capacitor may be placed in the wiring layout area.

[0327] In an embodiment, in a plan view, at least one capacitor may be separated from at least one transistor in a first direction, and signal lines may extend in a second direction that intersects the first direction.

[0328] In some aspects, the display module 1400 included in the electronic device 1010 may include a reference Figures 1 to 12 The characteristics of the display panel 10, the scan driver GP, and the data driver DP are described. Those skilled in the art will readily understand, with reference to... Figures 1 to 12 The description of the display panel 10, scan driver GP, and data driver DP is applicable to Figure 13 The display module 1400.

[0329] Unless otherwise described, it should be understood that the description of features or aspects in each embodiment is generally applicable to other similar features or aspects in another embodiment. Therefore, it will be apparent to those skilled in the art that features or elements described in connection with a particular embodiment can be combined with features or elements described in connection with other embodiments.

[0330] According to embodiments having the above configuration, a display device for achieving a thin bezel and an electronic device including the display device can be provided. However, the scope of this disclosure is not limited by this effect.

[0331] It should be understood that the embodiments described herein are to be considered in a descriptive sense and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: The substrate includes a display area and a peripheral area surrounding the display area; Pixel circuitry, disposed in the display area; and A scan driver, disposed in the peripheral area, the scan driver being electrically connected to the pixel circuit, and the scan driver comprising: Sensing transistor; A first wiring is electrically connected to the source electrode of the sensing transistor; and A first capacitor is electrically connected to the source electrode and the gate electrode of the sensing transistor. in: The peripheral area includes: A wiring layout area, wherein wiring is arranged in the wiring layout area; and A circuit layout area, in which at least one transistor is disposed, wherein the circuit layout area is located between the display area and the wiring layout area. The first capacitor is disposed in the wiring arrangement area. The sensing transistor is disposed in the circuit arrangement area, and The first capacitor includes: The first electrode is electrically connected to the first wiring; and The second electrode is electrically connected to the gate electrode of the sensing transistor.

2. The display device according to claim 1, wherein, The first electrode is the first wiring.

3. The display device according to claim 2, wherein, In the plan view, a portion of the first wiring overlaps with the second electrode.

4. The display device according to claim 2, wherein, A portion of the first wiring is perpendicular to the second electrode and separated from each other.

5. The display device according to claim 2, wherein: The first electrode is the lower electrode, and The second electrode is the upper electrode.

6. The display device according to claim 3, wherein, An insulating material is disposed between the first electrode and the second electrode.

7. The display device according to claim 2, wherein, In the plan view, the first capacitor is separated from the sensing transistor in a first direction.

8. The display device according to claim 7, wherein, The first wiring extends in a second direction that intersects the first direction.

9. The display device according to claim 7, wherein, The second electrode includes: The first portion overlaps with the first wiring in the plan view; and The second part connects the first part electrically to the gate electrode of the sensing transistor.

10. The display device according to claim 9, wherein: The first portion extends in the direction of the first wiring extension, and The second portion extends in the first direction.

11. The display device according to claim 10, wherein: The width of the first portion in the first direction is greater than the width of the second portion in the second direction, and The second direction intersects with the first direction.

12. A display device, wherein, The display device includes: The substrate includes a display area and a peripheral area surrounding the display area; Pixel circuitry, disposed in the display area; and A scan driver, disposed in the peripheral area, the scan driver being electrically connected to the pixel circuit, and the scan driver comprising: Sensing transistor; A first wiring is electrically connected to the source electrode of the sensing transistor; and A first capacitor is electrically connected to the source electrode and the gate electrode of the sensing transistor. The first capacitor includes: The first electrode is configured to receive a control signal from the controller; and The second electrode is electrically connected to the gate electrode of the sensing transistor. The first electrode is the first wiring.

13. The display device according to claim 12, wherein: The peripheral area includes: A wiring layout area, wherein wiring is arranged in the wiring layout area; and A circuit layout area, in which at least one transistor is disposed, is located between the display area and the wiring layout area. The first capacitor is disposed in the wiring arrangement area, and The sensing transistor is disposed in the circuit layout area.

14. The display device according to claim 12, wherein, In the plan view, a portion of the first wiring overlaps with the second electrode.

15. The display device according to claim 12, wherein, A portion of the first wiring is perpendicular to the second electrode and separated from each other.

16. The display device according to claim 12, wherein, In the plan view, the first capacitor is separated from the sensing transistor in a first direction.

17. The display device according to claim 16, wherein, The first wiring extends in a second direction that intersects the first direction.

18. An electronic device, wherein, The electronic device includes: The controller generates the scanning input signal; The power module generates the scanning input voltage; and The display module includes a display panel and a scan driver. in: The display panel is divided into: A display area, wherein pixel circuitry is disposed in the display area; and The outer area, surrounding the display area, The scan driver is disposed in the peripheral area. The scan driver receives the scan input signal and the scan input voltage, and the scan driver outputs a scan signal to the pixel circuit. The scan driver includes at least one capacitor, the at least one capacitor including one electrode and another electrode, wherein the one electrode is a signal line transmitting at least one of the scan input signal and the scan input voltage, and the other electrode overlaps with at least a portion of the signal line in a plan view.

19. The electronic device according to claim 18, wherein: The peripheral area includes: A wiring layout area, wherein wiring is arranged in the wiring layout area; and A circuit layout area, in which at least one transistor is disposed, wherein the circuit layout area is located between the display area and the wiring layout area, and The at least one capacitor is disposed in the wiring layout area.

20. The electronic device according to claim 19, wherein, In the plan view, the at least one capacitor is separated from the at least one transistor in a first direction, and the signal line extends in a second direction that intersects the first direction.

Images