Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of sub-pixels, and each sub-pixel comprises a pixel driving circuit and a light-emitting device. The pixel driving circuit at least comprises a second transistor and a node electrode, the second transistor at least comprises a second active layer, and the node electrode is connected with a second area of the second active layer through a node via hole; the light-emitting device at least comprises a first electrode and a pixel definition layer, the first electrode is connected with the node electrode through the anode via hole, and a pixel opening for exposing the first electrode is formed in the pixel definition layer; in at least one sub-pixel, the orthographic projection of the node via hole on the plane of the display substrate is not overlapped with the orthographic projection of the pixel opening on the plane of the display substrate, and the anode via hole is formed in the side, away from the pixel opening, of the node via hole. According to the invention, poor display such as watermarks is effectively eliminated, and the display quality is improved.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices that offer advantages such as self-illumination, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Currently, OLED display devices suffer from issues such as display watermarks (mura). Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the embodiments of this disclosure is to provide a display substrate and its preparation method, as well as a display device, so as to solve the problems such as display watermarks in existing display devices.

[0006] On one hand, this disclosure provides a display substrate including a plurality of repeating units, at least one repeating unit having a plurality of sub-pixels, and at least one sub-pixel including a pixel driving circuit and a light-emitting device; the pixel driving circuit includes at least a second transistor as a driving transistor and a node electrode, the second transistor including at least a second active layer, the node electrode being connected to a second region of the second active layer through a node via, and a first region of the second active layer being connected to a first power line; the light-emitting device includes at least a first electrode and a pixel defining layer, the first electrode being connected to the node electrode through an anode via, and the pixel defining layer having a pixel opening exposing the first electrode; in at least one sub-pixel, the orthographic projection of the node via on the display substrate plane does not overlap with the orthographic projection of the pixel opening on the display substrate plane, and the anode via is disposed on the side of the node via away from the pixel opening.

[0007] In an exemplary embodiment, the pixel driving circuit further includes a blocking electrode and a transparent storage capacitor. The storage capacitor includes a first electrode plate and a second electrode plate. The orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the blocking electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer on the display substrate plane. The blocking electrode is connected to the first electrode plate. In at least one sub-pixel, the node electrode is also connected to the blocking electrode through the node via.

[0008] In an exemplary embodiment, the node electrode includes at least a first sub-electrode and a second sub-electrode that are interconnected. The first sub-electrode is connected to both the second region of the second active layer and the shielding electrode through the node via. The first electrode is connected to the second sub-electrode through an anode via. The second sub-electrode is disposed on the side of the first sub-electrode away from the pixel opening.

[0009] In an exemplary embodiment, the orthographic projection of the second sub-electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer on the display substrate plane, and the orthographic projection of the anode via on the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer on the display substrate plane.

[0010] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening on the display substrate plane, and the orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening on the display substrate plane.

[0011] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, a semiconductor layer disposed on a side of the first conductive layer away from the substrate, and a second conductive layer disposed on a side of the semiconductor layer away from the substrate. A first electrode plate is disposed in the first transparent conductive layer, a shielding electrode is disposed in the first conductive layer, a second electrode plate and a second active layer are disposed in the semiconductor layer, and a node electrode is disposed in the second conductive layer.

[0012] In an exemplary embodiment, the second transistor further includes a second gate electrode, and the pixel driving circuit further includes a first connection electrode; in at least one sub-pixel, the first connection electrode is connected to both the second electrode plate and the second gate electrode through a first adapter via.

[0013] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the second gate electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane.

[0014] In an exemplary embodiment, in at least one first transition via, the orthographic projection of the second gate electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane.

[0015] In an exemplary embodiment, at least one repeating unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along a first direction. The first power line is in the shape of a straight line or a broken line extending along a second direction and is respectively disposed in the first sub-pixel and the fourth sub-pixel. The first direction and the second direction intersect. The first power line in the first sub-pixel is connected to the first region of the second active layer in the first sub-pixel through a power via. The first power line in the first sub-pixel is connected to the first region of the second active layer in the second sub-pixel through a power connection line and a power connection electrode. The first power line in the fourth sub-pixel is connected to the first region of the second active layer in the third sub-pixel through a power connection line and a power connection electrode. The first power line in the fourth sub-pixel is connected to the first region of the second active layer in the fourth sub-pixel through a power via.

[0016] In an exemplary embodiment, the pixel driving circuit further includes a blocking electrode, the orthographic projection of the blocking electrode on the display substrate plane at least partially overlapping the orthographic projection of the second active layer on the display substrate plane; in the first sub-pixel and the fourth sub-pixel, the orthographic projection of the power via on the display substrate plane does not overlap with the orthographic projection of the blocking electrode on the display substrate plane.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a blocking electrode, the orthographic projection of the blocking electrode on the display substrate plane at least partially overlapping the orthographic projection of the second active layer on the display substrate plane; in the second sub-pixel and the third sub-pixel, the first end of the power connection electrode is connected to the first region of the second active layer through a power via, the second end of the power connection electrode is connected to the first power line through the power connection line, and the orthographic projection of the power via on the display substrate plane at least partially overlaps the orthographic projection of the blocking electrode on the display substrate plane.

[0018] In an exemplary embodiment, at least one sub-pixel further includes a data signal line connected to the pixel driving circuit. The data signal line is a zigzag line extending along the second direction, and includes at least a straight first sub-line and a second sub-line, and a diagonal third sub-line. The third sub-line is disposed between the first sub-line and the second sub-line, and both ends of the third sub-line are respectively connected to the first sub-line and the second sub-line. In at least one sub-pixel of the first sub-pixel and the fourth sub-pixel, the first sub-line has a first distance from the first power line, and the second sub-line has a second distance from the first power line. The first distance is greater than the second distance, and the first distance and the second distance are dimensions in the first direction.

[0019] In an exemplary embodiment, at least one sub-pixel further includes a compensation signal line connected to the pixel driving circuit, the compensation signal line being disposed between the second sub-pixel and the third sub-pixel; in at least one sub-pixel of the second sub-pixel and the third sub-pixel, the first sub-line and the compensation signal line have a third distance, the second sub-line and the compensation signal line have a fourth distance, the third distance being less than the fourth distance, and the third distance and the fourth distance being the dimensions of the first direction.

[0020] In an exemplary embodiment, the orthographic projection of the compensation signal line on the display substrate plane does not overlap with the orthographic projection of the power connection line on the display substrate plane.

[0021] In an exemplary embodiment, the pixel driving circuit further includes a first transistor as a data writing transistor and a third transistor as a compensation transistor, wherein in at least one sub-pixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scan signal line.

[0022] In an exemplary embodiment, in at least one repeating unit, the gate electrodes of a plurality of first transistors and the gate electrodes of a plurality of third transistors are connected to the same scan signal line.

[0023] In an exemplary embodiment, in at least one repeating unit, at least one through hole is provided on the scanning signal line, and the orthographic projection of the through hole on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0025] In another aspect, this disclosure also provides a method for fabricating a display substrate, the display substrate comprising a plurality of sub-pixels; the fabrication method comprising:

[0026] A pixel driving circuit and a light-emitting device are formed in at least one sub-pixel; the pixel driving circuit includes at least a second transistor as a driving transistor and a node electrode, the second transistor includes at least a second active layer, the node electrode is connected to a second region of the second active layer through a node via, and a first region of the second active layer is connected to a first power line; the light-emitting device includes at least a first electrode and a pixel definition layer, the first electrode is connected to the node electrode through an anode via, and a pixel opening is provided on the pixel definition layer to expose the first electrode; in at least one sub-pixel, the orthographic projection of the node via on the display substrate plane does not overlap with the orthographic projection of the pixel opening on the display substrate plane, and the anode via is disposed on the side of the node via away from the pixel opening.

[0027] This disclosure provides a display substrate and its preparation method, as well as a display device. By setting the anode vias away from the pixel openings, light leakage is effectively reduced, display defects such as watermarks are effectively eliminated, and display quality and display performance are improved.

[0028] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0030] Figure 1 This is a schematic diagram of the structure of a display device;

[0031] Figure 2 This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure.

[0032] Figure 3 An equivalent circuit diagram of a pixel driving circuit in a repeating unit is provided in this exemplary embodiment.

[0033] Figure 4 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 5 for Figure 4 Sectional view along the middle AA direction;

[0035] Figure 6 This is a schematic diagram of a first transparent conductive layer pattern formed according to an embodiment of the present disclosure;

[0036] Figure 7A and Figure 7B This is a schematic diagram of a first conductive layer pattern after being formed according to an embodiment of the present disclosure;

[0037] Figure 8A and Figure 8B This is a schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0038] Figure 9A and Figure 9B This is a schematic diagram of a second conductive layer pattern formed according to an embodiment of the present disclosure;

[0039] Figure 10 This is a schematic diagram of a third insulating layer pattern formed according to an embodiment of the present disclosure;

[0040] Figure 11A and Figure 11B This is a schematic diagram of a third conductive layer pattern formed according to an embodiment of the present disclosure;

[0041] Figure 12 This is a schematic diagram of a fourth insulating layer and a planarization layer pattern formed according to an embodiment of the present disclosure;

[0042] Figure 13 This is a schematic diagram of a second transparent conductive layer pattern formed according to an embodiment of the present disclosure;

[0043] Figure 14 This is a schematic diagram of a pixel definition layer pattern formed according to an embodiment of the present disclosure.

[0044] Explanation of reference numerals in the attached figures:

[0045] 11—First electrode plate; 12—Connecting plate; 13—Connecting wire;

[0046] 21—Power connection cable; 22—Compensation connection cable; 22-1—Compensation connection block;

[0047] 23—Shielding electrode; 24—Interlayer connection electrode; 31—First active layer;

[0048] 32—Second active layer; 33—Third active layer; 34—Second electrode plate;

[0049] 42—Second gate electrode; 50—Scan signal line; 51—First connecting electrode;

[0050] 52—Second connecting electrode; 52-1—First sub-electrode; 52-2—Second sub-electrode;

[0051] 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode;

[0052] 56—Power connection electrode; 60—First power line; 70—Data signal line;

[0053] 70-1—First sub-line; 70-2—Second sub-line; 70-3—Third sub-line;

[0054] 80—Compensation signal line; 90—First electrode; 90A—Pixel aperture;

[0055] 100—Repeating unit; 200—Substrate; 201—First insulating layer;

[0056] 202—Second insulating layer; 203—Third insulating layer; 204—Fourth insulating layer;

[0057] 205—Planarization layer; 206—Pixel definition layer; DV—Power via;

[0058] JV—Node via; ZV—First adapter via; YV—Anode via. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0060] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0061] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0062] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0063] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0064] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0065] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0066] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0067] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0068] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0069] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0070] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0071] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is connected to both the data driver and the scan driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the scan driver is connected to multiple scan signal lines (S1 to Sm). The pixel array may include multiple sub-pixels Pxij, each sub-pixel Pxij being connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit, which is connected to both the scan signal line and the data signal line. The display unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. The sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines 531, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines 531 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0072] An exemplary embodiment of this disclosure provides a display substrate including a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit and a light-emitting device; the pixel driving circuit includes at least a second transistor as a driving transistor and a node electrode, the second transistor including at least a second active layer, the node electrode being connected to a second region of the second active layer through a node via, and a first region of the second active layer being connected to a first power line; the light-emitting device includes at least a first electrode and a pixel defining layer, the first electrode being connected to the node electrode through an anode via, and the pixel defining layer having a pixel opening exposing the first electrode; in at least one sub-pixel, the orthographic projection of the node via on the display substrate plane does not overlap with the orthographic projection of the pixel opening on the display substrate plane, and the anode via is disposed on the side of the node via away from the pixel opening.

[0073] In an exemplary embodiment, the pixel driving circuit further includes a blocking electrode and a transparent storage capacitor. The storage capacitor includes a first electrode plate and a second electrode plate. The orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the blocking electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer on the display substrate plane. The blocking electrode is connected to the first electrode plate. In at least one sub-pixel, the node electrode is also connected to the blocking electrode through the node via.

[0074] In an exemplary embodiment, the second transistor further includes a second gate electrode, and the pixel driving circuit further includes a first connection electrode; in at least one sub-pixel, the first connection electrode is connected to both the second electrode plate and the second gate electrode through a first adapter via.

[0075] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the second gate electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane.

[0076] In an exemplary embodiment, in at least one first transition via, the orthographic projection of the second gate electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane.

[0077] In an exemplary embodiment, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along a first direction. The first power line is in the shape of a straight line or a broken line extending along a second direction and is respectively disposed in the first sub-pixel and the fourth sub-pixel, wherein the first direction and the second direction intersect. The first power line in the first sub-pixel is connected to the first region of the second active layer in the first sub-pixel through a power via. The first power line in the first sub-pixel is connected to the first region of the second active layer in the second sub-pixel through a power connection line and a power connection electrode. The first power line in the fourth sub-pixel is connected to the first region of the second active layer in the third sub-pixel through a power connection line and a power connection electrode. The first power line in the fourth sub-pixel is connected to the first region of the second active layer in the fourth sub-pixel through a power via.

[0078] In an exemplary embodiment, at least one sub-pixel further includes a data signal line connected to the pixel driving circuit. The data signal line is a zigzag line extending along the second direction, and includes at least a straight first sub-line and a second sub-line, and a diagonal third sub-line. The third sub-line is disposed between the first sub-line and the second sub-line, and both ends of the third sub-line are respectively connected to the first sub-line and the second sub-line. In at least one sub-pixel of the first sub-pixel and the fourth sub-pixel, the first sub-line has a first distance from the first power line, and the second sub-line has a second distance from the first power line. The first distance is greater than the second distance, and the first distance and the second distance are dimensions in the first direction.

[0079] In an exemplary embodiment, at least one sub-pixel further includes a compensation signal line connected to the pixel driving circuit, the compensation signal line being disposed between the second sub-pixel and the third sub-pixel; in at least one sub-pixel of the second sub-pixel and the third sub-pixel, the first sub-line and the compensation signal line have a third distance, the second sub-line and the compensation signal line have a fourth distance, the third distance being less than the fourth distance, and the third distance and the fourth distance being the dimensions of the first direction.

[0080] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0081] Figure 2 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 2As shown, in an exemplary embodiment, the display substrate may include a plurality of repeating units 100 in a direction parallel to the display substrate, and at least one repeating unit 100 may include a plurality of sub-pixels. In an exemplary embodiment, the repeating unit is a basic unit constituting the display substrate, and the display substrate is formed by repeating and continuously arranging them along at least one direction; that is, the display substrate is composed of a plurality of repeating units spliced ​​together.

[0082] In an exemplary embodiment, a repeating unit 100 may include four sub-pixels. The four sub-pixels may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, a third sub-pixel P3 that emits a third color light, and a fourth sub-pixel P4 that emits a fourth color light. The four sub-pixels may be arranged in a horizontal side-by-side manner, which can effectively increase the aperture ratio.

[0083] In an exemplary embodiment, in at least one repeating unit 100, a second sub-pixel P2 may be disposed on one side of the first sub-pixel P1 in the first direction X, a third sub-pixel P3 may be disposed on one side of the second sub-pixel P2 in the first direction X, and a fourth sub-pixel P4 may be disposed on one side of the third sub-pixel P3 in the first direction X. In an exemplary embodiment, a plurality of sub-pixels arranged sequentially along the first direction X may be referred to as a pixel row, and a plurality of sub-pixels arranged sequentially along the second direction Y may be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array, wherein the first direction X intersects the second direction Y.

[0084] In an exemplary embodiment, the first direction X can be a horizontal direction, the second direction Y can be a vertical direction, and the first direction X and the second direction Y are perpendicular to each other.

[0085] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a white sub-pixel (W) emitting white light, the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light, and the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light. In some possible implementations, the arrangement of RWBG can be adjusted according to actual needs, and this disclosure does not specifically limit it.

[0086] In one exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. In at least one repeating unit, the driving circuit layer may include multiple circuit units, each circuit unit may include at least a pixel driving circuit, which is connected to scan signal lines and data signal lines, respectively. The pixel driving circuit is configured to receive data voltage transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the light-emitting device. The light-emitting structure layer may include multiple light-emitting units, each light-emitting unit may include at least a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the circuit unit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0087] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on the substrate, a color filter structure layer disposed on the side of the driving circuit layer away from the substrate, and a light-emitting structure layer disposed on the side of the color filter structure layer away from the substrate. In at least one repeating unit, the color filter structure layer may include a plurality of color filter units, and each color filter unit may include at least a color filter layer configured to cause the corresponding sub-pixel to emit light of the desired color.

[0088] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit. The color filter unit referred to in this disclosure refers to a region divided according to a color filter layer. The light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. The positions of the circuit unit projected onto the substrate, the color filter layer projected onto the substrate, and the light-emitting unit projected onto the substrate may be corresponding or non-corresponding.

[0089] In the exemplary embodiments of this disclosure, the positions of the circuit unit projected onto the substrate, the color filter unit projected onto the substrate, and the light-emitting unit projected onto the substrate are substantially corresponding. The circuit unit, the color filter unit, and the light-emitting unit constitute a sub-pixel. In the following text, sub-pixel is used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0090] Figure 3 This disclosure provides an exemplary embodiment of an equivalent circuit diagram of a pixel driving circuit in a repeating unit. (See diagram below.) Figure 3 As shown, at least one repeating unit may include four pixel driving circuits, which may be arranged in a horizontal parallel manner, and the pixel driving circuit may be a 3T1C structure.

[0091] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C. The pixel driving circuit is connected to a scan signal line 50, a first power supply line 60, a data signal line 70, and a compensation signal line 80, respectively.

[0092] In an exemplary embodiment, at least one pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first terminal of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second terminal of the storage capacitor C, respectively.

[0093] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the second node N2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0094] In an exemplary embodiment, the first transistor T1 can be referred to as the data writing transistor, the second transistor T2 can be referred to as the driving transistor, and the third transistor T3 can be referred to as the compensation transistor.

[0095] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the scan signal line 50, the first terminal of the first transistor T1 is connected to the data signal line 70, and the second terminal of the first transistor T1 is connected to the first node N1. The gate electrode of the second transistor T2 is connected to the first node N1, the first terminal of the second transistor T2 is connected to the first power supply line 60, and the second terminal of the second transistor T2 is connected to the second node N2. The gate electrode of the third transistor T3 is connected to the scan signal line 50, the first terminal of the third transistor T3 is connected to the compensation signal line 80, and the second terminal of the third transistor T3 is connected to the second node N2.

[0096] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 50.

[0097] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of a plurality of first transistors T1 are connected to the same scan signal line 50.

[0098] In an exemplary embodiment, in the pixel driving circuit of at least one repeating unit, the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 50.

[0099] In an exemplary embodiment, in the pixel driving circuit of at least one repeating unit, the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 50.

[0100] In an exemplary embodiment, in a plurality of pixel driving circuits of at least one pixel row, the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 50.

[0101] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or it can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line VSS. In an exemplary embodiment, the first electrode can be an anode, and the second electrode can be a cathode; or, the first electrode can be a cathode, and the second electrode can be an anode.

[0102] In an exemplary embodiment, the signal of the first power line 60 is a continuously supplied high-level signal, and the signal of the second power line VSS is a continuously supplied low-level signal.

[0103] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing complexity of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the third transistor T3 may include both P-type and N-type transistors.

[0104] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), or oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0105] Figure 4This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit (four sub-pixels) in a bottom-emitting display substrate. Figure 5 for Figure 4 A sectional view along the AA direction. (e.g.) Figure 4 and Figure 5 As shown, in the direction parallel to the display substrate, at least one repeating unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged sequentially along the first direction X. In an exemplary embodiment, in the direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer of at least one sub-pixel may include a pixel driving circuit, and the light-emitting structure layer of at least one sub-pixel may include a light-emitting device, with at least one light-emitting device connected to the pixel driving circuit of the sub-pixel.

[0106] In an exemplary embodiment, at least one repeating unit may include a scan signal line 50, two first power supply lines 60, four data signal lines 70 and a compensation signal line 80, all of which are connected to the pixel driving circuits of the four sub-pixels.

[0107] In an exemplary embodiment, multiple scan signal lines 50 in the display substrate may be arranged along a second direction Y, and at least one scan signal line 50 may extend along a first direction X. In at least one repeating unit, the shape of the scan signal line 50 may be a straight line or a broken line extending along the first direction X, and the shapes of the first power line 60, data signal line 70, and compensation signal line 80 may be straight lines or broken lines extending along the second direction Y. Two first power lines 60 may be respectively disposed on both sides of the repeating unit in the first direction X, four data signal lines 70 and one compensation signal line 80 may be disposed between the two first power lines 60, two of the four data signal lines 70 may be located between the compensation signal line 80 and one first power line 60, and the other two of the four data signal lines 70 may be located between the compensation signal line 80 and another first power line 60.

[0108] In an exemplary embodiment, a first sub-pixel P1 is formed between a first power line 60 and a data signal line 70 adjacent to the first direction X; a second sub-pixel P2 is formed between a compensation signal line 80 and a data signal line 70 adjacent to the opposite direction of the first direction X; a third sub-pixel P3 is formed between the compensation signal line 80 and a data signal line 70 adjacent to the first direction X; and a fourth sub-pixel P4 is formed between another first power line 60 and a data signal line 70 adjacent to the opposite direction of the first direction X. That is, two first power lines 60 are respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4, the compensation signal line 80 is disposed between the second sub-pixel P2 and the third sub-pixel P3, and four data signal lines 70 are respectively disposed in the first sub-pixel P1 to the fourth sub-pixel P4.

[0109] In an exemplary embodiment, the pixel driving circuit for at least one sub-pixel may include a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, a third transistor T3 as a compensation transistor, and a transparent storage capacitor. The first transistor T1, the second transistor T2, and the third transistor T3 may each include an active layer, a gate electrode, a first electrode, and a second electrode. The storage capacitor may include a transparent first electrode plate 11 and a transparent second electrode plate 34.

[0110] In an exemplary embodiment, in at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the scan signal line 50, the first electrode of the first transistor T2 is connected to the data signal line 70, the second electrode of the first transistor T1 is connected to the gate electrode and the second plate 34 of the second transistor T2, the first electrode of the second transistor T2 is connected to the first power supply line 60, the second electrode of the second transistor T2 is connected to the first electrode and the first plate 11 of the third transistor T3, and the first electrode of the third transistor T3 is connected to the compensation signal line 80.

[0111] In an exemplary embodiment, at least one repeating unit may further include two power connection lines 21 extending along a first direction X and two power connection electrodes 56 extending along a second direction Y. One power connection line 21 may span between the first sub-pixel P1 and the second sub-pixel P2, and the other power connection line 21 may span between the third sub-pixel P3 and the fourth sub-pixel P4. One power connection electrode 56 may be disposed in the second sub-pixel P2, and the other power connection electrode 56 may be disposed in the third sub-pixel P3.

[0112] In an exemplary embodiment, the second transistor T2 may include at least a second active layer 32 and a second gate electrode 42. The first power line 60 in the first sub-pixel P1 is connected to the first region of the second active layer via a power via DV, and simultaneously connected to the first end of the power connection line 21 via a via. The first end of the power connection electrode 56 in the second sub-pixel P2 is connected to the first region of the second active layer via a power via DV, and the second end of the power connection electrode 56 is connected to the second end of the power connection line 21 via a via. That is, the first power line 60 in the first sub-pixel P1 is connected to the first region of the second active layer in the second sub-pixel P2 via the power connection line 21 and the power connection electrode 56. The first power line 60 in the fourth sub-pixel P4 is connected to the first region of the second active layer via a power via DV, and simultaneously connected to the first end of the power connection line 21 via a via. The first end of the power connection electrode 56 in the third sub-pixel P3 is connected to the first region of the second active layer through a power via DV, and the second end of the power connection electrode 56 is connected to the second end of the power connection line 21 through a via. That is, the first power line 60 in the fourth sub-pixel P4 is connected to the first region of the second active layer in the third sub-pixel P3 through the power connection line 21 and the power connection electrode 56. In this way, the first power line 60 in the first sub-pixel P1 can provide power signals to the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2, and the first power line 60 in the fourth sub-pixel P4 can provide power signals to the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4, forming a one-to-two structure for the first power line.

[0113] In an exemplary embodiment, at least one repeating unit may further include two compensation connection lines 22 extending along a first direction X. One compensation connection line 22 may span between the first sub-pixel P1 and the second sub-pixel P2. This compensation connection line 22 is connected to the compensation signal line 80 via the compensation connection block 22-1, and is also connected to the first electrode of the third transistor T3 in both the first sub-pixel P1 and the second sub-pixel P2. The other compensation connection line 22 may span between the third sub-pixel P3 and the fourth sub-pixel P4. This compensation connection line 22 is connected to the compensation signal line 80 via the compensation connection block 22-1, and is also connected to the first electrode of the third transistor T3 in both the third sub-pixel P3 and the fourth sub-pixel P4. In this way, one compensation signal line 80 can provide compensation signals to the pixel driving circuits of the four sub-pixels, forming a one-to-four structure of the compensation signal line.

[0114] In an exemplary embodiment, at least one sub-pixel may further include a blocking electrode 23, the orthographic projection of the blocking electrode 23 on the display substrate plane at least partially overlapping the orthographic projection of the second active layer 32 on the display substrate plane, and connected to the first electrode plate 11 of the storage capacitor.

[0115] In an exemplary embodiment, the orthographic projection of the power via DV onto the display substrate plane and the orthographic projection of the shielding electrode 23 onto the display substrate plane do not overlap in the first sub-pixel P1 and the fourth sub-pixel P4.

[0116] In an exemplary embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the power via DV on the display substrate plane at least partially overlaps with the orthographic projection of the shielding electrode 23 on the display substrate plane.

[0117] In an exemplary embodiment, the orthographic projection of the power via DV onto the display substrate plane in the second sub-pixel P2 and the third sub-pixel P3 can be located within the range of the orthographic projection of the shielding electrode 23 onto the display substrate plane.

[0118] In an exemplary embodiment, at least one sub-pixel may further include a first connection electrode 51, which can be connected to the second electrode plate 34 and the second gate electrode 42 simultaneously through the same first transition via ZV.

[0119] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the second gate electrode 42 onto the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate 34 onto the display substrate plane.

[0120] In an exemplary embodiment, in the first transition via ZV, the orthographic projection of the second gate electrode 42 on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate 34 on the display substrate plane.

[0121] In an exemplary embodiment, at least one sub-pixel may further include a second connection electrode 52 as a node electrode, which can be connected to the second region of the second active layer and the occlusion electrode 23 simultaneously through the same node via JV.

[0122] In an exemplary embodiment, the light-emitting device of at least one sub-pixel may include at least a first electrode 90 and a pixel definition layer. The first electrode 90 may be connected to a second connection electrode 52 via an anode via YV. A pixel opening 90A may be provided on the pixel definition layer, exposing the surface of the first electrode 90.

[0123] In an exemplary embodiment, in at least one sub-pixel, the node via JV may be located on one side of the second direction Y of the pixel opening 90A, and the orthographic projection of the node via JV on the display substrate plane does not overlap with the orthographic projection of the pixel opening 90A on the display substrate plane.

[0124] In an exemplary embodiment, in at least one sub-pixel, the anode via YV may be located on one side of the node via JV in the second direction Y, that is, the anode via YV may be located on the side of the node via JV away from the pixel opening 90A.

[0125] In an exemplary embodiment, in at least one sub-pixel, the second connecting electrode 52 may include at least a first sub-electrode 52-1 and a second sub-electrode 52-2 that are connected to each other. The second sub-electrode 52-2 may be located on the side of the first sub-electrode 52-1 away from the pixel opening 90A. The first sub-electrode 52-1 may be connected to the second region of the second active layer and the blocking electrode 23 simultaneously through the node via JV. The first electrode 90 may be connected to the second sub-electrode 52-2 through the anode via YV.

[0126] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the second sub-electrode 52-2 onto the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer onto the display substrate plane.

[0127] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the anode via YV onto the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer onto the display substrate plane.

[0128] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the transparent storage capacitor on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening 90A on the display substrate plane, that is, the orthographic projection of the first electrode plate 11 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening 90A on the display substrate plane, and the orthographic projection of the second electrode plate 34 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening 90A on the display substrate plane.

[0129] In an exemplary embodiment, in at least one sub-pixel, the data signal line 70 may include a first sub-line 70-1, a second sub-line 70-2, and a third sub-line 70-3. The first sub-line 70-1 and the second sub-line 70-2 are straight lines extending along a second direction Y, and the third sub-line 70-3 is a straight line or a broken line extending along an inclined direction. The third sub-line 70-3 may be disposed between the first sub-line 70-1 and the second sub-line 70-2, and both ends of the third sub-line 70-3 are connected to the first sub-line 70-1 and the second sub-line 70-2, respectively.

[0130] In an exemplary embodiment, in at least one sub-pixel of the first sub-pixel P1 and the fourth sub-pixel P4, the first sub-line 70-1 and the first power line 60 may have a first distance L1, and the second sub-line 70-2 and the first power line 60 may have a second distance L2. The first distance L1 may be greater than the second distance L2, and the first distance L1 and the second distance L2 may be the dimensions of the first direction X.

[0131] In an exemplary embodiment, in at least one sub-pixel of the second sub-pixel P2 and the third sub-pixel P3, the first sub-line 70-1 may have a third distance L3 between it and the compensation signal line 80, and the second sub-line 70-2 may have a fourth distance L4 between it and the compensation signal line 80. The third distance L3 may be less than the fourth distance L4, and the third distance L3 and the fourth distance L4 may be the dimensions of the first direction X.

[0132] In an exemplary embodiment, in at least one repeating unit, the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2 and the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit, which is a broken line that bisects the repeating unit in the first direction X and extends along the second direction Y.

[0133] In an exemplary embodiment, in at least one repeating unit, the data signal lines 70 in the first sub-pixel P1 and the second sub-pixel P2 and the data signal lines 70 in the third sub-pixel P3 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. The positions and shapes of the two first power lines 60 can be arranged substantially symmetrically with respect to the center line of the repeating unit. The orthographic projection of the compensation signal line 80 on the display substrate plane at least partially overlaps with the orthographic projection of the center line of the repeating unit on the display substrate plane.

[0134] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least: a first transparent conductive layer disposed on a substrate 200, a first conductive layer disposed on the side of the first transparent conductive layer away from the substrate 200, a first insulating layer 201 disposed on the side of the first conductive layer away from the substrate 200, a semiconductor layer disposed on the side of the first insulating layer 201 away from the substrate 200, a second insulating layer 202 disposed on the side of the semiconductor layer away from the substrate 200, a second conductive layer disposed on the side of the second insulating layer 202 away from the substrate 200, a third insulating layer 203 disposed on the side of the second conductive layer away from the substrate 200, a third conductive layer disposed on the side of the third insulating layer 203 away from the substrate 200, a fourth insulating layer 204 disposed on the side of the third conductive layer away from the substrate 200, a planarization layer 205 disposed on the side of the fourth insulating layer 204 away from the substrate 200, a second transparent conductive layer disposed on the side of the planarization layer 205 away from the substrate 200, and a pixel definition layer 206 disposed on the side of the second transparent conductive layer away from the substrate 200.

[0135] In an exemplary embodiment, the first transparent conductive layer may include at least a first electrode 11, the first conductive layer may include at least a power connection line 21, a compensation connection line 22, a shielding electrode 23 and an interlayer connection electrode 24, the semiconductor layer may include at least a second active layer 32, a third active layer 33 and a second electrode 34, the second conductive layer may include at least a second gate electrode 42 and a scan signal line 50, the third conductive layer may include at least a first connection electrode 51, a second connection electrode 52, a fourth connection electrode 54 and a fifth connection electrode 55, the second transparent conductive layer may include at least a first electrode 90, and the pixel definition layer may include at least a pixel opening 90A.

[0136] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes coating the organic material, mask exposure, and development. Deposition can be performed using sputtering, evaporation, or chemical vapor deposition (CVD); coating can be performed using spraying, spin coating, or inkjet printing; and etching can be performed using dry etching or wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0137] In an exemplary embodiment, taking a repeating unit comprising four sub-pixels (first sub-pixel P1, second sub-pixel P2, third sub-pixel P3 and fourth sub-pixel P4) as an example, the fabrication process of the display substrate in an exemplary embodiment of this disclosure may include the following operations.

[0138] (1) Forming a first transparent conductive layer pattern. In an exemplary embodiment, forming the first transparent conductive layer pattern may include: depositing a first transparent conductive film on a substrate, patterning the first transparent conductive film using a patterning process, and forming the first transparent conductive layer pattern on the substrate, such as... Figure 6As shown. In an exemplary embodiment, the first transparent conductive layer may be referred to as the ITO1 layer.

[0139] In an exemplary embodiment, the first transparent conductive layer pattern of each sub-pixel in the repeating unit may include at least a first electrode 11 of the storage capacitor, a connecting plate 12, and a connecting line 13.

[0140] In an exemplary embodiment, the first electrode plate 11 may be rectangular in shape, with chamfers or grooves at the corners and straight or broken edges. The first electrode plate 11 may be disposed in the middle region of the sub-pixel in the second direction Y. The first electrode plate 11 is configured as a transparent electrode plate forming a transparent storage capacitor.

[0141] In an exemplary embodiment, the connecting plate 12 may be block-shaped (e.g., rectangular), and may be disposed on one side of the first electrode plate 11 in the second direction Y and connected to the first electrode plate 11. The connecting plate 12 is configured to be connected to the subsequently formed shielding electrode.

[0142] In an exemplary embodiment, the connecting line 13 may be a strip extending along the second direction Y. The connecting line 13 may be disposed on the side of the first electrode plate 11 away from the connecting plate 12 and connected to the first electrode plate 11. A connecting block 13-1 may be disposed at the end of the connecting line 13 away from the first electrode plate 11. The connecting block 13-1 may be a strip extending along the first direction X and connected to the connecting line 13. The connecting block 13-1 is configured to connect to the subsequently formed interlayer connection electrode.

[0143] In an exemplary embodiment, the first electrode plate 11, the connecting plate 12, and the connecting line 13 of each sub-pixel can be an integral structure that is interconnected.

[0144] In an exemplary embodiment, the first transparent conductive layers in the first sub-pixel P1 and the second sub-pixel P2, and the first transparent conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4, can be arranged substantially symmetrically with respect to the center line of the repeating unit. For example, the positions and shapes of the first electrode plate 11, the connecting plate 12, and the connecting line 13 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. Similarly, the positions and shapes of the first electrode plate 11, the connecting plate 12, and the connecting line 13 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0145] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on a first transparent conductive layer, such as... Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A A planar schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0146] In an exemplary embodiment, the first conductive layer pattern of each sub-pixel in the repeating unit may include at least a blocking electrode 23 and an interlayer connection electrode 24.

[0147] In an exemplary embodiment, the shielding electrode 23 can be rectangular in shape, with chamfered or grooved corners and straight or broken edges. The shielding electrode 23 can be located in the middle region of the sub-pixel in the second direction Y. The orthographic projection of the shielding electrode 23 onto the substrate at least partially overlaps with the orthographic projection of the connecting plate 12 onto the substrate, and the shielding electrode 23 is directly connected to the connecting plate 12. In an exemplary embodiment, the shielding electrode 23 is configured to provide shielding for the second transistor T2, preventing light from affecting the channel region of the second transistor T2, reducing leakage current, thereby preventing the influence of light on the characteristics of the second transistor T2 and ensuring the electrical performance of the second transistor T2.

[0148] In an exemplary embodiment, the orthographic projection of the shielding electrode 23 on the substrate may be located within the range of the orthographic projection of the connecting plate 12 on the substrate, or the orthographic projection of the shielding electrode 23 on the substrate may include the orthographic projection of the connecting plate 12 on the substrate.

[0149] In an exemplary embodiment, the interlayer connection electrode 24 may be block-shaped (e.g., rectangular), and the orthographic projection of the interlayer connection electrode 24 on the substrate at least partially overlaps with the orthographic projection of the connection block 13-1 in the connection line 13 on the substrate, and the interlayer connection electrode 24 and the connection block 13-1 are directly connected. In an exemplary embodiment, the interlayer connection electrode 24 is configured to connect with a subsequently formed fourth connection electrode.

[0150] In an exemplary embodiment, the first conductive layer pattern of the repeating unit may further include a power connection line 21 and a compensation connection line 22.

[0151] In an exemplary embodiment, the power connection line 21 can be a strip extending along the first direction X, and can be disposed on the side of the shielding electrode 23 away from the interlayer connection electrode 24. One power connection line 21 can span across the first sub-pixel P1 and the second sub-pixel P2, and another power connection line 21 can span across the third sub-pixel P3 and the fourth sub-pixel P4. The power connection line 21 can be multiplexed as a power lateral connection line of a repeating unit, and provides power signals to the second transistor T2 of the second sub-pixel P2 and the third sub-pixel P3 by connecting with the subsequently formed first power line.

[0152] In an exemplary embodiment, the compensation connection line 22 can be a strip extending along the first direction X, and can be disposed on the side of the interlayer connection electrode 24 away from the blocking electrode 23. One compensation connection line 22 can span across the first sub-pixel P1 and the second sub-pixel P2, and another compensation connection line 22 can span across the third sub-pixel P3 and the fourth sub-pixel P4. The compensation connection line 22 can be multiplexed as a compensation lateral connection line of a repeating unit, and by connecting with subsequently formed compensation signal lines, provides compensation signals to the third transistor T3 of the first sub-pixel P1 to the fourth sub-pixel P4.

[0153] In an exemplary embodiment, at least one repeating unit may further include a compensation connecting block 22-1. The compensation connecting block 22-1 may be in the shape of a broken line extending along the first direction X, and may be disposed between two compensation connecting lines 22, with both ends of the compensation connecting block 22-1 connected to the two compensation connecting lines 22 respectively.

[0154] In an exemplary embodiment, in at least one repeating unit, the compensation connection line 22 and compensation connection block 22-1 in the first sub-pixel P1 and the second sub-pixel P2, and the compensation connection line 22 in the third sub-pixel P3 and the fourth sub-pixel P4 can be an integral structure that is interconnected.

[0155] In an exemplary embodiment, the first conductive layers in the first sub-pixel P1 and the second sub-pixel P2, and the first conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4, can be arranged substantially symmetrically with respect to the center line of the repeating unit. For example, the positions and shapes of the power connection line 21, compensation connection line 22, blocking electrode 23, and interlayer connection electrode 24 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. Similarly, the positions and shapes of the power connection line 21, compensation connection line 22, blocking electrode 23, and interlayer connection electrode 24 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0156] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the semiconductor film using a patterning process to form a first insulating layer covering a first conductive layer; and a semiconductor layer pattern disposed on the first insulating layer, such as... Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A A planar schematic diagram of the semiconductor layer.

[0157] In an exemplary embodiment, the semiconductor layer pattern of each sub-pixel in the repeating unit may include at least a first active layer 31, a second active layer 32, a third active layer 33, and a second electrode plate 34.

[0158] In an exemplary embodiment, the second electrode plate 34 may be rectangular in shape, with chamfers or grooves at the corners and straight or broken edges. The orthographic projection of the second electrode plate 34 onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 onto the substrate. The second electrode plate 34 is configured to form another transparent electrode plate of a transparent storage capacitor, and the first electrode plate 11 and the second electrode plate 34 constitute a transparent storage capacitor.

[0159] In an exemplary embodiment, the first active layer 31 can serve as the active layer of the first transistor T1, the second active layer 32 can serve as the active layer of the second transistor T2, and the third active layer 33 can serve as the active layer of the third transistor T3. The first active layer 31 and the third active layer 33 can be disposed on the side of the second electrode plate 34 away from the power connection line 21, and the second active layer 32 can be disposed on the side of the second electrode plate 34 close to the power connection line 21.

[0160] In an exemplary embodiment, the first active layer 31, the second active layer 32, and the third active layer 33 may each include a channel region and a first region and a second region located on both sides of the channel region.

[0161] In an exemplary embodiment, the first active layer 31 may be in the shape of an "I" shape, the first region 31-1 of the first active layer may be located on the side of the channel region of the first active layer away from the second electrode plate 34, and the second region 31-2 of the first active layer may be located on the side of the channel region of the first active layer close to the second electrode plate 34.

[0162] In an exemplary embodiment, the first active layer 31 may be provided with an electrode connecting strip 31-1. The shape of the electrode connecting strip 31-1 may be a strip extending along the second direction Y, and it may be disposed between the first active layer 31 and the second electrode 34. The first end of the electrode connecting strip 31-1 is connected to the second region 31-2 of the first active layer, and the second end of the electrode connecting strip 31-1 is connected to the second electrode 34.

[0163] In an exemplary embodiment, the first active layer 31, the electrode connecting strip 31-1, and the second electrode 34 can be an integral structure that is interconnected.

[0164] In an exemplary embodiment, the second active layer 32 may be L-shaped, and the orthographic projection of the second active layer 32 onto the substrate at least partially overlaps with the orthographic projection of the shielding electrode 23 onto the substrate. In the first sub-pixel P1 and the second sub-pixel P2, the first region 32-1 of the second active layer may be located on the side opposite to the first direction X of the channel region of the second active layer, and the second region 32-2 of the second active layer may be located on the side of the first direction X of the channel region of the second active layer. In the third sub-pixel P3 and the fourth sub-pixel P4, the first region 32-1 of the second active layer may be located on the side of the first direction X of the channel region of the second active layer, and the second region 32-2 of the second active layer may be located on the side opposite to the first direction X of the channel region of the second active layer.

[0165] In an exemplary embodiment, the orthographic projection of the channel region of the second active layer and the second region 32-2 of the second active layer onto the substrate can be located within the range of the orthographic projection of the shielding electrode 23 onto the substrate. The shielding electrode 23 can shield the channel region of the second active layer 32, preventing light from affecting the channel, reducing leakage current, and thus preventing the influence of light on the transistor characteristics.

[0166] In an exemplary embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the first region 32-1 of the second active layer on the substrate does not overlap with the orthographic projection of the shielding electrode 23 on the substrate. In the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the first region 32-1 of the second active layer on the substrate can be located within the range of the orthographic projection of the shielding electrode 23 on the substrate.

[0167] In an exemplary embodiment, the third active layer 33 may be I-shaped, with its orthographic projection on the substrate and the second electrode 34 on the substrate spaced apart, meaning there is no overlapping area between the third active layer 33 and the second electrode 42. This facilitates the design of the channel aspect ratio of the third transistor according to relevant requirements. The first region 33-1 of the third active layer may be located on the side of the channel region of the third active layer away from the second electrode 34, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the compensation connection line 22 on the substrate. The second region 33-2 of the third active layer may be located on the side of the channel region of the third active layer closer to the second electrode 34, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the interlayer connection electrode 24 on the substrate.

[0168] In an exemplary embodiment, the semiconductor layer may be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0169] In an exemplary embodiment, the semiconductor layers in the first sub-pixel P1 and the second sub-pixel P2, and the semiconductor layers in the third sub-pixel P3 and the fourth sub-pixel P4, can be arranged substantially symmetrically with respect to the center line of the repeating unit. For example, the positions and shapes of the first active layer 31, the second active layer 32, the third active layer 33, and the second electrode 34 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. Similarly, the positions and shapes of the first active layer 31, the second active layer 32, the third active layer 33, and the second electrode 34 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0170] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film and the second insulating film using a patterning process to form a second insulating layer disposed on a semiconductor layer, and a second conductive layer pattern disposed on the second insulating layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as a gate metal (GATE) layer.

[0171] In an exemplary embodiment, the second conductive layer pattern of each sub-pixel in the repeating unit may include at least a second gate electrode 42 and a scan signal line 50.

[0172] In an exemplary embodiment, the scan signal line 50 may be a strip extending along a first direction X, and may be located between the compensation connection line 22 and the second electrode 34. The orthographic projection of the scan signal line 50 onto the substrate at least partially overlaps with the orthographic projection of the first active layer 31 in each sub-pixel onto the substrate, and the scan signal line 50 in the overlapping region may serve as the gate electrode of the first transistor T1. The orthographic projection of the scan signal line 50 onto the substrate at least partially overlaps with the orthographic projection of the third active layer 33 in each sub-pixel onto the substrate, and the scan signal line 50 in the overlapping region may serve as the gate electrode of the third transistor T3.

[0173] In an exemplary embodiment, the scan signal line 50 may be configured with a non-uniform width, the width of which is the dimension of the scan signal line 50 in the second direction Y. The scan signal line 50 may include a first region that overlaps with the first active layer 31 and the third active layer 33, and a second region that does not overlap with the first active layer 31 and the third active layer 33, wherein the width of the first region may be smaller than the width of the second region.

[0174] In an exemplary embodiment, in the second region of the scan signal line 50, a plurality of vias 50-1 may be provided on the scan signal line 50. The vias 50-1 may be strip-shaped extending along the first direction X. The orthographic projection of the vias 50-1 on the substrate at least partially overlaps with the orthographic projection of the subsequently formed first power line, data signal line or compensation signal line on the substrate. The vias 50-1 are configured to reduce the parasitic capacitance between the scan signal line 50 and the first power line, data signal line or compensation signal line.

[0175] In an exemplary embodiment, in at least one sub-pixel, a scan signal line 50 can simultaneously serve as the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3.

[0176] In an exemplary embodiment, in at least one repeating unit, the gate electrodes of four first transistors T1 in the multiple sub-pixels are connected to the same scan signal line 50. The scan signal line 50 can simultaneously serve as the gate electrode of the four first transistors T1. The scan signal line 50 is configured to simultaneously control the on or off state of all the first transistors T1 in the four sub-pixels of the repeating unit.

[0177] In an exemplary embodiment, in at least one repeating unit, the gate electrodes of four third transistors T3 in the multiple sub-pixels are connected to the same scan signal line 50. The scan signal line 50 can simultaneously serve as the gate electrode of all four third transistors T3. The scan signal line 50 is configured to simultaneously control the on or off state of all the third transistors T3 in the four sub-pixels of the repeating unit.

[0178] In an exemplary embodiment, in at least one repeating unit, the gate electrodes of four first transistors T1 and the gate electrodes of four third transistors T3 are connected to the same scan signal line 50 in the multiple sub-pixels of the repeating unit. The scan signal line 50 can simultaneously serve as the gate electrode of the four first transistors T1 and the gate electrode of the four third transistors T3. The scan signal line 50 is configured to simultaneously control the conduction or disconnection of all first transistors T1 and all third transistors T3 in the four sub-pixels of the repeating unit.

[0179] In an exemplary embodiment, in at least one pixel row of multiple sub-pixels, a scan signal line 50 can simultaneously serve as the gate electrode of multiple first transistors T1 and multiple third transistors T3.

[0180] In an exemplary embodiment, the second gate electrode 42 may be a strip extending along the second direction Y, and the second gate electrode 42 may serve as the gate electrode of the second transistor T2. On one hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer 32 on the substrate, and the overlapping region of the second active layer 32 is the channel region of the second active layer. On the other hand, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 34 on the substrate.

[0181] In an exemplary embodiment, the second conductive layers in the first sub-pixel P1 and the second sub-pixel P2, and the second conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4, can be arranged substantially symmetrically with respect to the center line of the repeating unit. For example, the positions and shapes of the second gate electrode 42 and the scan signal line 50 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. Similarly, the positions and shapes of the second gate electrode 42 and the scan signal line 50 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0182] In an exemplary embodiment, the pattern of the second insulating layer and the pattern of the second conductive layer formed by this process can be substantially the same, that is, the orthographic projection of the second insulating layer on the substrate and the orthographic projection of the second conductive layer on the substrate can be substantially the same.

[0183] In an exemplary embodiment, the process further includes a conductor-enhancing process. The conductor-enhancing process involves, after forming the second conductive layer pattern, performing plasma treatment using the second conductive layer as a shield. The semiconductor layer shielded by the second conductive layer serves as the channel region of the transistor, while the semiconductor layer not shielded by the second conductive layer is processed into a conductor-enhanced layer, forming a conductor-enhanced second electrode and conductor-enhanced first and second regions.

[0184] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein the third insulating layer has a plurality of vias, such as... Figure 10 As shown.

[0185] In an exemplary embodiment, the plurality of vias in each sub-pixel of the repeating unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, and a seventh via V7.

[0186] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate may be within the range of the orthographic projection of the first region of the first active layer onto the substrate. The third and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow subsequently formed data signal lines to be connected to the first region of the first active layer through the via.

[0187] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate may be within the range of the orthographic projection of the second region of the first active layer onto the substrate. The third insulating layer and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer. The second via V2 is configured to allow a subsequently formed third connection electrode to be connected to the second region of the first active layer through the via.

[0188] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate may be located within the range of the orthographic projection of the first region of the second active layer onto the substrate. The third and second insulating layers within the third via V3 are etched away, exposing the surface of the first region of the second active layer. The third via V3 is configured to allow a subsequently formed first power line or power connection electrode to connect to the first region of the second active layer through this via. In an exemplary embodiment, the third via V3 may serve as a power via of this disclosure.

[0189] In an exemplary embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the third via V3 on the substrate does not overlap with the orthographic projection of the shielding electrode 23 on the substrate.

[0190] In an exemplary embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the third via V3 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 23 on the substrate.

[0191] In an exemplary embodiment, the orthogonal projection of the third via V3 onto the substrate in the second sub-pixel P2 and the third sub-pixel P3 can be located within the range of the orthogonal projection of the shielding electrode 23 onto the substrate.

[0192] In an exemplary embodiment, the fourth via V4 can be located on one side of the second electrode plate 34 in the second direction Y. The orthographic projection of the fourth via V4 on the substrate simultaneously overlaps at least partially with the orthographic projections of the second region of the second active layer and the shielding electrode 23 on the substrate. The fourth via V4 is a transition via consisting of two half-holes. One half-hole is formed on the second region of the second active layer, and the third and second insulating layers within this half-hole are etched away to expose the surface of the second region of the second active layer. The other half-hole is formed on the shielding electrode 23, and the third, second, and first insulating layers within this half-hole are etched away to expose the surface of the shielding electrode 23. This allows the transition via consisting of the two half-holes to simultaneously expose the second region of the second active layer and the surface of the shielding electrode 23. In an exemplary embodiment, the fourth via V4 is configured to allow a subsequently formed second connection electrode to simultaneously connect to the second region of the second active layer and the shielding electrode 23 through this via. The fourth via V4 can serve as a node via of this disclosure.

[0193] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate simultaneously overlaps at least partially with the orthographic projections of the first region of the third active layer and the compensation connection line 22 onto the substrate. The fifth via V5 is a transition via consisting of two half-holes. One half-hole is formed on the first region of the third active layer, where the third and second insulating layers are etched away to expose the surface of the first region of the third active layer. The other half-hole is formed on the compensation connection line 22, where the third, second, and first insulating layers are etched away to expose the surface of the compensation connection line 22. This results in the transition via consisting of the two half-holes simultaneously exposing the surfaces of the first region of the third active layer and the compensation connection line 22. In an exemplary embodiment, the fifth via V5 is configured to allow a subsequently formed fifth connection electrode to be simultaneously connected to the first region of the third active layer and the compensation connection line 22 through this via.

[0194] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate simultaneously overlaps at least partially with the orthographic projections of the second region of the third active layer and the interlayer connection electrode 24 onto the substrate. The sixth via V6 is a transition via consisting of two half-holes. One half-hole is formed on the second region of the third active layer, where the third and second insulating layers are etched away to expose the surface of the second region of the third active layer. The other half-hole is formed on the interlayer connection electrode 24, where the third, second, and first insulating layers are etched away to expose the surface of the interlayer connection electrode 24. This results in the transition via consisting of the two half-holes simultaneously exposing the second region of the third active layer and the surface of the interlayer connection electrode 24. In an exemplary embodiment, the sixth via V6 is configured to allow a subsequently formed fourth connection electrode to be simultaneously connected to the second region of the third active layer and the interlayer connection electrode 24 through this via.

[0195] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate at least partially overlaps with the orthographic projections of the second electrode 34 and the second gate electrode 42 onto the substrate. The seventh via V7 is a transition via consisting of two half-holes. One half-hole is formed on the second electrode 34, where the third and second insulating layers are etched away to expose the surface of the second electrode 34. The other half-hole is formed on the second gate electrode 42, where the third insulating layer is etched away to expose the surface of the second gate electrode 42. This results in a transition via consisting of two half-holes that simultaneously exposes the surfaces of the second electrode 34 and the second gate electrode 42. In an exemplary embodiment, the seventh via V7 is configured to allow a subsequently formed first connection electrode to connect simultaneously to the second electrode 34 and the second gate electrode 42 through this via. The seventh via V7 can serve as the first transition via of this disclosure.

[0196] In an exemplary embodiment, in the seventh via V7, the orthographic projection of the second gate electrode 42 onto the substrate at least partially overlaps with the orthographic projection of the second electrode plate 34 onto the substrate. Studies have shown that if the second electrode plate 34 and the second gate electrode 42 within the seventh via V7 do not overlap, over-etching is likely to occur during the dry etching process of the via. Over-etching exposes the shielding electrode 23, causing the subsequently formed first connection electrode to connect with the shielding electrode 23, resulting in a short circuit and causing dark spot defects. This disclosure effectively avoids short circuits and dark spot defects by ensuring that the second electrode plate 34 and the second gate electrode 42 overlap within the first transition via.

[0197] In an exemplary embodiment, the repeating unit may further include an eighth via V8, a ninth via V9, and a tenth via V10.

[0198] In an exemplary embodiment, an eighth via V8 may be disposed between the first sub-pixel P1 and the fourth sub-pixel P4. The orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first end of the power connection line 21 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the eighth via V8 are etched away, exposing the surface of the first end of the power connection line 21. The eighth via V8 is configured to allow a subsequently formed first power line to be connected to the first end of the power connection line 21 through the via.

[0199] In an exemplary embodiment, a ninth via V9 may be disposed between the second sub-pixel P2 and the third sub-pixel P3. The orthographic projection of the ninth via V9 onto the substrate is located within the range of the orthographic projection of the second end of the power connection line 21 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the ninth via V9 are etched away, exposing the surface of the second end of the power connection line 21. The ninth via V9 is configured to allow a subsequently formed power connection electrode to be connected to the second end of the power connection line 21 through the via.

[0200] In an exemplary embodiment, the tenth via V10 may be disposed between the second sub-pixel P2 and the third sub-pixel P3. The orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the compensation connection block 22-1 on the substrate. The third insulating layer, the second insulating layer and the first insulating layer in the tenth via V10 are etched away to expose the surface of the compensation connection block 22-1. The tenth via V10 is configured to allow the subsequently formed compensation signal line to be connected to the compensation connection block 22-1 through the via.

[0201] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the third conductive thin film using a patterning process, and forming a third conductive layer disposed on a third insulating layer, such as... Figure 11A and Figure 11B As shown, Figure 11B for Figure 11A A schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the source / drain metal (SD) layer.

[0202] In an exemplary embodiment, the third conductive layer pattern of each sub-pixel in the repeating unit includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, and a fifth connecting electrode 55.

[0203] In an exemplary embodiment, the first connecting electrode 51 can be a strip extending along the second direction Y. The first connecting electrode 51 is connected to the second electrode plate 34 and the second gate electrode 42 simultaneously through the seventh via V7, realizing that the gate electrode of the second transistor T2 and the second electrode plate 34 of the storage capacitor have the same potential. Since the second gate electrode 42 and the second electrode plate 34 overlap in the seventh via V7, the seventh via V7 will not be over-etched and expose the shielding electrode 23, thus effectively avoiding short circuits between the second gate electrode 42 and the second electrode plate 34 and the shielding electrode 23, and effectively avoiding dark spot defects.

[0204] In an exemplary embodiment, the second connection electrode 52 can be a strip extending along the second direction Y. The second connection electrode 52 is simultaneously connected to the second region of the second active layer and the shielding electrode 23 via the fourth via V4. Since the shielding electrode 23 overlaps with the connecting plate 12, and the connecting plate 12 is connected to the first electrode plate 11, the second connection electrode 52 ensures that the second electrode of the second transistor T2 and the first electrode plate 11 of the storage capacitor have the same potential. In an exemplary embodiment, the second connection electrode 52 can serve as a node electrode of this disclosure.

[0205] In an exemplary embodiment, the second connection electrode 52 includes a first sub-electrode 52-1 and a second sub-electrode 52-2. The first sub-electrode 52-1 and the second sub-electrode 52-2 can be block-shaped (e.g., rectangular). The second sub-electrode 52-2 can be disposed on the side of the first sub-electrode 52-1 away from the second electrode plate 34 and connected to the first sub-electrode 52-1. The first sub-electrode 52-1 is simultaneously connected to the second region of the second active layer and the shielding electrode 23 through a fourth via V4. The second sub-electrode 52-2 is configured to connect to the subsequently formed first electrode.

[0206] In an exemplary embodiment, the third connecting electrode 53 may be block-shaped (e.g., rectangular), and is connected to the second region of the first active layer via the second via V2. Since the second region of the first active layer is connected to the second electrode 34 via the electrode connecting strip 31-1, the third connecting electrode 53 enables the second electrode of the first transistor T1 and the second electrode 34 of the storage capacitor to have the same potential.

[0207] In an exemplary embodiment, since the first connection electrode 51 realizes that the gate electrode of the second transistor T2 and the second plate 34 of the storage capacitor have the same potential, and the third connection electrode 53 realizes that the second electrode of the first transistor T1 and the second plate 34 of the storage capacitor have the same potential, the first connection electrode 51 and the third connection electrode 53 realize that the second electrode of the first transistor T1, the gate electrode of the second transistor T2 and the second plate 34 of the storage capacitor have the same potential, that is, the potential of the first node N1 in the pixel driving circuit.

[0208] In an exemplary embodiment, the fourth connection electrode 54 can be a strip shape extending along the second direction Y. The fourth connection electrode 54 is simultaneously connected to the second region of the third active layer and the interlayer connection electrode 24 through the sixth via V6. Since the interlayer connection electrode 24 is connected to the connection line 13, and the connection line 13 is connected to the first electrode plate 11, the fourth connection electrode 54 enables the second electrode of the third transistor T3 and the first electrode plate 11 of the storage capacitor to have the same potential.

[0209] In an exemplary embodiment, since the second connection electrode 52 realizes that the second pole of the second transistor T2 and the first plate 11 of the storage capacitor have the same potential, and the fourth connection electrode 54 realizes that the second pole of the third transistor T3 and the first plate 11 of the storage capacitor have the same potential, the second connection electrode 52 and the fourth connection electrode 54 realize that the second pole of the second transistor T2, the second pole of the third transistor T3 and the first plate 11 of the storage capacitor have the same potential, that is, the potential of the second node N2 in the pixel driving circuit.

[0210] In an exemplary embodiment, the fifth connection electrode 55 can be a strip shape extending along the second direction Y. The fifth connection electrode 55 is simultaneously connected to the first region of the third active layer and the compensation connection line 22 through the fifth via V5. Since the compensation connection line 22 is configured to be connected to the compensation signal line, the fifth connection electrode 55 enables the compensation signal line to write the compensation signal to the first pole of the third transistor T3 of each sub-pixel.

[0211] In an exemplary embodiment, the third conductive layer pattern of the repeating unit may further include a power connection electrode 56, a first power line 60, and a compensation signal line 80.

[0212] In an exemplary embodiment, the shape of the first power line 60 can be a straight line or a broken line extending along the second direction Y, and can be respectively disposed on the side of the first sub-pixel P1 away from the second sub-pixel P2 and the side of the fourth sub-pixel P4 away from the third sub-pixel P3. On one hand, the first power line 60 is connected to the first region of the second active layer through the third via V3 (power via), realizing that the first power line 60 writes the first power signal into the first terminal of the second transistor T2 in the first sub-pixel P1 and the fourth sub-pixel P4. On the other hand, the first power line 60 is connected to the first end of the power connection line 21 through the eighth via V8, realizing that the first power line 60 located in the first sub-pixel P1 transmits the power signal to the second sub-pixel P2 through the power connection line 21, and realizing that the first power line 60 located in the fourth sub-pixel P4 can transmit the power signal to the third sub-pixel P3 through the power connection line 21.

[0213] In an exemplary embodiment, the first power line 60 can be a straight line or a broken line with non-uniform width, which not only facilitates the layout of the pixel structure, but also reduces parasitic capacitance.

[0214] In an exemplary embodiment, the power connection electrode 56 can be a strip extending along the second direction Y, and can be disposed in the second sub-pixel P2 and the third sub-pixel P3 respectively. The first end of the power connection electrode 56 is connected to the first region of the second active layer through the third via V3 (power via), and the second end of the power connection electrode 56 is connected to the second end of the power connection line 21 through the ninth via V9. Since the first end of the power connection line 21 is connected to the first power line 60, the first power line 60 writes the first power signal into the first electrode of the second transistor T2 in the second sub-pixel P2 and the third sub-pixel P3.

[0215] In an exemplary embodiment, the first power line 60 in the first sub-pixel P1 can be connected to the first region of the second active layer through the third via V3, and simultaneously connected to the first end of the power connection line 21 through the eighth via V8. The first end of the power connection electrode 56 in the second sub-pixel P2 can be connected to the first region of the second active layer through the third via V3, and the second end of the power connection electrode 56 can be connected to the second end of the power connection line 21 through the ninth via V9. That is, the first power line 60 in the first sub-pixel P1 is connected to the first region of the second active layer in the second sub-pixel P2 through the power connection line 21 and the power connection electrode 56. The first power line 60 in the fourth sub-pixel P4 can be connected to the first region of the second active layer through the third via V3, and simultaneously connected to the first end of the power connection line 21 through the eighth via V8. The first end of the power connection electrode 56 in the third sub-pixel P3 is connected to the first region of the second active layer through the third via V3, and the second end of the power connection electrode 56 is connected to the second end of the power connection line 21 through the ninth via V9. That is, the first power line 60 in the fourth sub-pixel P4 is connected to the first region of the second active layer in the third sub-pixel P3 through the power connection line 21 and the power connection electrode 56. Thus, the first power line 60 in the first sub-pixel P1 can provide power signals to the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2, and the first power line 60 in the fourth sub-pixel P4 can provide power signals to the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4. This disclosure achieves the writing of power signals into the second transistor T2 of the four sub-pixels by setting two power connection lines 21 extending along the first direction X and two first power lines 60 extending along the second direction Y in the repeating unit, forming a one-to-two structure of the first power line.

[0216] In an exemplary embodiment, the compensation signal line 80 can be a straight line or a broken line extending along the second direction Y of the main body, and can be disposed between the second sub-pixel P2 and the third sub-pixel P3. The compensation signal line 80 is connected to the compensation connection block 22-1 through the tenth via V10. Since the compensation connection block 22-1 is connected to the compensation connection line 22 located in the first sub-pixel P1 and the second sub-pixel P2 on one hand, and to the compensation connection line 22 located in the third sub-pixel P3 and the fourth sub-pixel P4 on the other hand, one compensation connection line 22 is connected to the first electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2 through the fifth connection electrode 55, and the other compensation connection line 22 is connected to the first electrode of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4 through the fifth connection electrode 55. In this way, one compensation signal line 80 can provide compensation signals to the pixel driving circuits of four sub-pixels, forming a one-to-four structure of the compensation signal line.

[0217] This disclosure achieves the writing of compensation signals into the third transistor T3 of the four sub-pixels by setting a compensation signal line 80 extending along the second direction Y and two compensation connection lines 22 extending along the first direction X in the repeating unit. This ensures that the RC delay of the compensation signals is basically the same before they are written into the transistors, thus guaranteeing display uniformity.

[0218] In an exemplary embodiment, the third conductive layer pattern of each sub-pixel in the repeating unit may further include a data signal line 70.

[0219] In an exemplary embodiment, the data signal line 70 can be a zigzag shape in which the main body extends along the second direction Y. The data signal line 70 is connected to the first region of the first active layer through the first via V1, thereby enabling the data signal line 70 to write the data signal into the first electrode of the first transistor T1.

[0220] In an exemplary embodiment, in the first sub-pixel P1 and the third sub-pixel P3, the data signal line 70 may be disposed on one side of the storage capacitor (first electrode 11 and second electrode 34) in the first direction X. In the second sub-pixel P2 and the fourth sub-pixel P4, the data signal line 70 may be disposed on the side opposite to the first direction X of the storage capacitor.

[0221] In an exemplary embodiment, in at least one sub-pixel, the data signal line 70 may include a first sub-line 70-1, a second sub-line 70-2, and a third sub-line 70-3. The first sub-line 70-1 and the second sub-line 70-2 are straight lines extending along a second direction Y, and the third sub-line 70-3 is a straight line or a broken line extending along an inclined direction. The third sub-line 70-3 may be disposed between the first sub-line 70-1 and the second sub-line 70-2. The first end of the third sub-line 70-3 is connected to the first sub-line 70-1, and the second end of the third sub-line 70-3 is connected to the second sub-line 70-2.

[0222] In an exemplary embodiment, in at least one sub-pixel of the first sub-pixel P1 and the fourth sub-pixel P4, a first distance L1 may exist between the first sub-line 70-1 and the first power line 60, and a second distance L2 may exist between the second sub-line 70-2 and the first power line 60. The first distance L1 may be greater than the second distance L2. The first distance L1 may be the distance between the edge of the first sub-line 70-1 near the first power line 60 and the edge of the first power line 60 near the first sub-line 70-1, and is a dimension in the first direction X. The second distance L2 may be the distance between the edge of the second sub-line 70-2 near the first power line 60 and the edge of the first power line 60 near the second sub-line 70-2, and is a dimension in the first direction X.

[0223] In an exemplary embodiment, in at least one sub-pixel of the second sub-pixel P2 and the third sub-pixel P3, a third distance L3 may exist between the first sub-line 70-1 and the compensation signal line 80, and a fourth distance L4 may exist between the second sub-line 70-2 and the compensation signal line 80. The third distance L3 may be less than the fourth distance L4. The third distance L3 may be the distance between the edge of the first sub-line 70-1 near the compensation signal line 80 and the edge of the compensation signal line 80 near the first sub-line 70-1, and is a dimension in the first direction X. The fourth distance L4 may be the distance between the edge of the second sub-line 70-2 near the compensation signal line 80 and the edge of the compensation signal line 80 near the second sub-line 70-2, and is a dimension in the first direction X.

[0224] In an exemplary embodiment, the first distance L1 may be equal to the third distance L3.

[0225] In an exemplary embodiment, since the second sub-pixel P2 and the third sub-pixel P3 are provided with a power connection line 21 and a power connection electrode 56 to connect the first region of the second active layer to the first power line 60, while the first region of the second active layer in the first sub-pixel P1 and the fourth sub-pixel P4 is directly connected to the first power line 60, the layout space requirements of the second sub-pixel P2 and the third sub-pixel P3 are relatively large, while the layout space requirements of the first sub-pixel P1 and the fourth sub-pixel P4 are relatively small. This disclosure, by providing a zigzag-shaped data signal line 70, with the zigzag portion bending away from the compensation signal line 80, can effectively increase the area of ​​the second sub-pixel P2 and the third sub-pixel P3, satisfying the layout space requirements of the second sub-pixel P2 and the third sub-pixel P3, which is beneficial for achieving high-resolution display.

[0226] In an exemplary embodiment, the data signal line 70 can be a polygonal line with equal or non-equal width, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0227] In an exemplary embodiment, the third conductive layers in the first sub-pixel P1 and the second sub-pixel P2, and the third conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4, can be arranged substantially symmetrically with respect to the center line of the repeating unit. For example, the positions and shapes of the first connecting electrode 51 to the fifth connecting electrode 55, the power connecting electrode 56, the first power line 60, the data signal line 70, and the compensation signal line 80 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. Similarly, the positions and shapes of the first connecting electrode 51 to the fifth connecting electrode 55, the power connecting electrode 56, the first power line 60, the data signal line 70, and the compensation signal line 80 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0228] (7) Forming a fourth insulating layer and a planarization layer pattern. In an exemplary embodiment, forming the fourth insulating layer and planarization layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, then coating a planarization film, and patterning the planarization film and the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, and a planarization layer disposed on the fourth insulating layer, wherein the planarization layer and the fourth insulating layer have a plurality of vias, such as... Figure 12 As shown.

[0229] In an exemplary embodiment, the plurality of vias in each sub-pixel of the repeating unit includes at least an anode via YV.

[0230] In an exemplary embodiment, the orthographic projection of the anode via YV onto the substrate is within the range of the orthographic projection of the second sub-electrode 52-2 in the second connecting electrode 52 onto the substrate. The planarization layer and the fourth insulating layer within the anode via YV are removed, exposing the surface of the second sub-electrode 52-2. The anode via YV is configured to allow a subsequently formed first electrode to be connected to the second sub-electrode 52-2 through the via.

[0231] In an exemplary embodiment, the orthographic projection of the anode via YV onto the substrate does not overlap with the orthographic projection of the fourth via V4 (node ​​via) onto the substrate, and the anode via YV is located on the side of the fourth via V4 away from the second electrode plate 34.

[0232] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the anode via YV onto the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer onto the display substrate plane.

[0233] In some other embodiments, the display substrate may include a color filter layer. On a substrate with the aforementioned pattern, a fourth insulating layer is first formed, and then a color filter layer is formed on the fourth insulating layer. Subsequently, a planarization film is coated to form a fourth insulating layer covering a third conductive layer, a color filter layer disposed on the fourth insulating layer, and a planarization layer covering the color filter layer. The fourth insulating layer, color filter layer, and planarization layer in the anode via are removed to expose the surface of the second connecting electrode.

[0234] (8) Forming a second transparent conductive layer pattern. In an exemplary embodiment, forming a second transparent conductive layer pattern may include: depositing a second transparent conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second transparent conductive film using a patterning process to form a second transparent conductive layer pattern disposed on a planarization layer, such as... Figure 13 As shown.

[0235] In an exemplary embodiment, the second transparent conductive layer pattern of each sub-pixel in the repeating unit includes at least a first electrode 90.

[0236] In an exemplary embodiment, the first electrode 90 may be a strip extending along the second direction Y. A protrusion is provided on one side of the first electrode 90 in the second direction Y, and the protrusion is connected to the second sub-electrode 52-2 through an anode via YV. Since the second connecting electrode 52, which includes the second sub-electrode 52-2, has the potential of the second node N2 in the pixel driving circuit, the connection between the first electrode 90 and the second node N2 is realized.

[0237] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the first electrode 90 on the substrate at least partially overlaps with the orthographic projection of the storage capacitor (first electrode 11 and second electrode 34) in the sub-pixel on the substrate.

[0238] In an exemplary embodiment, in at least one sub-pixel, the orthogonal projection of the first electrode 90 onto the substrate may include the orthogonal projection of the storage capacitor in that sub-pixel onto the substrate.

[0239] In an exemplary embodiment, the second transparent conductive layers in the first sub-pixel P1 and the second sub-pixel P2, and the second transparent conductive layers in the third sub-pixel P3 and the fourth sub-pixel P4, can be arranged substantially symmetrically with respect to the center line of the repeating unit. For example, the position and shape of the first electrode 90 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. Similarly, the position and shape of the first electrode 90 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0240] (9) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer pattern, such as... Figure 14 As shown.

[0241] In an exemplary embodiment, the pixel definition layer pattern of each sub-pixel in the repeating unit includes at least a pixel opening 90A.

[0242] In an exemplary embodiment, the shape of the pixel opening 90A can be a strip shape extending along the second direction Y, and the orthographic projection of the pixel opening 90A on the substrate can be located within the range of the orthographic projection of the first electrode 90 on the substrate. The pixel definition film within the pixel opening 90A is removed, exposing the surface of the first electrode 90.

[0243] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the pixel opening 90A onto the substrate at least partially overlaps with the orthographic projection of the storage capacitor in the sub-pixel onto the substrate.

[0244] In an exemplary embodiment, in at least one sub-pixel, the fourth via V4 (node ​​via) may be located on one side of the second direction Y of the pixel opening 90A, and the orthographic projection of the fourth via V4 on the substrate does not overlap with the orthographic projection of the pixel opening 90A on the substrate.

[0245] In an exemplary embodiment, in at least one sub-pixel, the anode via YV can be located on one side of the fourth via V4 in the second direction Y, that is, the anode via YV can be located on the side of the fourth via V4 away from the pixel opening 90A, and the orthographic projection of the anode via YV on the substrate does not overlap with the orthographic projection of the pixel opening 90A on the substrate.

[0246] In an exemplary embodiment, the shape and area of ​​the pixel apertures of different sub-pixels can be different. By designing the four sub-pixels with different aperture ratios, the exemplary embodiment of this disclosure can adapt to the transmittance of different sub-pixel color filter layers, enabling the light-emitting devices of the four sub-pixels to emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring product lifespan.

[0247] In an exemplary embodiment, the shape of the pixel opening may include any one or more of the following: triangle, rectangle, trapezoid, parallelogram, pentagon, hexagon, circle, and ellipse.

[0248] In an exemplary embodiment, subsequent fabrication processes may include: forming an organic light-emitting layer using vapor deposition or inkjet printing; the organic light-emitting layer being connected to a first electrode through pixel openings; forming a second electrode on the organic light-emitting layer; and connecting the second electrode to the organic light-emitting layer. An encapsulation structure layer is then formed, which may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0249] Thus, a driving circuit layer, a light-emitting structure layer disposed on the driving circuit layer, and an encapsulation structure layer disposed on the light-emitting structure layer are fabricated on the substrate. In a plane perpendicular to the display substrate, the driving circuit layer may include a first transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a planarization layer, sequentially stacked on the substrate. The light-emitting structure layer may include a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, stacked on the substrate.

[0250] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, while the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0251] In an exemplary embodiment, the first and second transparent conductive layers can be made of transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first, second, and third conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first, second, third, and fourth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The planarization layer can be made of organic materials, such as resin, and the pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate.

[0252] According to the research of the inventors of this application, in a bottom-emitting OLED display device, when the pixel opening is close to the anode via, a waveguide effect is formed between the first electrode (ITO) in the anode via and the pixel opening. As a result, some of the light from the light-emitting device will be emitted from the boundary of the planarization layer, causing display defects such as watermarks to appear in the OLED display device.

[0253] An exemplary embodiment of this disclosure provides a display substrate that, by placing node vias near the pixel openings and anode vias away from the pixel openings, can not only effectively reduce light leakage and eliminate display defects such as watermarks, but also ensure the maximization of pixel openings, effectively improve image retention, and enhance display quality.

[0254] This disclosure effectively avoids short circuits and dark spot defects by setting the orthogonal projection of the second gate electrode on the substrate to at least partially overlap with the orthogonal projection of the second electrode plate on the substrate.

[0255] This disclosure achieves differentiated design of sub-pixels within repeating units by setting a zigzag-shaped data signal line, with the zigzag portion bending away from the compensation signal line. This effectively increases the area of ​​the second and third sub-pixels, meets the layout space requirements of the second and third sub-pixels, and is beneficial for achieving high resolution and high aperture ratio displays.

[0256] This disclosure employs a transparent storage capacitor, which consists of a transparent first transparent conductive layer and a transparent semiconductor layer. Since light can pass through the transparent storage capacitor, the storage capacitor can be positioned within the pixel aperture. This not only effectively increases the capacitance of the storage capacitor but also effectively increases the pixel aperture, which is beneficial for achieving a display with high storage capacitance and high aperture ratio.

[0257] This disclosure saves the number of signal lines and reduces the space occupied by setting up a one-to-two structure for the first power line and a one-to-four structure for the compensation signal line. The structure is simple, the layout is reasonable, and the layout space is fully utilized, which improves the space utilization rate and helps to improve the resolution.

[0258] The embodiments disclosed herein display a 3T1C pixel driving circuit with one scan signal line. This single scan signal line connects to all the first transistors and all the third transistors in a pixel row, effectively reducing the number of scan signal lines. This not only simplifies the structure of the pixel driving circuit and reduces its footprint, facilitating high-resolution displays, but also effectively increases the light-transmitting area and the space ratio of the light-transmitting region, thus promoting high-transparency displays. Furthermore, since only one scan signal line is needed to drive a repeating unit, the number of its corresponding gate drive circuit (GOA) and clock signal line (CLK) can be reduced significantly, effectively minimizing the footprint of the gate drive circuit and clock signal line. This facilitates narrow bezels and enhances product advantages.

[0259] The preparation process disclosed herein can be achieved using existing mature preparation equipment, requires minimal modification to existing processes, is highly compatible with existing preparation processes, is simple to implement, has high production efficiency, low production cost, and high yield.

[0260] The structure and its preparation process shown in this disclosure are merely illustrative examples. In exemplary embodiments, the corresponding structure and the patterning process can be changed or reduced as needed, and this disclosure does not limit them.

[0261] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0262] This exemplary embodiment also provides a method for fabricating a display substrate to prepare the display substrate of the foregoing embodiments. In an exemplary embodiment, the display substrate includes a plurality of sub-pixels; the fabrication method includes:

[0263] A pixel driving circuit and a light-emitting device are formed in at least one sub-pixel; the pixel driving circuit includes at least a second transistor as a driving transistor and a node electrode, the second transistor includes at least a second active layer, the node electrode is connected to a second region of the second active layer through a node via, and a first region of the second active layer is connected to a first power line; the light-emitting device includes at least a first electrode and a pixel definition layer, the first electrode is connected to the node electrode through an anode via, and a pixel opening is provided on the pixel definition layer to expose the first electrode; in at least one sub-pixel, the orthographic projection of the node via on the display substrate plane does not overlap with the orthographic projection of the pixel opening on the display substrate plane, and the anode via is disposed on the side of the node via away from the pixel opening.

[0264] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0265] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, characterized in that, The device includes multiple repeating units, at least one repeating unit includes multiple sub-pixels, and at least one sub-pixel includes a pixel driving circuit and a light-emitting device; the pixel driving circuit includes at least a second transistor as a driving transistor and a node electrode, the second transistor includes at least a second active layer, the node electrode is connected to a second region of the second active layer through a node via, and a first region of the second active layer is connected to a first power line; the light-emitting device includes at least a first electrode and a pixel definition layer, the first electrode is connected to the node electrode through an anode via, and the pixel definition layer has a pixel opening that exposes the first electrode; In at least one sub-pixel, the orthographic projection of the node via on the display substrate plane does not overlap with the orthographic projection of the pixel opening on the display substrate plane, and the anode via is disposed on the side of the node via away from the pixel opening.

2. The display substrate according to claim 1, characterized in that, The pixel driving circuit further includes a shielding electrode and a transparent storage capacitor. The storage capacitor includes a first electrode plate and a second electrode plate. The orthographic projection of the first electrode plate on the display substrate plane overlaps at least partially with the orthographic projection of the second electrode plate on the display substrate plane. The orthographic projection of the shielding electrode on the display substrate plane overlaps at least partially with the orthographic projection of the second active layer on the display substrate plane. The shielding electrode is connected to the first electrode plate. In at least one sub-pixel, the node electrode is also connected to the occlusion electrode through the node via.

3. The display substrate according to claim 2, characterized in that, The node electrode includes at least a first sub-electrode and a second sub-electrode that are interconnected. The first sub-electrode is connected to the second region of the second active layer and the shielding electrode through the node via. The first electrode is connected to the second sub-electrode through an anode via. The second sub-electrode is disposed on the side of the first sub-electrode away from the pixel opening.

4. The display substrate according to claim 3, characterized in that, The orthographic projection of the second sub-electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer on the display substrate plane, and the orthographic projection of the anode via on the display substrate plane at least partially overlaps with the orthographic projection of the second region of the second active layer on the display substrate plane.

5. The display substrate according to claim 2, characterized in that, In at least one sub-pixel, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening on the display substrate plane, and the orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the pixel opening on the display substrate plane.

6. The display substrate according to claim 2, characterized in that, In a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, a semiconductor layer disposed on a side of the first conductive layer away from the substrate, and a second conductive layer disposed on a side of the semiconductor layer away from the substrate. A first electrode plate is disposed in the first transparent conductive layer, a shielding electrode is disposed in the first conductive layer, a second electrode plate and a second active layer are disposed in the semiconductor layer, and a node electrode is disposed in the second conductive layer.

7. The display substrate according to claim 2, characterized in that, The second transistor further includes a second gate electrode, and the pixel driving circuit further includes a first connection electrode; in at least one sub-pixel, the first connection electrode is connected to both the second electrode plate and the second gate electrode through a first adapter via.

8. The display substrate according to claim 7, characterized in that, In at least one sub-pixel, the orthographic projection of the second gate electrode onto the display substrate plane at least partially overlaps with the orthographic projection of the second electrode onto the display substrate plane.

9. The display substrate according to claim 7, characterized in that, In at least one first adapter via, the orthographic projection of the second gate electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane.

10. The display substrate according to any one of claims 1 to 9, characterized in that, At least one repeating unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along a first direction. The first power line is in the shape of a straight line or a broken line extending along a second direction and is respectively disposed in the first sub-pixel and the fourth sub-pixel. The first direction and the second direction intersect. The first power line in the first sub-pixel is connected to the first region of the second active layer in the first sub-pixel through a power via. The first power line in the first sub-pixel is connected to the first region of the second active layer in the second sub-pixel through a power connection line and a power connection electrode. The first power line in the fourth sub-pixel is connected to the first region of the second active layer in the third sub-pixel through a power connection line and a power connection electrode. The first power line in the fourth sub-pixel is connected to the first region of the second active layer in the fourth sub-pixel through a power via.

11. The display substrate according to claim 10, characterized in that, The pixel driving circuit further includes a blocking electrode, the orthographic projection of the blocking electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second active layer on the display substrate plane; in the first sub-pixel and the fourth sub-pixel, the orthographic projection of the power via on the display substrate plane does not overlap with the orthographic projection of the blocking electrode on the display substrate plane.

12. The display substrate according to claim 10, characterized in that, The pixel driving circuit further includes a blocking electrode, the orthographic projection of the blocking electrode on the display substrate plane at least partially overlapping the orthographic projection of the second active layer on the display substrate plane; in the second sub-pixel and the third sub-pixel, the first end of the power connection electrode is connected to the first region of the second active layer through a power via, the second end of the power connection electrode is connected to the first power line through the power connection line, and the orthographic projection of the power via on the display substrate plane at least partially overlaps the orthographic projection of the blocking electrode on the display substrate plane.

13. The display substrate according to claim 10, characterized in that, At least one sub-pixel also includes a data signal line connected to the pixel driving circuit. The data signal line is in the shape of a broken line extending along the second direction, and includes at least a straight first sub-line and a second sub-line, and a diagonal third sub-line. The third sub-line is disposed between the first sub-line and the second sub-line, and its two ends are respectively connected to the first sub-line and the second sub-line. In at least one sub-pixel of the first sub-pixel and the fourth sub-pixel, the first sub-line has a first distance from the first power line, and the second sub-line has a second distance from the first power line. The first distance is greater than the second distance, and the first distance and the second distance are dimensions in the first direction.

14. The display substrate according to claim 13, characterized in that, At least one sub-pixel further includes a compensation signal line connected to the pixel driving circuit, the compensation signal line being disposed between the second sub-pixel and the third sub-pixel; in at least one sub-pixel of the second sub-pixel and the third sub-pixel, there is a third distance between the first sub-line and the compensation signal line, and a fourth distance between the second sub-line and the compensation signal line, the third distance being less than the fourth distance, the third distance and the fourth distance being the dimensions of the first direction.

15. The display substrate according to claim 14, characterized in that, The orthographic projection of the compensation signal line on the display substrate plane does not overlap with the orthographic projection of the power connection line on the display substrate plane.

16. The display substrate according to any one of claims 1 to 9, characterized in that, The pixel driving circuit further includes a first transistor as a data writing transistor and a third transistor as a compensation transistor. In at least one sub-pixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scan signal line.

17. The display substrate according to claim 16, characterized in that, In at least one repeating unit, the gate electrodes of a plurality of the first transistors and the gate electrodes of a plurality of the third transistors are connected to the same scan signal line.

18. The display substrate according to claim 16, characterized in that, In at least one repeating unit, at least one through hole is provided on the scanning signal line, and the orthographic projection of the through hole on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane.

19. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 18.

20. A method for preparing a display substrate, characterized in that, The display substrate includes a plurality of sub-pixels; the fabrication method includes: A pixel driving circuit and a light-emitting device are formed in at least one sub-pixel; the pixel driving circuit includes at least a second transistor as a driving transistor and a node electrode, the second transistor includes at least a second active layer, the node electrode is connected to a second region of the second active layer through a node via, and a first region of the second active layer is connected to a first power line; the light-emitting device includes at least a first electrode and a pixel definition layer, the first electrode is connected to the node electrode through an anode via, and a pixel opening is provided on the pixel definition layer to expose the first electrode; in at least one sub-pixel, the orthographic projection of the node via on the display substrate plane does not overlap with the orthographic projection of the pixel opening on the display substrate plane, and the anode via is disposed on the side of the node via away from the pixel opening.

Images