Display device and electronic device

Abstract

The invention discloses a display device and an electronic device. The display device includes: a first lower active pattern; a first lower gate electrode disposed on the first lower active pattern, and forming a storage capacitor together with the first lower active pattern; a second lower gate electrode disposed on the first lower gate electrode, and forming a first compensation capacitor together with the first lower gate electrode; an upper active pattern disposed on the second lower gate electrode and electrically connected to the first lower gate electrode; and an upper gate electrode disposed on the upper active pattern and electrically connected to the first lower active pattern.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to a display device. Background Technology

[0002] The display device includes a pixel circuit layer and a light-emitting layer. The pixel circuit layer generates a driving current, and the light-emitting layer emits light corresponding to the driving current.

[0003] Multiple transistors and multiple capacitors are formed in the pixel circuit layer. The transistors and capacitors are implemented using metal patterns and metal lines stacked on top of each other. Summary of the Invention

[0004] Embodiments of this disclosure provide a display device and an electronic device including the display device.

[0005] According to an embodiment, a display device includes: a first lower active pattern disposed on a substrate; a first lower gate electrode disposed on the first lower active pattern, and the first lower gate electrode together with the first lower active pattern forms a storage capacitor; a second lower gate electrode disposed on the first lower gate electrode, and the second lower gate electrode together with the first lower gate electrode forms a first compensation capacitor; an upper active pattern disposed on the second lower gate electrode and electrically connected to the first lower gate electrode; and an upper gate electrode disposed on the upper active pattern and electrically connected to the first lower active pattern.

[0006] The first lower gate electrode can overlap with the first lower active pattern and the second lower gate electrode.

[0007] The area of ​​the first active pattern can be larger than the area of ​​the upper gate electrode.

[0008] The area of ​​the first lower gate electrode can be larger than the area of ​​the upper gate electrode.

[0009] The area of ​​the second lower gate electrode can be larger than the area of ​​the upper gate electrode.

[0010] The second lower gate electrode, the upper active pattern, and the upper gate electrode can form a driving transistor.

[0011] Data voltage can be applied to the upper gate electrode.

[0012] Each of the first lower active pattern, the first lower gate electrode, the second lower gate electrode, the upper active pattern, and the upper gate electrode may have an island shape.

[0013] The display device may further include a memory connection electrode disposed on the upper gate electrode and connecting the first lower active pattern to the upper gate electrode.

[0014] Storage connection electrodes can have an island shape.

[0015] The display device may also include a reference voltage vertical line disposed on and overlapping the storage connection electrode.

[0016] The display device may further include a first compensation connection electrode disposed on the upper gate electrode and connecting the first lower gate electrode to the active pattern thereon.

[0017] The first compensation connection electrode can have an island shape.

[0018] The display device may further include a data line disposed on a first compensation connection electrode, and the first compensation connection electrode may overlap with the upper gate electrode and the data line.

[0019] The first active pattern may include silicon semiconductor material, and the first active pattern may be completely doped with impurities.

[0020] The display device may further include a first active pattern disposed on the same layer as the first lower active pattern and comprising a silicon semiconductor material, and the first active pattern may be partially doped with impurities.

[0021] The upper gate electrode can directly contact the first lower active pattern.

[0022] The display device may further include a second lower active pattern disposed on the same layer as the first lower active pattern. The second lower active pattern, together with the first lower gate electrode, forms a second compensation capacitor and is electrically connected to the second lower gate electrode.

[0023] The display device may further include: a first compensation connection electrode disposed on the upper gate electrode, and the first compensation connection electrode connects the first lower gate electrode to the upper active pattern; and a second compensation connection electrode disposed on the same layer as the first compensation connection electrode, and the second compensation connection electrode connects the second lower active pattern to the second lower gate electrode.

[0024] According to an embodiment, a display device includes: a first lower active pattern disposed on a substrate; a first lower gate electrode disposed on the first lower active pattern, and the first lower gate electrode together with the first lower active pattern forming a compensation capacitor; a second lower gate electrode disposed on the first lower gate electrode, and the second lower gate electrode together with the first lower gate electrode forming a storage capacitor; an upper active pattern disposed on the second lower gate electrode and electrically connected to the first lower gate electrode; and an upper gate electrode disposed on the upper active pattern and electrically connected to the first lower active pattern. A data voltage can be applied to the second lower gate electrode.

[0025] According to an embodiment, an electronic device includes: a host; a display device receiving control signals and image data from the host; and a power supply configured to provide power to the display device. The display device may include: a first lower active pattern disposed on a substrate; a first lower gate electrode disposed on the first lower active pattern, and the first lower gate electrode together with the first lower active pattern forming a storage capacitor; a second lower gate electrode disposed on the first lower gate electrode, and the second lower gate electrode together with the first lower gate electrode forming a first compensation capacitor; an upper active pattern disposed on the second lower gate electrode and electrically connected to the first lower gate electrode; and an upper gate electrode disposed on the upper active pattern and electrically connected to the first lower active pattern.

[0026] A display device according to embodiments of the present disclosure may include a lower active pattern, a first lower gate electrode, and a second lower gate electrode. The lower active pattern, the first lower gate electrode, and the second lower gate electrode may be disposed on different layers and may overlap each other. Therefore, the areas of the lower active pattern, the first lower gate electrode, and the second lower gate electrode can each be formed to be relatively large. In other words, the display device according to embodiments of the present disclosure can respectively ensure a relatively large area of ​​the lower active pattern, a relatively large area of ​​the first lower gate electrode, and a relatively large area of ​​the second lower gate electrode.

[0027] Since the area of ​​each of the lower active pattern and the first lower gate electrode is fully guaranteed, the capacitance of the storage capacitor formed by the lower active pattern and the first lower gate electrode can be increased.

[0028] Since the area of ​​each of the first lower gate electrode and the second lower gate electrode is fully guaranteed, the capacitance of the compensation capacitor formed by the first lower gate electrode and the second lower gate electrode can be increased. Attached Figure Description

[0029] The accompanying drawings, together with the description, illustrate embodiments of the inventive concept. The drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification.

[0030] Figure 1 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It is shown that it includes Figure 1 A block diagram of the pixel circuit layer in a display device.

[0032] Figure 3 It is shown that it includes Figure 2 The circuit diagram of the pixel circuit structure in the pixel circuit layer.

[0033] Figure 4 It is shown that it includes Figure 1 A plan view of the pixel circuit structure in a display device.

[0034] Figures 5 to 19 It shows the manufacturing process. Figure 4 A plan view of the pixel circuit structure method.

[0035] Figure 20 It is shown Figure 1 A cross-sectional view of the display device.

[0036] Figure 21 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0037] Figure 22 It is shown that it includes Figure 21 A circuit diagram of the pixel circuit structure in a display device.

[0038] Figure 23 It is shown Figure 21 A cross-sectional view of the display device.

[0039] Figure 24 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0040] Figure 25 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0041] Figure 26 It is shown that it includes Figure 25 A circuit diagram of the pixel circuit structure in a display device.

[0042] Figure 27 It is shown Figure 25 A cross-sectional view of the display device.

[0043] Figure 28 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0044] Figure 29 This is a schematic diagram of an electronic device. Detailed Implementation

[0045] The illustrative, non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0046] Figure 1 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0047] Reference Figure 1 The display device DD1 according to an embodiment of the present disclosure may include a substrate SUB, a pixel circuit layer PCL, an emissive layer ELL, and an encapsulation layer ENC.

[0048] The pixel circuit layer (PCL) may include at least one pixel circuit structure. For example, the pixel circuit layer (PCL) may include a first pixel circuit structure (PCS1) and a second pixel circuit structure (PCS2).

[0049] The light-emitting layer ELL may include at least one light-emitting structure. For example, the light-emitting layer ELL may include a first light-emitting structure ES1 and a second light-emitting structure ES2.

[0050] The pixel circuit layer (PCL) can be set on the substrate (SUB).

[0051] The first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 can be arranged side by side along the first direction D1. Each of the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 can receive signals and / or voltages and can generate drive currents.

[0052] The emitting layer ELL can be set on the pixel circuit layer PCL.

[0053] The first light-emitting structure ES1 and the second light-emitting structure ES2 can be electrically connected to the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2, respectively. The first light-emitting structure ES1 can receive driving current from the first pixel circuit structure PCS1 and can emit light. The second light-emitting structure ES2 can receive driving current from the second pixel circuit structure PCS2 and can emit light.

[0054] The encapsulation layer ENC can be placed on the light-emitting layer ELL. The encapsulation layer ENC can encapsulate the light-emitting layer ELL.

[0055] Figure 2 It is shown that it includes Figure 1 A block diagram of the pixel circuit layer in a display device. Figure 3 It is shown that it includes Figure 2 The circuit diagram of the pixel circuit structure in the pixel circuit layer.

[0056] Reference Figure 2 The display device DD1 may include a pixel circuit layer PCL, a data driver DDV, a gate driver GDV, an emitter driver EDV, and a timing controller CON.

[0057] The pixel circuit layer PCL may include a first pixel circuit structure PCS1 and a second pixel circuit structure PCS2. Each of the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 may be electrically connected to the data driver DDV, the gate driver GDV, and the transmit driver EDV.

[0058] The data driver DDV can receive output image data ODAT and data control signal DCTRL from the timing controller CON, and can generate data voltage DATA.

[0059] The gate driver GDV can receive the gate control signal GCTRL from the timing controller CON and can generate the gate signal GS (e.g., Figure 3 The first gate signal GW, the second gate signal GR, and the third gate signal GB).

[0060] The transmit driver EDV can receive the transmit drive control signal ECTRL from the timing controller CON and can generate the transmit control signal EM.

[0061] The timing controller CON can receive control signals CTRL and input image data IDAT from external devices (e.g., a host or processor), and can control the data driver DDV, gate driver GDV, and transmit driver EDV.

[0062] Reference Figure 3 The first pixel circuit structure PCS1 can provide driving current to the first light-emitting structure ES1. The first pixel circuit structure PCS1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor CST, and a compensation capacitor CTH.

[0063] The first transistor T1 may include a gate terminal, a lower gate terminal, a first terminal, and a second terminal.

[0064] The gate terminal of the first transistor T1 can be electrically connected to the second transistor T2 and the storage capacitor CST through the first node N1. The data voltage DATA can be applied to the gate terminal of the first transistor T1.

[0065] The lower gate terminal of the first transistor T1 can be electrically connected to the compensation capacitor CTH through the third node N3.

[0066] The first terminal of the first transistor T1 can be electrically connected to the fifth transistor T5 and the sixth transistor T6.

[0067] The second terminal of the first transistor T1 can be electrically connected to the fourth transistor T4 and the first light-emitting structure ES1 through the second node N2.

[0068] The first transistor T1 can generate a drive current based on the high power voltage ELVDD and the data voltage DATA. For example, the first transistor T1 can be referred to as the drive transistor.

[0069] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal.

[0070] The gate terminal of the second transistor T2 can be supplied with a first gate signal GW.

[0071] The first terminal of the second transistor T2 can be electrically connected to the data voltage DATA.

[0072] The second terminal of the second transistor T2 can be electrically connected to the first node N1.

[0073] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, when the second transistor T2 is an NMOS transistor, it can be turned on when the first gate signal GW has a positive voltage level (e.g., high voltage) and turned off when the first gate signal GW has a negative voltage level (e.g., low voltage). When the second transistor T2 is turned on, it can transmit the data voltage DATA to the first transistor T1.

[0074] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal.

[0075] The gate terminal of the third transistor T3 can be supplied with a second gate signal GR.

[0076] The first terminal of the third transistor T3 can be supplied with a reference voltage VREF.

[0077] The second terminal of the third transistor T3 can be electrically connected to the first node N1.

[0078] The third transistor T3 can be turned on or off in response to the second gate signal GR. For example, when the third transistor T3 is an NMOS transistor, it can be turned on when the second gate signal GR has a positive voltage level (e.g., high voltage) and turned off when the second gate signal GR has a negative voltage level (e.g., low voltage). When the third transistor T3 is turned on, it can transfer the reference voltage VREF to the first node N1.

[0079] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal.

[0080] The gate terminal of the fourth transistor T4 can be provided with a third gate signal GB.

[0081] The first terminal of the fourth transistor T4 can be supplied with an initialization voltage VAINT.

[0082] The second terminal of the fourth transistor T4 can be electrically connected to the first light-emitting structure ES1.

[0083] The fourth transistor T4 can be turned on or off in response to the third gate signal GB. For example, when the fourth transistor T4 is an NMOS transistor, it can be turned on when the third gate signal GB has a positive voltage level (e.g., high voltage) and turned off when the third gate signal GB has a negative voltage level (e.g., low voltage). When the fourth transistor T4 is turned on, it can transmit the initialization voltage VAINT to the first light-emitting structure ES1.

[0084] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal.

[0085] The gate terminal of the fifth transistor T5 can be supplied with an emitter control signal EM.

[0086] The first terminal of the fifth transistor T5 can be supplied with a high electrical voltage ELVDD.

[0087] The second terminal of the fifth transistor T5 can be electrically connected to the first transistor T1.

[0088] The fifth transistor T5 can be turned on or off in response to the emit control signal EM. For example, when the fifth transistor T5 is a PMOS transistor, it can be turned off when the emit control signal EM has a positive voltage level (e.g., high voltage) and turned on when the emit control signal EM has a negative voltage level (e.g., low voltage). When the fifth transistor T5 is turned on, it can deliver a high power voltage ELVDD to the first transistor T1.

[0089] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal.

[0090] The gate terminal of the sixth transistor T6 can be supplied with a second gate signal GR.

[0091] The first terminal of the sixth transistor T6 can be electrically connected to the first transistor T1.

[0092] The second terminal of the sixth transistor T6 can be electrically connected to the third node N3.

[0093] The sixth transistor T6 can be turned on or off in response to the second gate signal GR. For example, when the sixth transistor T6 is an NMOS transistor, the sixth transistor T6 can be turned on when the second gate signal GR has a positive voltage level (e.g., high voltage) and can be turned off when the second gate signal GR has a negative voltage level (e.g., low voltage).

[0094] As described above, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 can be an NMOS transistor, and the fifth transistor T5 can be a PMOS transistor. However, this disclosure is not limited thereto.

[0095] The storage capacitor CST may include a first terminal and a second terminal.

[0096] The first terminal of the storage capacitor CST can be electrically connected to the first node N1.

[0097] The second terminal of the storage capacitor CST can be electrically connected to the second node N2.

[0098] The compensation capacitor CTH may include a first terminal and a second terminal.

[0099] The first terminal of the compensation capacitor CTH can be electrically connected to the second node N2.

[0100] The second terminal of the compensation capacitor CTH can be electrically connected to the third node N3.

[0101] However, the circuit structure of the first pixel circuit structure PCS1 is not limited to this. For example, the number of transistors, the number of capacitors, and their connection relationships included in the first pixel circuit structure PCS1 can be appropriately set as needed.

[0102] Since the circuit structure of the second pixel circuit structure PCS2 can be basically the same as that of the first pixel circuit structure PCS1, a detailed description of the second pixel circuit structure PCS2 is omitted.

[0103] The first light-emitting structure ES1 may include a first terminal and a second terminal. The first terminal of the first light-emitting structure ES1 may be electrically connected to the second node N2. The second terminal of the first light-emitting structure ES1 may be applied with a low power voltage ELVSS. The first light-emitting structure ES1 may emit light corresponding to the driving current.

[0104] Figure 4 It is shown that it includes Figure 1 A plan view of the pixel circuit structure in a display device. Figures 5 to 19 It shows the manufacturing process. Figure 4 A plan view of the pixel circuit structure method. Figure 20 It is shown Figure 1 A cross-sectional view of the display device. See below for reference. Figures 4 to 20 The description can also refer to Figure 3 .

[0105] Reference Figure 4 Display device DD1 (see Figure 1The device may include a first pixel circuit structure PCS1 and a second pixel circuit structure PCS2. In an embodiment, the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 may be arranged side by side along a first direction D1. Furthermore, the second pixel circuit structure PCS2 may be symmetrical with the first pixel circuit structure PCS1 about an axis of symmetry extending in a second direction D2 intersecting the first direction D1 between the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2. Additionally, the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 may have a thickness in a third direction D3 intersecting the first direction D1 and the second direction D2.

[0106] Reference Figure 5 and Figure 20 The substrate SUB can comprise transparent or opaque materials. In embodiments, the substrate SUB can comprise any of glass, quartz, and plastic. For example, when the substrate SUB is formed of plastic, it can comprise at least one of polyimide, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polycarbonate, and cellulose acetate propionate.

[0107] A preliminary lower active pattern PLACT' and a preliminary first active pattern PACT1' can be formed on the substrate SUB.

[0108] According to an embodiment, the initial lower active pattern PLACT' and the initial first active pattern PACT1' may include silicon semiconductors. For example, the initial lower active pattern PLACT' and the initial first active pattern PACT1' may include amorphous silicon or polycrystalline silicon.

[0109] Each of the initial lower active pattern PLACT' and the initial first active pattern PACT1' can have an island shape. For example, the initial lower active pattern PLACT' and the initial first active pattern PACT1' can be unconnected to each other.

[0110] Reference Figure 6 A barrier pattern BLP can be formed on the initial first active pattern PACT1'. In an embodiment, the barrier pattern BLP may partially overlap with the initial first active pattern PACT1'. Although the initial first active pattern PACT1' is doped with impurities (e.g., boron, phosphorus, etc.), the barrier pattern BLP can block the impurities.

[0111] Reference Figure 7 and Figure 20 , combined Figure 6After the initial lower active pattern PLACT' and the initial first active pattern PACT1' are doped with impurities, the lower active pattern LACT and the first active pattern ACT1 can be formed. In an embodiment, the lower active pattern LACT may have an island shape, and the lower active pattern LACT may be completely doped with impurities. For example, the lower active pattern LACT may be associated with a storage capacitor CST (see...). Figure 3 The first terminal corresponds to ).

[0112] The first active pattern ACT1 can have an island shape, and due to the blocking pattern BLP, the first active pattern ACT1 can be partially doped with impurities.

[0113] In an embodiment, the blocking pattern BLP can be removed after the above doping process.

[0114] The first insulating layer IL1 can be formed on the substrate SUB and can cover the lower active pattern LACT and the first active pattern ACT1. In an embodiment, the first insulating layer IL1 can include an insulating material. For example, the first insulating layer IL1 can include silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or tantalum oxide, and can have a single-layer or multi-layer structure.

[0115] Reference Figure 8 , Figure 9 and Figure 20 A first lower gate electrode LGAT1 and an emitter control signal line EML can be disposed on the first insulating layer IL1.

[0116] In an embodiment, the first lower gate electrode LGAT1 and the emitter control signal line EML may include metal, alloy, metal oxide, or metal nitride, etc.

[0117] For example, the first lower gate electrode LGAT1 and the emitter control signal line EML may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0118] Additionally, each of the first lower gate electrode LGAT1 and the emitter control signal line EML may comprise a single layer or multiple layers in combination with each other.

[0119] In an embodiment, the first lower gate electrode LGAT1 may have an island shape and may overlap with the lower active pattern LACT.

[0120] For example, the first lower gate electrode LGAT1 can correspond to the second terminal of the storage capacitor CST. Alternatively, the first lower gate electrode LGAT1 can correspond to the compensation capacitor CTH (see...). Figure 3 The first terminal corresponds to ).

[0121] The transmit control signal line EML can extend in the first direction D1, and the protrusion of the transmit control signal line EML can overlap with the first active pattern ACT1.

[0122] For example, the transmit control signal line EML can transmit the transmit control signal EM. The first active pattern ACT1 and the transmit control signal line EML can form the fifth transistor T5 (see...). Figure 3 ).

[0123] The second insulating layer IL2 can be formed on the first insulating layer IL1 and can cover the first lower gate electrode LGAT1 and the emitter control signal line EML. In an embodiment, the second insulating layer IL2 may include an insulating material. For example, the second insulating layer IL2 may include silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or tantalum oxide, and may have a single-layer or multi-layer structure.

[0124] Reference Figure 10 , Figure 11 and Figure 20 A second lower gate electrode LGAT2 and an initialization voltage line VAINTL can be set on the second insulating layer IL2.

[0125] The second lower gate electrode LGAT2 and the initialization voltage line VAINTL can include metals, alloys, metal oxides, or metal nitrides. For example, the second lower gate electrode LGAT2 and the initialization voltage line VAINTL can include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). These can be used individually or in combination with each other.

[0126] Additionally, each of the second lower gate electrode LGAT2 and the initialization voltage line VAINTL may comprise a single layer or multiple layers in combination with each other.

[0127] In an embodiment, the second lower gate electrode LGAT2 may have an island shape and may overlap with the lower active pattern LACT and the first lower gate electrode LGAT1.

[0128] For example, the second lower gate electrode LGAT2 can be connected to the second terminal of the compensation capacitor CTH and the first transistor T1 (see...). Figure 3 The lower gate terminal corresponds to ).

[0129] In an embodiment, the initialization voltage line VAINTL may extend in the first direction D1.

[0130] For example, the initialization voltage line VAINTL can transmit the initialization voltage VAINT.

[0131] A third insulating layer IL3 may be formed on the second insulating layer IL2 and may cover the second lower gate electrode LGAT2 and the initialization voltage line VAINTL. In embodiments, the third insulating layer IL3 may include an insulating material. For example, the third insulating layer IL3 may include silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or tantalum oxide, and may have a single-layer or multi-layer structure.

[0132] Reference Figure 12 , Figure 13 and Figure 20 An active pattern UACT, a second active pattern ACT2, a third active pattern ACT3, and a fourth active pattern ACT4 can be set on the third insulating layer IL3.

[0133] In this embodiment, the active pattern UACT, the second active pattern ACT2, the third active pattern ACT3, and the fourth active pattern ACT4 may include oxide semiconductors.

[0134] For example, the upper active pattern UACT, the second active pattern ACT2, the third active pattern ACT3, and the fourth active pattern ACT4 may include IGZO (InGaZnO) or ITZO (InSnZnO), etc. Additionally, the upper active pattern UACT, the second active pattern ACT2, the third active pattern ACT3, and the fourth active pattern ACT4 may also include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), or zinc (Zn). These can be used individually or in combination with each other.

[0135] The upper active pattern UACT can have an island shape and can overlap with the second lower gate electrode LGAT2. Furthermore, the upper active pattern UACT can further overlap with the lower active pattern LACT and the first lower gate electrode LGAT1.

[0136] Each of the second active pattern ACT2, the third active pattern ACT3, and the fourth active pattern ACT4 can have an island shape.

[0137] The fourth insulating layer IL4 can be formed on the third insulating layer IL3 and can cover the active pattern UACT, the second active pattern ACT2, the third active pattern ACT3, and the fourth active pattern ACT4. In embodiments, the fourth insulating layer IL4 may include an insulating material. For example, the fourth insulating layer IL4 may include silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or tantalum oxide, and may have a single-layer or multi-layer structure.

[0138] Reference Figure 14 , Figure 15 and Figure 20 The reference voltage level line VREFHL, the second gate signal line GRL, the upper gate electrode UGAT, the first gate signal pattern GWP, and the third gate signal line GBL can be set on the fourth insulating layer IL4.

[0139] In an embodiment, the reference voltage level line VREFHL, the second gate signal line GRL, the upper gate electrode UGAT, the first gate signal pattern GWP, and the third gate signal line GBL may include metals, alloys, metal oxides, or metal nitrides, etc.

[0140] For example, the reference voltage level line VREFHL, the second gate signal line GRL, the upper gate electrode UGAT, the first gate signal pattern GWP, and the third gate signal line GBL may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0141] Additionally, each of the reference voltage level line VREFHL, the second gate signal line GRL, the upper gate electrode UGAT, the first gate signal pattern GWP, and the third gate signal line GBL may comprise a single layer or multiple layers in combination with each other.

[0142] The reference voltage level line VREFHL can extend in the first direction D1 and can overlap with the transmit control signal line EML.

[0143] For example, the reference voltage level line VREFHL can transmit the reference voltage VREF.

[0144] The second gate signal line GRL can extend in the first direction D1 and can overlap with the third active pattern ACT3 and the fourth active pattern ACT4.

[0145] For example, the second gate signal line GRL can transmit the second gate signal GR.

[0146] The third active pattern ACT3 and the second gate signal line GRL can form the third transistor T3, and the fourth active pattern ACT4 and the second gate signal line GRL can form the sixth transistor T6.

[0147] The upper gate electrode UGAT can have an island shape and can overlap with the upper active pattern UACT. In addition, the upper gate electrode UGAT can overlap with the lower active pattern LACT, the first lower gate electrode LGAT1, and the second lower gate electrode LGAT2.

[0148] The data voltage DATA can be applied to the upper gate electrode UGAT. The second lower gate electrode LGAT2, the active pattern UACT, and the upper gate electrode UGAT can form the first transistor T1 (see [link to transistor]). Figure 3 ).

[0149] The area of ​​the lower active pattern (LACT) can be larger than the area of ​​the upper gate electrode (UGAT). Because the area of ​​the lower active pattern (LACT) is relatively large, the capacitance of the storage capacitor (CST) can be increased.

[0150] The area of ​​the first lower gate electrode LGAT1 can be larger than the area of ​​the upper gate electrode UGAT. Because the area of ​​the first lower gate electrode LGAT1 is formed to be relatively large, the capacitance of the storage capacitor CST and the capacitance of the compensation capacitor CTH can be increased.

[0151] The area of ​​the second lower gate electrode LGAT2 can be larger than the area of ​​the upper gate electrode UGAT. Because the area of ​​the second lower gate electrode LGAT2 is relatively large, the capacitance of the compensation capacitor CTH can be increased.

[0152] The first gate signal pattern GWP can have an island shape and can overlap with the second active pattern ACT2.

[0153] For example, the first gate signal pattern GWP can transmit the first gate signal GW. The second active pattern ACT2 and the first gate signal pattern GWP can form the second transistor T2 (see...). Figure 3 ).

[0154] The third gate signal line GBL can extend in the first direction D1 and can overlap with the active pattern UACT.

[0155] For example, the third gate signal line GBL can transmit the third gate signal GB. An active pattern UACT and the third gate signal line GBL can form a fourth transistor T4 (see [link to relevant documentation]). Figure 3 ).

[0156] A fifth insulating layer IL5 may be formed on the fourth insulating layer IL4 and may cover the reference voltage level line VREFHL, the second gate signal line GRL, the upper gate electrode UGAT, the first gate signal pattern GWP, and the third gate signal line GBL. In embodiments, the fifth insulating layer IL5 may include an insulating material. For example, the fifth insulating layer IL5 may include an organic insulating material, such as a photoresist, polyacrylic resin, polyimide resin, or acrylic resin.

[0157] Reference Figure 16 , Figure 17 and Figure 20 , combined Figure 15 The reference voltage pattern VREFP, the high power voltage level line ELVDDHL, the first connection electrode CE1, the second connection electrode CE2, the storage connection electrode STCE, the compensation connection electrode THCE, the first gate signal line GWL, the data voltage connection pattern DP, the initialization voltage connection pattern VAINTP, and the data voltage level connection line BRSH can be set on the fifth insulating layer IL5.

[0158] In the embodiments, the reference voltage pattern VREFP, the high power voltage level line ELVDDHL, the first connection electrode CE1, the second connection electrode CE2, the storage connection electrode STCE, the compensation connection electrode THCE, the first gate signal line GWL, the data voltage connection pattern DP, the initialization voltage connection pattern VAINTP, and the data voltage level connection line BRSH may include metals, alloys, metal oxides, or metal nitrides, etc.

[0159] For example, the reference voltage pattern VREFP, the high power voltage level line ELVDDHL, the first connection electrode CE1, the second connection electrode CE2, the storage connection electrode STCE, the compensation connection electrode THCE, the first gate signal line GWL, the data voltage connection pattern DP, the initialization voltage connection pattern VAINTP, and the data voltage level connection line BRSH may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0160] Additionally, each of the following can include a single layer or multiple layers in combination: the reference voltage pattern VREFP, the high power voltage level line ELVDDHL, the first connection electrode CE1, the second connection electrode CE2, the storage connection electrode STCE, the compensation connection electrode THCE, the first gate signal line GWL, the data voltage connection pattern DP, the initialization voltage connection pattern VAINTP, and the data voltage level connection line BRSH.

[0161] The reference voltage pattern VREFP can have an island shape and can contact the reference voltage level line VREFHL and the third active pattern ACT3.

[0162] For example, the reference voltage pattern VREFP can transfer the reference voltage VREF to the third active pattern ACT3.

[0163] The high power voltage level line ELVDDHL can extend in the first direction D1 and can contact the first active pattern ACT1.

[0164] For example, the high power voltage level line ELVDDHL can transmit the high power voltage ELVDD to the first active pattern ACT1.

[0165] The first connecting electrode CE1 may have an island shape and may contact the first active pattern ACT1, the upper active pattern UACT, and the fourth active pattern ACT4.

[0166] The second connecting electrode CE2 may have an island shape and may contact the second lower gate electrode LGAT2 and the fourth active pattern ACT4.

[0167] The storage connection electrode STCE can have an island shape and can contact the lower active pattern LACT, the second active pattern ACT2, the third active pattern ACT3 and the upper gate electrode UGAT.

[0168] For example, the storage connection electrode STCE can contact the lower active pattern LACT and the upper gate electrode UGAT. In other words, the upper gate electrode UGAT can be electrically connected to the lower active pattern LACT through the storage connection electrode STCE.

[0169] The compensation connection electrode THCE can have an island shape and can contact the first lower gate electrode LGAT1 and the upper active pattern UACT.

[0170] For example, the active pattern UACT can be electrically connected to the first lower gate electrode LGAT1 via the compensation connection electrode THCE.

[0171] The first gate signal line GWL can extend in the first direction D1 and can contact the first gate signal pattern GWP.

[0172] For example, the first gate signal line GWL can transmit the first gate signal GW to the first gate signal pattern GWP.

[0173] The data voltage connection pattern DP can have an island shape and can contact the second active pattern ACT2.

[0174] For example, the data voltage connection pattern DP can transmit the data voltage DATA to the second active pattern ACT2.

[0175] The initial voltage connection pattern VAINTP can have an island shape and can contact the active pattern UACT.

[0176] For example, the initial voltage connection pattern VAINTP can transmit the initial voltage VAINT to the upper active pattern UACT.

[0177] The data voltage level connection line BRSH can extend in the first direction D1.

[0178] A sixth insulating layer IL6 may be formed on the fifth insulating layer IL5 and may cover the reference voltage pattern VREFP, the high power voltage level line ELVDDHL, the first connection electrode CE1, the second connection electrode CE2, the storage connection electrode STCE, the compensation connection electrode THCE, the first gate signal line GWL, the data voltage connection pattern DP, the initialization voltage connection pattern VAINTP, and the data voltage level connection line BRSH. In embodiments, the sixth insulating layer IL6 may include an insulating material. For example, the sixth insulating layer IL6 may include an organic insulating material, such as a photoresist, polyacrylic resin, polyimide resin, or acrylic resin.

[0179] Reference Figure 18 , Figure 19 and Figure 20 , combined Figure 17 High power voltage vertical line ELVDDVL, pixel connection pad ACP, data line DL, data voltage vertical connection line BRSV, and reference voltage vertical line VREFVL can be set on the sixth insulating layer IL6.

[0180] In the embodiments, the high power voltage vertical line ELVDDVL, pixel connection pad ACP, data line DL, data voltage vertical connection line BRSV, and reference voltage vertical line VREFVL may include metals, alloys, metal oxides, or metal nitrides, etc.

[0181] For example, the high power voltage vertical line ELVDDVL, pixel connection pad ACP, data line DL, data voltage vertical connection line BRSV, and reference voltage vertical line VREFVL can include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0182] Additionally, the high power voltage vertical line ELVDDVL, pixel connection pad ACP, data line DL, data voltage vertical connection line BRSV, and reference voltage vertical line VREFVL can be single layers or multiple layers combined with each other.

[0183] The high-voltage vertical line ELVDDVL can extend in the second direction D2 and can contact the high-voltage horizontal line ELVDDHL.

[0184] For example, a high-voltage vertical line ELVDDVL can transmit high-voltage ELVDD to a high-voltage horizontal line ELVDDHL.

[0185] The pixel connection pad (ACP) can have an island shape and can contact the compensation connection electrode (THCE).

[0186] The data line DL can extend in the second direction D2 and can contact the data voltage connection pattern DP.

[0187] For example, the data line DL can transmit the data voltage DATA to the data voltage connection pattern DP.

[0188] The compensation connection electrode THCE can be positioned between the upper gate electrode UGAT and the data line DL, and can overlap with both the upper gate electrode UGAT and the data line DL. Therefore, the compensation connection electrode THCE can shield the upper gate electrode UGAT from the influence of the data line DL.

[0189] The data voltage vertical connection line BRSV can extend in the second direction D2 and can contact the data voltage horizontal connection line BRSH.

[0190] The reference voltage vertical line VREFVL can extend in the second direction D2 and can contact the reference voltage pattern VREFP.

[0191] For example, the reference voltage vertical line VREFVL can transfer the reference voltage VREF to the reference voltage pattern VREFP.

[0192] The reference voltage vertical line VREFVL can overlap with the storage connection electrode STCE. Therefore, the reference voltage vertical line VREFVL can shield the storage connection electrode STCE.

[0193] A seventh insulating layer IL7 may be formed on the sixth insulating layer IL6 and may cover the high-voltage vertical line ELVDDVL, pixel connection pad ACP, data line DL, data voltage vertical connection line BRSV, and reference voltage vertical line VREFVL. In embodiments, the seventh insulating layer IL7 may include an insulating material. For example, the seventh insulating layer IL7 may include an organic insulating material, such as a photoresist, polyacrylic resin, polyimide resin, or acrylic resin.

[0194] The pixel electrode PE can be disposed on the seventh insulating layer IL7.

[0195] In embodiments, the pixel electrode PE may include metals, alloys, metal oxides, or metal nitrides. For example, the pixel electrode PE may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0196] In addition, the pixel electrode PE can include a single layer or multiple layers combined with each other.

[0197] The pixel defining layer PDL can be disposed on the seventh insulating layer IL7, and an opening can be formed in the pixel defining layer PDL to extend to the pixel electrode PE.

[0198] For example, the pixel defining layer (PDL) may include organic materials such as polyimide resins (e.g., photosensitive polyimide resins (PSPI)), photoresists, polyacrylic resins, or acrylic resins, or inorganic materials such as silicon oxide or silicon nitride.

[0199] The emitter layer EL can be disposed on the pixel electrode PE. In an embodiment, the emitter layer EL can have a multilayer structure including an organic light-emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0200] The common electrode (CTE) can be placed on the emitter layer (EL).

[0201] In embodiments, the common electrode CTE may include metals, alloys, or conductive metal oxides. For example, the common electrode CTE may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO), etc. These can be used individually or in combination with each other.

[0202] The first encapsulation inorganic layer IOL1 can be disposed on the common electrode CTE and can include inorganic materials.

[0203] The organic encapsulation layer OL can be disposed on the first encapsulation inorganic layer IOL1, and can include organic materials.

[0204] The second encapsulation inorganic layer IOL2 can be disposed on the organic encapsulation layer OL, and can include inorganic materials.

[0205] The first encapsulation inorganic layer IOL1, the organic encapsulation layer OL, and the second encapsulation inorganic layer IOL2 can protect the emitter layer EL from moisture or oxygen that permeates from the outside.

[0206] Further reference Figure 20 The storage connection electrode STCE can contact the upper gate electrode UGAT and the lower active pattern LACT. The upper gate electrode UGAT can correspond to the gate terminal of the first transistor T1. The lower active pattern LACT can be electrically connected to the upper gate electrode UGAT and can correspond to the first terminal of the storage capacitor CST.

[0207] The compensation connection electrode THCE can contact a portion of the active pattern UACT and the first lower gate electrode LGAT1. The portion of the active pattern UACT can correspond to the second terminal of the first transistor T1. The first lower gate electrode LGAT1 can be electrically connected to the portion of the active pattern UACT and can correspond to the second terminal of the storage capacitor CST and the first terminal of the compensation capacitor CTH.

[0208] The lower active pattern LACT, the first lower gate electrode LGAT1, and the second lower gate electrode LGAT2 can be disposed on different layers and can overlap each other. Therefore, as described above, the area of ​​each of the lower active pattern LACT, the first lower gate electrode LGAT1, and the second lower gate electrode LGAT2 can be formed to be relatively larger than the area of ​​the upper gate electrode UGAT, ensuring sufficient capacitance for the storage capacitor CST and the compensation capacitor CTH.

[0209] Since the area of ​​each of the lower active pattern LACT and the first lower gate electrode LGAT1 is fully guaranteed, the capacitance of the storage capacitor CST formed by the lower active pattern LACT and the first lower gate electrode LGAT1 can be increased.

[0210] Since the area of ​​each of the first lower gate electrode LGAT1 and the second lower gate electrode LGAT2 is fully guaranteed, the capacitance of the compensation capacitor CTH formed by the first lower gate electrode LGAT1 and the second lower gate electrode LGAT2 can be increased.

[0211] Figure 21 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure. Figure 22 It is shown that it includes Figure 21 A circuit diagram of the pixel circuit structure in a display device. Figure 23 It is shown Figure 21 A cross-sectional view of the display device.

[0212] Reference Figure 21 The display device DD2 according to embodiments of the present disclosure may include a substrate SUB, a pixel circuit layer PCL, an emissive layer ELL, and an encapsulation layer ENC.

[0213] The pixel circuit layer (PCL) may include at least one pixel circuit structure. For example, the pixel circuit layer (PCL) may include a first pixel circuit structure (PCS1) and a second pixel circuit structure (PCS2).

[0214] The light-emitting layer ELL may include at least one light-emitting structure. For example, the light-emitting layer ELL may include a first light-emitting structure ES1 and a second light-emitting structure ES2.

[0215] The pixel circuit layer (PCL) can be set on the substrate (SUB).

[0216] The first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 can be arranged side by side along the first direction D1. Each of the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 can receive signals or voltages and generate drive currents.

[0217] The emitting layer ELL can be set on the pixel circuit layer PCL.

[0218] The first light-emitting structure ES1 and the second light-emitting structure ES2 can be electrically connected to the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2, respectively. The first light-emitting structure ES1 can receive driving current from the first pixel circuit structure PCS1 and can emit light. The second light-emitting structure ES2 can receive driving current from the second pixel circuit structure PCS2 and can emit light.

[0219] The encapsulation layer ENC can be placed on the light-emitting layer ELL. The encapsulation layer ENC can encapsulate the light-emitting layer ELL.

[0220] In addition to the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2, the display device DD2 can be compared with the above reference. Figure 1 The described display device DD1 is basically the same.

[0221] Reference Figure 22 The first pixel circuit structure PCS1 can provide driving current to the first light-emitting structure ES1. The first pixel circuit structure PCS1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor CST, and a compensation capacitor CTH.

[0222] The first transistor T1 may include a gate terminal, a lower gate terminal, a first terminal, and a second terminal.

[0223] The gate terminal of the first transistor T1 can be electrically connected to the compensation capacitor CTH through the third node N3.

[0224] The lower gate terminal of the first transistor T1 can be electrically connected to the second transistor T2 and the storage capacitor CST through the first node N1. The data voltage DATA can be applied to the lower gate terminal of the first transistor T1.

[0225] The first terminal of the first transistor T1 can be electrically connected to the fifth transistor T5 and the sixth transistor T6.

[0226] The second terminal of the first transistor T1 can be electrically connected to the fourth transistor T4 and the first light-emitting structure ES1 through the second node N2.

[0227] According to an embodiment, the first transistor T1 may have a back gate structure in which a data voltage DATA is applied to the lower gate terminal of the first transistor T1.

[0228] The first transistor T1 can generate a drive current based on the high power voltage ELVDD and the data voltage DATA. For example, the first transistor T1 can be referred to as the drive transistor.

[0229] The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be referenced above. Figure 3 The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are described as being basically the same.

[0230] The storage capacitor CST may include a first terminal and a second terminal.

[0231] The first terminal of the storage capacitor CST can be electrically connected to the first node N1.

[0232] The second terminal of the storage capacitor CST can be electrically connected to the second node N2.

[0233] The compensation capacitor CTH may include a first terminal and a second terminal.

[0234] The first terminal of the compensation capacitor CTH can be electrically connected to the second node N2.

[0235] The second terminal of the compensation capacitor CTH can be electrically connected to the third node N3.

[0236] Reference Figure 23 The display device DD2 may include a lower active pattern LACT', a first lower gate electrode LGAT1', a second lower gate electrode LGAT2', an upper active pattern UACT', an upper gate electrode UGAT', a storage connection electrode STCE', a compensation connection electrode THCE', a reference voltage vertical line VREFVL, a data line DL, a data voltage vertical connection line BRSV, a pixel electrode PE, an emitter layer EL, and a common electrode CTE.

[0237] In addition to the lower active pattern LACT', the first lower gate electrode LGAT1', the second lower gate electrode LGAT2', the upper active pattern UACT', the upper gate electrode UGAT', the storage connection electrode STCE', and the compensation connection electrode THCE', the display device DD2 can be connected to the aforementioned display device DD1 (see...). Figure 20 They are basically the same.

[0238] The lower active pattern (LACT) can be disposed on the substrate (SUB). In an embodiment, the lower active pattern (LACT) may include a silicon semiconductor.

[0239] For example, the lower active pattern LACT' can be used with a compensation capacitor CTH (see...) Figure 22 The second terminal corresponds to ).

[0240] The first lower gate electrode LGAT1' can be disposed on the first insulating layer IL1.

[0241] In an embodiment, the first lower gate electrode LGAT1' may have an island shape and may overlap with the lower active pattern LACT'.

[0242] For example, the first lower gate electrode LGAT1' can be connected to the storage capacitor CST (see...). Figure 22 The second terminal corresponds to the first lower gate electrode LGAT1'. Additionally, the first lower gate electrode LGAT1' can be connected to the compensation capacitor CTH (see...). Figure 22 The first terminal corresponds to ).

[0243] The second lower gate electrode LGAT2' can be disposed on the second insulating layer IL2.

[0244] In an embodiment, the second lower gate electrode LGAT2' may have an island shape and may overlap with the lower active pattern LACT' and the first lower gate electrode LGAT1'.

[0245] For example, the second lower gate electrode LGAT2' can be connected to the first terminal of the storage capacitor CST and the first transistor T1 (see...). Figure 22 The lower gate terminal corresponds to ).

[0246] An active pattern UACT' can be disposed on the third insulating layer IL3. In an embodiment, the active pattern UACT' may include an oxide semiconductor.

[0247] In an embodiment, the upper active pattern UACT' may have an island shape and may overlap with the second lower gate electrode LGAT2'. Additionally, the upper active pattern UACT' may also overlap with the lower active pattern LACT' and the first lower gate electrode LGAT1'.

[0248] The upper gate electrode UGAT' can be disposed on the fourth insulating layer IL4.

[0249] In an embodiment, the upper gate electrode UGAT' may have an island shape and may overlap with the upper active pattern UACT'. Additionally, the upper gate electrode UGAT' may overlap with the lower active pattern LACT', the first lower gate electrode LGAT1', and the second lower gate electrode LGAT2'.

[0250] Data voltage (see DATA) Figure 22 An active pattern UACT' can be applied to the second lower gate electrode LGAT2'. The second lower gate electrode LGAT2', the active pattern UACT', and the upper gate electrode UGAT' can form the first transistor T1 (see...). Figure 22 ).

[0251] In this embodiment, the area of ​​the lower active pattern LACT' can be larger than the area of ​​the upper gate electrode UGAT'. Because the area of ​​the lower active pattern LACT' is formed to be relatively large, the capacitance of the compensation capacitor CTH can be increased.

[0252] In this embodiment, the area of ​​the first lower gate electrode LGAT1' can be larger than the area of ​​the upper gate electrode UGAT'. Because the area of ​​the first lower gate electrode LGAT1' is relatively large, the capacitance of the storage capacitor CST and the capacitance of the compensation capacitor CTH can be increased.

[0253] In this embodiment, the area of ​​the second lower gate electrode LGAT2' can be larger than the area of ​​the upper gate electrode UGAT'. Because the area of ​​the second lower gate electrode LGAT2' is relatively large, the capacitance of the storage capacitor CST can be increased.

[0254] The storage connection electrode STCE' and the compensation connection electrode THCE' can be disposed on the fifth insulating layer IL5.

[0255] In an embodiment, the storage connection electrode STCE' may have an island shape and may contact the lower active pattern LACT' and the upper gate electrode UGAT'.

[0256] For example, the storage connection electrode STCE' can contact the lower active pattern LACT' and the upper gate electrode UGAT'. In other words, the upper gate electrode UGAT' can be electrically connected to the lower active pattern LACT' through the storage connection electrode STCE'.

[0257] In an embodiment, the compensation connection electrode THCE' may have an island shape and may contact the first lower gate electrode LGAT1' and the upper active pattern UACT'.

[0258] For example, the active pattern UACT' can be electrically connected to the first lower gate electrode LGAT1' via the compensation connection electrode THCE'.

[0259] Figure 24 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0260] Reference Figure 24 The display device DD3 according to an embodiment of the present disclosure may include a lower active pattern LACT, a first lower gate electrode LGAT1, a second lower gate electrode LGAT2, an upper active pattern UACT, an upper gate electrode UGAT", a compensation connection electrode THCE, a reference voltage vertical line VREFVL, a data line DL, a data voltage vertical connection line BRSV, a pixel electrode PE, an emitter layer EL, and a common electrode CTE.

[0261] Except for the upper gate electrode "UGAT", display device DD3 can be connected to the aforementioned display device DD1 (see above). Figure 20 They are basically the same.

[0262] The upper gate electrode "UGAT" can be disposed on the fourth insulating layer IL4.

[0263] According to an embodiment, the upper gate electrode "UGAT" may have an island shape and may directly contact the lower active pattern "LACT". In other words, the display device DD3 may not include a separate memory connection electrode (e.g., Figure 20The storage connection electrode STCE, and the lower active pattern LACT can be directly connected to the upper gate electrode UGAT.

[0264] Figure 25 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure. Figure 26 It is shown that it includes Figure 25 A circuit diagram of the pixel circuit structure in a display device. Figure 27 It is shown Figure 25 A cross-sectional view of the display device.

[0265] The display device DD4 according to embodiments of the present disclosure may include a substrate SUB, a pixel circuit layer PCL, an emissive layer ELL, and an encapsulation layer ENC.

[0266] The pixel circuit layer (PCL) may include at least one pixel circuit structure. For example, the pixel circuit layer (PCL) may include a first pixel circuit structure (PCS1) and a second pixel circuit structure (PCS2).

[0267] The light-emitting layer ELL may include at least one light-emitting structure. For example, the light-emitting layer ELL may include a first light-emitting structure ES1 and a second light-emitting structure ES2.

[0268] The pixel circuit layer (PCL) can be set on the substrate (SUB).

[0269] The first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 can be arranged side by side along the first direction D1. Each of the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2 can receive signals or voltages and can generate drive currents.

[0270] The emitting layer ELL can be set on the pixel circuit layer PCL.

[0271] The first light-emitting structure ES1 and the second light-emitting structure ES2 can be electrically connected to the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2, respectively. The first light-emitting structure ES1 can receive driving current from the first pixel circuit structure PCS1 and can emit light. The second light-emitting structure ES2 can receive driving current from the second pixel circuit structure PCS2 and can emit light.

[0272] The encapsulation layer ENC can be placed on the light-emitting layer ELL. The encapsulation layer ENC can encapsulate the light-emitting layer ELL.

[0273] Apart from the first pixel circuit structure PCS1 and the second pixel circuit structure PCS2, the display device DD4 can be compared with the above reference. Figure 1 The described display device DD1 is basically the same.

[0274] Reference Figure 26 The first pixel circuit structure PCS1 can provide driving current to the first light-emitting structure ES1. The first pixel circuit structure PCS1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor CST, a first compensation capacitor CTH1, and a second compensation capacitor CTH2.

[0275] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be referenced above. Figure 3 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are described in a basically the same way.

[0276] The storage capacitor CST may include a first terminal and a second terminal.

[0277] The first terminal of the storage capacitor CST can be electrically connected to the first node N1.

[0278] The second terminal of the storage capacitor CST can be electrically connected to the second node N2.

[0279] The first compensation capacitor CTH1 may include a first terminal and a second terminal.

[0280] The first terminal of the first compensation capacitor CTH1 can be electrically connected to the second node N2.

[0281] The second terminal of the first compensation capacitor CTH1 can be electrically connected to the third node N3.

[0282] The second compensation capacitor CTH2 may include a first terminal and a second terminal.

[0283] The first terminal of the second compensation capacitor CTH2 can be electrically connected to the second node N2.

[0284] The second terminal of the second compensation capacitor CTH2 can be electrically connected to the third node N3.

[0285] Reference Figure 27 The display device DD4 may include a first lower active pattern LACT1, a second lower active pattern LACT2, a first lower gate electrode LGAT1, a second lower gate electrode LGAT2, an upper active pattern UACT, an upper gate electrode UGAT, a storage connection electrode STCE, a first compensation connection electrode THCE1, a second compensation connection electrode THCE2, a reference voltage vertical line VREFVL, a data line DL, a data voltage vertical connection line BRSV, a pixel electrode PE, an emitter layer EL, and a common electrode CTE.

[0286] Except for the first lower active pattern LACT1, the second lower active pattern LACT2, the first lower gate electrode LGAT1, the second lower gate electrode LGAT2, the upper active pattern UACT, the upper gate electrode UGAT, the storage connection electrode STCE, the first compensation connection electrode THCE1, and the second compensation connection electrode THCE2, the display device DD4 can be connected to the aforementioned display device DD1 (see...). Figure 20 They are basically the same.

[0287] The first active pattern LACT1 and the second active pattern LACT2 can be disposed on the substrate SUB. The first active pattern LACT1 and the second active pattern LACT2 can be disposed on the same layer.

[0288] In this embodiment, the first lower active pattern LACT1 and the second lower active pattern LACT2 may include silicon semiconductors. For example, the first lower active pattern LACT1 and the second lower active pattern LACT2 may include amorphous silicon or polycrystalline silicon.

[0289] Each of the first lower active pattern LACT1 and the second lower active pattern LACT2 may have an island shape, and both the first lower active pattern LACT1 and the second lower active pattern LACT2 may be completely doped with impurities.

[0290] For example, the first lower active pattern LACT1 can correspond to the first terminal of the storage capacitor CST, and the second lower active pattern LACT2 can correspond to the second terminal of the second compensation capacitor CTH2.

[0291] The first lower gate electrode LGAT1 can be disposed on the first insulating layer IL1.

[0292] The first lower gate electrode LGAT1 may have an island shape and may overlap with the first lower active pattern LACT1 and the second lower active pattern LACT2.

[0293] For example, the first lower gate electrode LGAT1 can correspond to the second terminal of the storage capacitor CST. Alternatively, the first lower gate electrode LGAT1 can correspond to the first terminal of the first compensation capacitor CTH1 and the first terminal of the second compensation capacitor CTH2.

[0294] The second lower gate electrode LGAT2 can be disposed on the second insulating layer IL2.

[0295] The second lower gate electrode LGAT2 may have an island shape and may overlap with the first lower active pattern LACT1, the second lower active pattern LACT2 and the first lower gate electrode LGAT1.

[0296] For example, the second lower gate electrode LGAT2 can correspond to the second terminal of the first compensation capacitor CTH1. Alternatively, the second lower gate electrode LGAT2 can correspond to the lower gate terminal of the first transistor T1.

[0297] The active pattern UACT can be set on the third insulating layer IL3.

[0298] In an embodiment, the active pattern UACT may include an oxide semiconductor.

[0299] The upper active pattern UACT can have an island shape and can overlap with the second lower gate electrode LGAT2. In addition, the upper active pattern UACT can further overlap with the first lower active pattern LACT1, the second lower active pattern LACT2 and the first lower gate electrode LGAT1.

[0300] The upper gate electrode UGAT can be disposed on the fourth insulating layer IL4.

[0301] The upper gate electrode UGAT can have an island shape and can overlap with the upper active pattern UACT. In addition, the upper gate electrode UGAT can overlap with the first lower active pattern LACT1, the second lower active pattern LACT2, the first lower gate electrode LGAT1, and the second lower gate electrode LGAT2.

[0302] Data voltage (see DATA) Figure 26 The upper gate electrode UGAT can be applied. The second lower gate electrode LGAT2, the active pattern UACT, and the upper gate electrode UGAT can form the first transistor T1 (see...). Figure 26 ).

[0303] The storage connection electrode STCE, the first compensation connection electrode THCE1, and the second compensation connection electrode THCE2 can be disposed on the fifth insulating layer IL5.

[0304] The storage connection electrode STCE can have an island shape and can contact the first lower active pattern LACT1 and the upper gate electrode UGAT.

[0305] For example, the storage connection electrode STCE can contact the first lower active pattern LACT1 and the upper gate electrode UGAT. In other words, the upper gate electrode UGAT can be electrically connected to the first lower active pattern LACT1 through the storage connection electrode STCE.

[0306] The first compensation connection electrode THCE1 may have an island shape and may contact the first lower gate electrode LGAT1 and the upper active pattern UACT.

[0307] For example, the active pattern UACT can be electrically connected to the first lower gate electrode LGAT1 via the first compensation connection electrode THCE1.

[0308] The second compensation connection electrode THCE2 may have an island shape and may contact the second lower active pattern LACT2 and the second lower gate electrode LGAT2.

[0309] For example, the second lower gate electrode LGAT2 can be electrically connected to the second lower active pattern LACT2 via the second compensation connection electrode THCE2.

[0310] The first lower active pattern LACT1 and the first lower gate electrode LGAT1 can form a storage capacitor CST, the second lower active pattern LACT2 and the first lower gate electrode LGAT1 can form a second compensation capacitor CTH2, and the first lower gate electrode LGAT1 and the second lower gate electrode LGAT2 can form a first compensation capacitor CTH1.

[0311] Based on the area of ​​the first lower active pattern LACT1 and the area of ​​the second lower active pattern LACT2, the capacitance of the storage capacitor CST and the capacitance of the second compensation capacitor CTH2 can be set.

[0312] The display device DD1 according to the embodiment (see also) Figure 20 ), display device DD2 (see Figure 23 ), display device DD3 (see Figure 24 The display device DD4 can be applied to various electronic devices. According to the embodiments, the electronic device may include the aforementioned display devices DD1, DD2, DD3, and DD4, and may also include additional modules or devices having functions different from those of the display devices DD1, DD2, DD3, and DD4.

[0313] Figure 28 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0314] Reference Figure 28 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0315] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0316] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0317] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0318] At least one of the components of the electronic device 10 described above may be included in the display device according to the above embodiment. Additionally, some of the aforementioned independent modules may be included in the display device, while other modules may be provided separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided separately from the display device.

[0319] Figure 29 This is a schematic diagram of an electronic device.

[0320] Reference Figure 29 The various electronic devices used in the display device according to the embodiments may include not only image display electronic devices, but also wearable electronic devices including display modules or vehicle electronic devices 10_3 including display modules. Image display electronic devices may be smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, or desktop monitors 10_1e, etc. Wearable electronic devices may be smart glasses 10_2a, head-mounted displays 10_2b, or smartwatches 10_2c, etc. Vehicle electronic devices 10_3 may be central information displays (CIDs) or rearview mirror displays installed on the vehicle's dashboard and center console, etc.

[0321] Although the above description has been explained with reference to embodiments of this disclosure, it will be understood that those skilled in the art can modify and alter this disclosure in various ways without substantially departing from the novel teachings and advantages of this disclosure. Therefore, it will be understood that all such modifications are intended to be included within the scope of this disclosure as defined in the appended claims.

Claims

1. A display device, wherein, The display device includes: The first active pattern is set on the substrate; A first lower gate electrode is disposed on the first lower active pattern, and the first lower gate electrode together with the first lower active pattern forms a storage capacitor; The second lower gate electrode is disposed on the first lower gate electrode, and the second lower gate electrode together with the first lower gate electrode form the first compensation capacitor; An active pattern is disposed on the second lower gate electrode and electrically connected to the first lower gate electrode; and The upper gate electrode is disposed on the upper active pattern and electrically connected to the first lower active pattern.

2. The display device according to claim 1, wherein, The first lower gate electrode overlaps with the first lower active pattern and the second lower gate electrode.

3. The display device according to claim 1, wherein, The area of ​​the first lower active pattern is larger than the area of ​​the upper gate electrode.

4. The display device according to claim 1, wherein, The area of ​​the first lower gate electrode is larger than the area of ​​the upper gate electrode.

5. The display device according to claim 1, wherein, The area of ​​the second lower gate electrode is larger than the area of ​​the upper gate electrode.

6. The display device according to claim 1, wherein, The second lower gate electrode, the active pattern, and the upper gate electrode form a driving transistor.

7. The display device according to claim 6, wherein, A data voltage is applied to the upper gate electrode.

8. The display device according to claim 1, wherein, Each of the first lower active pattern, the first lower gate electrode, the second lower gate electrode, the upper active pattern, and the upper gate electrode has an island shape.

9. The display device according to claim 1, wherein, The display device further includes: A storage connection electrode is disposed on the upper gate electrode, and the first lower active pattern is connected to the upper gate electrode.

10. The display device according to claim 9, wherein, The storage connection electrode has an island shape.

11. The display device according to claim 9, wherein, The display device further includes: A reference voltage vertical line is disposed on the storage connection electrode and overlaps with the storage connection electrode.

12. The display device according to claim 1, wherein, The display device further includes: A first compensation connection electrode is disposed on the upper gate electrode, and the first lower gate electrode is connected to the upper active pattern.

13. The display device according to claim 12, wherein, The first compensation connection electrode has an island shape.

14. The display device according to claim 12, wherein, The display device further includes: The data cable is mounted on the first compensation connection electrode. The first compensation connection electrode overlaps with the upper gate electrode and the data line.

15. The display device according to claim 1, wherein, The first lower active pattern includes silicon semiconductor material, and The first lower active pattern is completely doped with impurities.

16. The display device according to claim 15, wherein, The display device further includes: The first active pattern is disposed on the same layer as the first lower active pattern and includes silicon semiconductor material. The first active pattern portion is doped with impurities.

17. The display device according to claim 1, wherein, The upper gate electrode is in direct contact with the first lower active pattern.

18. The display device according to claim 1, wherein, The display device further includes: The second lower active pattern is disposed on the same layer as the first lower active pattern. The second lower active pattern and the first lower gate electrode together form a second compensation capacitor and are electrically connected to the second lower gate electrode. A first compensation connection electrode is disposed on the upper gate electrode, and the first compensation connection electrode connects the first lower gate electrode to the upper active pattern; and The second compensation connection electrode is disposed on the same layer as the first compensation connection electrode, and the second compensation connection electrode connects the second lower active pattern to the second lower gate electrode.

19. A display device, wherein, The display device includes: The first active pattern is set on the substrate; A first lower gate electrode is disposed on the first lower active pattern, and the first lower gate electrode together with the first lower active pattern forms a compensation capacitor; The second lower gate electrode is disposed on the first lower gate electrode, and the second lower gate electrode together with the first lower gate electrode form a storage capacitor; An active pattern is disposed on the second lower gate electrode and electrically connected to the first lower gate electrode; and The upper gate electrode is disposed on the upper active pattern and electrically connected to the first lower active pattern. The data voltage is applied to the second lower gate electrode.

20. An electronic device, wherein, The electronic device includes: Host; The display device receives control signals and image data from the host computer; and The power supply is configured to provide power to the display device. The display device is the display device according to any one of claims 1 to 19.

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