Display panel, display device and preparation method of display panel

Abstract

The invention relates to a display panel, a display device and a preparation method of the display panel. The display panel is provided with a display area and a binding area located on one side of the display area. The display panel comprises a substrate, a first signal lead and a binding bonding pad. The first signal lead is arranged on one side of the substrate and located in the binding area. The binding pad is arranged on one side, far away from the substrate, of the first signal lead; the binding bonding pad comprises a first bonding pad and a second bonding pad which are stacked in the direction away from the substrate; the first bonding pad is used for connecting the second bonding pad and the first signal lead. Wherein in the thickness direction of the substrate, the outer contour of at least part of the orthographic projection of the second bonding pad on the substrate is located in the outer contour of the orthographic projection of the first bonding pad on the substrate. Therefore, the discontinuity of the subsequently prepared cathode can be avoided, so that the first bonding pad and the second bonding pad are prevented from forming a cavity through the cathode in the subsequent etching process, and the reliability of the binding process can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a display device, and a method for manufacturing the display panel. Background Technology

[0002] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Currently, the cathode in the bonding area of ​​an OLED display panel is affected by other structures in the bonding area, leading to discontinuities in the cathode and affecting the reliability of the bonding process between the display panel and the bonding chip. Summary of the Invention

[0003] Therefore, it is necessary to provide a display panel, a display device, and a method for manufacturing the display panel that can improve the reliability of the bonding process.

[0004] In a first aspect, embodiments of this application provide a display panel having a display area and a binding area located on one side of the display area. The display panel includes:

[0005] Substrate;

[0006] The first signal lead is located on one side of the substrate and in the bonding region;

[0007] A bonding pad is provided on the side of the first signal lead away from the substrate; the bonding pad includes a first pad and a second pad stacked in a direction away from the substrate; the first pad is used to connect the second pad and the first signal lead;

[0008] Wherein, along the thickness direction of the substrate, at least a portion of the outer contour of the orthographic projection of the second pad on the substrate is located within the outer contour of the orthographic projection of the first pad on the substrate.

[0009] The display panel provided in this application embodiment has a first signal lead disposed on one side of the substrate and located in the bonding area. A bonding pad is disposed on the side of the first signal lead away from the substrate; the bonding pad includes a first pad and a second pad stacked along a direction away from the substrate. Specifically, along the thickness direction of the substrate, the outer contour of at least a portion of the orthographic projection of the second pad on the substrate lies within the outer contour of the orthographic projection of the first pad on the substrate. This application can prevent the edge tip of the second pad from affecting the structure of the first pad by ensuring that the outer contour of at least a portion of the orthographic projection of the second pad on the substrate lies within the outer contour of the orthographic projection of the first pad on the substrate along the thickness direction of the substrate. This avoids discontinuities in the subsequently fabricated cathode, thereby preventing the formation of voids between the first and second pads during subsequent etching, and improving the reliability of the bonding process.

[0010] In one embodiment, along the thickness direction of the substrate, the outer contour of the entire orthographic projection of the second pad on the substrate lies within the outer contour of the orthographic projection of the first pad on the substrate.

[0011] In one embodiment, the display panel further includes:

[0012] A first insulating layer is disposed on the side of the bonding pad away from the substrate; the first insulating layer includes an opening that exposes a portion of the second pad, and the orthographic projection of the opening onto the substrate is located within the outer contour of the orthographic projection of the second pad onto the substrate along the thickness direction of the substrate.

[0013] In one embodiment, the first insulating layer includes insulating sidewalls that enclose an opening; the first pad includes a first sidewall away from the opening, the first sidewalls intersecting the thickness direction of the substrate, and along the thickness direction of the substrate, the outline of the orthographic projection of the first sidewall on the substrate is located outside the outer outline of the orthographic projection of the second pad on the substrate, and the outline of the orthographic projection of the first sidewall on the substrate does not overlap with the outline of the orthographic projection of the insulating sidewall on the substrate.

[0014] Optionally, the outline of the orthographic projection of the first sidewall onto the substrate is located outside the outline of the orthographic projection of the insulating sidewall onto the substrate.

[0015] In one embodiment, the second pad includes a second sidewall away from the opening, the second sidewall intersecting the thickness direction of the substrate, the outline of the orthographic projection of the second sidewall on the substrate along the thickness direction of the substrate is outside the outline of the orthographic projection of the opening on the substrate, and the outline of the orthographic projection of the second sidewall on the substrate does not overlap with the outline of the orthographic projection of the insulating sidewall on the substrate.

[0016] Optionally, the outline of the orthographic projection of the first sidewall onto the substrate and the outline of the orthographic projection of the second sidewall onto the substrate do not overlap.

[0017] In one embodiment, the first pad has a first recess, the second pad has a second recess, and along the thickness direction of the substrate, the outline of the orthogonal projection of the second recess on the substrate is located within the outline of the orthogonal projection of the opening on the substrate, and the outline of the orthogonal projection of the second recess on the substrate is located within the outline of the orthogonal projection of the first recess on the substrate.

[0018] Optionally, along the thickness direction of the substrate, the outline of the orthographic projection of the first recess on the substrate lies within the outline of the orthographic projection of the opening on the substrate.

[0019] In one embodiment, the display panel further includes:

[0020] An insulating structure is disposed between a first signal lead and a first pad. The insulating structure includes a first via and a first recessed portion disposed within the first via and connected to the first signal lead.

[0021] Optionally, along the thickness direction of the substrate, the orthographic projection of the first via on the substrate lies within the outline of the orthographic projection of the first signal lead on the substrate;

[0022] Optionally, the insulation structure includes a second insulation layer and a third insulation layer;

[0023] The second insulating layer is disposed between the first signal lead and the first pad. The second insulating layer includes a first sub-hole, and a first recess is disposed in the first sub-hole and connected to the first signal lead.

[0024] The third insulating layer is disposed between the second insulating layer and the first pad. The third insulating layer includes a second sub-hole, and a first recess is disposed in the second sub-hole and connected to the first signal lead.

[0025] The first sub-hole and the second sub-hole form a first via; the first recess is electrically connected to the first signal lead, and the first recess is insulated from the hole wall of the first sub-hole and the hole wall of the second sub-hole.

[0026] Optionally, along the thickness direction of the substrate, the orthographic projection of the first sub-hole on the substrate is located within the outline of the orthographic projection of the first signal lead on the substrate, and a portion of the outline of the orthographic projection of the second insulating layer on the substrate is located within the outline of the orthographic projection of the first signal lead on the substrate.

[0027] Optionally, along the thickness direction of the substrate, the orthographic projection of the second sub-hole on the substrate is located within the outline of the orthographic projection of the first signal lead on the substrate, the outline of the orthographic projection of the third insulating layer on the substrate is located within the outline of the orthographic projection of the second insulating layer on the substrate, and a portion of the outline of the orthographic projection of the third insulating layer on the substrate is located within the outline of the orthographic projection of the first signal lead on the substrate.

[0028] In one embodiment, the first pad further includes a first flat portion and a first connecting portion that are interconnected; the first flat portion is connected to a first signal lead, and the first connecting portion and the first flat portion form a first recess; the first connecting portion is disposed on the sidewall of the first via.

[0029] Optionally, the second pad further includes a second flat portion and a second connecting portion that are interconnected; the second flat portion is connected to the first flat portion, and the second connecting portion and the second flat portion surround to form a second recess; the second connecting portion is disposed on the sidewall of the first recess.

[0030] Optionally, the first pad further includes a third flat portion, which is connected to the side of the first connection portion away from the first flat portion. Along the thickness direction of the substrate, the outline of the orthographic projection of the third flat portion on the substrate is outside the outline of the orthographic projection of the first sub-hole on the substrate.

[0031] Optionally, the first pad further includes a third connecting portion and a fourth flat portion, a first sidewall located on the side surface of the third connecting portion, the first sidewall being connected to the third flat portion and the fourth flat portion, and along the thickness direction of the substrate, the outline of the orthographic projection of the fourth flat portion on the substrate is outside the outline of the orthographic projection of the first sub-hole on the substrate.

[0032] Optionally, the second pad further includes a fifth flat portion, which is connected to the side of the second connection portion away from the second flat portion. The second sidewall is located on the side surface of the fifth flat portion. Along the thickness direction of the substrate, the outline of the orthogonal projection of the fifth flat portion on the substrate is outside the outline of the orthogonal projection of the second sub-hole on the substrate.

[0033] In one embodiment, the first pad includes at least two metal layers, and the second pad includes at least two metal layers;

[0034] Optionally, the first pad includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially.

[0035] Optionally, the material of the first metal layer includes titanium, the material of the second metal layer includes aluminum, and the material of the third metal layer includes titanium.

[0036] Optionally, the first pad and the second pad are made of the same material.

[0037] In one embodiment, the display area includes a gate, a capacitor, a data signal line, and a power signal line;

[0038] The display panel also includes a second signal lead, which is disposed on the side of the substrate facing the first pad, connected to the first pad, and located in the bonding area;

[0039] The first signal lead is set on the same layer as the gate, the first pad is set on the same layer as the data signal line, and the second pad is set on the same layer as the power signal line; some of the second signal leads are set on the same layer as the gate, and the remaining second signal leads are set on the same layer as the capacitor.

[0040] Optionally, there are multiple first signal leads and multiple second signal leads;

[0041] Optionally, the number of the first signal lead and the second signal lead are the same;

[0042] Optionally, the second signal lead and the first signal lead are arranged alternately.

[0043] In one embodiment, along the thickness direction of the substrate, the orthographic projection of the first pad on the substrate covers a portion of the orthographic projection of the first signal lead on the substrate.

[0044] And / or the orthogonal projection of the first pad on the substrate covers a portion of the orthogonal projection of the second signal lead on the substrate.

[0045] In one embodiment, the display panel further includes a first electrode layer, a light-emitting layer group, and a second electrode layer;

[0046] The first electrode layer, the light-emitting layer group layer, and the second electrode layer are stacked on one side of the substrate and located in the display area.

[0047] In one embodiment, the display panel further includes:

[0048] A pixel definition layer is disposed on the same layer as the first insulating layer; the pixel definition layer encloses and forms a pixel opening, and at least a portion of the light-emitting layer group is located within the pixel opening.

[0049] In one embodiment, the display panel further includes an isolation structure disposed on a substrate, the isolation structure defining a plurality of isolation openings;

[0050] The light-emitting layer group includes multiple light-emitting parts, which are correspondingly disposed in multiple isolation openings;

[0051] Optionally, the isolation structure includes an isolation body and a blocking portion stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the blocking portion on the substrate is located outside the outer contour of the orthographic projection of the isolation body on the substrate.

[0052] Optionally, the insulator includes a conductive material, and the first electrode layer is electrically connected to the insulator;

[0053] Optionally, the insulator includes at least one metal layer;

[0054] Optionally, the insulator includes a fourth metal layer and a fifth metal layer stacked in a direction away from the substrate, wherein the outer contour of the orthographic projection of the fourth metal layer on the substrate is located outside the outer contour of the orthographic projection of the fifth metal layer on the substrate.

[0055] In one embodiment, the display panel includes:

[0056] Substrate;

[0057] The first signal lead is located on one side of the substrate;

[0058] A bonding pad is provided on the side of the first signal lead away from the substrate; the bonding pad includes a first sidewall that intersects the thickness direction of the substrate;

[0059] A first insulating layer is disposed on the side of the bonding pad away from the substrate; the first insulating layer includes an opening and an insulating sidewall, the opening exposing a portion of the bonding pad, and the insulating sidewall enclosing the opening;

[0060] Wherein, along the thickness direction of the substrate, the outline of the orthographic projection of the first sidewall on the substrate is located outside the outer outline of the orthographic projection of the opening on the substrate, and the outline of the orthographic projection of the first sidewall on the substrate does not overlap with the outline of the orthographic projection of the insulating sidewall on the substrate.

[0061] Secondly, embodiments of this application provide a display device, including a display panel and a bonding chip, wherein the bonding chip and the bonding pads of the display panel are electrically connected.

[0062] The display device provided in this application embodiment can prevent the edge tip of the second pad from affecting the structure of the first pad by ensuring that at least a portion of the orthographic projection of the second pad on the substrate lies within the orthographic projection of the first pad on the substrate along the thickness direction of the substrate. This avoids discontinuities in the subsequently fabricated cathode, thereby preventing the formation of voids between the first and second pads during subsequent etching and improving the reliability of the bonding process.

[0063] Thirdly, embodiments of this application provide a method for manufacturing a display panel, which can manufacture the display panel described in the first aspect. The method includes:

[0064] A substrate is provided, having a display area and a bonding area located on one side of the display area;

[0065] A first signal lead, a first pad, a second pad, and a first insulating layer are sequentially stacked on one side of a substrate. The first signal lead, the first pad, the second pad, and the first insulating layer are all located in a bonding region. The first insulating layer includes an opening that exposes a portion of the second pad. Along the thickness direction of the substrate, the orthographic projection of the opening on the substrate is located within the outer contour of the orthographic projection of the second pad on the substrate. At least a portion of the outer contour of the orthographic projection of the second pad on the substrate is located within the outer contour of the orthographic projection of the first pad on the substrate.

[0066] A second electrode layer is formed on the side of the first insulating layer away from the second pad. The second electrode layer includes a first portion and a second portion. The first portion is at least partially located in the display area, and the second portion extends from the surface of the first insulating layer to the surface of the exposed second pad.

[0067] Remove the second portion of the second electrode layer.

[0068] The display panel fabrication method provided in this application embodiment can, along the thickness direction of the substrate, ensure that at least a portion of the outer contour of the orthographic projection of the second pad on the substrate lies within the outer contour of the orthographic projection of the first pad on the substrate, thereby preventing the edge tip of the second pad from affecting the structure of the first pad. This avoids discontinuities in the subsequently fabricated cathode, thus preventing the formation of voids between the first and second pads during subsequent etching, and improving the reliability of the bonding process. Attached Figure Description

[0069] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0070] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application.

[0071] Figure 2 This is a top view schematic diagram of a display panel provided in an embodiment of this application.

[0072] Figure 3 This is a schematic diagram of another structure of a display panel provided in one embodiment of this application.

[0073] Figure 4 This is a schematic diagram of another structure of a display panel provided in an embodiment of this application.

[0074] Figure 5 This is a schematic diagram of another structure of a display panel provided in an embodiment of this application.

[0075] Figure 6 This is a schematic diagram of another structure of a display panel provided in an embodiment of this application.

[0076] Figure 7 This is another top view schematic diagram of a display panel provided in an embodiment of this application.

[0077] Figure 8 This is a top view of the arrangement of the first signal lead and the second signal lead in a display panel provided in an embodiment of this application.

[0078] Figure 9 This is a schematic diagram of another structure of a display panel provided in an embodiment of this application.

[0079] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0080] Figure 11 This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application.

[0081] Explanation of reference numerals in the attached figures:

[0082] 100. Display device; 10. Display panel; 101. Display area; 102. Bonding area; 11. Substrate; 12. First signal lead; 13. Bonding pad; 131. First pad; 1311. First sidewall; 1312. First recess; 1313. First flat portion; 1314. First connecting portion; 1315. Third flat portion; 1316. Third connecting portion; 1317. Fourth flat portion; 132. Second pad; 132 1. Second sidewall; 1322. Second recessed portion; 1323. Second flat portion; 1324. Second connecting portion; 1325. Fifth flat portion; 14. First insulating layer; 141. Insulating sidewall; 15. Insulating structure; 151. Second insulating layer; 152. Third insulating layer; 16. Second signal lead; 17. First electrode layer; 18. Light-emitting layer group; 19. Second electrode layer; 20. Isolation structure; 21. Isolator; 22. Blocking portion. Detailed Implementation

[0083] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0084] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0086] Currently, the cathode in the bonding area of ​​an OLED display panel is affected by other structures in the bonding area, which can lead to discontinuity of the cathode in the bonding area and affect the reliability of the bonding process between the display panel and the bonding chip.

[0087] Specifically, in the related technology, bonding pads and signal leads are provided in the bonding area of ​​the display panel. The signal leads are used to connect the bonding pads and the substrate of the display panel, and the bonding pads are used to connect with the bonding chip, thereby controlling the display of the display panel through the bonding chip.

[0088] In this bonding process, one bonding pad covers another. Because the covered pad is composed of multiple metal layers with varying properties (e.g., different etching resistance and developer resistance), this can cause a bend or pit at the edge of the covered pad, resulting in discontinuities in the subsequently fabricated cathode. After cathode fabrication, multiple etching processes are required. Due to these discontinuities, the bonding pads cannot be protected from etching, leading to voids in the bonding pads. This disrupts the subsequent bonding process and compromises the reliability of the bonding between the display panel and the bonding chip.

[0089] In addition, in related technologies, the overlap of the slope of the insulating layer and the bonding pad along the thickness direction of the substrate of the display panel can lead to an excessively large height difference in the subsequent cathode, resulting in cathode discontinuity. Similarly, it can cause voids in the bonding pad, affecting the normal progress of the subsequent bonding process and the reliability of the bonding process between the display panel and the bonding chip.

[0090] Firstly, referring to Figure 1 As shown, this application embodiment provides a display panel 10, having a display area 101 and a bonding area 102 located on one side of the display area 101. The display panel 10 includes a substrate 11, a first signal lead 12, and bonding pads 13. The first signal lead 12 is disposed on one side of the substrate 11 and located in the bonding area 102. The bonding pads 13 are disposed on the side of the first signal lead 12 away from the substrate 11; the bonding pads 13 include a first pad 131 and a second pad 132 stacked along a direction away from the substrate 11. Wherein, along the thickness direction of the substrate 11, at least a portion of the outer contour of the orthographic projection of the second pad 132 onto the substrate 11 lies within the outer contour of the orthographic projection of the first pad 131 onto the substrate 11.

[0091] The display panel 10 provided in this application embodiment has a first signal lead 12 disposed on one side of a substrate 11 and located in a bonding area 102. A bonding pad 13 is disposed on the side of the first signal lead 12 away from the substrate 11. The bonding pad 13 includes a first pad 131 and a second pad 132 stacked along a direction away from the substrate 11. The first pad 131 is used to connect the second pad 132 and the first signal lead 12. Specifically, along the thickness direction of the substrate 11, the outer contour of at least a portion of the orthographic projection of the second pad 132 on the substrate 11 lies within the outer contour of the orthographic projection of the first pad 131 on the substrate 11. This application can prevent the edge tip of the second pad 132 from affecting the structure of the first pad 131 by ensuring that the outer contour of at least a portion of the orthographic projection of the second pad 132 on the substrate 11 lies within the outer contour of the orthographic projection of the first pad 131 on the substrate 11 along the thickness direction of the substrate 11. In this way, discontinuities in the cathode fabricated later can be avoided, thereby preventing the formation of voids in the first pad 131 and the second pad 132 during the subsequent etching process, which can improve the reliability of the bonding process.

[0092] Specifically, the display panel 10 includes a display area 101 and a bonding area 102. The display area 101 is used to display text, images, videos, and other functions. The bonding area 102 is used to bond the display area 101 to a bonding chip, so that the display of the display area 101 can be controlled by driving the bonding chip to display the content required by the user. The first signal lead 12 is located on one side of the substrate 11, and the bonding pad 13 is located on the side of the first signal lead 12 away from the substrate 11, so that the substrate 11 can support and fix the first signal lead 12 and the bonding pad 13, etc.

[0093] Since the distance between the bonding chip and the first signal lead 12 is quite large, if only one pad is set to connect the bonding chip and the first signal lead 12, the thickness of the first pad 131 will be too large, which will easily cause damage to the first pad 131 and affect the normal bonding process between the bonding chip and the display panel 10.

[0094] Furthermore, the bonding pad 13 includes a first pad 131 and a second pad 132 stacked along a direction away from the substrate 11, which can reduce the risk of damage to the bonding pad 13. At the same time, it can reduce the resistance of the bonding pad 13, so that the bonding process between the bonding chip and the display panel 10 can be carried out smoothly.

[0095] Because the outer contour of at least a portion of the orthographic projection of the second pad 132 on the substrate 11 lies within the outer contour of the orthographic projection of the first pad 131 on the substrate 11 along the thickness direction of the substrate 11, it can be ensured that the edge tip of the second pad 132 does not contact the edge tip of the first pad 131. This avoids the edge tip of the second pad 132 affecting the structure of the first pad 131 and prevents the edge tip of the second pad 132 from causing the first pad 131 to form a bend or pit. Consequently, during the subsequent cathode fabrication process, the cathode can form a continuous and complete structure. Furthermore, because the cathode forms a continuous and complete structure, the bonding pad 13 can be protected from etching during subsequent etching processes, thereby preventing voids in the bonding pad 13, ensuring the integrity of the bonding pad 13 structure, and improving the reliability of the bonding process.

[0096] In one embodiment, along the thickness direction of the substrate, the outer contour of the entire orthographic projection of the second pad 132 on the substrate 11 lies within the outer contour of the orthographic projection of the first pad 131 on the substrate 11.

[0097] Thus, it can be understood that this ensures the edges of the second pad 132 and the first pad 131 are completely out of contact, thereby preventing the edges of the second pad 132 from affecting the structure of the first pad 131 and avoiding the formation of bends or pits in the first pad 131. Consequently, during the subsequent cathode fabrication process, a continuous and complete cathode structure can be formed. Furthermore, because the cathode forms a continuous and complete structure, the bonding pad 13 can be protected from etching during subsequent etching processes, thus preventing voids in the bonding pad 13, ensuring the integrity of the bonding pad 13 structure, and improving the reliability of the bonding process.

[0098] In one embodiment, reference Figure 3 As shown, the display panel 10 also includes a first insulating layer 14. The first insulating layer 14 is disposed on the side of the bonding pad 13 away from the substrate 11; the first insulating layer 14 includes an opening that exposes a portion of the second pad 132, and the orthographic projection of the opening on the substrate 11 along the thickness direction of the substrate 11 is located within the outer contour of the orthographic projection of the second pad 132 on the substrate 11.

[0099] Thus, on the one hand, the first insulating layer 14 can prevent electrical connections between the bonding pad 13 and other structures in the display panel 10, thus avoiding short circuits in the display panel 10 and ensuring the normal operation of each component of the display panel 10. On the other hand, since the orthographic projection of the opening on the substrate 11 is located within the outer contour of the orthographic projection of the second bonding pad 132 on the substrate 11, the first insulating layer 14 can continuously cover the surfaces of the first bonding pad 131 and the second bonding pad 132, thereby ensuring the continuity of the first insulating layer 14, and further ensuring the continuity of the cathode prepared on the first insulating layer 14, ultimately improving the reliability of the bonding process.

[0100] In one embodiment, reference Figure 3 As shown, the first insulating layer 14 includes an insulating sidewall 141, which encloses an opening; the first pad 131 includes a first sidewall 1311 away from the opening, which intersects the thickness direction of the substrate 11. Along the thickness direction of the substrate 11, the outline of the orthographic projection of the first sidewall 1311 on the substrate 11 is outside the outer outline of the orthographic projection of the second pad 132 on the substrate 11, and the outline of the orthographic projection of the first sidewall 1311 on the substrate 11 does not overlap with the outline of the orthographic projection of the insulating sidewall 141 on the substrate 11.

[0101] It should be noted that the first sidewall 1311 is located away from the opening of the first pad 131 and intersects with the thickness direction of the substrate 11. Specifically, the first sidewall 1311 can be formed for various reasons. For example, the first sidewall 1311 can be formed based on the thickness of the first pad 131, or it can be formed due to the presence of other film layers below the first pad 131, or due to the height difference between the first pad 131 and the lower film layer. Here, the reasons for the formation of the first sidewall 1311 will not be elaborated further. It should be noted that, regardless of how the first sidewall 1311 is formed, along the thickness direction of the substrate 11, the outline of the orthogonal projection of the first sidewall 1311 on the substrate 11 is located outside the outer outline of the orthogonal projection of the second pad 132 on the substrate 11, and the outline of the orthogonal projection of the first sidewall 1311 on the substrate 11 does not overlap with the outline of the orthogonal projection of the insulating sidewall 141 on the substrate 11, that is, the outline of the orthogonal projection of the first sidewall 1311 on the substrate 11 does not coincide with the outline of the orthogonal projection of the insulating sidewall 141 on the substrate 11.

[0102] Thus, since the outline of the orthographic projection of the first sidewall 1311 on the substrate 11 along the thickness direction of the substrate 11 is outside the outer outline of the orthographic projection of the second pad 132 on the substrate 11, and the outline of the orthographic projection of the first sidewall 1311 on the substrate 11 does not overlap with the outline of the orthographic projection of the insulating sidewall 141 on the substrate 11, the insulating sidewall 141 of the first insulating layer 14 will not stack at the orthographic projection position of the first sidewall 1311 along the thickness direction of the substrate 11, and there is no large height difference at the position of the insulating sidewall 141. Therefore, in the subsequent cathode fabrication process, it can be ensured that the cathode also does not have a large height difference at the position corresponding to the insulating sidewall 141, thereby ensuring the continuity of the cathode. In the subsequent etching process, the bonding pad 13 can be protected from etching by the continuous and complete cathode, thereby avoiding voids in the bonding pad 13, ensuring the integrity of the bonding pad 13 structure, and thus improving the reliability of the bonding process.

[0103] In one embodiment, the outline of the orthographic projection of the first sidewall 1311 onto the substrate 11 is outside the outline of the orthographic projection of the insulating sidewall 141 onto the substrate 11.

[0104] Thus, along the thickness direction of the substrate 11, it can be further ensured that there is no large height difference at the position of the insulating sidewall 141, and that the first insulating layer 14 covers part of the surface of the first pad 131, thereby further ensuring the integrity of the cathode and further improving the reliability of the bonding process.

[0105] In one embodiment, reference Figure 3 and Figure 4 As shown, the second pad 132 includes a second sidewall 1321 away from the opening. The second sidewall 1321 intersects the thickness direction of the substrate 11. Along the thickness direction of the substrate 11, the outline of the orthographic projection of the second sidewall 1321 on the substrate 11 is outside the outline of the orthographic projection of the opening on the substrate 11, and the outline of the orthographic projection of the second sidewall 1321 on the substrate 11 does not overlap with the outline of the orthographic projection of the insulating sidewall 141 on the substrate 11.

[0106] Similarly, it should be noted that the second sidewall 1321 is located away from the opening of the second pad 132 and intersects with the thickness direction of the substrate 11. Specifically, the second sidewall 1321 can be formed for various reasons. For example, the second sidewall 1321 can be formed based on the thickness of the second pad 132, or it can be formed due to the height difference between the second pad 132 and the first pad 131, which is disposed on the lower layer of the second pad 132. Here, the reasons for the formation of the second sidewall 1321 will not be elaborated. It should be noted that, regardless of how the second sidewall 1321 is formed, the outline of the orthographic projection of the second sidewall 1321 on the substrate 11 is outside the outline of the orthographic projection of the opening on the substrate 11, and the outline of the orthographic projection of the second sidewall 1321 on the substrate 11 does not overlap with the outline of the orthographic projection of the insulating sidewall 141 on the substrate 11. That is, the outline of the orthographic projection of the second sidewall 1321 on the substrate 11 does not coincide with the outline of the orthographic projection of the insulating sidewall 141 on the substrate 11.

[0107] Thus, since the outline of the orthographic projection of the second sidewall 1321 on the substrate 11 along the thickness direction of the substrate 11 is outside the outline of the orthographic projection of the opening on the substrate 11, and the outline of the orthographic projection of the second sidewall 1321 on the substrate 11 does not overlap with the outline of the orthographic projection of the insulating sidewall 141 on the substrate 11, the insulating sidewall 141 of the first insulating layer 14 will not stack at the orthographic projection position of the second sidewall 1321 along the thickness direction of the substrate 11, and there is no large height difference at the position of the insulating sidewall 141. Therefore, in the subsequent cathode fabrication process, it can be ensured that the cathode also does not have a large height difference at the position corresponding to the insulating sidewall 141, thereby ensuring the continuity of the cathode. In the subsequent etching process, the bonding pad 13 can be protected from etching by the continuous and complete cathode, thereby avoiding voids in the bonding pad 13, ensuring the integrity of the bonding pad 13 structure, and thus improving the reliability of the bonding process.

[0108] In one embodiment, the outline of the orthographic projection of the first sidewall 1311 onto the substrate 11 and the outline of the orthographic projection of the second sidewall 1321 onto the substrate 11 do not overlap.

[0109] Thus, along the thickness direction of the substrate 11, it can be further ensured that there is no large height difference at the position of the insulating sidewall 141, and that the first insulating layer 14 covers part of the surface of the second pad 132, thereby further ensuring the integrity of the cathode and further improving the reliability of the bonding process.

[0110] In one embodiment, reference Figure 3 and Figure 4As shown, the first pad 131 has a first recess 1312, and the second pad 132 has a second recess 1322. Along the thickness direction of the substrate 11, the outline of the orthogonal projection of the second recess 1322 on the substrate 11 is located within the outline of the orthogonal projection of the opening on the substrate 11, and the outline of the orthogonal projection of the second recess 1322 on the substrate 11 is located within the outline of the orthogonal projection of the first recess 1312 on the substrate 11.

[0111] Thus, by setting the first recess 1312 and the second recess 1322, the height difference between the first pad 131 and the second pad 132 can be changed, thereby enabling the bonding pad 13 to connect with the first signal lead 12 and the bonding chip at different positions, thereby enabling the bonding chip to control the display panel 10.

[0112] In one embodiment, along the thickness direction of the substrate 11, the outline of the orthographic projection of the first recess 1312 on the substrate 11 lies within the outline of the orthographic projection of the opening on the substrate 11.

[0113] In this way, on the one hand, the first recess 1312 can be located inside the opening, thereby reducing the manufacturing difficulty of the opening; on the other hand, in the subsequent preparation of the second electrode layer 19, the contact position of the second electrode layer 19 at the opening and the first recess 1312 can be smoothly transitioned, thereby ensuring the continuity of the second electrode layer 19 and improving the reliability of the bonding process.

[0114] In one embodiment, reference Figure 5 As shown, the display panel 10 also includes an insulating structure 15. The insulating structure 15 is disposed between the first signal lead 12 and the first pad 131. The insulating structure 15 includes a first via, and a first recess 1312 is disposed in the first via and connected to the first signal lead 12.

[0115] In this way, the insulating structure 15 can block the positions of the first pad 131 and the first signal lead 12 that do not require electrical connection, thereby preventing the first pad 131 and the first signal lead 12 from short-circuiting.

[0116] In one embodiment, along the thickness direction of the substrate 11, the orthographic projection of the first via on the substrate 11 lies within the outline of the orthographic projection of the first signal lead 12 on the substrate 11.

[0117] In this way, the first pad 131 and the first signal lead 12 can be prevented from being electrically connected in places where electrical connection is not required, thus avoiding affecting the normal operation of the first pad 131 and the first signal lead 12.

[0118] In one embodiment, reference Figure 6As shown, the insulating structure 15 includes a second insulating layer 151 and a third insulating layer 152. The second insulating layer 151 is disposed between the first signal lead 12 and the first pad 131. The second insulating layer 151 includes a first sub-hole, and a first recess 1312 is disposed within the first sub-hole and connected to the first signal lead 12. The third insulating layer 152 is disposed between the second insulating layer 151 and the first pad 131. The third insulating layer 152 includes a second sub-hole, and the first recess 1312 is disposed within the second sub-hole and connected to the first signal lead 12. The first sub-hole and the second sub-hole form a first via. The first recess is electrically connected to the first signal lead 12, and the first recess 1312 is insulated from the walls of both the first and second sub-holes.

[0119] In this way, different insulation functions can be achieved through two different insulating layers, thereby blocking different electrical signals from the first pad 131 and the first signal lead 12. Since the insulating structure 15 includes a second insulating layer 151 and a third insulating layer 152, on the one hand, diversified insulation of the insulating structure 15 can be achieved, thereby improving the insulation effect on the first pad 131 and the first signal lead 12; on the other hand, it can avoid the problem of excessive thickness of a single insulating structure 15 due to the use of a single insulating layer, which would affect the service life of the insulating structure 15.

[0120] In one embodiment, along the thickness direction of the substrate 11, the orthographic projection of the first sub-hole on the substrate 11 lies within the outline of the orthographic projection of the first signal lead 12 on the substrate 11, and a portion of the outline of the orthographic projection of the second insulating layer 151 on the substrate 11 lies within the outline of the orthographic projection of the first signal lead 12 on the substrate 11.

[0121] In this way, the insulation effect on the first pad 131 and the first signal lead 12 can be improved by the second insulating layer 151.

[0122] In one embodiment, along the thickness direction of the substrate 11, the orthographic projection of the second sub-hole on the substrate 11 lies within the outline of the orthographic projection of the first signal lead 12 on the substrate 11, the outline of the orthographic projection of the third insulating layer 152 on the substrate 11 lies within the outline of the orthographic projection of the second insulating layer 151 on the substrate 11, and a portion of the outline of the orthographic projection of the third insulating layer 152 on the substrate 11 lies within the outline of the orthographic projection of the first signal lead 12 on the substrate 11.

[0123] In this way, the insulation effect on the first pad 131 and the first signal lead 12 can be improved by the third insulating layer 152.

[0124] In one embodiment, reference Figure 3As shown, the first pad 131 also includes a first flat portion 1313 and a first connecting portion 1314 that are connected to each other; the first flat portion 1313 is connected to the first signal lead 12, and the first connecting portion 1314 and the first flat portion 1313 surround to form a first recess 1312; the first connecting portion 1314 is provided on the side wall of the first via.

[0125] Thus, the first recessed portion 1312 can be formed by the first connecting portion 1314 and the first flat portion 1313, thereby changing the height difference of the first pad 131. Then, the first recessed portion 1312 can be used to connect with the first signal lead 12, so that the bonding pad 13 can be connected with the first signal lead 12 and the bonding chip at different positions, thereby enabling the bonding chip to control the display panel 10.

[0126] In one embodiment, the second pad 132 further includes a second flat portion 1323 and a second connecting portion 1324 that are interconnected; the second flat portion 1323 is connected to the first flat portion 1313, and the second connecting portion 1324 and the second flat portion 1323 surround to form a second recess 1322; the second connecting portion 1324 is disposed on the sidewall of the first recess 1312.

[0127] Thus, the second recessed portion 1322 can be formed by the second connecting portion 1324 and the second flat portion 1323, thereby changing the height difference of the second pad 132. Then, the first recessed portion 1312 can be connected to the first signal lead 12, so that the bonding pad 13 can be connected to the first signal lead 12 and the bonding chip at different positions, thereby realizing the control of the display panel 10 by the bonding chip.

[0128] In one embodiment, the first pad 131 further includes a third flat portion 1315, which is connected to the side of the first connection portion 1314 away from the first flat portion 1313. Along the thickness direction of the substrate 11, the outline of the orthographic projection of the third flat portion 1315 on the substrate 11 is outside the outline of the orthographic projection of the first sub-hole on the substrate 11.

[0129] Thus, the third flat portion 1315 can serve as a transition for the first connecting portion 1314, thereby preventing the first insulating layer 14 from bending at the inclined position of the first connecting portion 1314. Since the third flat portion 1315 is connected to the first connecting portion 1314, the third flat portion 1315 can be ensured to be continuous at the position of the first connecting portion 1314, thereby improving the reliability of the bonding process.

[0130] In one embodiment, the first pad 131 further includes a third connecting portion 1316 and a fourth flat portion 1317. A first sidewall 1311 is located on the side surface of the third connecting portion 1316. The first sidewall 1311 is connected to the third flat portion 1315 and the fourth flat portion 1317. Along the thickness direction of the substrate 11, the outline of the orthographic projection of the fourth flat portion 1317 on the substrate 11 is outside the outline of the orthographic projection of the first sub-hole on the substrate 11.

[0131] Thus, the fourth flat portion 1317 can be used to transition the first sidewall 1311, thereby preventing the first insulating layer 14 from bending at the inclined position of the first sidewall 1311. Since the fourth flat portion 1317 is connected to the first sidewall 1311, the first insulating layer 14 can be ensured to be continuous at the position of the first sidewall 1311, thereby improving the reliability of the bonding process.

[0132] In one embodiment, the second pad 132 further includes a fifth flat portion 1325, which is connected to the side of the second connection portion 1324 away from the second flat portion 1323. The second sidewall 1321 is located on the side surface of the fifth flat portion 1325. Along the thickness direction of the substrate 11, the outline of the orthographic projection of the fifth flat portion 1325 on the substrate 11 is outside the outline of the orthographic projection of the second sub-hole on the substrate 11.

[0133] In this way, the fifth flat portion 1325 can be used to transition the second connecting portion 1324, which can ensure that the film layer on the side of the second pad 132 away from the substrate 11 is continuous at the position of the second connecting portion 1324, thereby improving the reliability of the bonding process.

[0134] In one embodiment, the first pad 131 includes at least two metal layers, and the second pad 132 includes at least two metal layers.

[0135] In this way, the connection between the two metal layers, and subsequently the connection between the first signal lead 12 and the bonding chip, enables the bonding chip to control the display panel 10, thereby ensuring the normal operation of the bonding area 102. Meanwhile, since both the first pad 131 and the second pad 132 include at least two metal layers, the stability of the connection between the first signal lead 12 and the bonding chip can be improved by the arrangement of these metal layers.

[0136] In one embodiment, the first pad 131 includes a first metal layer, a second metal layer and a third metal layer stacked sequentially.

[0137] Thus, on the one hand, the height difference of the first pad 131 can be increased through the multi-layer metal first pad 131, thereby enabling the bonding pad 13 to connect with the first signal lead 12 and the bonding chip at different locations, thereby realizing the control of the display panel 10 by the bonding chip. On the other hand, the overall resistance of the first pad 131 can be reduced through the multi-layer metal first pad 131, thereby improving the stability of the connection between the first signal lead 12 and the bonding chip.

[0138] In one embodiment, the second pad 132 includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially.

[0139] Thus, on the one hand, the height difference of the second pad 132 can be increased through the multi-layered metal layers, thereby enabling the bonding pad 13 to connect with the first signal lead 12 and the bonding chip at different locations, thereby realizing the control of the display panel 10 by the bonding chip. On the other hand, the overall resistance of the second pad 132 can be reduced through the multi-layered metal layers, thereby improving the stability of the connection between the first signal lead 12 and the bonding chip.

[0140] In one embodiment, the first metal layer is made of titanium, the second metal layer is made of aluminum, and the third metal layer is made of titanium.

[0141] In this way, the resistance of the first pad 131 can be reduced by stacking three metal layers, thereby reducing the power consumption of the display panel 10 and the bonding chip.

[0142] In one example, the cross-sectional shape of the first pad 131, which is formed by the first metal layer, the second metal layer and the third metal layer, can be I-shaped.

[0143] In one embodiment, the first pad 131 and the second pad 132 are made of the same material.

[0144] Thus, on the one hand, the same material can be used to manufacture the first pad 131 and the second pad 132, reducing the manufacturing difficulty and facilitating the operator's preparation. On the other hand, since the first pad 131 and the second pad 132 are made of the same material, the compatibility of the connection between the first pad 131 and the second pad 132 can be improved during the connection process, thereby improving the stability of the connection between the first pad 131 and the second pad 132, and ultimately achieving reliable bonding between the display panel 10 and the bonding chip.

[0145] In one embodiment, reference Figure 7 and Figure 8 As shown, the display area 101 includes a gate, a capacitor, data signal lines, and power signal lines; the display panel 10 also includes a second signal lead 16. The second signal lead 16 is disposed on the side of the substrate 11 facing the first pad 131, connected to the first pad 131, and located in the bonding area 102; the first signal lead 12 is disposed on the same layer as the gate, the first pad 131 is disposed on the same layer as the data signal lines, and the second pad 132 is disposed on the same layer as the power signal lines; a portion of the second signal lead 16 is disposed on the same layer as the gate, and the remaining portion of the second signal lead 16 is disposed on the same layer as the capacitor.

[0146] In this way, the connection between the first pad 131 and the display panel 10 can be improved by adding an additional second signal lead 16, which in turn improves the connection between the display panel 10 and the bonding chip, thereby enhancing the bonding chip's control over the display panel 10 and improving the reliability of the bonding process. Simultaneously, the first signal lead 12 can be arranged on the same layer as the gate, the first pad 131 on the same layer as the data signal line, and the second pad 132 on the same layer as the power signal line; some of the second signal leads 16 can be arranged on the same layer as the gate, and the remaining second signal leads 16 can be arranged on the same layer as the capacitor, enabling the normal operation of the display area 101 and the bonding area 102 of the display panel 10.

[0147] In one embodiment, reference Figure 7 and Figure 8 As shown, there are multiple first signal leads 12 and multiple second signal leads 16.

[0148] In this way, the connection between the display panel 10 and the bonding chip can be further improved through multiple first signal leads 12 and multiple second signal leads 16, thereby further improving the bonding chip's control over the display panel 10 and further improving the reliability of the bonding process.

[0149] In one embodiment, reference Figure 7 and Figure 8 As shown, the number of first signal leads 12 and second signal leads 16 are the same.

[0150] In this way, the connection capability between the first signal lead 12 and the first pad 131 can be guaranteed to be the same as that between the second signal lead 16 and the first pad 131. This ensures that the resistance of the first signal lead 12 and the second signal lead 16 is the same during the connection process, avoiding the possibility that the resistance in one of the connection circuits is too large and will affect the electrical connection process, thus improving the stability of the bonding process.

[0151] In one embodiment, reference Figure 7 and Figure 8 As shown, the second signal lead 16 and the first signal lead 12 are arranged alternately.

[0152] This ensures uniform electrical signal transmission between the first signal lead 12 and the second signal lead 16, preventing confusion in the electrical signals and thus guaranteeing the normal progress of the bonding process.

[0153] In one embodiment, reference Figure 7 As shown, along the thickness direction of the substrate 11, the orthogonal projection of the first pad 131 on the substrate 11 covers a portion of the orthogonal projection of the first signal lead 12 on the substrate 11; and / or the orthogonal projection of the first pad 131 on the substrate 11 covers a portion of the orthogonal projection of the second signal lead 16 on the substrate 11.

[0154] In this way, the first pad 131 and the first signal lead 12 can be avoided from being concentrated in one place, thereby reducing the stress concentration at the connection between the first pad 131 and the first signal lead 12, which can reduce the probability of cracks appearing in the first pad 131, improve the problem of poor bonding of the first pad 131, and improve the yield of the display panel 10.

[0155] Similarly, this can prevent the first pad 131 and the second signal lead 16 from concentrating in one place, thereby reducing stress concentration at the connection between the first pad 131 and the second signal lead 16, reducing the probability of cracks appearing in the first pad 131, improving the problem of poor bonding of the first pad 131, and increasing the yield of the display panel 10.

[0156] In one embodiment, the display panel 10 further includes a first electrode layer 17, a light-emitting layer group 18, and a second electrode layer 19. The first electrode layer 17, the light-emitting layer group 18, and the second electrode layer 19 are stacked on one side of the substrate 11 and located in the display area 101.

[0157] It should be noted that the first electrode layer 17 and the second electrode layer 19 have opposite electrical properties, with the first electrode layer 17 being the anode.

[0158] In this way, the first electrode layer 17 and the second electrode layer 19 can be connected to the light-emitting layer group 18 respectively, thereby realizing the display function of the light-emitting layer group 18 and thus realizing the normal display of the display panel 10.

[0159] In one embodiment, the display panel 10 further includes a pixel definition layer. The pixel definition layer is disposed on the same layer as the first insulating layer 14; the pixel definition layer encloses to form a pixel opening, and at least a portion of the light-emitting layer group 18 is located within the pixel opening.

[0160] Thus, the pixel definition layer is an important component of the display panel 10, used to define and limit pixels, ensuring that each light-emitting functional structure can function properly. It enables precise alignment and positioning of the light-emitting functional structures, ensures isolation between adjacent light-emitting functional structures, and prevents crosstalk. At the same time, the pixel definition layer can increase the aperture ratio and improve the display effect.

[0161] In one embodiment, reference Figure 9 As shown, the display panel 10 also includes an isolation structure 20. The isolation structure 20 is disposed on the substrate 11 and defines a plurality of isolation openings; the light-emitting layer group 18 includes a plurality of light-emitting parts, which are correspondingly disposed within the plurality of isolation openings.

[0162] Among them, patents 202311317611.4, 202310855006.6, 202310854718.6 and 202311134638.X describe the relevant technical solutions of the isolation structure 200. Their contents are incorporated herein by reference and will not be repeated in this embodiment.

[0163] It should be noted that, Figure 9 The first electrode layer 17, the light-emitting layer group 18, and the second electrode layer 19 are only schematically marked in the figure. Figure 9 The markings on the first electrode layer 17, the light-emitting layer group 18, and the second electrode layer 19 do not only represent the structure between the two isolation structures 20; in fact, Figure 9 The first electrode layer 17, the light-emitting layer group 18, and the second electrode layer 19 represent the corresponding functional layers at that location.

[0164] In this way, the isolation structure 20 can form an undercut structure that is "larger at the top and smaller at the bottom". When the sub-pixel is deposited, the undercut structure can isolate the light-emitting layer group 18 structure of the sub-pixel, so that multiple light-emitting parts are correspondingly set in multiple isolation openings, thereby improving the display effect of the display panel 10.

[0165] In one embodiment, the isolation structure 20 includes an isolator 21 and a blocking portion 22 stacked along a direction away from the substrate 11. The outer contour of the orthographic projection of the blocking portion 22 on the substrate 11 is located outside the outer contour of the orthographic projection of the isolator 21 on the substrate 11. In this way, the isolation structure 20 can form an undercut structure that is larger at the top and smaller at the bottom. When the sub-pixel is deposited, this undercut structure can isolate the light-emitting layer group 18 of the sub-pixel.

[0166] In one embodiment, the isolator 21 includes a conductive material, and the second electrode layer 19 is electrically connected to the isolator 21. This facilitates the electrical connection of the second electrode layer 19 to the isolator 21 of the isolation structure 20, thereby connecting the second electrode layer 19 of the sub-pixel to the pixel circuit through the isolator 21, and optimizing the wiring layout of the display area 101.

[0167] In one embodiment, the insulator 21 includes at least one metal layer. In one example, the insulator 21 includes one metal layer. Further, the material of the insulator 21 includes at least one of a metal and a metal oxide. Exemplarily, the metal may be silver, copper, titanium, aluminum, etc. The metal oxide may be tin oxide, zinc oxide, cadmium oxide, indium oxide, indium tin oxide, zinc indium oxide, zinc gallium oxide, zinc aluminum oxide, titanium tantalum oxide, etc.

[0168] In one embodiment, the isolator 21 includes a fourth metal layer and a fifth metal layer stacked in a direction away from the substrate 11, wherein the orthographic projection of the fourth metal layer onto the substrate 11 is located outside the orthographic projection of the fifth metal layer onto the substrate 11. Here, the fourth metal layer and the fifth metal layer are stacked sequentially in a direction away from the substrate 11. In one example, the fourth metal layer may be made of molybdenum, and the fifth metal layer may be made of aluminum.

[0169] In one embodiment, the blocking portion 22 is made of metal. For example, the blocking portion 22 is made of titanium. In this way, by setting three stacked metal layers, the resistance of the isolation structure 20 can be reduced, thereby reducing the power consumption of the display panel 10.

[0170] In one example, the cross-sectional shape of the isolation structure 20, which is composed of the fourth metal layer, the fifth metal layer, and the barrier 22, can be I-shaped.

[0171] In one embodiment, the display panel 10 includes a substrate 11, a first signal lead 12, a bonding pad 13, and a first insulating layer 14. The first signal lead 12 is disposed on one side of the substrate 11; the bonding pad 13 is disposed on the side of the first signal lead 12 away from the substrate 11; the bonding pad 13 includes a first sidewall 1311, which intersects the thickness direction of the substrate 11; the first insulating layer 14 is disposed on the side of the bonding pad 13 away from the substrate 11; the first insulating layer 14 includes an opening and an insulating sidewall 141, the opening exposing a portion of the bonding pad 13, and the insulating sidewall 141 enclosing the opening. Along the thickness direction of the substrate 11, the outline of the orthographic projection of the first sidewall 1311 onto the substrate 11 is outside the outer outline of the orthographic projection of the opening onto the substrate 11, and the outline of the orthographic projection of the first sidewall 1311 onto the substrate 11 does not overlap with the outline of the orthographic projection of the insulating sidewall 141 onto the substrate 11.

[0172] In this way, the insulating sidewalls 141 of the first insulating layer 14 will not be stacked at the orthographic projection position of the first sidewall 1311 along the thickness direction of the substrate 11, and there will be no large height difference at the position of the insulating sidewalls 141. Therefore, in the subsequent cathode fabrication process, it can be ensured that the cathode also does not have a large height difference at the position corresponding to the insulating sidewalls 141, thus ensuring the continuity of the cathode. In the subsequent etching process, the bonding pads 13 can be protected from etching by the continuous and complete cathode, thereby avoiding voids in the bonding pads 13, ensuring the integrity of the bonding pad structure, and thus improving the reliability of the bonding process.

[0173] Secondly, referring to Figure 10 As shown, this application embodiment provides a display device 100, including a display panel 10 as described in the first aspect and a bonding chip, wherein the bonding chip and the bonding pads of the display panel 10 are electrically connected.

[0174] The display device 100 provided in this application embodiment can, along the thickness direction of the substrate 11, ensure that at least a portion of the outer contour of the orthographic projection of the second pad 132 on the substrate 11 lies within the outer contour of the orthographic projection of the first pad 131 on the substrate 11, thereby preventing the edge tip of the second pad 132 from affecting the structure of the first pad 131. This avoids discontinuities in the subsequently fabricated cathode, and during subsequent etching, prevents the formation of voids between the first pad 131 and the second pad 132 through the cathode, thus improving the reliability of the bonding process.

[0175] It is understood that the display device 100 in the embodiments of this application may be a laptop computer, mobile phone, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, TV monitor, flat panel display, computer monitor, car display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, display of camera view (e.g., display of rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, etc.

[0176] Thirdly, see Figure 11 As shown, this application provides a method for manufacturing a display panel 10, which can manufacture the display panel 10 in the first aspect. The manufacturing method includes:

[0177] S100: Provides a substrate 11 having a display area 101 and a bonding area 102 located on one side of the display area 101;

[0178] S200: A first signal lead 12, a first pad 131, a second pad 132, and a first insulating layer 14 are sequentially stacked on one side of a substrate 11. The first signal lead 12, the first pad 131, the second pad 132, and the first insulating layer 14 are all located in the bonding region 102. The first insulating layer 14 includes an opening that exposes a portion of the second pad 132. Along the thickness direction of the substrate 11, the orthographic projection of the opening on the substrate 11 is located within the outer contour of the orthographic projection of the second pad 132 on the substrate 11. At least a portion of the outer contour of the orthographic projection of the second pad 132 on the substrate 11 is located within the outer contour of the orthographic projection of the first pad 131 on the substrate 11.

[0179] S300: A second electrode layer 19 is formed on the side of the first insulating layer 14 away from the second pad 132. The second electrode layer 19 includes a first portion and a second portion. The first portion is at least partially located in the display area 101, and the second portion extends from the surface of the first insulating layer 14 to the exposed surface of the second pad 132.

[0180] S400: Remove the second portion of the second electrode layer 19.

[0181] It should be noted that the second electrode layer 19 in this application exists only in the bonding area 102 during the fabrication of the display panel 10. In the subsequent etching process, the cathode prevents the formation of voids in the first pad 131 and the second pad 132, thereby improving the reliability of the bonding process. After the display panel 10 is fabricated, the second electrode layer 19 does not exist in the bonding area 102. The second electrode layer 19 exists only in the display area 101 of the display panel 10, thereby working together with the light-emitting layer group 18 and the first electrode 17 to perform the display.

[0182] The method for fabricating the display panel 10 provided in this application embodiment can, along the thickness direction of the substrate 11, ensure that at least a portion of the outer contour of the orthographic projection of the second pad 132 on the substrate 11 lies within the outer contour of the orthographic projection of the first pad 131 on the substrate 11, thereby preventing the edge tip of the second pad 132 from affecting the structure of the first pad 131. This avoids discontinuities in the subsequently fabricated cathode, and during subsequent etching, prevents the formation of voids between the first pad 131 and the second pad 132 through the cathode, thus improving the reliability of the bonding process.

[0183] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0184] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0185] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel having a display area and a bonding area located on one side of the display area, characterized in that, The display panel includes: Substrate; A first signal lead is disposed on one side of the substrate and located in the bonding area; A bonding pad is provided on the side of the first signal lead away from the substrate; the bonding pad includes a first pad and a second pad stacked in a direction away from the substrate; the first pad is used to connect the second pad and the first signal lead; Wherein, along the thickness direction of the substrate, at least a portion of the outer contour of the orthographic projection of the second pad on the substrate is located within the outer contour of the orthographic projection of the first pad on the substrate.

2. The display panel according to claim 1, characterized in that, Along the thickness direction of the substrate, the outer contour of the entire orthographic projection of the second pad on the substrate lies within the outer contour of the orthographic projection of the first pad on the substrate.

3. The display panel according to claim 1, characterized in that, The display panel also includes: A first insulating layer is disposed on the side of the bonding pad away from the substrate; the first insulating layer includes an opening that exposes a portion of the second pad along the thickness direction of the substrate, the orthographic projection of the opening on the substrate being located within the outer contour of the orthographic projection of the second pad on the substrate.

4. The display panel according to claim 3, characterized in that, The first insulating layer includes insulating sidewalls that enclose the opening; the first pad includes a first sidewall away from the opening, the first sidewall intersecting the thickness direction of the substrate, and along the thickness direction of the substrate, the outline of the orthographic projection of the first sidewall on the substrate is located outside the outer outline of the orthographic projection of the second pad on the substrate, and the outline of the orthographic projection of the first sidewall on the substrate does not overlap with the outline of the orthographic projection of the insulating sidewall on the substrate; Optionally, the outline of the orthographic projection of the first sidewall onto the substrate is located outside the outline of the orthographic projection of the insulating sidewall onto the substrate.

5. The display panel according to claim 4, characterized in that, The second pad includes a second sidewall away from the opening, the second sidewall intersecting the thickness direction of the substrate. Along the thickness direction of the substrate, the outline of the orthographic projection of the second sidewall on the substrate is outside the outline of the orthographic projection of the opening on the substrate, and the outline of the orthographic projection of the second sidewall on the substrate does not overlap with the outline of the orthographic projection of the insulating sidewall on the substrate. Optionally, the outlines of the orthographic projections of the first sidewall onto the substrate and the outlines of the orthographic projections of the second sidewall onto the substrate do not overlap.

6. The display panel according to claim 5, characterized in that, The first pad has a first recess, and the second pad has a second recess. Along the thickness direction of the substrate, the outline of the orthographic projection of the second recess on the substrate is located within the outline of the orthographic projection of the opening on the substrate, and the outline of the orthographic projection of the second recess on the substrate is located within the outline of the orthographic projection of the first recess on the substrate. Optionally, along the thickness direction of the substrate, the outline of the orthographic projection of the first recess on the substrate lies within the outline of the orthographic projection of the opening on the substrate.

7. The display panel according to claim 6, characterized in that, The display panel also includes: An insulating structure is disposed between the first signal lead and the first pad. The insulating structure includes a first via, and the first recess is disposed in the first via and connected to the first signal lead. Optionally, along the thickness direction of the substrate, the orthographic projection of the first via on the substrate lies within the outline of the orthographic projection of the first signal lead on the substrate; Optionally, the insulating structure includes a second insulating layer and a third insulating layer; The second insulating layer is disposed between the first signal lead and the first pad. The second insulating layer includes a first sub-hole, and the first recess is disposed in the first sub-hole and connected to the first signal lead. The third insulating layer is disposed between the second insulating layer and the first pad, and the third insulating layer includes a second sub-hole. The first recess is disposed in the second sub-hole and connected to the first signal lead. Wherein, the first sub-hole and the second sub-hole form the first via; the first recess is electrically connected to the first signal lead, and the first recess is insulated from the hole wall of the first sub-hole and the hole wall of the second sub-hole; Optionally, along the thickness direction of the substrate, the orthographic projection of the first sub-hole on the substrate is located within the outline of the orthographic projection of the first signal lead on the substrate, and a portion of the outline of the orthographic projection of the second insulating layer on the substrate is located within the outline of the orthographic projection of the first signal lead on the substrate. Optionally, along the thickness direction of the substrate, the orthographic projection of the second sub-hole on the substrate lies within the outline of the orthographic projection of the first signal lead on the substrate, the outline of the orthographic projection of the third insulating layer on the substrate lies within the outline of the orthographic projection of the second insulating layer on the substrate, and a portion of the outline of the orthographic projection of the third insulating layer on the substrate lies within the outline of the orthographic projection of the first signal lead on the substrate.

8. The display panel according to claim 7, characterized in that, The first pad further includes a first flat portion and a first connecting portion that are interconnected; the first flat portion is connected to the first signal lead, and the first connecting portion and the first flat portion surround to form the first recess; the first connecting portion is disposed on the sidewall of the first via. Optionally, the second pad further includes a second flat portion and a second connecting portion that are interconnected; the second flat portion is connected to the first flat portion, and the second connecting portion and the second flat portion surround to form the second recess; the second connecting portion is disposed on the sidewall of the first recess; Optionally, the first pad further includes a third flat portion, which is connected to the side of the first connection portion away from the first flat portion. Along the thickness direction of the substrate, the outline of the orthographic projection of the third flat portion on the substrate is located outside the outline of the orthographic projection of the first sub-hole on the substrate. Optionally, the first pad further includes a third connecting portion and a fourth flat portion, the first sidewall is located on the side surface of the third connecting portion, the first sidewall is connected to the third flat portion and the fourth flat portion, and along the thickness direction of the substrate, the outline of the orthographic projection of the fourth flat portion on the substrate is outside the outline of the orthographic projection of the first sub-hole on the substrate; Optionally, the second pad further includes a fifth flat portion connected to the side of the second connection portion away from the second flat portion, the second sidewall being located on the side surface of the fifth flat portion, and along the thickness direction of the substrate, the outline of the orthographic projection of the fifth flat portion on the substrate is located outside the outline of the orthographic projection of the second sub-hole on the substrate.

9. The display panel according to any one of claims 1-8, characterized in that, The first pad includes at least two metal layers, and the second pad includes at least two metal layers; Optionally, the first pad includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially. Optionally, the first metal layer is made of titanium, the second metal layer is made of aluminum, and the third metal layer is made of titanium. Optionally, the first pad and the second pad are made of the same material.

10. The display panel according to any one of claims 1-8, characterized in that, The display area includes a gate, a capacitor, data signal lines, and power signal lines; The display panel further includes a second signal lead, which is disposed on the side of the substrate facing the first pad, connected to the first pad, and located in the bonding area; The first signal lead is disposed on the same layer as the gate, the first pad is disposed on the same layer as the data signal line, and the second pad is disposed on the same layer as the power signal line; a portion of the second signal lead is disposed on the same layer as the gate, and the remaining portion of the second signal lead is disposed on the same layer as the capacitor; Optionally, both the first signal lead and the second signal lead are multiple; Optionally, the number of the first signal lead and the number of the second signal lead are the same; Optionally, the second signal lead and the first signal lead are arranged alternately.

11. The display panel according to claim 10, characterized in that, Along the thickness direction of the substrate, the orthographic projection of the first pad on the substrate covers a portion of the orthographic projection of the first signal lead on the substrate; And / or the orthogonal projection of the first pad on the substrate covers a portion of the orthogonal projection of the second signal lead on the substrate.

12. The display panel according to any one of claims 3-8, characterized in that, The display panel further includes a first electrode layer, a light-emitting layer group, and a second electrode layer; The first electrode layer, the light-emitting layer group layer, and the second electrode layer are stacked on one side of the substrate and located in the display area.

13. The display panel according to claim 12, characterized in that, The display panel also includes: A pixel definition layer is disposed on the same layer as the first insulating layer; the pixel definition layer encloses to form a pixel opening, and at least a portion of the light-emitting layer group is located within the pixel opening.

14. The display panel according to claim 12, characterized in that, The display panel further includes an isolation structure disposed on the substrate, the isolation structure defining a plurality of isolation openings; The light-emitting layer group includes multiple light-emitting parts, and the multiple light-emitting parts are correspondingly disposed within the multiple isolation openings; Optionally, the isolation structure includes an isolation body and a blocking portion stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the blocking portion on the substrate is located outside the outer contour of the orthographic projection of the isolation body on the substrate; Optionally, the insulator includes a conductive material, and the first electrode layer is electrically connected to the insulator; Optionally, the insulator includes at least one metal layer; Optionally, the isolator includes a fourth metal layer and a fifth metal layer stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the fourth metal layer on the substrate is located outside the outer contour of the orthographic projection of the fifth metal layer on the substrate.

15. A display panel, characterized in that, The display panel includes: Substrate; A first signal lead is disposed on one side of the substrate; A bonding pad is provided on the side of the first signal lead away from the substrate; the bonding pad includes a first sidewall that intersects the thickness direction of the substrate; A first insulating layer is disposed on the side of the bonding pad away from the substrate; the first insulating layer includes an opening and an insulating sidewall, the opening exposing a portion of the bonding pad, and the insulating sidewall enclosing the opening; Wherein, along the thickness direction of the substrate, the outline of the orthographic projection of the first sidewall on the substrate is located outside the outer outline of the orthographic projection of the opening on the substrate, and the outline of the orthographic projection of the first sidewall on the substrate does not overlap with the outline of the orthographic projection of the insulating sidewall on the substrate.

16. A display device, characterized in that, The device includes a display panel and a bonding chip as described in any one of claims 1-15, wherein the bonding chip and the bonding pads of the display panel are electrically connected.

17. A method for manufacturing a display panel, characterized in that, The preparation method includes: A substrate is provided, having a display area and a bonding area located on one side of the display area; A first signal lead, a first pad, a second pad, and a first insulating layer are sequentially stacked on one side of the substrate, wherein the first signal lead, the first pad, the second pad, and the first insulating layer are all located in the bonding region; the first insulating layer includes an opening that exposes a portion of the second pad, and along the thickness direction of the substrate, the orthographic projection of the opening on the substrate is located within the outer contour of the orthographic projection of the second pad on the substrate, and the outer contour of at least a portion of the orthographic projection of the second pad on the substrate is located within the outer contour of the orthographic projection of the first pad on the substrate; A second electrode layer is formed on the side of the first insulating layer away from the second pad. The second electrode layer includes a first portion and a second portion. The first portion is at least partially located in the display area, and the second portion extends from the surface of the first insulating layer to the surface of the exposed second pad. Remove the second portion of the second electrode layer.

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