Display device

Abstract

A display device according to an embodiment of the present specification may include: a substrate having a notch and including a display area including a plurality of sub-pixels and a non-display area around the display area; a plurality of transistors disposed on the substrate and including a gate electrode, a source electrode, and a drain electrode; a display panel including a light emitting portion disposed on the plurality of transistors and including an anode electrode, a cathode electrode, and a light emitting layer between the anode electrode and the cathode electrode; and a microlens disposed on the light emitting area of the sub-pixel, in which a pad portion and a link portion may be disposed in the non-display area, and a plurality of data lines may be alternately disposed in the link portion, in which some of the data lines are formed on different layers between which an insulating layer is disposed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0113417, filed on August 23, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This manual relates to display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices are being used, such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices.

[0005] In display devices, the advantages of self-emissive OLED displays include: wider viewing angles and higher contrast ratios; and because they do not require a separate backlight, they are lighter, thinner, and consume less power than LCDs. Additionally, OLED displays can be driven at low voltages, have fast response times, and, most importantly, are inexpensive to manufacture.

[0006] OLED displays can also be used in vehicles. In vehicle-mounted displays, those in front of the driver's seat and front passenger seat need to limit the driver's field of vision based on driving conditions. The display also needs to limit the field of vision based on user privacy and information protection requirements. Summary of the Invention

[0007] This manual aims to provide display devices with aesthetically improved designs.

[0008] This specification also aims to provide a display device in which puncture and scratch defects of the display panel can be suppressed or prevented.

[0009] This specification also aims to provide a display device in which puncture and scratch defects of the display panel can be suppressed or prevented due to deposition mask.

[0010] This specification is also intended to provide a display device with improved reliability by suppressing or preventing defects in the display panel.

[0011] The purpose of this specification is not limited to the purposes described above, and other technical purposes can be inferred from the following embodiments.

[0012] According to embodiments of this specification, a display device is provided, comprising: a substrate having a notch and including a display area containing a plurality of pixels and a non-display area surrounding the display area; a plurality of transistors disposed on the substrate and including a gate electrode, a source electrode, and a drain electrode; a display panel including a light-emitting portion disposed on the plurality of transistors and including an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode; and a microlens disposed on the light-emitting area of ​​a sub-pixel, wherein pad portions and link portions are disposed in the non-display area, and a plurality of data lines are alternately disposed in the link portions, some of which are formed on different layers, and an insulating layer is disposed between the different layers.

[0013] In addition to the technical objectives described above, other features and advantages of this specification are described below, or will be clearly understood by those skilled in the art based on such technology and description.

[0014] According to the embodiments described in this specification, a display device with improved aesthetics can be provided.

[0015] According to the embodiments described in this specification, puncture and scratch defects of the display panel can be suppressed or prevented.

[0016] According to the embodiments described in this specification, puncture and scratch defects in the display panel caused by the deposition mask can be suppressed or prevented.

[0017] According to the embodiments described in this specification, reliability can be improved by suppressing or preventing defects in the display panel.

[0018] According to the embodiments described in this specification, defects such as punctures or scratches can be suppressed or prevented during the manufacturing process of the display panel, thereby preventing defects in the display device, increasing its lifespan, and reducing production energy.

[0019] However, the effects that can be obtained from this specification are not limited to those described above, and other effects not mentioned will be clearly understood by those skilled in the art to which this specification pertains based on the following description. Attached Figure Description

[0020] Figure 1 This is a plan view of a display device according to one embodiment.

[0021] Figure 2 yes Figure 1 A magnified view of region Q1 in the image.

[0022] Figure 3 Is only shown Figure 2 The view of the display panel.

[0023] Figure 4 This is a plan view showing the pixel arrangement of a display panel according to one embodiment.

[0024] Figure 5 It is along Figure 4 A cross-sectional view of line V-V' in the diagram.

[0025] Figure 6 It was captured from different angles. Figure 5 A cross-sectional view of the touch portion.

[0026] Figure 7 It is along Figure 1 A cross-sectional view of line A-A' in the diagram.

[0027] Figure 8 It is along Figure 3 A cross-sectional view of line B-B' in the diagram.

[0028] Figure 9 It is along Figure 3 A cross-sectional view of line C-C' in the diagram.

[0029] Figure 10 It is along Figure 3 A cross-sectional view of line D-D' in the diagram.

[0030] Figure 11 This is a plan view of the recessed non-display area of ​​the second non-display area.

[0031] Figure 12 It is along Figure 11 A cross-sectional view of line E-E' in the diagram.

[0032] Figure 13 This is a plan view of a display device according to another embodiment. Detailed Implementation

[0033] In the following description, embodiments will be described with reference to the accompanying drawings. In the specification, when a first component (or region, layer, portion, etc.) is described as being "on", "attached", "connected" or "coupled" to a second component, it means that the first component can be directly attached / connected / coupled to the second component, or that a third component can be disposed between the first component and the second component.

[0034] The same reference numerals indicate the same parts. Additionally, in the drawings, the thickness, scale, and dimensions of parts are exaggerated for effective description of the technical content. The term "and / or" includes all one or more combinations that can be defined by associated configurations.

[0035] Terms such as "first" and "second" may be used to describe various components, but components are not limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the implementation, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular includes the plural.

[0036] Terms such as "below," "under," "above," and "on top" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described relative to the directions indicated by the markings in the drawings.

[0037] It should be understood that terms such as “comprising” or “having” are intended to specify the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0038] Figure 1 This is a plan view of a display device according to one embodiment. Figure 2 yes Figure 1 A magnified view of region Q1 in the image. Figure 3 Is only shown Figure 2 The view of the display panel.

[0039] Figure 3 From Figure 2 The view of the flexible film COF, motherboard MB, and driver IC DIC, excluding the display panel 100, is omitted. Figure 3 In this document, the ratios between components have been adjusted for ease of description.

[0040] Reference Figures 1 to 3 The display device 1 may be a device that includes both a display function for displaying video and a touch sensing function for sensing user touch, but is not limited thereto. For example, the display device 1 may include only one of the display function for displaying video and the touch sensing function for sensing user touch.

[0041] Display device 1 may be an electroluminescent display device including a touch sensor or a micro light-emitting diode display device. The electroluminescent display device including a touch sensor may be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0042] The display device 1 according to this embodiment may be a vehicle display device, but is not limited thereto. For example, as long as the display device includes a display function, the description of the display device 1 may be applied without being limited to the type of device.

[0043] When the display device 1 according to this embodiment is a vehicle display device, the display device 1 may include functions such as operating at least some of the various functions of the vehicle and displaying various information about the vehicle.

[0044] When the display device 1 according to this embodiment is a vehicle display device, the display device 1 can be installed on the vehicle's dashboard. The display device 1 can be installed across the driver's seat and the front passenger seat located in the front row of the vehicle, but is not limited thereto. Both the driver in the driver's seat and the passenger in the front passenger seat can use the display device 1.

[0045] The display device 1 may include a display panel 100. The display panel 100 may include a display area DA and a non-display area NDA.

[0046] The display area DA can be an area that emits light outward to display on a screen. The display area DA can also include the function of sensing user touch. In this case, the display area DA can correspond to the touch sensing area, but is not limited to this.

[0047] The display area DA may correspond to the shape of the display panel 100, but is not limited to it.

[0048] Multiple sub-pixels (SPs) can be set in the display area DA. Multiple sub-pixels (SPs) can be repeatedly set on the first direction DR1 and the second direction DR2.

[0049] The non-display area NDA can be an area that does not emit light to the outside so as not to display a screen. The non-display area NDA can be located around the display area DA. The non-display area NDA can surround the display area DA, but the embodiments described in this specification are not limited thereto. The border area of ​​the display device 1 can be defined by the non-display area NDA, but the embodiments described in this specification are not limited thereto.

[0050] The display panel 100 may be a rigid display panel, but is not limited thereto. The display panel 100 may be a flexible display panel whose shape can be deformed, such as a foldable, bendable, rollable, or stretchable display panel.

[0051] The display panel 100 may include a first long side LE1, a second long side LE2, a first short side SE1, and a second short side SE2 forming the edges of the display panel 100.

[0052] The first long side LE1 and the second long side LE2 may extend in the first direction DR1, and the first short side SE1 and the second short side SE2 may extend in the direction between the first direction DR1 and the second direction DR2. The first long side LE1 and the second long side LE2 may have two ends connected by the first short side SE1 and the second short side SE2.

[0053] The first long side LE1 can be located on one side of the second long side LE2 in the second direction DR2. The first long side LE1 and the second long side LE2 can extend parallel to each other, but are not limited thereto.

[0054] The length of the first long side LE1 can be shorter than the length of the second long side LE2. For example, since the length of the second long side LE2 is longer than the length of the first long side LE1, the first short side SE1 and the second short side SE2 that connect the two ends of the first long side LE1 to the two ends of the second long side LE2 can extend in a direction that intersects each other, but are not limited thereto.

[0055] The first direction DR1 and the second direction DR2 may be intersecting directions. The first direction DR1 and the second direction DR2 may be orthogonal, but are not limited thereto. The first direction DR1 and the second direction DR2 are provided to clarify the description of this disclosure. The first direction DR1 and the second direction DR2 are relative, and the embodiments of this specification are not limited thereto.

[0056] In the plan view, the first long side LE1 can be set above the display area DA, and the second long side LE2 can be set below the display area DA.

[0057] In the plan view, the first short side SE1 can be set to the right of the display area DA, and the second short side SE2 can be set to the left of the display area DA.

[0058] The display panel 100 may include a curved notch NCP. The notch NCP may be formed at the second long side LE2, but is not limited thereto. For example, the second long side LE2 may extend entirely in the first direction DR1, but may include a notch NCP that curves toward the first long side LE1.

[0059] Because of the recessed NCP, components such as the driver's seat handle can be installed on the corresponding part to maximize the display area DA of the screen, thereby improving user convenience and enhancing aesthetics.

[0060] The non-display area NDA may include a first non-display area NDA1 set along a first long side LE1, a first short side SE1, and a second short side SE2, and a second non-display area NDA2 set along a second long side LE2. The second non-display area NDA2 may be set along the second long side LE2, which includes a curved notch NCP.

[0061] The first non-display area NDA1 can be disposed on one side and the other side of the display area DA in the first direction DR1, and on one side of the display area DA in the second direction DR2.

[0062] The second non-display area NDA2 may include a notched non-display area N_NDA disposed around the notch NCP and an extended non-display area E_NDA disposed around the notched non-display area N_NDA.

[0063] The extended non-display area E_NDA can extend from the notched non-display area N_NDA in the first direction DR1. The extended non-display area E_NDA can be located between the notched non-display area N_NDA and the first non-display area NDA1. The extended non-display area E_NDA can connect the notched non-display area N_NDA to the first non-display area NDA1.

[0064] The display device 1 may also include a pad area ("pad portion" implementation) PA, a link area LA, a gate drive unit GIP, a motherboard MB, a flexible film COF, a driver IC DIC, a gate line GL, a gate control line GCL, a data line DL, a low-potential voltage line VSSL, and a high-potential voltage line VDDL.

[0065] The pad area PA can overlap with the flexible film COF. The pad area PA can be attached to the flexible film COF. For example, the display panel 100 and the flexible film COF can be attached through the pad area PA.

[0066] The pad area PA can be set in the non-display area NDA. The pad area PA can be set in the second non-display area NDA2. The pad area PA can be set in each of the notch non-display area N_NDA and the extended non-display area E_NDA.

[0067] The pad area PA can include multiple pads. The pad area PA can include a low-potential voltage pad VSSP, a high-potential voltage pad VDDP, a gate control pad GCP, a first data pad DP1, and a second data pad DP2. The low-potential voltage pad VSSP, the high-potential voltage pad VDDP, the gate control pad GCP, the first data pad DP1, and the second data pad DP2 can be set in the pad area PA.

[0068] Figure 3The diagram shows a low-potential voltage pad VSSP, a high-potential voltage pad VDDP, a first data pad DP1, and a second data pad DP2 arranged sequentially; however, the embodiments described herein are not limited to this arrangement. For example, the first data pad DP1 and the second data pad DP2 may be positioned between the low-potential voltage pad VSSP and the high-potential voltage pad VDDP. Additionally, the gate control pad GCP is shown positioned between the high-potential voltage pad VDDP and the data pad DP, but this is not a limitation. Furthermore, the arrangement of the low-potential voltage pad VSSP, the high-potential voltage pad VDDP, the gate control pad GCP, the first data pad DP1, and the second data pad DP2 within the pad region PA can vary according to the design. The pad region PA is located at both ends of a flexible film COF positioned along the non-display area NDA and overlaps with the flexible film COF.

[0069] Multiple pads VSSP, VDDP, DP and GCP located in the pad area PA can be connected to the high-potential voltage line VDDL, low-potential voltage line VSSL, data line DL and gate control line GCL in the link area LA.

[0070] The gate driving unit GIP can be disposed in the non-display area NDA. The gate driving unit GIP can be disposed on at least one side and the other side of the display area DA in the first direction DR1, but is not limited thereto. In a plan view, the gate driving unit GIP can be disposed on the left side and the other side of the display area DA.

[0071] The gate drive unit (GIP) may include multiple transistors G120 (see...) Figure 7 Transistor G120 is located in the gate drive unit GIP (see...). Figure 7 The gate drive unit (GIP) can be connected to the sub-pixel (SP) (or pixel) via the gate line GL. The gate drive unit (GIP) can apply a gate signal to each sub-pixel (SP) (or each pixel) via the gate line GL.

[0072] The gate drive unit (GIP) can receive gate control signals from the driver IC (DIC) via the gate control line (GCL). The GIP can then generate scan signals and light emission signals (or light emission control signals) based on the gate control signals.

[0073] The gate driving unit (GIP) may include a scan driver and a light emission signal driver. The scan driver may generate scan signals in a row-sequential manner and supply the scan signals to scan lines to drive one or more scan lines connected to each sub-pixel (SP) (or each pixel) row. The light emission signal driver may generate light emission signals in a row-sequential manner and supply the light emission signals to light emission signal lines to drive one or more light emission signal lines connected to each sub-pixel (SP) (or each pixel) row.

[0074] The motherboard MB can be connected to the display panel 100 via a flexible film COF. The motherboard MB can also be electrically connected to the sub-pixels SP (or pixels) of the display area DA via the flexible film COF. The motherboard MB and the flexible film COF can be electrically connected via multiple pads VSSP, VDDP, and DP.

[0075] The motherboard (MB) can have various types of components for supplying various signals, such as gate control signals, drive signals, and data signals, to the driver IC (DIC). The motherboard (MB) can be a printed circuit board, but is not limited to this.

[0076] The motherboard MB can be connected to the display panel 100 via a flexible film COF in the second non-display area NDA2. The motherboard MB can be configured as multiple motherboards along the second non-display area NDA2, but is not limited to this. The number of motherboard MBs can vary depending on the design.

[0077] At least one of the motherboards MB can be positioned around the notch NCP and connected to the display panel 100 via a flexible film COF in the notch non-display area N_NDA.

[0078] The flexible film COF can be connected to the display panel 100 and the motherboard MB. The flexible film COF can be attached to and electrically connected to each of the display panel 100 and the motherboard MB. For example, the display panel 100 and the motherboard MB can be electrically connected via the flexible film COF. Multiple flexible films can be configured, but are not limited to this.

[0079] The flexible film COF can be attached to the display panel 100 in the second non-display area NDA2. The flexible film COF can be repeatedly disposed along the second non-display area NDA2. The flexible film COF can be attached to the display panel 100 across the notched non-display area N_NDA and the extended non-display area E_NDA.

[0080] A single motherboard MB can be electrically connected to the display panel 100 via at least one flexible film COF. For example, among a plurality of motherboard MBs disposed along the second non-display area NDA2, the motherboard MBs located at both ends can be electrically connected to the display panel 100 via one flexible film COF, and the remaining motherboard MBs can be electrically connected to the display panel 100 via two flexible film COFs.

[0081] The flexible film COF can be electrically connected to the pad area PA. Therefore, the flexible film COF can supply gate control signals, drive signals, power supply voltage, data voltage, etc. to multiple sub-pixels SP (or pixels) and gate drive units GIP located in the display area DA.

[0082] The flexible COF (Coated Film of Form) can be a flexible insulating film comprising multiple conductive lines. The flexible COF can include, for example, polycarbonate, polyethylene terephthalate, polyimide, polyamide, polyester, polyacrylate, polymethyl methacrylate, etc., but is not limited to these.

[0083] The driver IC DIC can be mounted on a flexible film COF. Depending on the mounting method, the driver IC DIC can be mounted using methods such as chip-on-glass, chip-on-film, or tape-and-carrier packaging. In this disclosure, the driver IC DIC is described as being mounted on a flexible film COF using a chip-on-film method, but it is not limited to this.

[0084] The driver IC (DIC) can drive the display device 1. The driver IC (DIC) can process data signals used for displaying images, various drive signals used for processing data signals, etc. The driver IC (DIC) may include gate driver ICs, data driver ICs, etc.

[0085] Although not shown, the display device 1 may also include a low-dropout (LDO) regulator and a level shifter. The LDO regulator and level shifter may be located on the motherboard MB, but are not limited thereto.

[0086] The driver IC DIC can be electrically connected to the LDO regulator and level shifter, and can transmit the signals generated by the LDO regulator and level shifter to the gate drive unit GIP.

[0087] Gate lines GL can extend from the gate drive unit GIP and can be connected to sub-pixels SP (or pixels). Gate lines GL can electrically connect the gate drive unit GIP to the sub-pixels SP (or pixels). Gate lines GL can apply gate signals from the gate drive unit GIP to each sub-pixel SP (or pixel).

[0088] The gate control line GCL can be located in the non-display area NDA. The gate control line GCL can be located in the second non-display area NDA2, but is not limited thereto. The gate control line GCL can be located in the extending direction of the second non-display area NDA2.

[0089] The gate control line (GCL) can extend from the pad area (PA) to the gate drive unit (GIP) and can be electrically connected to the gate drive unit (GIP). Multiple gate control lines (GCLs) can be configured, and multiple gate control lines (GCLs) can supply at least two different signals.

[0090] The gate control line (GCL) applies gate control signals to the gate driver unit (GIP). These gate control signals can be transmitted from the motherboard (MB) or the driver IC (DIC). The GCL electrically connects the gate driver unit (GIP) to the motherboard (MB) or the driver IC (DIC).

[0091] The gate control line GCL can be electrically connected to one of the flexible film COFs located at both ends of a plurality of flexible film COFs connected to the display panel 100 along the second non-display area NDA2. The gate control line GCL can be located at the outermost edge of a plurality of lines connected to a flexible film COF, but is not limited thereto. The data line DL can extend from the pad area PA and can be connected to the sub-pixel SP (or pixel) of the display area DA through the link area LA between the pad area PA and the display area DA. The data line DL can apply a data signal to each sub-pixel SP (or each pixel). The data signal can be applied from the motherboard MB or the driver IC DIC. The data line DL can electrically connect the sub-pixel SP (or pixel) to the motherboard MB or the driver IC DIC.

[0092] The data cable DL may include a first data cable DL1 and a second data cable DL2. The data cable DL can be connected to data pads DP1 and DP2. The first data cable DL1 can be electrically connected to the first data pad DP1 via a first data contact hole CNT1. The second data cable DL2 can be electrically connected to the second data pad DP2 via a second data contact hole CNT2.

[0093] A low-potential voltage line VSSL can be positioned within the non-display area NDA, surrounding the display area DA. The low-potential voltage line VSSL can also be positioned within the non-display area NDA between the display area DA and the gate drive unit GIP. For example, the gate drive unit GIP can be positioned between the display area DA and the low-potential voltage line VSSL.

[0094] The low-potential voltage line VSSL can apply a low-potential voltage to the sub-pixel SP (or pixel). The low-potential voltage line VSSL can be electrically connected to the cathode electrode 153 of the sub-pixel SP (or pixel) (see [link to documentation]). Figure 5 To apply a low potential voltage.

[0095] The low-potential voltage line VSSL can be connected to the pad area PA. The low-potential voltage line VSSL can be physically connected to the low-potential voltage pad VSSP, and electrically connected to the low-potential voltage pad VSSP. The low-potential voltage line VSSL and the low-potential voltage pad VSSP can be formed integrally, but are not limited to this.

[0096] A high-potential voltage line VDDL can be disposed between a low-potential voltage line VSSL in the display area DA and the non-display area NDA. The high-potential voltage line VDDL may also include a high-potential connection electrode (not shown). The high-potential connection electrode (not shown) may be disposed on a different layer than the high-potential voltage line VDDL. For example, the high-potential connection electrode (not shown) may be disposed between the second insulating layer 104 and the third insulating layer 105. The high-potential connection electrode (not shown) may electrically connect the high-potential voltage line VDDL to the anode electrode 151 (see [reference]) across a line disposed on the same layer as the high-potential voltage line VDDL. Figure 5 The high-potential connection electrode can be wire-connected to the anode electrode 151 across the same layer as the high-potential voltage line VDDL (see [reference]). Figure 5 ).

[0097] The high-potential voltage line VDDL can apply a high-potential voltage to the sub-pixel SP (or pixel). The high-potential voltage line VDDL can be electrically connected to the anode electrode 151 of the sub-pixel SP (or pixel) (see [link to relevant documentation]). Figure 5 To apply a high potential voltage.

[0098] The high-potential voltage line VDDL can be connected to the pad area PA. The high-potential voltage line VDDL can be physically connected to the high-potential voltage pad VDDP, and is also electrically connected to the high-potential voltage pad VDDP. The high-potential voltage line VDDL can contact the high-potential voltage pad VDDP through the contact hole S_CNT.

[0099] However, the embodiments described in this specification are not limited to this, and the high-potential voltage line VDDL can be disposed on the same layer as the high-potential voltage pad VDDP and integrally formed with the high-potential voltage pad VDDP. For example, the high-potential voltage line VDDL can be formed of the same material and the same conductive layer as the high-potential voltage pad VDDP, and the high-potential voltage line VDDL and the high-potential voltage pad VDDP can be formed together using the same mask process.

[0100] Even in this case, a high-potential connection electrode (not shown) disposed on a different layer than the high-potential voltage pad VDDP may also be included. The high-potential connection electrode (not shown) may electrically connect the high-potential voltage line VDDL to the anode electrode 151 across a line disposed on the same layer as the high-potential voltage line VDDL (see [link to documentation]). Figure 5 ).

[0101] The display device 1 may further include a dam portion DMP. The dam portion DMP may be disposed in the non-display area NDA. The dam portion DMP may be disposed around the display area DA, but is not limited thereto. At least a portion of the dam portion DMP may be disposed to overlap with the low-potential voltage line VSSL. The dam portion DMP may be disposed between the display area DA and the pad area PA in the second non-display area NDA2.

[0102] The display device 1 may also include a crack-resistant pattern CSP. The crack-resistant pattern CSP may be disposed at the outermost edge of the non-display area NDA. The crack-resistant pattern CSP may be formed using an inorganic film disposed above the substrate 101.

[0103] Additionally, the pad area PA and the link area LA can be positioned between the dam portion DMP and the crack prevention pattern CSP. At least a portion of the dam portion DMP can be configured to overlap with the link area LA, but the embodiments described in this specification are not limited thereto.

[0104] High-potential voltage lines VDDL, low-potential voltage lines VSSL, data lines DL, and gate control lines GCL, which connect to multiple pads VSSP, VDDP, DP, and GCP, can be located in the link region LA. These high-potential voltage lines VDDL, VSSL, DL, and GCL can be located on different layers within the link region LA, and at least a portion of them can overlap each other. For example, a high-potential voltage line VDDL or a low-potential voltage line VSSL can be configured to cross a data line DL or a gate control line GCL.

[0105] Figure 4 This is a plan view showing the pixel arrangement of a display panel according to one embodiment. Figure 4 The plan view is an enlarged view showing a portion of the display area DA in which pixels PX are set.

[0106] Reference Figure 4 The display panel 100 may include a first pixel group PXG1 and a second pixel group PXG2.

[0107] Each pixel group in the first pixel group PXG1 and the second pixel group PXG2 can be repeatedly set in the first direction DR1. The first pixel group PXG1 and the second pixel group PXG2 can be alternately and repeatedly set in the second direction DR2.

[0108] Subpixels SP can include subpixels SP1_1 (1_1), SP1_2 (1_2), SP1_3 (1_3), SP1_4 (1_4), SP2_1 (2_1), SP2_2 (2_2), and SP2_3 (2_3).

[0109] The first pixel group PXG1 may include sub-pixels SP1_1 (1_1), SP1_2 (1_2), SP1_3 (1_3), and SP1_4 (1_4). Sub-pixels SP1_1 (1_1), SP1_2 (1_2), SP1_3 (1_3), and SP1_4 (1_4) may be arranged in a row in a first direction.

[0110] Subpixel 1_1 SP1_1 can emit red (R) light, subpixel 1_2 SP1_2 can emit green (G) light, subpixel 1_3 SP1_3 can emit blue (B) light, and subpixel 1_4 SP1_4 can emit red (R) light.

[0111] Subpixels SP1_1, SP1_2, SP1_3, and SP1_4 may include light-emitting areas EA1_1, EA1_2, EA1_3, and EA1_4, as well as non-light-emitting areas NEA1_1, NEA1_2, NEA1_3, and NEA1_4 respectively disposed around the light-emitting areas EA1_1, EA1_2, EA1_3, and EA1_4.

[0112] Subpixel SP1_1 can include a light-emitting area EA1_1 and a non-light-emitting area NEA1_1 surrounding the light-emitting area EA1_1.

[0113] Subpixel SP1_2 can include a light-emitting area EA1_2 and a non-light-emitting area NEA1_2 disposed around the light-emitting area EA1_2.

[0114] The 1_3 sub-pixel SP1_3 may include a 1_3 luminous area EA1_3 and a 1_3 non-luminous area NEA1_3 disposed around the 1_3 luminous area EA1_3.

[0115] The 1_4 sub-pixel SP1_4 may include a 1_4 luminous area EA1_4 and a 1_4 non-luminous area NEA1_4 disposed around the 1_4 luminous area EA1_4.

[0116] The second pixel group PXG2 may include sub-pixels SP2_1 (2_1), SP2_2 (2_2), and SP2_3 (2_3). Sub-pixels SP2_1 (2_1), SP2_2 (2_2), and SP2_3 (2_3) may be arranged in a row in the second direction.

[0117] Subpixel 2_1 SP2_1 can emit blue (B) light, subpixel 2_2 SP2_2 can emit red (R) light, and subpixel 2_3 SP2_3 can emit green (G) light.

[0118] Sub-pixels SP2_1, SP2_2, and SP2_3 may include light-emitting regions EA2_1, EA2_2, and EA2_3, as well as non-light-emitting regions NEA2_1, NEA2_2, and NEA2_3 disposed around the light-emitting regions EA2_1, EA2_2, and EA2_3.

[0119] The 2_1 sub-pixel SP2_1 may include a 2_1 luminous area EA2_1 and a 2_1 non-luminous area NEA2_1 disposed around the 2_1 luminous area EA2_1.

[0120] The 2_2 sub-pixel SP2_2 may include a 2_2 luminous area EA2_2 and a 2_2 non-luminous area NEA2_2 disposed around the 2_2 luminous area EA2_2.

[0121] The 2_3 sub-pixel SP2_3 may include a 2_3 luminous area EA2_3 and a 2_3 non-luminous area NEA2_3 disposed around the 2_3 luminous area EA2_3.

[0122] In the planar diagram, no subpixel can be set below subpixel SP1_1 (on the other side of the second direction DR2).

[0123] In the planar diagram, sub-pixel 2_1 SP2_1 can be positioned below sub-pixel 1_2 SP1_2 (on the other side of the second direction DR2).

[0124] In the planar diagram, sub-pixel SP2_2 can be positioned below sub-pixel SP1_3 (on the other side of the second direction DR2).

[0125] In the planar view, sub-pixel SP2_3 of type 2 can be positioned below sub-pixel SP1_4 of type 1 (on the other side of the second direction DR2).

[0126] Figure 1 The sub-pixel SP shown in the image (see Figure 1 ) can refer to one of the sub-pixels: 1_1 sub-pixel SP1_1, 1_2 sub-pixel SP1_2, 1_3 sub-pixel SP1_3, 1_4 sub-pixel SP1_4, 2_1 sub-pixel SP2_1, 2_2 sub-pixel SP2_2, and 2_3 sub-pixel SP2_3.

[0127] Microlenses ML can be set on sub-pixels SP1_1 (1_1), SP1_2 (1_2), SP1_3 (1_3), SP1_4 (1_4), SP2_1 (2_1), SP2_2 (2_2), and SP2_3 (2_3). Microlenses ML can also be set within each sub-pixel SP (SP1_1, SP1_2, SP1_3, SP1_4, SP2_1, SP2_2, or SP2_3).

[0128] One microlens ML is shown as being disposed in each sub-pixel SP, but the embodiments described herein are not limited thereto. For example, depending on the design of each sub-pixel SP, the microlens ML disposed in each sub-pixel SP can be configured as two or more microlenses. When an opening (light-emitting region EA) formed in a sub-pixel SP is configured as multiple openings, the microlens ML can be disposed in each opening, or multiple microlenses ML can be disposed in one opening.

[0129] Each sub-pixel SP (SP1_1, SP1_2, SP1_3, SP1_4, SP2_1, SP2_2 or SP2_3) may include a light-emitting area EA (EA1_1, EA1_2, EA1_3, EA1_4, EA2_1, EA2_2 or EA2_3) and a non-light-emitting area NEA (NEA1_1, NEA1_2, NEA1_3, NEA1_4, NEA2_1, NEA2_2 or NEA2_3) disposed around the light-emitting area EA.

[0130] The microlens ML and its corresponding light-emitting region EA may not be aligned. Specifically, the center of the microlens ML and the center of the light-emitting region EA may not be aligned.

[0131] The center EC1 of the 1_1 light-emitting area EA1_1 of sub-pixel SP1_1 may not be aligned with the center LC1 of the microlens ML disposed on sub-pixel SP1_1. In the plan view, the center LC1 of the microlens ML may be offset from the center EC1 of the 1_1 light-emitting area EA1_1 to the other side (left side in the plan view) on the first direction DR1.

[0132] The description of the misalignment of sub-pixel SP1_1 can be applied in essentially the same way to the remaining sub-pixels SP1_2, SP1_3, and SP1_4 of the first pixel group PXG1. However, the degree of misalignment between the microlens ML and the luminous region EA can differ in each of the sub-pixels SP1_1, SP1_2, SP1_3, and SP1_4 of the first pixel group PXG1.

[0133] However, the implementation of this specification is not limited to this, and the direction in which the center LC1 of the microlens ML is misaligned with the center EC1 of the 1_1 light-emitting region EA1_1 can be varied according to the design.

[0134] The center EC2 of the 2_1 emitting region EA2_1 of the 2_1 sub-pixel SP2_1 and the center LC2 of the microlens ML disposed on the 2_1 sub-pixel SP2_1 may not be aligned. In the plan view, the center LC2 of the microlens ML may be offset from the center EC2 of the 2_1 emitting region EA2_1 to one side of the first direction DR1 (the right side in the plan view).

[0135] The description of the misalignment of subpixel SP2_1 can be applied in essentially the same way to the remaining subpixels SP2_2 and SP2_3 of the second pixel group PXG2. However, the degree of misalignment between the microlens ML and the luminous region EA can differ in each of the subpixels SP2_1, SP2_2, and SP2_3 of the second pixel group PXG2.

[0136] However, the implementation of this specification is not limited to this, and the direction in which the center LC2 of the microlens ML is misaligned with the center EC2 of the 2_1 light-emitting area EA2_1 can be varied according to the design.

[0137] In the following text, reference will be made to Figure 5 The description describes the cross-sectional structure of the display area DA of the display panel 100, which includes sub-pixels SP (SP1_1, SP1_2, SP1_3, SP1_4, SP2_1, SP2_2 and SP2_3).

[0138] Figure 5 It is along Figure 4 A cross-sectional view of line V-V' in the diagram. Figure 6 It was captured from different angles. Figure 5 A cross-sectional view of the touch portion.

[0139] Reference Figures 4 to 6 The display panel 100 may include a substrate 101, a thin-film transistor 120, a storage electrode 140, a light-emitting portion 150, an encapsulation portion 170, a touch portion 180, etc. However, the embodiments described in this specification are not limited thereto.

[0140] The substrate 101 can provide space on which various components can be mounted. The substrate 101 can correspond to Figure 1 The display panel 100 has a flat surface shape. For example, the substrate 101 may include a notched NCP. The substrate 101 may include the display area DA and the non-display area NDA of the display panel 100 in substantially the same manner.

[0141] The substrate 101 may include one or more plastic materials, but is not limited thereto, and may include glass materials.

[0142] The substrate 101 may be a multi-substrate comprising multiple substrates such as a first substrate 101a, a second substrate 101b, and a third substrate 101c, each substrate comprising a plastic material, such as polyimide, but embodiments described herein are not limited thereto. For example, the substrate 101 may be a single substrate formed from a single layer.

[0143] Substrate 101 may include a rigid substrate. However, embodiments of this specification are not limited thereto, and substrate 101 may include a flexible substrate.

[0144] A buffer layer 102 can be disposed on the substrate 101. The buffer layer 102 can minimize or delay the diffusion of moisture or oxygen permeating the substrate 101. The buffer layer 102 can be formed by alternately stacking silicon nitride (SiN) x ) and silicon oxide (SiO) x It may be formed at least once, but the implementation methods described in this specification are not limited thereto.

[0145] This specification describes the buffer layer 102 as being formed as a multilayer consisting of three layers, but the number of layers forming the buffer layer 102 is not limited to this, and the buffer layer 102 can also be formed as a single layer.

[0146] The first light-shielding layer 126 may be disposed on the buffer layer 102. The first light-shielding layer 126 can prevent light from passing through the semiconductor layer 123 of the thin-film transistor 120. For example, the first semiconductor layer 123 may be disposed overlapping the first light-shielding layer 126. The first light-shielding layer 126 may be formed of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd) and copper (Cu), but the embodiments described herein are not limited thereto.

[0147] A first insulating layer 103 may be disposed on the first light-shielding layer 126. The first insulating layer 103 prevents short circuits between components of the first thin-film transistor 120 and the first light-shielding layer 126. The first insulating layer 103 may be formed of the same material as the buffer layer 102, but embodiments described herein are not limited thereto. For example, the first insulating layer 103 may be made of materials such as silicon nitride (SiN). x ) or silicon oxide (SiO) x It can be formed from inorganic materials such as ), but the embodiments described in this specification are not limited to this.

[0148] The thin-film transistor 120 may be disposed on the first insulating layer 103. The thin-film transistor 120 may include a source electrode 121, a gate electrode 122, a semiconductor layer 123, and a drain electrode 124.

[0149] Semiconductor layer 123 may be disposed on first insulating layer 103. Semiconductor layer 123 may include metal oxide semiconductors such as indium gallium zinc oxide (IGZO), and silicon-based semiconductor materials such as amorphous silicon or polycrystalline silicon, but embodiments described herein are not limited thereto. Semiconductor layer 123 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0150] Because polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers and oxide semiconductor layers, power consumption can be lower and reliability can be superior. Therefore, driving transistors can be formed from polycrystalline semiconductor layers, but the embodiments described in this specification are not limited to this.

[0151] The second insulating layer 104 may be disposed on the semiconductor layer 123. The second insulating layer 104 may be formed of the same material as the first insulating layer 103, but the embodiments described herein are not limited thereto. The second insulating layer 104 can prevent short circuits between the semiconductor layer 123 and another component of the thin-film transistor 120.

[0152] The gate electrode 122 may be disposed on the second insulating layer 104. The gate electrode 122 may be disposed on the second insulating layer 104 to overlap with the channel region of the semiconductor layer 123. The gate electrode 122 may be formed of a single layer or multiple layers made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or compounds thereof, but the embodiments described herein are not limited thereto. The gate electrode 122 may be disposed together with the gate line, but the embodiments described herein are not limited thereto.

[0153] The third insulating layer 105 may be disposed on the gate electrode 122. The third insulating layer 105 may be formed of the same material as the first insulating layer 103 or the second insulating layer 104, but the embodiments described herein are not limited thereto.

[0154] The storage electrode 140 may be configured to be spaced apart from the thin-film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0155] The first storage electrode 141 may be formed of the same material as the gate electrode 122 and on the same layer as the gate electrode 122, but the embodiments described herein are not limited thereto.

[0156] The second storage electrode 142 may be disposed on the first storage electrode 141. The second storage electrode 142 may be disposed on the third insulating layer 105, and the third insulating layer 105 between the first storage electrode 141 and the second storage electrode 142 may serve as a dielectric to generate a capacitor. The first storage electrode 141 may be formed on the same layer as the gate electrode 122 of the thin-film transistor 120, using the same material as the gate electrode 122 of the thin-film transistor 120. The second storage electrode 142 may be formed of the same material as the first storage electrode 141, but the embodiments described herein are not limited thereto, and the second storage electrode 142 may be formed of a different material than the first storage electrode 141.

[0157] The fourth insulating layer 106 may be disposed on the second storage electrode 142. The fourth insulating layer 106 may be formed of the same material as the first insulating layer 103, the second insulating layer 104 or the third insulating layer 105, but the embodiments described herein are not limited thereto.

[0158] The source electrode 121 and the drain electrode 124 can be disposed on the fourth insulating layer 106.

[0159] The source electrode 121 and drain electrode 124 can be electrically connected to the semiconductor layer 123 through contact holes. The source electrode 121 and drain electrode 124 can be formed of a metallic material. For example, the source electrode 121 and drain electrode 124 can be formed of a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (nd), and copper (Cu), but the embodiments described in this specification are not limited thereto.

[0160] The source electrode 121 and the drain electrode 124 can be disposed together with the data line. For example, the data line can be formed of the same material as the source electrode 121 and the drain electrode 124, and formed on the same layer as the source electrode 121 and the drain electrode 124, but the embodiments described herein are not limited thereto.

[0161] The thin-film transistor 120 may be a driving transistor, and although not shown, the display panel 100 may also include a switching transistor, but the embodiments described herein are not limited thereto.

[0162] The first protective layer 111 can be disposed on the source electrode 121 and the drain electrode 124.

[0163] The first protective layer 111 can planarize the upper part of the thin-film transistor 120 and protect the thin-film transistor 120. The first protective layer 111 can be formed of an organic material. For example, the first protective layer 111 can be formed of an organic material including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but the embodiments in this specification are not limited thereto.

[0164] The second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be formed of the same material as the first protective layer 111, but the embodiments described herein are not limited thereto.

[0165] The connecting electrode 145 can be disposed between the first protective layer 111 and the second protective layer 112.

[0166] The connection electrode 145 can electrically connect the thin-film transistor 120 to the light-emitting portion 150. The connection electrode 145 can be formed of the same material as the source electrode 121 and the drain electrode 124, but the embodiments described herein are not limited thereto.

[0167] The connecting electrode 145 can contact the drain electrode 124 through the contact hole formed in the first protective layer 111, and can be electrically connected to the drain electrode 124.

[0168] The connecting electrode 145 may be formed from a single layer or multiple layers of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but the embodiments described herein are not limited thereto.

[0169] The light-emitting portion 150 may be disposed on the second protective layer 112. The light-emitting portion 150 may include an anode electrode 151, an organic layer 152, and a cathode electrode 153.

[0170] The anode electrode 151 may be disposed on the second protective layer 112. The anode electrode 151 may be electrically connected to the thin-film transistor 120 through contact holes formed in the first protective layer 111 and the second protective layer 112.

[0171] The anode electrode 151 may be a reflective electrode that reflects light, but the embodiments described herein are not limited thereto. The anode electrode 151 may include a metallic material with high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), or an APC alloy, and the anode electrode 151 may be formed of a single layer or multiple layers, but the embodiments described herein are not limited thereto.

[0172] For example, the cathode electrode 153 may include materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiments described herein are not limited thereto.

[0173] Organic layer 152 may be disposed on anode electrode 151. Organic layer 152 may include one or more light-emitting structures (or light-emitting elements or components) stacked on anode electrode 151 in the order of hole transfer layer and electron transfer layer, or in reverse order. For example, hole transfer layer may include hole transport layer, hole injection layer, electron blocking layer, p-type charge generation layer, etc., but the embodiments described herein are not limited thereto. For example, electron transfer layer may include electron transport layer, electron injection layer, hole blocking layer, n-type charge generation layer, etc., but the embodiments described herein are not limited thereto.

[0174] The organic layer 152 can be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, a miniature light-emitting diode, etc., but the embodiments described herein are not limited to these. For example, the organic layer 152 of the display panel 100 according to one embodiment of this specification may include an organic light-emitting layer. The organic layer 152 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, but the embodiments described herein are not limited to these. The organic layer 152 may be a white light-emitting layer, but the embodiments described herein are not limited to these.

[0175] The cathode electrode 153 may be disposed on the organic layer 152. The cathode electrode 153 may be a transparent electrode that transmits light, but the embodiments described herein are not limited thereto. For example, the cathode electrode 153 may comprise a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal that transmits visible light, but the embodiments described herein are not limited thereto.

[0176] A capping layer 156 can also be provided on the cathode electrode 153. The capping layer 156 can reduce or minimize the damage of the external light source to the cathode electrode 153 of the light-emitting element EL and the organic layer 152 located below the cathode electrode 153. The capping layer 156 can be formed of an organic or inorganic film.

[0177] The capping layer 156 can be configured as an inorganic film using materials such as LiF, and may also include an organic film, but the embodiments described herein are not limited thereto. For example, the capping layer 156 may be formed by a stacked structure of organic and inorganic films, and the thickness of the organic film may differ from the thickness of the inorganic film. In this case, the thickness of the organic film may be greater than the thickness of the inorganic film. As another example, the capping layer 156 can be formed by stacking two or more layers of materials with different refractive indices. Therefore, the light efficiency of the display panel 100 can be improved.

[0178] The dam 154 can be configured to expose the anode electrode 151. The dam 154 can define an opening (or light-emitting region EA) of the sub-pixel SP and can be configured to cover the edge of the anode electrode 151. An organic layer 152 can be disposed in the opening of the sub-pixel SP. For example, the organic layer 152 can be disposed on the anode electrode 151 exposed by the dam 154.

[0179] The dam 154 can be formed from a material containing black pigment or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, photosensitive polymer, etc., but the embodiments described herein are not limited to these. When the dam 154 is formed from a material containing black pigment or black dye, the dam 154 can be a black dam. When the dam 154 is formed from a material containing black pigment or black dye, it can shield external light or light reflected from the outside, thereby further enhancing the brightness of the display device.

[0180] Spacers 155 may also be provided on the embankment 154. Spacers 155 may be formed of the same material as the embankment 154, but the embodiments described herein are not limited thereto. Spacers 155 can prevent the mask from sagging during the masking process, thereby suppressing or preventing puncture defects and scratches on the display panel 100.

[0181] The encapsulation portion 170 may be disposed on the dam 154 or the light-emitting portion 150. The encapsulation portion 170 may include one or more insulating layers. For example, the encapsulation portion 170 may include a first inorganic encapsulation layer 171, an organic encapsulation layer 172 formed on the first inorganic encapsulation layer 171, and a second inorganic encapsulation layer 173 formed on the organic encapsulation layer 172. The encapsulation portion 170 may include one or more inorganic layers and one or more organic layers. For example, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 may include inorganic materials, and the organic encapsulation layer 172 may include organic materials, but the embodiments described herein are not limited thereto.

[0182] Even when the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can be configured to extend to the end of the non-display area NDA, the organic encapsulation layer 172 can terminate inside the dam portion DMP. For example, the organic encapsulation layer 172 can be disposed inside the area surrounded by the dam portion DMP, without extending beyond the dam portion DMP.

[0183] The touch portion 180 may be disposed on the package portion 170. The touch portion 180 may include a touch buffer layer 181, a first touch electrode 182, a first touch insulating layer 183, a black matrix BM, a second touch insulating layer 184, a second touch electrode 185, and a third touch insulating layer 186.

[0184] Touch buffer layer 181 may be disposed on encapsulation portion 170. For example, touch buffer layer 181 may be disposed on second inorganic encapsulation layer 173. Touch buffer layer 181 may be formed of the same material as buffer layer 102, but the embodiments described herein are not limited thereto.

[0185] The first touch electrode 182 can be disposed on the touch buffer layer 181.

[0186] The first touch insulating layer 183 can be disposed on the first touch electrode 182. The first touch insulating layer 183 can be made of silicon oxide (SiO2). x ), silicon nitride (SiN) x It may be formed in multiple layers or in combination, but the embodiments described herein are not limited thereto.

[0187] The black matrix BM can be disposed on the first touch insulating layer 183. The black matrix BM can include a material capable of absorbing light. The black matrix BM can include, but is not limited to, black pigments or dyes. The black matrix BM can prevent light leakage defects that may occur between sub-pixels SP.

[0188] The second touch insulating layer 184 may be disposed on the black matrix BM. The second touch insulating layer 184 may include an organic insulating material. For example, the second touch insulating layer 184 may be formed of acrylic acid, benzocyclobutene (BCB), polyimide (PI) or polyamide (PA), but is not limited thereto.

[0189] The second touch electrode 185 may be disposed on the second touch insulating layer 184. The second touch electrode 185 may include a 1a touch electrode 185a extending in the first direction DR1 and a 1b touch electrode 185b extending in the second direction DR2, which is different from the first direction.

[0190] The first touch electrode 182 can be electrically connected to the 1a touch electrode 185a through a contact hole formed in the insulating layer 184. For example, the 1a touch electrode 185a and the first touch electrode 182 can extend in the first direction DR1.

[0191] The first touch electrode 182 and the second touch electrode 185 may include metallic materials. For example, the sensor electrode 185 and the bridge electrode 182 may be formed of titanium (Ti), nickel (Ni), aluminum (Al) or alloys thereof, and may be formed of a three-layer structure such as titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments described herein are not limited thereto.

[0192] One of the first touch electrode 182 and the second touch electrode 185 may include the function of detecting touch, and the other touch electrode may include the function of driving touch, but the embodiments described herein are not limited thereto.

[0193] The third touch insulating layer 186 may be disposed on the second touch electrode 185. The third touch insulating layer 186 may be formed of the same material as the first touch insulating layer 183, but is not limited thereto.

[0194] The microlens ML can be disposed on the third touch insulating layer 186. The microlens ML can be hemispherical or semi-cylindrical in shape, but is not limited to these. The shape of the microlens ML can vary depending on the size, shape, etc. of the light-emitting region EA.

[0195] In addition, by arranging microlenses (ML), light leakage can be prevented by shielding leaked light and reflected light, ensuring wide viewing angle characteristics and enhancing brightness.

[0196] The center of the microlens ML and the center of its corresponding light-emitting region EA may not be aligned. However, since some components of the light-emitting part 150 may be tilted, light emitted from the light-emitting region EA may travel to the microlens ML.

[0197] A lens protective film 190 can be applied to the microlens ML. The lens protective film 190 may include, but is not limited to, an organic insulating material. The lens protective film 190 can protect the microlens ML by covering it.

[0198] The refractive index of the lens protective film 190 can be less than that of the microlens ML. Therefore, due to the difference in refractive index between the microlens ML and the lens protective film 190, light that has passed through the microlens ML can be prevented from being reflected toward the substrate 101.

[0199] In the region where the light-emitting portion 150 is disposed, a portion of the upper surface of the second protective layer 112 may be formed to have an angle. The light-emitting portion 150 may be disposed on the second protective layer 112, at least a portion of which is angled. Therefore, at least a portion of each of the anode electrode 151 and the organic layer 152 may be angled. At least a portion of each of the anode electrode 151 and the organic layer 152 may be angled toward the microlens ML.

[0200] Specifically, each of the anode electrode 151 and the organic layer 152 may be disposed on at least a portion of the inclined second protective layer 112. Each of the anode electrode 151 and the organic layer 152 may be disposed on the inclined second protective layer 112 over its entire area, but is not limited thereto.

[0201] A portion of the second protective layer 112 may include a sloping surface. Embodiments of this specification are not limited thereto; rather, for example, the sloping surface of the second protective layer 112 may be formed using a slot mask process.

[0202] The anode electrode 151 and the organic layer 152 disposed on the inclined second protective layer 112 can be configured to be inclined (tilted) corresponding to the inclined second protective layer 112. Therefore, a portion of the cathode electrode 153 disposed on the organic layer 152 can be configured to be inclined.

[0203] For example, the anode electrode 151 and the organic layer 152 can be configured to be tilted in the thickness direction (third direction DR3) of the display panel 100 in the 1_1 light-emitting region EA1_1, the 2_1 light-emitting region EA2_1 and their surrounding areas. For example, the directions facing the upper surfaces of the anode electrode 151 and the upper surfaces of the organic layer 152 can be tilted in the thickness direction (third direction DR3) of the display panel 100.

[0204] In the first light-emitting region EA1_1, the second light-emitting region EA2_1 and the surrounding region, the anode electrode 151 and the organic layer 152 may be tilted in different directions.

[0205] exist Figure 5 The anode electrode 151 and organic layer 152 around the 1_1 light-emitting region EA1_1 of sub-pixel SP1_1 and the 2_1 light-emitting region EA2_1 of sub-pixel SP2_1 have been described, but the description can be applied to all sub-pixels in sub-pixel SP.

[0206] Therefore, the light emitted from each sub-pixel SP can be tilted in the thickness direction (third direction DR3) of the display panel 100.

[0207] Because the microlens ML and the light-emitting area EA are misaligned, even when the light L1 and L2 emitted from the light-emitting part 150 travel at an angle relative to the thickness direction (third direction DR3), each light L1 or L2 can travel toward the microlens ML.

[0208] Subpixels SP1_1, SP1_2, SP1_3, and SP1_4, located in the first pixel group PXG1, can emit light L1 to the left (on the other side of the first direction DR1) in the planar view. Subpixels SP2_1, SP2_2, and SP2_3, located in the second pixel group PXG2, can emit light L2 to the right (on one side of the first direction DR1) in the planar view.

[0209] For example, light L1 emitted from sub-pixels SP1_1, SP1_2, SP1_3, and SP1_4 of the first pixel group PXG1 can travel while tilted to one side of the first direction DR1 relative to the thickness direction (third direction DR3). Light L2 emitted from sub-pixels SP2_1, SP2_2, and SP2_3 of the second pixel group PXG2 can travel while tilted to one side of the first direction DR1 relative to the thickness direction (third direction DR3).

[0210] The degree and direction of misalignment between the microlens ML and the luminous region EA can vary depending on the direction of light travel emitted from the sub-pixels SP of each pixel group PXG1 or PXG2.

[0211] In the plan view, the sub-pixels SP1_1, SP1_2, SP1_3, and SP1_4 set in the first pixel group PXG1 and the sub-pixels SP2_1, SP2_2, and SP2_3 set in the second pixel group PXG2 can emit light in different directions. Therefore, the screen displayed to the driver sitting in the driver's seat can be distinguished from the screen displayed to the passenger sitting in the passenger seat so that each can be controlled separately, and different screens can be displayed to the driver and the passenger.

[0212] The cross-sectional structure of the non-display area NDA of the display device 1 will be described below. Content identical to that described in the cross-sectional structure of the display area DA will be briefly described or omitted.

[0213] Figure 7 It is along Figure 1 A cross-sectional view of line A-A' in the diagram. Figure 7 The cross-sectional structure of the first non-display area NDA1 is shown.

[0214] Reference Figure 1 , Figure 5 and Figure 7 In the first non-display area NDA1, the display panel 100 may include a substrate 101, a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, a fourth insulating layer 106, a first protective layer 111, a second protective layer 112, a dam 154, an encapsulation portion 170, a touch buffer layer 181, a first touch insulating layer 183, and a third touch insulating layer 186 arranged sequentially.

[0215] In the first non-display area NDA1, the display panel 100 may further include a gate control transistor G120, a low potential voltage line VSSL, a dam section DMP, and a crack-resistant pattern CSP.

[0216] The gate control transistor G120 may have a configuration substantially the same as that of the thin-film transistor 120 of the pixel SP, and may be formed together with the thin-film transistor 120 of the pixel SP by the same process, but is not limited thereto.

[0217] The gate control transistor G120 may include a control source electrode G121, a control gate electrode G122, a control semiconductor layer G123, and a control drain electrode G124.

[0218] The low-potential voltage line VSSL can be disposed on the fourth insulating layer 106 in the non-display area NDA. The low-potential voltage pad VSSL can be disposed on the same layer as the source electrode 121 and the drain electrode 124, and can include the same material as the source electrode 121 and the drain electrode 124, and can be formed together with the source electrode 121 and the drain electrode 124 using a mask through the same process, but is not limited thereto.

[0219] Although not shown, the low-potential voltage line VSSL may also include a separate low-potential voltage connection electrode for contact with the cathode electrode 153. The low-potential voltage connection electrode may be disposed on a different layer than the low-potential voltage line VSSL and may be made of a different material than the low-potential voltage line VSSL, but is not limited thereto. Through the low-potential voltage connection electrode, the low-potential voltage line VSSL can be electrically connected across other lines disposed on the same layer to the anode electrode 151 of the light-emitting portion 150 disposed in the display area DA.

[0220] The dam section DMP includes a first dam DM1 and a second dam DM2. The first dam DM1 and the second dam DM2 may overlap with the low potential voltage line VSSL. The first dam DM1 may be located outside the second dam DM2, but is not limited thereto.

[0221] The first dam DM1 can be formed in a multi-layered structure. Each layer of the first dam DM1 may include the same material as the second protective layer 112, the dike 154 and the spacer 155, and may be formed together using a mask with the same process as the second protective layer 112, the dike 154 and the spacer 155, but is not limited thereto.

[0222] The second dam DM2 can be formed in a multi-layered structure. Each layer of the second dam DM2 may include the same material as the second protective layer 112 and the dike 154, and may be formed together using a mask with the same process as the second protective layer 112 and the dike 154, but is not limited thereto.

[0223] The crack-resistant pattern CSP can be disposed at the outermost edge of the non-display area NDA. Although not shown, multiple crack-resistant patterns can be provided, but this is not a limitation. The crack-resistant pattern CSP can be defined by making at least one of the inorganic films disposed on the substrate 101 recessed.

[0224] For example, the crack-resistant pattern CSP can be defined by recessing the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186, but is not limited thereto. For example, at least one of the first protective layer 111, the second protective layer 112, and the dam 154 can also be disposed around the crack-resistant pattern CSP. In this case, the crack-resistant pattern CSP can be defined by further recessing the first protective layer 111, the second protective layer 112, the dam 154, and at least one of the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186.

[0225] At least some of the inorganic films disposed on the substrate 101 may extend to the end of the non-display area NDA. For example, at least some of the inorganic films disposed on the substrate 101 may extend to the end of the substrate 101.

[0226] The buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to the end of the first non-display area NDA1.

[0227] For example, in the first non-display area NDA1, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may extend to the end of the substrate 101.

[0228] In the first non-display area NDA1, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can substantially cover the entire area of ​​the substrate 101.

[0229] The ends (or side surfaces) of the substrate 101, buffer layer 102, first insulating layer 103, second insulating layer 104, third insulating layer 105, fourth insulating layer 106, first inorganic encapsulation layer 171, second inorganic encapsulation layer 173, touch buffer layer 181, first touch insulating layer 183 and third touch insulating layer 186 may be aligned, but are not limited thereto.

[0230] However, the embodiments described herein are not limited thereto, and in the first non-display area NDA1, at least one of the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may not extend to the end of the substrate 101.

[0231] For example, in the first non-display area NDA1, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer 106 can extend to the end of the substrate 101, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can extend only to the dam portion DMP, and the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend up to before the dam portion DMP. For example, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer 106 can be disposed between the dam portion DMP and the crack-resistant pattern CSP, and the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can be omitted.

[0232] Figure 8 It is along Figure 3 A cross-sectional view of line B-B' in the diagram. Figure 9 It is along Figure 3 A cross-sectional view of line C-C' in the diagram. Figure 10 It is along Figure 3 A cross-sectional view of line D-D' in the diagram.

[0233] Figures 8 to 10 The cross-sectional structure of the second non-display area NDA2 is shown. Figures 8 to 10 A cross-section of the notched non-display area N_NDA of the second non-display area NDA2 is shown, but its description can be applied to the extended non-display area E_NDA in substantially the same manner. However, embodiments of this specification are not limited thereto, and the notched non-display area N_NDA and the extended non-display area E_NDA may have different cross-sectional structures.

[0234] Reference Figure 3 , Figure 5 and Figures 8 to 10 In the notched non-display area N_NDA, the display panel 100 may include a substrate 101, a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, a fourth insulating layer 106, a first protective layer 111, a second protective layer 112, a dam 154, an encapsulation portion 170, a touch buffer layer 181, a first touch insulating layer 183, and a third touch insulating layer 186 arranged sequentially.

[0235] In the recessed non-display area N_NDA, the display panel 100 may also include a high-potential voltage line VDDL, a low-potential voltage line VSSL, a dam portion DMP, multiple pads VSSP, VDDP and DP disposed in the pad area PA, data lines DL (DL1 and DL2) and a crack-resistant pattern CSP.

[0236] The high-potential voltage line VDDL can be disposed on the buffer layer 102 and covered by the first insulating layer 103 in the non-display area NDA. The high-potential voltage line VDDL may include the same material as the first light-shielding layer 126 and can be formed together with a mask using the same process as the first light-shielding layer 126, but is not limited thereto.

[0237] Although not shown, the high-potential voltage pad VDDP can be disposed on the same layer as the source electrode 121 and the drain electrode 124, can include the same material as the source electrode 121 and the drain electrode 124, and can be formed together with a mask using the same process as the source electrode 121 and the drain electrode 124, but is not limited thereto.

[0238] In this case, the high-potential voltage pad VDDP can be electrically connected to the high-potential voltage line VDDL through the contact hole S_CNT that exposes the high-potential voltage line VDDL.

[0239] The high-potential voltage line VDDL may also include a high-potential connection electrode (not shown). The high-potential connection electrode (not shown) may be disposed on a different layer than the high-potential voltage line VDDL. For example, the high-potential connection electrode (not shown) may be disposed between the second insulating layer 104 and the third insulating layer 105. The high-potential connection electrode (not shown) may electrically connect the high-potential voltage line VDDL to the anode electrode 151 across a line disposed on the same layer as the high-potential voltage line VDDL.

[0240] When the high-potential voltage line VDDL is formed on the same layer as the high-potential voltage pad VDDP and integrally formed therewith, it may also include a high-potential connection electrode (not shown) disposed on a different layer than the high-potential voltage pad VDDP. The high-potential connection electrode (not shown) can electrically connect the high-potential voltage line VDDL to the anode electrode 151 across a line disposed on the same layer as the high-potential voltage line VDDL.

[0241] The first data pad DP1 and the second data pad DP2 can be disposed on the fourth insulating layer 106. The first data pad DP1 and the second data pad DP2 can be disposed on the same layer as the source electrode 121 and the drain electrode 124, and can include the same material as the source electrode 121 and the drain electrode 124, and can be formed together using a mask using the same process as the source electrode 121 and the drain electrode 124, but are not limited thereto.

[0242] In the non-display area NDA, the first data line DL1 may be disposed on the second insulating layer 104 and covered by the third insulating layer 105. The first data line DL1 may include the same material as the gate electrode 122 and may be formed together with the gate electrode 122 using a mask through the same process, but is not limited thereto.

[0243] The display panel 100 may also include a first data connection line (not shown). The first data connection line (not shown) may be disposed on a different layer from the first data line DL1, and the first data line DL1 may be electrically connected to the thin-film transistor 120 of the display area DA.

[0244] In the non-display area NDA, the second data line DL2 may be disposed on the third insulating layer 105 and covered by the fourth insulating layer 106. The second data line DL2 may include the same material as the second storage electrode 142 and may be formed together with the second storage electrode 142 using a mask through the same process, but is not limited thereto.

[0245] The display panel 100 may also include a second data connection line (not shown). The second data connection line (not shown) may be disposed on a different layer than the second data line DL2, and the second data line DL2 may be electrically connected to the thin-film transistor 120 of the display area DA.

[0246] The first data line DL1 can be electrically connected to the first data pad DP1 via the first data contact hole CNT1. The second data line DL2 can be electrically connected to the second data pad DP2 via the second data contact hole CNT2.

[0247] The first data line DL1 and the second data line DL2 can be insulated by the third insulating layer 105 and arranged alternately. For example, the first data line DL1 and the second data line DL2 that are adjacent to each other can be arranged on different layers in the link area LA and extend thereon, thereby reducing or minimizing the border area.

[0248] The first data line DL1 can be formed on the same layer as the first electrode of the storage electrode using the same material as the first electrode of the storage electrode, and the second data line can be formed on the same layer as the second electrode of the storage electrode using the same material as the second electrode of the storage electrode.

[0249] The gate control pad (GCP) may include, but is not limited to, the same material as the gate control line (GCL). The gate control pad (GCP) and the gate control line (GCL) may be formed integrally, but are not limited to.

[0250] For example, the gate control pad GCP and the gate control line GCL can be disposed on the fourth insulating layer 106 in the non-display area NDA. The gate control pad GCP and the gate control line GCL can be disposed near the source electrode 121 (see...). Figure 5 ) and drain electrode 124 (see Figure 5 On the same layer, and may include the same material as the source electrode 121 and drain electrode 124, and the gate control pad GCP, gate control line GCL, source electrode 121 and drain electrode 124 may be formed together using a mask through the same process, but the embodiments described herein are not limited thereto.

[0251] The gate control pad (GCP) and gate control line (GCL) can be formed of different materials. For example, in the non-display area (NDA), the gate control pad (GCP) can be disposed on the fourth insulating layer 106, and the gate control line (GCL) can be disposed on the second insulating layer 104 and covered by the third insulating layer 105, like the first data line DL1, or disposed on the third insulating layer 105 and covered by the fourth insulating layer 106, like the second data line DL2.

[0252] The crack-resistant pattern CSP can be set outside the pad area PA. The crack-resistant pattern CSP can be set between the ends of the pad area PA and the non-display area NDA2.

[0253] At least some of the inorganic films disposed on the substrate 101 can extend to the end of the non-display area NDA2. For example, at least some of the inorganic films disposed on the substrate 101 in the notched non-display area N_NDA and the extended non-display area E_NDA can extend to the end of the substrate 101.

[0254] In the notched non-display area N_NDA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to the end of the substrate 101.

[0255] In the notched non-display area N_NDA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can substantially cover the entire area of ​​the substrate 101 except for the pad area PA.

[0256] The ends (or side surfaces) of the substrate 101, buffer layer 102, first insulating layer 103, second insulating layer 104, third insulating layer 105, fourth insulating layer 106, first inorganic encapsulation layer 171, second inorganic encapsulation layer 173, touch buffer layer 181, first touch insulating layer 183 and third touch insulating layer 186 may be aligned, but are not limited thereto.

[0257] However, multiple pads VSSP, VDDP, and DP may not be covered by multiple inorganic films. Multiple inorganic films disposed on the fourth insulating layer 106 can expose multiple pads VSSP, VDDP, and DP. Multiple inorganic films disposed on the fourth insulating layer 106 may not be disposed within the pad area PA.

[0258] For example, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can be disposed in the notched non-display area N_NDA up to the end of the substrate 101, but may not be disposed in the pad area PA. Therefore, the plurality of pads VSSP, VDDP, and DP disposed on the fourth insulating layer 106 can be exposed, and the display panel 100 can be attached to and electrically connected to the flexible film COF.

[0259] However, the embodiments described herein are not limited thereto, and in the extended non-display area E_NDA, at least one of the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may not extend to the end of the substrate 101.

[0260] For example, in the extended non-display area E_NDA, buffer layer 102, first insulating layer 103, second insulating layer 104, third insulating layer 105, and fourth insulating layer 106 can extend to the end of substrate 101, first inorganic encapsulation layer 171 and second inorganic encapsulation layer 173 can extend only to the dam portion DMP, and touch buffer layer 181, first touch insulating layer 183, and third touch insulating layer 186 can extend up to before the dam portion DMP. For example, buffer layer 102, first insulating layer 103, second insulating layer 104, third insulating layer 105, and fourth insulating layer 106 can be disposed between the dam portion DMP and the crack-resistant pattern CSP, and the first inorganic encapsulation layer 171, second inorganic encapsulation layer 173, touch buffer layer 181, first touch insulating layer 183, and third touch insulating layer 186 may not be disposed. However, multiple pads VSSP, VDDP, DP, and GCP may not be covered by multiple inorganic films. Multiple inorganic films disposed on the fourth insulating layer 106 can expose multiple pads VSSP, VDDP, DP, and GCP. The multiple inorganic films disposed on the fourth insulating layer 106 may not be disposed within the pad area PA.

[0261] For example, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can be disposed in the notched non-display area N_NDA up to the end of the substrate 101, but may not be disposed in the pad area PA. Therefore, the plurality of pads VSSP, VDDP, DP, and GCP disposed on the fourth insulating layer 106 can be exposed, and the display panel 100 can be attached to and electrically connected to the flexible film COF.

[0262] Figure 11 This is a plan view of the recessed non-display area of ​​the second non-display area. Figure 12 It is along Figure 11 A cross-sectional view of line E-E' in the diagram.

[0263] Reference Figure 11 and Figure 12 In the notched non-display area N_NDA, an anti-scratch area SA can also be set on the link area LA.

[0264] In the scratch-resistant area SA, the display panel 100 may sequentially include a substrate 101, a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, a fourth insulating layer 106, a first protective layer 111, a first scratch-resistant pattern SSP1, a second protective layer 112, a second scratch-resistant pattern SSP2, a first inorganic encapsulation layer 171, a second inorganic encapsulation layer 173, a touch buffer layer 181, a first touch insulating layer 183, and a third touch insulating layer 186.

[0265] The scratch-resistant area SA can be formed in at least a portion of the link area LA in which multiple data lines DL connected to the data pad DP extend diagonally toward the display area DA. Alternatively, the scratch-resistant area SA can be located between the pad area PA and the dam portion DMP.

[0266] In the scratch-resistant area SA, the display panel 100 may include a scratch-resistant pattern SSP. The scratch-resistant pattern SSP may be formed by a first scratch-resistant pattern SSP1 and a second scratch-resistant pattern SSP2 that overlaps with the first scratch-resistant pattern SSP1.

[0267] A first scratch-resistant pattern SSP1 may be formed on the first protective layer 111. At least a portion of the first scratch-resistant pattern SSP1 may be configured to overlap with the first data line DL1 and the second data line DL2 in the link area LA. The first scratch-resistant pattern SSP1 may be implemented in an all-metal form throughout the entire scratch-resistant area SA. However, embodiments of this specification are not limited thereto, and the first scratch-resistant pattern SSP1 may be implemented in an all-metal form or in the form of multiple islands in some areas.

[0268] The first scratch-resistant pattern SSP1 can be formed on the same layer as the connecting electrode 145 using the same material. The first scratch-resistant pattern SSP1 and the connecting electrode 145 can be formed together using the same process with a mask, but are not limited thereto.

[0269] A second scratch-resistant pattern SSP2 can be formed on the second protective layer 112. At least a portion of the second scratch-resistant pattern SSP2 can be configured to overlap with the first data line DL1 and the second data line DL2 in the link area LA. The second scratch-resistant pattern SSP2 can be implemented in the link area LA in the form of a strip or in the form of multiple islands.

[0270] The second scratch-resistant pattern SSP2 can be formed on the same layer as spacer 155 using the same material. The second scratch-resistant pattern SSP2 and spacer 155 can be formed together using the same process with a mask, but are not limited thereto.

[0271] The second scratch-resistant pattern SSP2 can be formed to be covered by the first inorganic encapsulation layer 171. For example, in the scratch-resistant area SA, at least a portion of the first inorganic layer 171 can be formed to contact the second protective layer 112 and to cover the upper and side surfaces of the second scratch-resistant pattern SSP2.

[0272] In this way, the display panel 100 can be designed to include a notched NCP by including a scratch-resistant area SA in which a scratch-resistant pattern SSP is formed, and users can obtain improved aesthetics and convenience. Furthermore, puncture or scratch defects in the display panel 100 caused by mask sagging, which may occur in the notched NCP due to the manufacturing process, can be suppressed and prevented. In addition, defects in the display device 1 can be prevented, the lifespan of the display device 1 can be increased, and the production energy of the display device 1 can be reduced.

[0273] Figure 13 This is a plan view of a display device according to another embodiment.

[0274] Reference Figure 13 In the display device 2 according to this embodiment, a separate gate driving unit GIP (see...) Figure 1 The pixel gate drive unit (GIA) can be set outside the non-display area NDA, and the pixel gate drive unit (GIA) can be set in the display area DA.

[0275] A pixel gate driving unit (GIA) can be configured as multiple pixel gate driving units, and each pixel gate driving unit (GIA) can be connected to each of the multiple sub-pixels (SPs). Pixel gate driving units (GIAs) can be arranged between adjacent sub-pixels (SPs).

[0276] For example, a pixel gate driving unit GIA can be disposed between adjacent sub-pixels SP in the first direction DR1. Sub-pixels SP and pixel gate driving units GIA can be disposed alternately and repeatedly in the first direction DR1. Sub-pixels SP can be disposed continuously and repeatedly in the second direction DR2. Pixel gate driving units GIA can be disposed continuously and repeatedly in the second direction DR2.

[0277] The pixel gate drive unit GIA can be represented by the gate drive unit GIP (see [link]). Figure 1 They serve essentially the same function. The pixel gate drive unit (GIA) can include at least one transistor.

[0278] The pixel gate drive unit (GIA) can be electrically connected to the adjacent sub-pixel (SP).

[0279] The pixel gate driving unit (GIA) receives gate control signals from the driver IC (DIC) via the gate control line (GCL_2). The GIA can then generate scan signals and emission signals (or emission control signals) based on the gate control signals. Therefore, it can control the driving of adjacent sub-pixels (SPs).

[0280] Since the pixel gate drive unit (GIA) is located in the display area (DA), the non-display area (NDA) or the border area can be minimized, thereby providing the user with an improved aesthetic.

[0281] The display device according to the embodiments of this specification can be described as follows.

[0282] A display device according to an embodiment of this specification includes: a substrate having a notch and including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; a plurality of transistors disposed on the substrate and including a gate electrode, a source electrode, and a drain electrode; a display panel including a light-emitting portion disposed on the plurality of transistors and including an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode; and a microlens disposed on the light-emitting area of ​​the sub-pixels, wherein pad portions and link portions may be disposed in the non-display area, and a plurality of data lines may be alternately disposed in the link portions, some of which are formed on different layers, wherein an insulating layer is disposed between the different layers.

[0283] In the display device according to the embodiments of this specification, a metal layer may be disposed above multiple data lines.

[0284] In the display device according to the embodiments of this specification, the metal layer may be implemented in an all-metal form throughout the entire link portion.

[0285] In the display device according to the embodiments of this specification, the metal layer may be implemented in the form of multiple islands in the link portion.

[0286] The display device according to the embodiments of this specification may further include spacers overlapping the metal layer.

[0287] In the display device according to the embodiments of this specification, the spacer may be formed to correspond to a metal layer in the form of a strip or multiple islands.

[0288] The display device according to the embodiments of this specification may further include a storage electrode, which includes a first electrode formed on the same layer as the gate electrode of the transistor and a second electrode corresponding to the first electrode, wherein the plurality of data lines may include the first data lines and the second data lines formed of a different material from the first data lines.

[0289] In a display device according to an embodiment of this specification, a first data line may be formed on the same layer as the gate electrode of a transistor.

[0290] In a display device according to an embodiment of this specification, a second data line may be formed on the same layer as the second electrode of the storage electrode.

[0291] In the display device according to the embodiments of this specification, at least one printed circuit film may be attached to the pad portion.

[0292] The display device according to the embodiments of this specification may further include voltage lines and gate control lines electrically connected to the pad portion, wherein the voltage lines may cross the gate control lines or multiple data lines.

[0293] In the display device according to the embodiments of this specification, the substrate may further include a dam and a crack-resistant portion, and the pad portion and the link portion may be disposed between the dam and the crack-resistant portion.

[0294] In a display device according to an embodiment of this specification, the dam may be configured to overlap with the voltage lines and surround the display area.

[0295] In a display device according to an embodiment of this specification, the anti-crack portion may be formed at the outermost edge of the non-display area by recessing at least one insulating layer.

[0296] In the display device according to the embodiments of this specification, the center of the microlens and the center of the light-emitting area may not be aligned.

[0297] In the display device according to the embodiments of this specification, the anode electrode may be tilted toward the microlens.

[0298] In a display device according to an embodiment of this specification, a plurality of sub-pixels may include a first pixel group and a second pixel group, wherein in the first pixel group, the center of the microlens is offset to the other side in a first direction compared to the center of the light-emitting region, and in the second pixel group, the center of the microlens is offset to one side in the first direction compared to the center of the light-emitting region.

[0299] In the display device according to the embodiments of this specification, the non-display area may further include a gate driving unit between the voltage line and the display area.

[0300] The display device according to the embodiments of this specification may further include a pixel gate driving unit located in the display area, wherein the pad portion and the pixel gate driving unit may be electrically connected via a gate control line.

[0301] In a display device according to an embodiment of this specification, the display panel may include a first long side, a second long side, and a first short side and a second short side connecting the first long side to the second long side, and the second long side may be formed to be longer than the first long side.

[0302] The features, structures, effects, etc., described above in the examples of this specification are included in at least one example of this specification, and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc., shown in at least one example of this specification can be implemented by combination or modification by those skilled in the art to which this specification pertains in other examples. Therefore, the content related to such combinations and modifications should be construed as being included within the scope of this specification.

[0303] This specification is not limited to the embodiments and drawings described above, and it will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the technical subject matter of this specification. Therefore, the scope of this specification is determined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as including within the scope of this specification.

[0304] Description of reference numerals in the attached figures

[0305] 1: Display device

[0306] 100: Display panel

[0307] 101: Substrate

[0308] NCP: Notch

[0309] DA: Display Area

[0310] NDA: Non-display area

[0311] NDA1: First Non-Display Area

[0312] NDA2: Second Non-Display Area

[0313] N_NDA: Non-display area of ​​the notch

[0314] E_NDA: Extended non-display area

[0315] PA: Pad area

[0316] LA: Linked Area

[0317] SA: Scratch-resistant area

[0318] SP: Subpixel

[0319] EA: Emitting area

[0320] NEA: Non-luminescent area

[0321] ML: Microlens

[0322] 150: Light-emitting part

[0323] 170: Package section

Claims

1. A display device, comprising: A substrate having a notch and including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; A plurality of transistors are disposed on the substrate and include a gate electrode, a source electrode, and a drain electrode; The display panel includes a light-emitting portion disposed on the plurality of transistors and includes an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode; as well as Microlenses, wherein the microlenses are disposed on the light-emitting area of ​​the sub-pixels. The pad portion and the link portion are located in the non-display area, and Multiple data lines are alternately arranged in the link section, some of which are formed on different layers, with an insulating layer placed between the different layers.

2. The display device according to claim 1, wherein, A metal layer is disposed above the multiple data lines.

3. The display device according to claim 2, wherein, The metal layer is implemented in an all-metal form throughout the entire link section.

4. The display device according to claim 2, wherein, The metal layer is implemented in the form of multiple islands in the link portion.

5. The display device according to claim 2, further comprising a spacer overlapping the metal layer.

6. The display device according to claim 5, wherein, The spacers are formed to correspond to the metal layer, which is in the form of strips or multiple islands.

7. The display device according to claim 1, further comprising a storage electrode, the storage electrode comprising a first electrode formed on the same layer as the gate electrode of the transistor and a second electrode corresponding to the first electrode. in, The plurality of data lines includes a first data line and a second data line formed of a different material than the first data line.

8. The display device according to claim 7, wherein, The first data line is formed on the same layer as the gate electrode of the transistor.

9. The display device according to claim 7, wherein, The second data line is formed on the same layer as the second electrode of the storage electrode.

10. The display device according to claim 1, wherein, At least one printed circuit film is attached to the pad portion.

11. The display device according to claim 1, further comprising a gate control line and a voltage line electrically connected to the pad portion, wherein, The voltage line intersects with the gate control line or the multiple data lines.

12. The display device according to claim 11, wherein, The substrate further includes a dam and a crack-resistant portion, and the pad portion and the link portion are disposed between the dam and the crack-resistant portion.

13. The display device according to claim 12, wherein, The dam overlaps with the voltage line and surrounds the display area.

14. The display device according to claim 12, wherein, The anti-crack portion is formed at the outermost edge of the non-display area by recessing at least one insulating layer.

15. The display device according to claim 1, wherein, The center of the microlens is not aligned with the center of the light-emitting area.

16. The display device according to claim 1, wherein, The anode electrode is tilted toward the microlens.

17. The display device according to claim 1, wherein, The plurality of sub-pixels includes a first pixel group and a second pixel group. In the first pixel group, the center of the microlens is offset to the other side of the first direction compared to the center of the light-emitting region. In the second pixel group, the center of the microlens is offset to one side of the first direction compared to the center of the light-emitting region.

18. The display device according to claim 11, wherein, The non-display area also includes a gate driving unit between the voltage line and the display area.

19. The display device according to claim 11, further comprising a pixel gate driving unit located in the display area, wherein, The pad portion and the pixel gate driving unit are electrically connected via the gate control line.

20. The display device according to claim 1, wherein, The display panel includes a first long side, a second long side, and a first short side and a second short side connecting the first long side to the second long side, wherein the second long side is formed to be longer than the first long side.

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