Array substrate, display panel and display device

Abstract

The invention provides an array substrate which comprises a display area, and the display area comprises a plurality of pixel areas. A substrate, a pixel driving circuit and a scanning signal line; the thin film transistor comprises a grid electrode and a channel layer, and the grid electrode is the overlapped part of the scanning signal line and the channel layer; an auxiliary signal line extending in a first direction; the resistance of the film layer where the auxiliary signal lines are located is smaller than that of the film layer where the scanning signal lines are located, and the auxiliary signal lines are in different layers from the scanning signal lines and electrically connected with the scanning signal lines through line changing via holes. The scanning signal line connected with the grid electrode of the silicon transistor is electrically connected with the auxiliary signal line, so that the voltage drop of the scanning signal transmitted on the scanning signal line connected with the grid electrode of the silicon transistor is reduced. The scanning signal line connected with the grid electrode of the oxide transistor is electrically connected with the auxiliary signal line, so that the voltage drop of the scanning signal transmitted on the scanning signal line connected with the grid electrode of the oxide transistor is reduced.

Description

[0001] This application is a divisional application filed on February 22, 2023, with application number 202310162909.6, and entitled "An array substrate, display panel and display device". Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0003] With the continuous development of science and technology, more and more display devices, such as mobile phones, tablets, laptops, and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience and becoming indispensable tools for people today. The main component of a display device that enables its display function is the display panel.

[0004] In a display panel, the pixel driving circuit provides the driving current required for the display to the light-emitting elements and controls whether the light-emitting elements enter the light-emitting stage, thus becoming an indispensable component in most self-emissive display panels. Summary of the Invention

[0005] This disclosure provides an array substrate, a display panel, and a display device, which reduce the transmission voltage drop of the scanning signal and improve display performance.

[0006] In a first aspect, embodiments of this disclosure provide an array substrate, including a display area, the display area including a plurality of pixel areas;

[0007] The substrate, pixel driving circuit, and scan signal line are located in the display area, on the same side of the substrate, with at least a portion of the pixel driving circuit and the scan signal line extending along a first direction;

[0008] At least a portion of the pixel driving circuit is located in the pixel region, including a thin-film transistor; the thin-film transistor includes a gate and a channel layer, wherein the gate is the portion where the scan signal line overlaps with the channel layer;

[0009] The array substrate further includes auxiliary signal lines, which are located in the display area and extend along the first direction; the resistance of the auxiliary signal lines is less than that of the scan signal lines, they are on a different layer from the scan signal lines, and they are electrically connected to the scan signal lines via a cable replacement via.

[0010] The scan signal lines include first-type scan signal lines and second-type scan signal lines;

[0011] The thin-film transistor includes a silicon transistor and an oxide transistor, wherein the silicon transistor is electrically connected to the first type of scan signal line and the oxide transistor is electrically connected to the second type of scan signal line;

[0012] The auxiliary signal lines include a first type of auxiliary signal lines and a second type of auxiliary signal lines. The first type of scan signal lines are electrically connected to the first type of auxiliary signal lines through the cable switching via, and the second type of scan signal lines are electrically connected to the second type of auxiliary signal lines through the cable switching via.

[0013] The first type of auxiliary signal line and the second type of auxiliary signal line are located on the same layer.

[0014] In a second aspect, embodiments of this disclosure provide a display panel, including the array substrate described in the first aspect, and a plurality of light-emitting elements;

[0015] The light-emitting element is electrically connected to the pixel driving circuit and is configured to emit light under the drive of the pixel driving circuit.

[0016] Thirdly, embodiments of this disclosure provide a display device including the display panel described in the second aspect.

[0017] This disclosure provides an array substrate where the gate control signal lines include scan signal lines and auxiliary signal lines. An auxiliary signal line is provided for the scan signal lines. The resistance of the film layer containing the auxiliary signal line is lower than that of the film layer containing the scan signal lines. The auxiliary signal line is electrically connected to the scan signal lines via a switching via. Therefore, when transmitting the scan signal, the scan signal can be transmitted not only on the scan signal line with higher resistance but also on the auxiliary signal line with lower resistance, reducing the resistance of the gate control signal lines, reducing the transmission voltage drop of the scan signal, and improving display performance. The auxiliary signal line is electrically connected to the scan signal line connected to the gate of a silicon transistor, reducing the voltage drop of the scan signal transmitted on the scan signal line connected to the gate of the silicon transistor. The auxiliary signal line is also electrically connected to the scan signal line connected to the gate of an oxide transistor, reducing the voltage drop of the scan signal transmitted on the scan signal line connected to the gate of the oxide transistor. Attached Figure Description

[0018] Figure 1 This is a top view of an array substrate provided in an embodiment of the present disclosure;

[0019] Figure 2 A schematic diagram of the circuit structure of a pixel driving circuit provided in an embodiment of this disclosure;

[0020] Figure 3 A top view of a pixel driving circuit provided in an embodiment of this disclosure;

[0021] Figure 4 A cross-sectional structural schematic diagram of a pixel driving circuit provided in an embodiment of this disclosure;

[0022] Figure 5 for Figure 3 A partial structural schematic diagram of the pixel driving circuit shown in the figure;

[0023] Figure 6 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0024] Figure 7 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0025] Figure 8 for Figure 3 The diagram shows a pixel driving circuit forming an array.

[0026] Figure 9 for Figure 8 A partial structural schematic diagram of the pixel driving circuit shown in the figure;

[0027] Figure 10 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0028] Figure 11 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0029] Figure 12 A top view schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure;

[0030] Figure 13 for Figure 12 A partial structural schematic diagram of the pixel driving circuit shown in the figure;

[0031] Figure 14 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0032] Figure 15 A top view schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure;

[0033] Figure 16 for Figure 15 A partial structural schematic diagram of the pixel driving circuit shown in the figure;

[0034] Figure 17 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0035] Figure 18 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0036] Figure 19 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0037] Figure 20 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0038] Figure 21 A top view schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure;

[0039] Figure 22 for Figure 3 A partial structural schematic diagram of the pixel driving circuit shown in the figure;

[0040] Figure 23 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0041] Figure 24 A top view of another array substrate provided in an embodiment of this disclosure;

[0042] Figure 25 for Figure 3 A partial structural schematic diagram of the pixel driving circuit shown in the figure;

[0043] Figure 26 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0044] Figure 27 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0045] Figure 28 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure;

[0046] Figure 29 A cross-sectional structural diagram of a display panel provided in an embodiment of this disclosure;

[0047] Figure 30 This is a schematic diagram of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0048] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present disclosure and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the drawings, not the entire structure.

[0049] Figure 1This is a top view schematic diagram of an array substrate provided in an embodiment of the present disclosure. Figure 2 This is a schematic diagram of the circuit structure of a pixel driving circuit provided in an embodiment of the present disclosure. Figure 3 This is a top view schematic diagram of a pixel driving circuit provided in an embodiment of the present disclosure. Figure 4 This is a cross-sectional structural diagram of a pixel driving circuit provided in an embodiment of the present disclosure. Figure 5 for Figure 3 The schematic diagram of a partial structure of the pixel driving circuit shown is for reference. Figures 1-5 The array substrate includes a display area 101, which includes a plurality of pixel areas P. In the display area 101, the plurality of pixel areas P are arranged in rows and columns along a first direction X and a second direction Y. This disclosure does not limit the arrangement of the pixel areas P.

[0050] The array substrate includes a substrate 10, a pixel driving circuit 20, and a gate control signal line 30. The gate control signal line 30 is configured to provide a scan signal to the pixel driving circuit 20 for controlling the thin-film transistors of the pixel driving circuit 20 to be turned on or off.

[0051] In known technologies, the gate control signal line 30 is the same as the scan signal line 31, and the film layer where the scan signal line 31 is located has a relatively high resistance.

[0052] In this disclosure, the gate control signal line 30 includes a scan signal line 31 and an auxiliary signal line 32. At least a portion of the pixel driving circuit 20 and the scan signal line 31 are located in the display area 101. The scan signal line 31 may be located in the display area 101, or it may extend from within the display area 101 to outside the display area 101. The pixel driving circuit 20 and the scan signal line 31 are located on the same side of the substrate 10. The scan signal line 31 extends along a first direction X. At least a portion of the pixel driving circuit 20 is located in the pixel area P, and the pixel driving circuit 20 includes a thin-film transistor 21. The thin-film transistor 21 includes a gate 201 and a channel layer 202, wherein the gate 201 is the portion where the scan signal line 31 overlaps with the channel layer 202. The auxiliary signal line 32 is located in the display area 101 and extends along the first direction X. The resistance of the auxiliary signal line 32 is less than that of the scan signal line 31. The auxiliary signal line 32 and the scan signal line 31 are on different layers and are electrically connected through the cable switching via 51.

[0053] An array substrate provided in this embodiment includes a gate control signal line 30 comprising a scan signal line 31 and an auxiliary signal line 32. An auxiliary signal line 32 is provided for the scan signal line 31. The resistance of the auxiliary signal line 32 is less than that of the scan signal line 31. The auxiliary signal line 32 is electrically connected to the scan signal line 31 via a switching via 51. Therefore, when transmitting the scan signal, the scan signal can be transmitted not only on the scan signal line 31 with higher resistance but also on the auxiliary signal line 32 with lower resistance. This reduces the resistance of the gate control signal line 30, reduces the transmission voltage drop of the scan signal, and improves display performance.

[0054] For example, refer to Figure 2 The pixel driving circuit 20 includes a power writing transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a first reset transistor T5, a light emission control transistor T6, a second reset transistor T7, an adjustment transistor T8, and a storage capacitor C. The first terminal of the power writing transistor T1 is electrically connected to the first power line VDD, the second terminal of the power writing transistor T1 is electrically connected to the second node N2, and the gate of the power writing transistor T1 is electrically connected to the light emission control signal line EM. The first terminal of the data writing transistor T2 is electrically connected to the data line VDATA, the second terminal of the data writing transistor T2 is electrically connected to the second node N2, and the gate of the data writing transistor T2 is electrically connected to the data control signal line SCP1. The first terminal of the driving transistor T3 is electrically connected to the second node N2, the second terminal of the driving transistor T3 is electrically connected to the third node N3, and the gate of the driving transistor T3 is electrically connected to the first node N1. The first terminal of the compensation transistor T4 is electrically connected to the first node N1, the second terminal of the compensation transistor T4 is electrically connected to the third node N3, and the gate of the compensation transistor T4 is electrically connected to the second scan line SN2. The first terminal of the first reset transistor T5 is electrically connected to the first reset signal transmission line VREF1, the second terminal of the first reset transistor T5 is electrically connected to the first node N1, and the gate of the first reset transistor T5 is electrically connected to the first scan line SN1. The first terminal of the light-emitting control transistor T6 is electrically connected to the third node N3, the second terminal of the light-emitting control transistor T6 is electrically connected to the fourth node N4, and the gate of the light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM. The first terminal of the second reset transistor T7 is electrically connected to the second reset signal transmission line VREF2, the second terminal of the second reset transistor T7 is electrically connected to the fourth node N4, and the gate of the second reset transistor T7 is electrically connected to the anode reset control signal line SCP2. The first terminal of the regulating transistor T8 is electrically connected to the regulating signal transmission line DVH, the second terminal of the regulating transistor T8 is electrically connected to the second node N2, and the gate of the regulating transistor T8 is electrically connected to the regulating control signal line SCP3. The first plate C1 of the storage capacitor C is electrically connected to the first node N1, and the second plate C2 of the storage capacitor C is electrically connected to the first power supply line VDD.

[0055] Among them, the first node N1, the second node N2, the third node N3, and the fourth node N4 can be virtual connection nodes or actual connection nodes.

[0056] It should be noted that, as Figure 2 The circuit diagram shown is only an example and is not intended to limit the scope of this disclosure. In other embodiments, pixel driving circuits 20 with other circuit structures may also be used.

[0057] For example, refer to Figure 2 The gate control signal line 30 includes a scan signal line 31, which includes a light emission control signal line EM, a first scan line SN1, a second scan line SN2, a data control signal line SCP1, an anode reset control signal line SCP2, and an adjustment control signal line SCP3.

[0058] For example, refer to Figure 4 The array substrate includes a silicon semiconductor layer POLY, a first metal layer M1, a first sub-gate metal layer MC, an oxide semiconductor layer IGZO, a second sub-gate metal layer MG, a second metal layer M2, and a third metal layer M3, which are stacked sequentially. The silicon semiconductor layer POLY is located between the substrate 10 and the first metal layer M1. The silicon semiconductor layer POLY comprises silicon. The oxide semiconductor layer IGZO comprises an oxide semiconductor material.

[0059] Multiple thin-film transistors 21 include silicon transistors 211 and oxide transistors 212. Silicon transistor 211 includes a gate 201, a channel layer 202, a source 203, and a drain 204. The gate 201 of silicon transistor 211 is located in a first metal layer M1, the channel layer 202 is located in a silicon semiconductor layer POLY, and the source 203 and drain 204 are both located in a second metal layer M2. A scan signal line 31 electrically connected to the gate 201 of silicon transistor 211 is located in the first metal layer M1. Oxide transistor 212 includes a gate 201, a channel layer 202, a source 203, and a drain 204. The gate 201 of oxide transistor 212 includes a first sub-gate 2011 and a second sub-gate 2012. Perpendicular to the substrate 10, the first sub-gate 2011 is located between the channel layer 202 and the substrate 10, and the second sub-gate 2012 is located on the side of the channel layer 202 away from the substrate 10. The channel layer 202 of the oxide transistor 212 is located in the oxide semiconductor layer IGZO. The source 203 and drain 204 of the oxide transistor 212 are both located in the second metal layer M2. The scan signal line 31, which is electrically connected to the gate 201 of the oxide transistor 212, is located in the first sub-gate metal layer MC or the second sub-gate metal layer MG.

[0060] For example, refer to Figures 2-4The power supply transistor T1, data write transistor T2, drive transistor T3, light-emitting control transistor T6, second reset transistor T7, and regulating transistor T8 are silicon transistors 211. The compensation transistor T4 and the first reset transistor T5 are oxide transistors 212. Since both the compensation transistor T4 and the first reset transistor T5 are connected to the first node N1, setting the compensation transistor T4 and the first reset transistor T5 as oxide transistors 212 can reduce the leakage current to the first node N1.

[0061] For example, refer to Figures 2-4 The first scan line SN1 includes a first sub-scan line SN11 and a second sub-scan line SN12. The second scan line SN2 includes a third sub-scan line SN21 and a fourth sub-scan line SN22. The data control signal line SCP1, the light emission control signal line EM, the anode reset control signal line SCP2, and the adjustment control signal line SCP3 are all located in the first metal layer M1. The first sub-scan line SN11 and the third sub-scan line SN21 are both located in the first sub-gate metal layer MC. The second sub-scan line SN12 and the fourth sub-scan line SN22 are both located in the second sub-gate metal layer MG.

[0062] Optionally, refer to Figures 3-5 The auxiliary signal line 32 is located on the side of the scanning signal line 31 that is furthest from the substrate 10. The auxiliary signal line 32 can be fabricated using the existing metal layer of the second sub-gate metal layer MG on the side furthest from the substrate 10, thus eliminating the need for additional metal layers.

[0063] Optionally, refer to Figures 3-5 The thin-film transistor 21 includes a source 203 and a drain 204. The auxiliary signal line 31, source 203, and drain 204 are on the same layer. This allows the same materials to be used and the auxiliary signal line 31, source 203, and drain 204 to be formed in the same process, saving on fabrication steps. The auxiliary signal line 31 is located in the second metal layer M2, which has a lower resistance, reducing the voltage drop across the scan signal.

[0064] Optionally, refer to Figures 3-5 Along the first direction, the length of the scan signal line 31 is less than the length of the auxiliary signal line 32. The resistance of the scan signal line 31 is relatively large, while the resistance of the auxiliary signal line 32 is relatively small. Therefore, setting a larger length for the auxiliary signal line 32 with lower resistance and a smaller length for the scan signal line 31 with higher resistance helps to reduce the resistance of the gate control signal line 30 formed by the electrical connection of the scan signal line 31 and the auxiliary signal line 32, thereby reducing the transmission voltage drop of the scan signal.

[0065] Optionally, refer to Figures 3-5In a direction perpendicular to the substrate 10, the scan signal line 31 and the auxiliary signal line 32 overlap in the area outside the region where the switching via 51 is located. Both the scan signal line 31 and the auxiliary signal line 32 overlap with the switching via 51. Thus, the light-shielding area of ​​the scan signal line 31 overlaps with the light-shielding area of ​​the auxiliary signal line 32, reducing the shared light-shielding area of ​​the scan signal line 31 and the auxiliary signal line 32, and increasing the light transmittance.

[0066] For example, refer to Figures 3-5 In thin-film transistor 21 (e.g. Figure 5 In the region where the second reset transistor T7 and the regulating transistor T8 are located, perpendicular to the substrate 10, the scan signal line 31 overlaps with the auxiliary signal line 32. If the scan signal line 31 and the auxiliary signal line 32 are misaligned in the region where the thin-film transistor 21 is located, a slope will be formed at the edge of the scan signal line 31 after its formation (understandably, the film thickness at the location where the scan signal line 31 is formed is greater than the film thickness at the location where the scan signal line 31 is not formed). During the formation of the auxiliary signal line 32, the second metal layer M2 where the auxiliary signal line 32 is located becomes uneven. Therefore, the overlap of the scan signal line 31 and the auxiliary signal line 32 can also increase the flatness of the second metal layer M2 where the auxiliary signal line 32 is located.

[0067] Optionally, refer to Figure 1 , Figure 3 and Figure 5 Multiple collinear scan signal lines 31 are electrically connected to the same auxiliary signal line 32. These collinear scan signal lines 31 are arranged along the first direction X and electrically connected to the same auxiliary signal line 32 through a crossover via 51. The auxiliary signal line 32 is a single straight segment with a relatively large length. This longer length is chosen for the auxiliary signal line 32, which has lower resistance, to reduce the voltage drop during scan signal transmission.

[0068] For example, along the first direction X, multiple scan signal lines 31 are collinear with an auxiliary signal line 32.

[0069] Figure 6 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 6 The ends of the scan signal lines 31 and 32 are electrically connected. Along the first direction X, the scan signal lines 31 and 32 are arranged at intervals, with an auxiliary signal line 32 positioned between adjacent scan signal lines 31. Adjacent scan signal lines 31 are electrically connected via the auxiliary signal line 32 between them.

[0070] For example, along the first direction X, multiple scan signal lines 31 and multiple auxiliary signal lines 32 are collinear. A scan signal line 31 is provided between two adjacent auxiliary signal lines 32.

[0071] Optionally, continue to refer to Figure 3 and Figure 5 The collinear multiple scan signal lines 31 include a first scan signal line 311 and a second scan signal line 312 spaced apart, and the first scan signal line 311 and the second scan signal line 312 are located in the same pixel area P. In this embodiment of the present disclosure, in the same pixel area P, the two collinear scan signal lines 31 are spaced apart by a certain distance, and the two collinear scan signal lines 31 are set separately, independently, and disconnected.

[0072] Optionally, continue to refer to Figure 2 , Figure 3 and Figure 5 The thin-film transistor 21 includes a driving transistor T3 for providing driving current to the light-emitting element LD. A first scan signal line 311 is configured to control the thin-film transistor 21 (specifically, the second reset transistor T7) to transmit a reset signal to the anode of the light-emitting element LD. A second scan signal line 312 is configured to control the thin-film transistor 21 (specifically, the regulating transistor T8) to transmit an regulating signal to the first terminal of the driving transistor T3. In this embodiment, the first scan signal line 311 includes an anode reset control signal line SCP2, and the second scan signal line 312 includes a regulating control signal line SCP3. The first scan signal line 311 and the second scan signal line 312 are collinear and electrically connected to the same auxiliary signal line 32. Therefore, the anode reset control signal line SCP2 is multiplexed as the regulating control signal line SCP3. The second reset transistor T7 and the regulating transistor T8 share the same gate control signal line 30.

[0073] For example, refer to Figures 3-5 The first scan signal line 311 includes an anode reset control signal line SCP2, and the position where the anode reset control signal line SCP2 overlaps with the channel layer 202 forms the gate of the second reset transistor T7. The second scan signal line 312 includes an adjustment control signal line SCP3, and the position where the adjustment control signal line SCP3 overlaps with the channel layer 202 forms the gate of the adjustment transistor T8. The gates of the second reset transistor T7 and the adjustment transistor T8 are on the same layer, collinear, and disconnected; that is, the gates of the second reset transistor T7 and the adjustment transistor T8 are not connected together by metal of the same layer.

[0074] Figure 7 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 4 and Figure 7 The scan signal line 31 includes a first signal line segment 331 and a second signal line segment 332 connected to each other. The first signal line segment 331 and the second signal line segment 332 are located in the same pixel region P. The first signal line segment 331 and the second signal line segment 332 each include a gate 201. In this embodiment of the present disclosure, in the same pixel region P, the first signal line segment 331 and the second signal line segment 332 are different parts of the same scan signal line 31, and the same scan signal line 31 overlaps with at least two channel layers 202 to form at least two gates 201.

[0075] For example, refer to Figure 3 , Figure 4 and Figure 7 The scan signal line 31 includes a first signal segment 331 and a second signal segment 332, which are different parts of the same scan signal line 31. The first signal segment 331 includes an anode reset control signal line SCP2, and the position where the anode reset control signal line SCP2 overlaps with the channel layer 202 forms the gate of the second reset transistor T7. The second signal segment 332 includes an adjustment control signal line SCP3, and the position where the adjustment control signal line SCP3 overlaps with the channel layer 202 forms the gate of the adjustment transistor T8. The gates of the second reset transistor T7 and the adjustment transistor T8 are on the same layer and connected together; that is, the gates of the second reset transistor T7 and the adjustment transistor T8 are connected together by metal of the same layer.

[0076] Figure 8 for Figure 3 The diagram shows a pixel driving circuit forming an array. Figure 9 for Figure 8 The schematic diagram of a partial structure of the pixel driving circuit shown is for reference. Figure 8 and Figure 9 The plurality of pixel regions P includes a first pixel region P1 and a second pixel region P2 arranged adjacent to each other along a first direction X. Multiple collinear scan signal lines 31 include a third scan signal line 313 and a fourth scan signal line 314 arranged at intervals. The third scan signal line 313 is located in the first pixel region P1, and the fourth scan signal line 314 is located in the second pixel region P2. In this embodiment, the third scan signal line 313 in the first pixel region P1 and the fourth scan signal line 314 in the second pixel region P2 are collinear, and are arranged at a certain distance from each other. The collinear scan signal lines 31 in adjacent pixel regions P are arranged discretely, independently, and disconnected.

[0077] For example, refer to Figure 8and Figure 9 Both the third scan signal line 313 and the fourth scan signal line 314 include an adjustment control signal line SCP3. The position where the adjustment control signal line SCP3 overlaps with the channel layer 202 forms the gate of the adjustment transistor T8. The gate of the adjustment transistor T8 in the first pixel region P1 is disconnected from the gate of the adjustment transistor T8 in the second pixel region P2.

[0078] For example, refer to Figure 9 In the first pixel region P1, the gate of the second reset transistor T7 is disconnected from the gate of the adjustment transistor T8. In the second pixel region P2, the gate of the second reset transistor T7 is disconnected from the gate of the adjustment transistor T8. The gate of the adjustment transistor T8 in the first pixel region P1 is disconnected from the gate of the adjustment transistor T8 in the second pixel region P2.

[0079] Figure 10 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 10 In the first pixel region P1, the gate of the second reset transistor T7 is connected to the gate of the adjustment transistor T8. In the second pixel region P2, the gate of the second reset transistor T7 is connected to the gate of the adjustment transistor T8. The gate of the adjustment transistor T8 in the first pixel region P1 is disconnected from the gate of the adjustment transistor T8 in the second pixel region P2.

[0080] Figure 11 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 11 The plurality of pixel regions P includes a first pixel region P1 and a second pixel region P2 disposed adjacently along a first direction X. The scan signal line 31 includes a third signal segment 333 and a fourth signal segment 334 connected to each other. The third signal segment 333 is located in the first pixel region P1 and includes a gate 201. The fourth signal segment 334 is located in the second pixel region P2 and includes a gate 201. In this embodiment, the third signal segment 333 and the fourth signal segment 334 are different portions of the same scan signal line 31, which is located in the first pixel region P1 and the second pixel region P2, and overlaps with at least two channel layers 202 in the first pixel region P1 and the second pixel region P2 to form at least two gates 201.

[0081] For example, refer to Figure 11The scan signal line 31 includes a third signal line segment 333 and a fourth signal line segment 334 connected together. The third signal line segment 333 includes an adjustment control signal line SCP3. The position where the third signal line segment 333 overlaps with the channel layer 202 in the first pixel region P1 forms the gate 201 of the adjustment transistor T8 in the first pixel region P1. The fourth signal line segment 334 includes the adjustment control signal line SCP3. The position where the fourth signal line segment 334 overlaps with the channel layer 202 in the second pixel region P2 forms the gate 201 of the adjustment transistor T8 in the second pixel region P2. The gate 201 of the adjustment transistor T8 in the first pixel region P1 and the gate 201 of the adjustment transistor T8 in the second pixel region P2 are connected together.

[0082] It should be further explained that if the gate 201 of the regulating transistor T8 in the first pixel region P1 is disconnected from the gate 201 of the regulating transistor T8 in the second pixel region P2, the distance between the channel layers 202 in the first pixel region P1 and the second pixel region P2 is relatively small. The scan signal line 31 formed on the silicon semiconductor layer POLY (specifically the channel layer 202) needs to completely overlap with the channel layer 202. That is, the edge of the scan signal line 31 cannot overlap with the silicon semiconductor layer POLY, but needs to extend beyond the channel layer 202 by a certain distance in the first direction X. This margin design is used to prevent the scan signal line 31 from shifting relative to the channel layer 202 due to process variations. If the gate 201 of the regulating transistor T8 in the first pixel region P1 is connected to the gate 201 of the regulating transistor T8 in the second pixel region P2, there is no need to reserve space for process variations, reducing process difficulty and decreasing the space occupied by a single pixel region P, thereby increasing pixel density.

[0083] Figure 12 This is a top view schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure. Figure 13 for Figure 12 The schematic diagram of a partial structure of the pixel driving circuit shown is for reference. Figure 12 and Figure 13The multiple auxiliary signal lines 32 include a first auxiliary signal line 321 and a second auxiliary signal line 322 arranged along a second direction Y, which intersects with the first direction X. The thin-film transistor 21 includes a driving transistor T3 for providing driving current to the light-emitting element LD. The multiple scan signal lines 31 include a first scan signal line 311 and a second scan signal line 312. The first scan signal line 311 is configured to control the thin-film transistor 21 (specifically, the second reset transistor T7) to transmit a reset signal to the anode of the light-emitting element LD. The second scan signal line 312 is configured to control the thin-film transistor 21 (specifically, the adjustment transistor T8) to transmit an adjustment signal to the first electrode of the driving transistor T3. The first scan signal line 311 is electrically connected to the first auxiliary signal line 321, and the second scan signal line 312 is electrically connected to the second auxiliary signal line 322. In this embodiment, the first scan signal line 311 and the second scan signal line 312 are not collinear and are arranged along the second direction Y. Therefore, the second reset transistor T7 and the regulating transistor T8 are respectively connected to two different gate control signal lines 30.

[0084] Figure 14 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 14 The end of the scan signal line 31 is electrically connected to the end of the auxiliary signal line 32. The gate of the second reset transistor T7 in the first pixel area P1 is disconnected from the gate of the second reset transistor T7 in the second pixel area P2. The end of the first scan signal line 311 in the first pixel area P1 is electrically connected to the first end of the first auxiliary signal line 321, and the end of the first scan signal line 311 in the second pixel area P2 is electrically connected to the second end of the first auxiliary signal line 321. The gate of the adjustment transistor T8 in the first pixel area P1 is disconnected from the gate of the adjustment transistor T8 in the second pixel area P2. The end of the second scan signal line 312 in the first pixel area P1 is electrically connected to the first end of the second auxiliary signal line 322, and the end of the second scan signal line 312 in the second pixel area P2 is electrically connected to the second end of the second auxiliary signal line 322.

[0085] Optionally, refer to Figures 3-5The pixel driving circuit 20 also includes a storage capacitor C. The vertical projection of the auxiliary signal line 32 onto the substrate 10 and the vertical projection of the storage capacitor C onto the substrate 10 are arranged along a second direction Y, which intersects the first direction X. Along the second direction Y, the auxiliary signal line 32 is located on one side of the storage capacitor C. Perpendicular to the substrate 10, the auxiliary signal line 32 and the storage capacitor C do not overlap. In this embodiment, the auxiliary signal line 32 is a line extending along the first direction X, not a light-shielding metal layer. A light-shielding metal layer typically does not avoid the storage capacitor C. In this embodiment, the auxiliary signal line 32 is offset from the storage capacitor C, not for light-shielding purposes, but rather designed to increase transmittance and reduce the transmission voltage drop of the scan signal. Multiple auxiliary signal lines 32 arranged along the second direction Y can be provided within a pixel region P to reduce the transmission voltage drop of the scan signal transmitted on multiple scan signal lines 31.

[0086] Optionally, refer to Figure 3 , Figure 5 , Figure 12 and Figure 13 The multiple scanning signal lines 31 include an anode reset control signal line SCP2 and an adjustment control signal line SCP3. Along the second direction Y, the anode reset control signal line SCP2 and the adjustment control signal line SCP3 are located on the same side of the storage capacitor C. The auxiliary signal line 32 electrically connected to the anode reset control signal line SCP2 is a straight segment, and the auxiliary signal line 32 electrically connected to the adjustment control signal line SCP3 is also a straight segment. Compared to bent or curved segments, straight segments have a simpler structure, are less prone to over-etching problems, and reduce the difficulty of the manufacturing process.

[0087] For example, refer to Figure 3 , Figure 5 , Figure 12 and Figure 13 Both the anode reset control signal line SCP2 and the regulation control signal line SCP3 are located between the fourth node N4 and the regulation signal transmission line DVH. There are no other lines or holes in the second metal layer M2 between the fourth node N4 and the regulation signal transmission line DVH; therefore, the auxiliary signal line 32 electrically connected to the anode reset control signal line SCP2 and the auxiliary signal line 32 electrically connected to the regulation control signal line SCP3 do not need to be bent or folded for avoidance.

[0088] For example, refer to Figure 12 and Figure 13 Both the first auxiliary signal line 321 and the second auxiliary signal line 322 are straight segments.

[0089] Optionally, refer to Figure 3 , Figure 5 , Figure 12 and Figure 13The scan signal line 31 includes a data control signal line SCP1, which is configured to control the thin-film transistor 21 (specifically, the data writing transistor T2) to transmit data signals to the first electrode of the driving transistor T3. The array substrate also includes a data line VDATA and a data line via 52. The data line VDATA is connected to the semiconductor trace 60 in a different layer via the data line via 52. The channel layer 202 is the portion where the semiconductor trace 60 overlaps with the gate 201. The portion of the semiconductor trace 60 that does not overlap with the gate 201 is used as a connection line. Typically, the conductivity of the portion of the semiconductor trace 60 that does not overlap with the gate 201 is improved by doping. Along the second direction Y, the data control signal line SCP1 is located on the side of the storage capacitor C away from the anode reset control signal line SCP2. At least one scan signal line 31 is spaced between the data control signal line SCP1 and the data line via 52. The data control signal line SCP1 is far from the data line via 52, eliminating the need for bending or skewing to avoid it. The auxiliary signal line 32, which is electrically connected to the data control signal line SCP1, is a straight segment.

[0090] For example, refer to Figure 3 , Figure 5 , Figure 12 and Figure 13 Along the second direction Y, the first scan line SN1 is located between the data control signal line SCP1 and the data line via 52. The data control signal line SCP1 and the data line via 52 are relatively far apart.

[0091] Optionally, refer to Figure 3 and Figure 12 The array substrate also includes a modulation signal transmission line DVH for transmitting modulation signals, which extends along a first direction X. The film layer containing the modulation signal transmission line DVH is located between the film layer containing the modulation control signal line SCP3 and the film layer containing the auxiliary signal line 32. The vertical projection of the modulation control signal line SCP3 onto the substrate 10 is offset from the vertical projection of the modulation signal transmission line DVH onto the substrate 10. Perpendicular to the substrate 10, the modulation control signal line SCP3 and the modulation signal transmission line DVH do not overlap. Therefore, the modulation signal transmission line DVH, located between the film layer containing the modulation control signal line SCP3 and the film layer containing the auxiliary signal line 32, will not overlap with the via 51 connecting the modulation control signal line SCP3 to the auxiliary signal line 32, thus avoiding unwanted electrical connections between the modulation signal transmission line DVH and the modulation control signal line SCP3.

[0092] For example, refer to Figure 3 , Figure 4 and Figure 12The adjustment signal transmission line DVH is located in the second sub-gate metal layer MG, the adjustment control signal line SCP3 is located in the first metal layer M1, and the auxiliary signal line 32 is located in the second metal layer M2. The second sub-gate metal layer MG is located between the first metal layer M1 and the second metal layer M2. If the adjustment signal transmission line DVH and the adjustment control signal line SCP3 are overlapped, the via 51 connecting the second metal layer M2 to the first metal layer M1 will be electrically connected to the adjustment signal transmission line DVH, causing the adjustment signal transmission line DVH to be electrically connected to the adjustment control signal line SCP3, resulting in the pixel driving circuit 20 malfunctioning.

[0093] Figure 15 This is a top view schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure. Figure 16 for Figure 15 The schematic diagram of a partial structure of the pixel driving circuit shown is for reference. Figure 4 , Figure 15 and Figure 16 The scan signal line 31 includes a first sub-signal line 3101 and a second sub-signal line 3102. The gate 201 includes a first sub-gate 2011 and a second sub-gate 2012. Perpendicular to the substrate 10, the first sub-gate 2011 is located between the channel layer 202 (specifically, the channel layer 202 in the IGZO oxide semiconductor layer) and the substrate 10, and the second sub-gate 2012 is located on the side of the channel layer 202 (specifically, the channel layer 202 in the IGZO oxide semiconductor layer) away from the substrate 10. The first sub-gate 2011 is the overlapping portion of the first sub-signal line 3101 and the channel layer 202, and the second sub-gate 2012 is the overlapping portion of the second sub-signal line 3102 and the channel layer 202. The first sub-signal line 3101 and / or the second sub-signal line 3102 are electrically connected to the auxiliary signal line 32 via a switching via 51.

[0094] For example, refer to Figure 15 and Figure 16 The scan signal line 31 includes a first scan line SN1. The first scan line SN1 includes a first sub-scan line SN11 and a second sub-scan line SN12. The first sub-scan line SN11 is a first sub-signal line 3101, and the second sub-scan line SN12 is a second sub-signal line 3102. The first sub-scan line SN11 and the second scan line SN12 are electrically connected to two auxiliary signal lines 32 through two cable switching vias 51, respectively.

[0095] Understandably, an auxiliary signal line 32 is electrically connected to the scan signal line 31 connected to the gate of the silicon transistor 211 to reduce the voltage drop of the scan signal transmitted on the scan signal line 31 connected to the gate of the silicon transistor 211. Similarly, an auxiliary signal line 32 is electrically connected to the scan signal line 31 connected to the gate of the oxide transistor 212 to reduce the voltage drop of the scan signal transmitted on the scan signal line 31 connected to the gate of the oxide transistor 212. This reduces the difference between the voltage drop of the scan signal from the silicon transistor 211 and the voltage drop of the scan signal from the oxide transistor 212.

[0096] Figure 17 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 17 In this embodiment, the first sub-scan line SN11 is the first sub-signal line 3101, and the second sub-scan line SN12 is the second sub-signal line 3102. The first sub-scan line SN11 is electrically connected to the auxiliary signal line 32 through a cable switching via 51. The second sub-scan line SN12 is not electrically connected to the auxiliary signal line 32. In other embodiments, the second sub-scan line SN12 is electrically connected to the auxiliary signal line 32 through the cable switching via 51, and the first sub-scan line SN11 is not electrically connected to the auxiliary signal line 32.

[0097] Figure 18 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 18 The first sub-signal line 3101 and the second sub-signal line 3102 are electrically connected to the same auxiliary signal line 32.

[0098] For example, refer to Figure 18 The first sub-scan line SN11 is electrically connected to the auxiliary signal line 32 through the line switching via 51, and the second sub-scan line SN12 is electrically connected to the auxiliary signal line 32 through the line switching via 51. The first sub-scan line SN11 and the second sub-scan line SN12 are electrically connected to the same auxiliary signal line 32.

[0099] Continue to refer to Figure 16The auxiliary signal line 20 includes a first sub-auxiliary signal line 3201 and a second sub-auxiliary signal line 3202 spaced apart. The first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are arranged along a second direction Y. The switching via 51 includes a first switching via 511 and a second switching via 512. The first sub-signal line 3101 is electrically connected to the first sub-auxiliary signal line 3201 via the first switching via 511, and the second sub-signal line 3102 is electrically connected to the second sub-auxiliary signal line 3202 via the second switching via 512. The vertical projection of the first switching via 511 onto the substrate 10 is offset from the vertical projection of the second switching via 512 onto the substrate 10. Perpendicular to the substrate 10, the first line-changing via 511 and the second line-changing via 512 do not overlap, and are spaced apart. The first line-changing via 511 and the second line-changing via 512 are not electrically connected within the display area 101, thereby ensuring that the first sub-signal line 3101 and the second sub-signal line 3102 are not electrically connected within the display area 101.

[0100] For example, refer to Figure 16 The first sub-scan line SN11 is electrically connected to the first sub-auxiliary signal line 3201 through the first line-changing via 511, and the second sub-scan line SN12 is electrically connected to the second sub-auxiliary signal line 3202 through the second line-changing via 512. Perpendicular to the substrate 10, the first line-changing via 511 and the second line-changing via 512 do not overlap, and the first sub-scan line SN11 and the second sub-scan line SN12 are not electrically connected within the display area 101.

[0101] Figure 19 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 15 and Figure 19The array substrate also includes a data line VDATA and a data line via 52. The data line VDATA is connected to the semiconductor trace 60 of a different layer via the data line via 52. The channel layer 202 is the portion where the semiconductor trace 60 overlaps with the gate 201. The array substrate also includes a reset signal transmission line VREF for transmitting a reset signal, which extends along a first direction X. An auxiliary signal line 32 electrically connected to the first sub-signal line 3101 or the second sub-signal line 3102 is a third auxiliary signal line 323. Along a second direction Y, the third auxiliary signal line 323 is located between the reset signal transmission line VREF and the data line via 52. The third auxiliary signal line 323 includes a first auxiliary signal segment 3231, a second auxiliary signal segment 3232, and a third auxiliary signal segment 3233, with the second auxiliary signal segment 3232 connecting the first auxiliary signal segment 3231 and the third auxiliary signal segment 3233. Along the second direction Y, the second auxiliary signal segment 3232 is located on the side of the cable switching via 51 away from the data cable via 52. Along the second direction Y, the cable switching via 51 is located between the second auxiliary signal segment 3232 and the data cable via 52. The second auxiliary signal segment 3232 is the portion of the third auxiliary signal line 323 that protrudes towards the side away from the data cable via 52. In this embodiment, because the third auxiliary signal line 323 is adjacent to the data cable via 52, and the distance between the third auxiliary signal line 323 and the data cable via 52 is relatively short, the third auxiliary signal line 323 is bent or kinked to avoid the data cable via 52.

[0102] For example, refer to Figure 15 and Figure 19 Along the second direction Y, the first scan line SN1 is located between the reset signal transmission line VREF (specifically, the first reset signal transmission line VREF1) and the data line via 52. The first sub-scan line SN11 is the first sub-signal line 3101, and the second sub-scan line SN12 is the second sub-signal line 3102. The first sub-scan line SN11 is electrically connected to the first sub-auxiliary signal line 3201 through the first cable switching via 511. The second sub-scan line SN12 is electrically connected to the second sub-auxiliary signal line 3202 through the second cable switching via 512. Both the first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are bent third auxiliary signal lines 323. Both the first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are wound around the data line via 52.

[0103] Figure 20 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 15 and Figure 20The scan signal line 31 includes a data control signal line SCP1, which is configured to control the thin-film transistor 21 to transmit data signals to the first terminal of the driving transistor T3. The pixel driving circuit 20 also includes a storage capacitor C. Along the second direction Y, a third auxiliary signal line 323 is located between the storage capacitor C and the data control signal line SCP1. The third auxiliary signal line 323 is a straight line segment. Compared with bent or curved lines, straight lines have a simpler structure, are less prone to over-etching problems, and reduce the difficulty of the manufacturing process.

[0104] For example, refer to Figure 15 and Figure 20 Along the second direction Y, the second scan line SN2 is located between the storage capacitor C and the data control signal line SCP1. The third sub-scan line SN21 is the first sub-signal line 3101, and the fourth sub-scan line SN22 is the second sub-signal line 3102. The third sub-scan line SN21 is electrically connected to the first sub-auxiliary signal line 3201 through the first cable switching via 511. The fourth sub-scan line SN22 is electrically connected to the second sub-auxiliary signal line 3202 through the second cable switching via 512. Both the first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are straight lines 323 without bending. Both the first sub-auxiliary signal line 3201 and the second sub-auxiliary signal line 3202 are straight segments.

[0105] Optionally, refer to Figure 3 , Figure 12 or Figure 15 The array substrate also includes a reset signal transmission line VREF and a reset signal auxiliary transmission line VREF'. The reset signal transmission line VREF is configured to transmit a reset signal. VREF extends along a first direction X, and is on a different layer than the reset signal auxiliary transmission line VREF'. VREF and VREF' are electrically connected via a connecting via 53. Perpendicular to the substrate 10, the reset signal auxiliary transmission line VREF' overlaps with a switching via 51. Thus, the light-shielding area of ​​the switching via 51 overlaps with the light-shielding area of ​​the reset signal auxiliary transmission line VREF', reducing the shared light-shielding area of ​​the switching via 51 and the reset signal auxiliary transmission line VREF', thereby increasing light transmittance.

[0106] For example, refer to Figure 3The reset signal transmission line VREF includes a first reset signal transmission line VREF1 and a second reset signal transmission line VREF2. The reset signal auxiliary transmission line VREF' extends along the second direction Y. The reset signal auxiliary transmission line VREF' includes a first reset signal auxiliary transmission line VREF3 and a second reset signal auxiliary transmission line VREF4. The first reset signal transmission line VREF1 and the first reset signal auxiliary transmission line VREF3 are electrically connected via a connection via 53. The second reset signal transmission line VREF2 and the second reset signal auxiliary transmission line VREF4 are also electrically connected via a connection via 53. Perpendicular to the substrate 10, the first reset signal auxiliary transmission line VREF3 overlaps with the line-changing via 51 at the positions of the anode reset control signal line SCP2 and the adjustment control signal line SCP3. Perpendicular to the substrate 10, the second reset signal auxiliary transmission line VREF4 overlaps with the line-changing via 51 at the position of the data control signal line SCP1.

[0107] Optionally, refer to Figure 3 , Figure 4 , Figure 12 or Figure 15 The thin-film transistor 21 includes a driving transistor T3 for providing driving current to the light-emitting element LD. The array substrate also includes a light-shielding light 40 located between the substrate 10 and the driving transistor T3. The light-shielding light 40 is located in a light-shielding metal layer M0, which is situated between the silicon semiconductor layer POLY and the substrate 10. The light-shielding light 40 extends along a second direction Y. Perpendicular to the substrate 10, the light-shielding light 40 overlaps with the transceiver via 51. Thus, the light-shielding area of ​​the transceiver via 51 overlaps with the light-shielding area of ​​the light-shielding light 40, reducing the shared light-shielding area of ​​the transceiver via 51 and increasing light transmittance.

[0108] For example, refer to Figure 3 The shielding light 40 overlaps with the switching via 51 at the position of the anode reset control signal line SCP2 in the direction perpendicular to the substrate 10.

[0109] For example, refer to Figure 3 In a direction perpendicular to the substrate 10, the light-shielding light 40 overlaps with the connecting via 53. For example, in a direction perpendicular to the substrate 10, the light-shielding light 40 overlaps with the connecting via 53 at the location of the first reset signal transmission line VREF1. Thus, the light-shielding area of ​​the connecting via 53 overlaps with the light-shielding area of ​​the light-shielding light 40, reducing the common light-shielding area of ​​the connecting via 53 and the light-shielding light 40, and increasing the light transmittance.

[0110] For example, refer to Figure 3The light shield 40, perpendicular to the substrate 10, overlaps with the driving transistor T3 to block the light projected from one side of the substrate 10 to the driving transistor T3, thereby reducing the impact of photogenerated carriers on the channel layer 202 of the driving transistor T3.

[0111] In some implementations, the light-shielding layer 40 may not be provided. The light-shielding metal layer M0 is a newly added metal layer.

[0112] In some embodiments, the light-shielding line 40 extending along the second direction Y can be replaced with a light-shielding layer, which is a single film layer rather than a line, thus reducing light transmittance. The light-shielding layer has no definite extension direction. Perpendicular to the substrate 10, the light-shielding layer overlaps with multiple scan signal lines 31. When the light-shielding layer is used as an auxiliary signal line 32, it can only be electrically connected to scan signal lines 31 that transmit the same scan signal, and cannot be electrically connected to two scan signal lines 31 that transmit different scan signals. Furthermore, the thickness of the array substrate increases due to the addition of the light-shielding metal layer M0.

[0113] Optionally, refer to Figure 8 and Figure 9 The plurality of pixel regions P includes a first pixel region P1 and a second pixel region P2 arranged adjacent to each other along a first direction X, and a boundary line LN is formed between the first pixel region P1 and the second pixel region P2. The portion of the auxiliary signal line 32 within the first pixel region P1 is symmetrical to the portion of the auxiliary signal line 32 within the second pixel region P2 about the boundary line LN.

[0114] Optionally, refer to Figure 8 and Figure 9 The pixel driving circuit 20 located in the first pixel region P1 is a first pixel driving circuit 2001, and the pixel driving circuit 20 located in the second pixel region P2 is a second pixel driving circuit 2002. The first pixel driving circuit 2001 and the second pixel driving circuit 2002 are at least partially axially symmetrical about the boundary line LN. In this embodiment, the pixel driving circuit 20 adopts a mirror design.

[0115] For example, refer to Figure 3 and Figure 8 The storage capacitor C of the first pixel driving circuit 2001 and the storage capacitor C of the second pixel driving circuit 2002 are symmetrical about the boundary line LN axis. The thin film transistor 21 (e.g., driving transistor T3) of the first pixel driving circuit 2001 and the thin film transistor 21 (e.g., driving transistor T3) of the second pixel driving circuit 2002 are symmetrical about the boundary line LN axis.

[0116] For example, refer to Figure 3 and Figure 8The first power line VDD passing through the first pixel region P1 and the first power line VDD passing through the second pixel region P2 are symmetrical about the boundary line LN. The data line VDATA passing through the first pixel region P1 and the data line VDATA passing through the second pixel region P2 are symmetrical about the boundary line LN. The first reset signal auxiliary transmission line VREF3 passing through the first pixel region P1 and the first reset signal auxiliary transmission line VREF3 passing through the second pixel region P2 are symmetrical about the boundary line LN. The second reset signal auxiliary transmission line VREF4 passing through the first pixel region P1 and the second reset signal auxiliary transmission line VREF4 passing through the second pixel region P2 are symmetrical about the boundary line LN. The shielding light 40 passing through the first pixel region P1 and the shielding light 40 passing through the second pixel region P2 are symmetrical about the boundary line LN.

[0117] For example, refer to Figure 3 and Figure 8 Two adjacent pixel regions P along the first direction X share the same first power line VDD, thus eliminating the need to set two separate first power lines VDD for each pixel region P, reducing the number of first power lines VDD and improving light transmittance.

[0118] Optionally, refer to Figures 3-5 The array substrate also includes a reset signal transmission line VREF for transmitting a reset signal. VREF extends along a first direction X and is on the same layer as the channel layer 202. Since VREF is on the same layer as the semiconductor trace 60, when VREF and 60 are electrically connected, there is no need to provide connection vias for both, reducing the number of vias and increasing light transmittance.

[0119] For example, refer to Figures 3-5 The reset signal transmission line VREF includes a first reset signal transmission line VREF1 and a second reset signal transmission line VREF2. Both the first reset signal transmission line VREF1 and the second reset signal transmission line VREF2 are on the same layer as the channel layer 202. Both the first reset signal transmission line VREF1 and the second reset signal transmission line VREF2 are located on the silicon semiconductor layer POLY. Along the second direction Y, after passing through the second reset transistor T7, the semiconductor trace 60 is directly connected to the second reset signal transmission line VREF2 on the same layer, without the need to provide a connection via 53 for the second reset signal transmission line VREF2 and the semiconductor trace 60.

[0120] Figure 21 This is a top view schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 21The first reset signal transmission line VREF1 is on the same layer as the first plate C1 of the storage capacitor C, and is located in the first metal layer M1. The second reset signal transmission line VREF2 is on the same layer as the second plate C2 of the storage capacitor C, and is located in the first sub-gate metal layer MC. The resistance of both the first metal layer M1 and the first sub-gate metal layer MC is less than the resistance of the silicon semiconductor layer POLY, thus providing better conductivity.

[0121] For example, refer to Figure 21 Along the second direction Y, after passing the second reset transistor T7, the semiconductor trace 60 is electrically connected to the second reset signal transmission line VREF2 of the different layer through the connecting via 53.

[0122] Figure 22 for Figure 3 The schematic diagram of a partial structure of the pixel driving circuit shown is for reference. Figure 3 , Figure 4 and Figure 22 The pixel driving circuit 20 also includes a storage capacitor C, which includes a first electrode C1 and a second electrode C2. The first electrode C1 is located between the second electrode C2 and the substrate 10. The array substrate also includes semiconductor traces 60, interconnect vias 53, and interconnect lines 81. At least a portion of the semiconductor traces 60 extends along a second direction Y. The channel layer 202 is the portion where the semiconductor traces 60 overlap with the gate 201, and the channel layer 202 includes an oxide semiconductor material. The semiconductor traces 60 are electrically connected to the interconnect lines 81 vias 53, and the interconnect lines 81 are on the same layer as the auxiliary signal lines 32.

[0123] Figure 23 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 23 The semiconductor trace 60 connected to the first node N1 is located in the IGZO oxide semiconductor layer. The semiconductor trace 60 located in the IGZO oxide semiconductor layer extends along the second direction Y and is connected to the first electrode C1 of the storage capacitor C via a connecting line 81. In this embodiment, the connecting line 81 and the first electrode C1 are on the same layer, thus the connecting line 81 and the first electrode C1 are electrically connected on the same layer. This eliminates the need for connecting vias between the connecting line 81 and the first electrode C1, reducing the number of connecting vias and increasing light transmittance.

[0124] Figure 24 This is a top view schematic diagram of another array substrate provided in an embodiment of this disclosure, with reference to... Figure 3 and Figure 24The array substrate also includes a non-display area 102, located around the display area 101. The array substrate includes a virtual pixel driving circuit 82, a repair line 70, and a bonding layer 83. The virtual pixel driving circuit 82 is located in the non-display area 102. The repair line 70 is at least partially located in the display area 101 and can extend from the display area 101 to the non-display area 102. The repair line 70 is electrically connected to the virtual pixel driving circuit 82. The bonding layer 83 is located in the display area 101, with one end electrically connected to the anode of the light-emitting element LD. The other end of the bonding layer 83 overlaps with the repair line 70 in a direction perpendicular to the substrate 10. When the pixel driving circuit 20 in the display area 101 malfunctions, the overlapping bonding layer 83 and the repair line 70 can be connected together by means such as laser welding, thereby electrically connecting the anode of the light-emitting element LD to the virtual pixel driving circuit 82 in the non-display area 102, driving the light-emitting element LD to emit light for display via the virtual pixel driving circuit 82 in the non-display area 102.

[0125] Figure 25 for Figure 3 The schematic diagram of a partial structure of the pixel driving circuit shown is for reference. Figure 3 , Figure 4 and Figure 25 The thin-film transistor 21 includes a source 203 and a drain 204. A bonding layer 83, the source 203, and the drain 204 are on the same layer, and the bonding layer 83 is located in the second metal layer M2. The gate 201 includes a first sub-gate 2011 and a second sub-gate 2012. Perpendicular to the substrate 10, the first sub-gate 2011 is located between the channel layer 202 and the substrate 10, and the second sub-gate 2012 is located on the side of the channel layer 202 away from the substrate 10. A repair line 70 is on the same layer as the first sub-gate 2011 and is located in the first sub-gate metal layer MC. Therefore, the repair line 70 and the first sub-gate 2011 can be formed simultaneously in the same process, reducing the number of process steps.

[0126] Figure 26 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 4 and Figure 26 The repair line 70 is on the same layer as the second sub-gate 2012, and is located in the second sub-gate metal layer MG. Therefore, the repair line 70 and the second sub-gate 2012 can be formed simultaneously in the same process, reducing the number of process steps. Furthermore, in the direction perpendicular to the substrate 10, the repair line 70 and the second sub-gate 2012 are relatively close, allowing the via 53 connecting the repair line 70 and the second sub-gate 2012 to have a smaller depth, which simplifies the fabrication process.

[0127] Figure 27 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 27 The repair line 70 includes a first sub-repair line 71 and a second sub-repair line 72. The first sub-repair line 71 is on the same layer as the first sub-gate 2011 and is located in the first sub-gate metal layer MC. The second sub-repair line 72 is on the same layer as the second sub-gate 2012 and is located in the second sub-gate metal layer MG. Perpendicular to the substrate 10, the first sub-repair line 71 and the second sub-repair line 72 overlap with the same bonding layer 83. When a pixel driving circuit 20 in the display area 101 malfunctions, the first sub-repair line 71 and the second sub-repair line 72 can be connected to the same bonding layer 83 by means such as laser welding. Because two repair lines 70 are configured for the same bonding layer 83, the repair rate is improved.

[0128] For example, refer to Figure 27 Perpendicular to the substrate 10, the first sub-repair line 71 and the second sub-repair line 72 are staggered and do not overlap. Therefore, the overlap position (i.e., the welding position) of the first sub-repair line 71 and the welding layer 83 is staggered from the overlap position (i.e., the welding position) of the second sub-repair line 72 and the welding layer 83. This embodiment provides two welding positions for a pixel area P, with two connection vias respectively at each welding position. Even if one of the connection vias fails, it will not affect the electrical connection between the virtual pixel driving circuit 82 and the light-emitting element LD, thus improving the repair rate.

[0129] Figure 28 This is a partial structural schematic diagram of another pixel driving circuit provided in an embodiment of this disclosure, with reference to... Figure 28 In a direction perpendicular to the substrate 10, the first sub-repair line 71 and the second sub-repair line 72 overlap, and any two of the first sub-repair line 71, the second sub-repair line 72 and the welding layer 83 overlap.

[0130] Figure 29 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present disclosure, with reference to... Figure 29 The display panel includes the array substrate and multiple light-emitting elements (LDs) as described in any of the above embodiments. Figure 29 An exemplary light-emitting element (LD) is illustrated. The light-emitting element LD is electrically connected to the pixel driving circuit 20, and the light-emitting element LD is configured to emit light under the drive of the pixel driving circuit 20.

[0131] For example, refer to Figure 29 The light-emitting element (LD) includes an anode (RE), a light-emitting functional layer (84), and a cathode (COM), with the light-emitting functional layer (84) located between the anode (RE) and the cathode (COM). The light-emitting functional layer (84) may include organic light-emitting materials and / or inorganic light-emitting materials.

[0132] Figure 30 This is a schematic diagram of a display device provided in an embodiment of the present disclosure, with reference to... Figure 30 The display device includes the display panel in the above embodiments. The display device provided in this disclosure can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. This disclosure does not impose any special limitations on these categories.

[0133] Note that the above description is merely a preferred embodiment and the technical principles employed in this disclosure. Those skilled in the art will understand that this disclosure is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of this disclosure. Therefore, although this disclosure has been described in detail through the above embodiments, it is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this disclosure, and the scope of this disclosure is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that, Includes a display area, which comprises multiple pixel areas; The substrate, pixel driving circuit, and scan signal line are located in the display area, on the same side of the substrate, with at least a portion of the pixel driving circuit and the scan signal line extending along a first direction; At least a portion of the pixel driving circuit is located in the pixel region, including a thin-film transistor; the thin-film transistor includes a gate and a channel layer, wherein the gate is the portion where the scan signal line overlaps with the channel layer; The array substrate further includes auxiliary signal lines, which are located in the display area and extend along the first direction; the resistance of the film layer where the auxiliary signal lines are located is less than the resistance of the film layer where the scan signal lines are located, they are on different layers from the scan signal lines, and are electrically connected to the scan signal lines via a line-switching via. The scan signal lines include first-type scan signal lines and second-type scan signal lines; The thin-film transistor includes a silicon transistor and an oxide transistor, wherein the silicon transistor is electrically connected to the first type of scan signal line and the oxide transistor is electrically connected to the second type of scan signal line; The auxiliary signal lines include a first type of auxiliary signal line and a second type of auxiliary signal line. The first type of scan signal line is electrically connected to the first type of auxiliary signal line through the cable switching via, and the second type of scan signal line is electrically connected to the second type of auxiliary signal line through the cable switching via. The first type of auxiliary signal line and the second type of auxiliary signal line are located on the same layer.

2. The array substrate according to claim 1, characterized in that, The auxiliary signal line is located on the side of the film layer where the scan signal line is located, away from the substrate.

3. The array substrate according to claim 2, characterized in that, The thin-film transistor includes a source and a drain, and the auxiliary signal line, the source, and the drain are on the same layer.

4. The array substrate according to claim 1, characterized in that, Along the first direction, the length of the scanning signal line is less than the length of the auxiliary signal line.

5. The array substrate according to claim 1, characterized in that, In the plan view, the scanning signal line and the auxiliary signal line overlap in an area outside the area where the switching via is located.

6. The array substrate according to claim 1, characterized in that, The end of the scanning signal line is electrically connected to the end of the auxiliary signal line.

7. The array substrate according to claim 1, characterized in that, The collinear multiple scan signal lines include a first scan signal line and a second scan signal line spaced apart, and the first scan signal line and the second scan signal line are located in the same pixel area.

8. The array substrate according to claim 7, characterized in that, The thin-film transistor includes a driving transistor for providing driving current to the light-emitting element; The first scan signal line is configured to control the thin-film transistor to transmit a reset signal to the anode of the light-emitting element, and the second scan signal line is configured to control the thin-film transistor to transmit an adjustment signal to the first electrode of the driving transistor.

9. The array substrate according to claim 1, characterized in that, The scan signal line includes a first signal line segment and a second signal line segment connected to each other. The first signal line segment and the second signal line segment are located in the same pixel area. The first signal line segment and the second signal line segment each include the gate.

10. The array substrate according to claim 1, characterized in that, The plurality of pixel regions include a first pixel region and a second pixel region that are arranged adjacent to each other along the first direction; The collinear multiple scan signal lines include a third scan signal line and a fourth scan signal line spaced apart, wherein the third scan signal line is located in the first pixel area and the fourth scan signal line is located in the second pixel area.

11. The array substrate according to claim 1, characterized in that, The plurality of pixel regions include a first pixel region and a second pixel region that are arranged adjacent to each other along the first direction; The scanning signal line includes a third signal line segment and a fourth signal line segment connected to each other. The third signal line segment is located in the first pixel area and includes the gate; the fourth signal line segment is located in the second pixel area and includes the gate.

12. The array substrate according to claim 1, characterized in that, The plurality of auxiliary signal lines include a first auxiliary signal line and a second auxiliary signal line arranged along a second direction, the second direction intersecting the first direction; The thin-film transistor includes a driving transistor for providing driving current to the light-emitting element; The plurality of scan signal lines include a first scan signal line and a second scan signal line. The first scan signal line is configured to control the thin-film transistor to transmit a reset signal to the anode of the light-emitting element, and the second scan signal line is configured to control the thin-film transistor to transmit an adjustment signal to the first electrode of the driving transistor. The first scan signal line is electrically connected to the first auxiliary signal line, and the second scan signal line is electrically connected to the second auxiliary signal line.

13. The array substrate according to claim 1, characterized in that, The pixel driving circuit also includes a storage capacitor; In the plan view, the auxiliary signal line and the storage capacitor are arranged along a second direction, which intersects the first direction.

14. The array substrate according to claim 13, characterized in that, The thin-film transistor includes a driving transistor for providing driving current to the light-emitting element; The multiple scanning signal lines include an anode reset control signal line and an adjustment control signal line. The anode reset control signal line is configured to control the thin-film transistor to transmit a reset signal to the anode of the light-emitting element, and the adjustment control signal line is configured to control the thin-film transistor to transmit an adjustment signal to the first electrode of the driving transistor. Along the second direction, the anode reset control signal line and the adjustment control signal line are located on the same side of the storage capacitor; The auxiliary signal line electrically connected to the anode reset control signal line is a straight line segment, and the auxiliary signal line electrically connected to the adjustment control signal line is also a straight line segment.

15. The array substrate according to claim 14, characterized in that, The scan signal line includes a data control signal line, which is configured to control the thin-film transistor to transmit a data signal to the first electrode of the driving transistor. The array substrate further includes data lines and data line vias, the data lines being connected to semiconductor traces on a different layer via the data line vias, and the channel layer being the portion where the semiconductor traces overlap with the gate. Along the second direction, the data control signal line is located on the side of the storage capacitor away from the anode reset control signal line, and is spaced apart from the data line via by at least one scan signal line; The auxiliary signal line electrically connected to the data control signal line is a straight segment.

16. The array substrate according to claim 14, characterized in that, It also includes an adjustment signal transmission line for transmitting adjustment signals, the adjustment signal transmission line extending along the first direction; The membrane layer containing the regulating signal transmission line is located between the membrane layer containing the regulating control signal line and the membrane layer containing the auxiliary signal line; In the plan view, the adjustment control signal line is offset from the adjustment signal transmission line.

17. The array substrate according to claim 1, characterized in that, The second type of scan signal line includes a first sub-signal line and a second sub-signal line; The gate includes a first sub-gate and a second sub-gate, which are perpendicular to the substrate. The first sub-gate is located between the channel layer and the substrate, and the second sub-gate is located on the side of the channel layer away from the substrate. The first sub-gate is the portion where the first sub-signal line overlaps with the channel layer, and the second sub-gate is the portion where the second sub-signal line overlaps with the channel layer; The first sub-signal line and / or the second sub-signal line are electrically connected to the second type of auxiliary signal line via the switching via.

18. The array substrate according to claim 17, characterized in that, The second type of auxiliary signal line includes a first sub-auxiliary signal line and a second sub-auxiliary signal line that are spaced apart; The cable switching via includes a first cable switching via and a second cable switching via. The first sub-signal line and the first sub-auxiliary signal line are electrically connected through the first cable switching via, and the second sub-signal line and the second auxiliary signal line are electrically connected through the second cable switching via. In the plan view, the first cable switching via is offset from the second cable switching via.

19. The array substrate according to claim 17, characterized in that, It also includes data lines and data line vias, wherein the data lines are connected to semiconductor traces on a different layer via the data line vias, and the channel layer is the portion where the semiconductor traces overlap with the gate. The array substrate further includes a reset signal transmission line for transmitting a reset signal, the reset signal transmission line extending along the first direction; The second type of auxiliary signal line electrically connected to the first sub-signal line or the second sub-signal line is a third auxiliary signal line. Along the second direction, the third auxiliary signal line is located between the reset signal transmission line and the data line via. The second direction intersects the first direction. The third auxiliary signal line includes a first auxiliary signal line segment, a second auxiliary signal line segment, and a third auxiliary signal line segment. The second auxiliary signal line segment connects the first auxiliary signal line segment and the third auxiliary signal line segment. Along the second direction, the second auxiliary signal line segment is located on the side of the cable switching via that is away from the data line via.

20. The array substrate according to claim 17, characterized in that, The scan signal line includes a data control signal line, which is configured to control the thin-film transistor to transmit a data signal to the first electrode of the driving transistor. The pixel driving circuit also includes a storage capacitor; The second type of auxiliary signal line electrically connected to the first sub-signal line or the second sub-signal line is a third auxiliary signal line. Along the second direction, the third auxiliary signal line is located between the storage capacitor and the data control signal line, and the second direction intersects the first direction.

21. The array substrate according to claim 20, wherein the third auxiliary signal line is a straight line.

22. The array substrate according to claim 1, characterized in that, It also includes a reset signal transmission line and a reset signal auxiliary transmission line; The reset signal transmission line is configured to transmit a reset signal, extends along the first direction, is on a different layer from the reset signal auxiliary transmission line, and is electrically connected to the reset signal auxiliary transmission line via a connection via. In a direction perpendicular to the substrate, the reset signal auxiliary transmission line overlaps with the line-changing via.

23. The array substrate according to claim 1, characterized in that, The thin-film transistor includes a driving transistor for providing driving current to the light-emitting element; The array substrate further includes a light shielding line located between the substrate and the driving transistor, extending along a second direction that intersects the first direction. In a direction perpendicular to the substrate, the light shielding line overlaps with the transceiver via.

24. The array substrate according to claim 1, characterized in that, The plurality of pixel regions include a first pixel region and a second pixel region arranged adjacent to each other along the first direction, and a boundary line is formed between the first pixel region and the second pixel region; The portion of the auxiliary signal line within the first pixel area is symmetrical to the portion of the auxiliary signal line within the second pixel area about the boundary line.

25. The array substrate according to claim 24, characterized in that, The pixel driving circuit located in the first pixel area is a first pixel driving circuit, and the pixel driving circuit located in the second pixel area is a second pixel driving circuit; The first pixel driving circuit and the second pixel driving circuit are at least partially axially symmetrical about the boundary line.

26. The array substrate according to claim 1, characterized in that, It also includes a reset signal transmission line for transmitting a reset signal, the reset signal transmission line extending along the first direction and being in the same layer as the channel layer.

27. The array substrate according to claim 1, characterized in that, The pixel driving circuit further includes a storage capacitor, which includes a first electrode plate and a second electrode plate, with the first electrode plate located between the second electrode plate and the substrate. The array substrate further includes semiconductor traces, interconnect vias, and interconnect lines; at least a portion of the semiconductor traces extends along a second direction, the channel layer is the portion where the semiconductor traces overlap with the gate, and the channel layer includes an oxide semiconductor material; The semiconductor trace is electrically connected to the connecting line via the connecting via, and the connecting line is on the same layer as the first electrode plate.

28. The array substrate according to claim 1, characterized in that, The pixel driving circuit further includes a storage capacitor, which includes a first electrode plate and a second electrode plate, with the first electrode plate located between the second electrode plate and the substrate. The array substrate further includes semiconductor traces, interconnect vias, and interconnect lines; at least a portion of the semiconductor traces extends along a second direction, the channel layer is the portion where the semiconductor traces overlap with the gate, and the channel layer includes an oxide semiconductor material; The semiconductor trace is electrically connected to the connecting line via the connecting via, and the connecting line is on the same layer as the auxiliary signal line.

29. The array substrate according to claim 1, characterized in that, It also includes a non-display area, which is located on the periphery of the display area; The system includes a virtual pixel driving circuit, a repair line, and a solder layer. The virtual pixel driving circuit is located in the non-display area, and the repair line is at least partially located in the display area and electrically connected to the virtual pixel driving circuit. The welding layer is located in the display area. One end of the welding layer is electrically connected to the anode of the light-emitting element and is perpendicular to the substrate. The other end of the welding layer overlaps with the repair line.

30. The array substrate according to claim 29, characterized in that, The thin-film transistor includes a source and a drain, and the welding layer, the source, and the drain are in the same layer; The gate includes a first sub-gate and a second sub-gate, which are perpendicular to the substrate. The first sub-gate is located between the channel layer and the substrate, and the second sub-gate is located on the side of the channel layer away from the substrate. The repair line is on the same layer as the first sub-gate; or, The repair line is on the same layer as the second sub-gate; or... The repair line includes a first sub-repair line and a second sub-repair line, wherein the first sub-repair line is on the same layer as the first sub-gate, and the second sub-repair line is on the same layer as the second sub-gate.

31. A display panel, characterized in that, It includes the array substrate as described in any one of claims 1-30, and a plurality of light-emitting elements; The light-emitting element is electrically connected to the pixel driving circuit and is configured to emit light under the drive of the pixel driving circuit.

32. A display device, characterized in that, Includes the display panel as described in claim 31.

Images