Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, the display panel comprises an array layer, and a flat layer, a pixel definition layer, a pixel opening, a touch opening, a luminescent material layer and a cathode layer which are arranged on one side of the array layer, the pixel opening penetrates through the pixel definition layer along the thickness direction of the display panel, and the touch opening penetrates through the luminescent material layer along the thickness direction of the display panel. The touch opening penetrates through the pixel definition layer and at least part of the flat layer and exposes the connecting metal; the light-emitting material layer is at least located in the pixel opening, and the cathode layer is located on the side, away from the flat layer, of the light-emitting material layer; the cathode layer comprises a display cathode and a touch electrode, and the touch electrode is at least located in the touch opening and electrically connected with the connecting metal; in the touch opening, one side, facing the pixel definition layer, of the connecting metal comprises a first flat part and a first insulating part, and the first insulating part and the first flat part form an undercut space. The accurate undercut space is constructed in the touch opening, so that both the display performance and the touch reliability are considered.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0003] For touch-enabled display panels, the touch sensing layer and display panel can typically be integrated in three ways: on-chip, semi-in-cell, and in-cell. In an on-chip structure, the touch panel and display panel are manufactured independently and then assembled together via bonding, resulting in a thicker and heavier display product. A semi-in-cell structure integrates the touch sensing layer on top of the display panel, making the display product thinner and lighter than an on-chip structure. An in-cell structure embeds the touch functionality layer inside the display panel, resulting in the thinnest and lightest module.

[0004] However, for fully embedded structures, ensuring that the introduction of the touch function layer does not interfere with other structures of the display product has become one of the technical problems that urgently need to be solved at this stage. Summary of the Invention

[0005] To address the aforementioned technical issues, this disclosure provides a display panel and display device that balances display performance and touch reliability by constructing a precise undercut space within the touch opening.

[0006] In a first aspect, this disclosure provides a display panel, including: An array layer and a flat layer disposed on one side of the array layer; The pixel definition layer is located on the side of the flat layer that faces away from the array layer. Multiple pixel openings and multiple touch openings are provided along the thickness direction of the display panel. The pixel openings penetrate the pixel definition layer, and the touch openings penetrate the pixel definition layer and at least part of the planarization layer, and expose the connecting metal. The light-emitting material layer and the cathode layer are provided, with the light-emitting material layer located at least in the pixel opening and the cathode layer located on the side of the light-emitting material layer opposite to the planarization layer; the cathode layer includes a display cathode and a touch electrode, with the touch electrode located at least in the touch opening and electrically connected to the connecting metal. In the touch opening, the side of the connecting metal facing the pixel definition layer includes a first flat portion and a first insulating portion. The first flat portion is located between the connecting metal and the first insulating portion. Along the thickness direction of the display panel, the edge of the orthographic projection of the first insulating portion is located outside the edge of the orthographic projection of the first flat portion. The first insulating portion and the first flat portion form an undercut space.

[0007] In a second aspect, this disclosure provides a display device, including the display panel provided in the first aspect of this disclosure.

[0008] The technical solution provided in this disclosure has the following advantages compared with the prior art: In the display panel and display device provided in this disclosure, the touch electrode is connected to the connecting metal below in the touch opening, allowing touch signals to be extracted from inside the panel, thereby realizing in-cell touch functionality. The flatness of the first flat portion ensures that the subsequent vapor-deposited touch electrode can form a stable, low-resistance ohmic contact. This structure ensures that the touch electrode and the connecting metal can reliably connect to the undercut area. The edge of the first insulating portion is located outside the edge of the first flat portion, forming a cantilevered or recessed undercut space. This precise geometry can control the deposition path of the subsequent cathode layer (touch electrode), helping to guide the cathode material to uniformly and continuously cross the step and enter the undercut area, avoiding electrode breakage or uneven deposition caused by excessively steep steps, thereby improving manufacturing yield and electrode performance.

[0009] Furthermore, in the display area, the pixel opening only penetrates the pixel definition layer. In the area where the touch electrode is located, the touch opening penetrates not only the pixel definition layer but also part of the planarization layer. Therefore, the planarization layer in the display area is relatively thick. This allows the planarization layer to be used to planarize the underlying connecting metal film layer, so that the subsequent display anode is formed on a flat surface. This helps to avoid uneven anode caused by uneven structures in the area below the pixel opening, which in turn leads to uneven display or poor color shift.

[0010] Therefore, this disclosure achieves a reliable electrical connection between the touch electrode and the underlying auxiliary metal by constructing a precise undercut space within the touch opening. At the same time, by controlling the film thickness of the planar layer in the display area and the area where the touch electrode is located, it resolves the contradiction between display uniformity and touch function integration, thus balancing display performance and touch reliability. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0012] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 The figure shown is a planar structural diagram of a display panel provided in an embodiment of this disclosure; Figure 2 The diagram shown is a schematic diagram of a film layer of a display panel provided in an embodiment of this disclosure; Figure 3 The diagram shown is a planar structural diagram of the cathode layer in a display panel provided in an embodiment of this disclosure; Figure 4 As shown Figure 3 An enlarged schematic diagram of region Q in the middle region; Figure 5 The diagram shown is a schematic of a film layer at the pixel opening and touch opening in a display panel provided in an embodiment of this disclosure; Figure 6 The image shown is an enlarged schematic diagram of the undercut space formed in the touch opening; Figure 7 The diagram shown is a schematic diagram of another film layer at the pixel opening and touch opening in the display panel provided in the embodiment of this disclosure; Figure 8 The diagram shown is a schematic diagram of another film layer at the pixel opening and touch opening in the display panel provided in the embodiment of this disclosure; Figure 9 The diagram shown is a schematic diagram of another film layer at the pixel opening and touch opening in the display panel provided in the embodiment of this disclosure; Figure 10 The diagram shown is a schematic diagram of another film layer at the pixel opening and touch opening in the display panel provided in the embodiment of this disclosure; Figure 11 The diagram shows one possible arrangement of the touch electrodes and display cathode in a display panel. Figure 12 The diagram shows another arrangement of the touch electrodes and display cathode in the display panel; Figure 13 The diagram shown is a schematic of a film layer at the pixel opening and touch opening in a display panel provided in an embodiment of this disclosure; Figure 14 The diagram shows another arrangement of the touch electrodes and display cathode in the display panel; Figure 15 The diagram shown is a structural schematic of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0014] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0015] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0016] With the continuous development of science and technology, new display technologies such as OLED (Organic Light-Emitting Diode) have been widely used in display products such as mobile phones, tablets, laptops, and smart wearable devices due to their advantages such as self-illumination, high contrast, and fast response speed. To achieve thinner and lighter products and integrated functionality, touch functionality is typically embedded in the display panel. For OLED display panels with a fully embedded structure, the touch electrodes can be placed on the same layer or adjacent to the display electrodes. Therefore, ensuring that the introduction of the touch function layer does not interfere with the normal operation of the display electrodes, and how to solve problems such as color shift or unevenness caused by differences in film thickness in different functional areas through structural optimization, are among the key technical challenges that urgently need to be addressed in the current fully embedded structure of OLED display products.

[0017] To address the aforementioned problems, this disclosure provides a display panel and a display device. Figure 1 The diagram shown is a planar structural diagram of a display panel provided in an embodiment of this disclosure. The display panel includes a plurality of light-emitting elements D0, which are driven by a driving circuit P0 to achieve the light-emitting function. Figure 1 The arrangement of the light-emitting element D0 and the driving circuit P0 is merely illustrative and is not intended to limit the scope of this disclosure. For example, the display panel 100 provided in this disclosure may be an OLED (Organic Light Emitting Diode) display panel.

[0018] Figure 2The diagram shows a film layer schematic of a display panel according to an embodiment of this disclosure, illustrating two light-emitting elements in the display panel. In the display panel, an array layer 40 is disposed on one side of a substrate 00. The basic structure of the light-emitting element D0 includes a first electrode 31, a light-emitting material layer 32, and a second electrode 33. Optionally, the first electrode 31 is a display anode, and the second electrode 33 is a display cathode, located in the cathode layer. Along a direction perpendicular to the substrate 00, the first electrode 31 and the second electrode 33 are respectively located on opposite sides of the light-emitting material layer 32, with the first electrode 31 located on the side of the second electrode 33 facing the substrate 00. The first electrode 31 is electrically connected to the array layer 40, which contains a pixel driving circuit. The pixel driving circuit P0 includes at least one transistor T, which is electrically connected to the first electrode 31 and provides a driving voltage to the light-emitting element D0, driving the light-emitting element D0 to emit light. When an appropriate voltage is supplied, holes generated by the first electrode 31 and electrons generated by the second electrode 33 combine in the light-emitting material layer 32, producing light.

[0019] Optionally, an encapsulation layer 50 is provided on the side of the second electrode 33 of the light-emitting element D away from the first electrode 31. Optionally, the encapsulation layer 50 includes an organic encapsulation layer 51 and two inorganic encapsulation layers 52 stacked together, with the organic encapsulation layer 51 located between the two inorganic encapsulation layers 52.

[0020] Figure 3 The diagram shown is a planar structural diagram of the cathode layer in a display panel provided in an embodiment of this disclosure. Figure 4 As shown Figure 3 This is an enlarged schematic diagram of the central region Q. It should be noted that, in order to clearly show the display cathode 33 and touch electrode 39 in the cathode layer 30, Figure 4 Different patterns were applied to the display cathode 33 and the touch electrode 39, although both are actually located in the cathode layer 30. Figure 5 The diagram shown is a schematic of a film layer at the pixel opening K1 and touch opening K2 in a display panel provided in this embodiment of the present disclosure. It should be noted that... Figure 5 Other film layers above the cathode layer 30 are not shown. Optionally, additional film layers such as those above the cathode layer 30 may also be provided. Figure 2 The encapsulation layer 50 shown is an example.

[0021] Please refer to Figures 1 to 5This disclosure provides a display panel 100, including: an array layer 40 and a planarization layer 80, a pixel definition layer 60, a plurality of pixel openings K1 and a plurality of touch openings K2 disposed on one side of the array layer 40, a light-emitting material layer 32 and a cathode layer 30, wherein the pixel definition layer 60 is located on the side of the planarization layer 80 away from the array layer 40; along the thickness direction of the display panel, the pixel openings K1 penetrate the pixel definition layer 60, and the touch openings K2 penetrate the pixel definition layer 60 and at least a portion of the planarization layer 80, and expose a connecting metal L0; wherein the connecting metal L0 can be regarded as a film layer disposed on the side of the planarization layer 80 away from the pixel definition layer 60, and the connecting metal L0 can be used, for example, to connect to the touch electrode 39.

[0022] The light-emitting material layer 32 is located at least in the pixel opening K1, and the cathode layer 30 is located on the side of the light-emitting material layer 32 opposite to the planarization layer 80. The cathode layer 30 includes a display cathode 33 and a touch electrode 39, and the touch electrode 39 is located at least in the touch opening K2 and electrically connected to the connecting metal L0. The light-emitting material layer 32 may include, for example, an organic light-emitting material located in the pixel opening K1, such as any one of red, green, and blue light-emitting materials. The light-emitting material in each pixel opening K1 can emit light and be driven independently, achieving full-color display through the mixing of the three primary colors. Of course, in some other embodiments of this disclosure, the light-emitting material layer 32 may also include only blue organic material, with quantum dots introduced above the blue organic material. After absorbing the blue light emitted by the blue light-emitting material, the quantum dots can convert it into green or red light, also achieving full-color display.

[0023] In the touch opening K2, the side of the connecting metal L0 facing the pixel definition layer 60 includes a first flat portion 71 and a first insulating portion 91. The first flat portion 71 is located between the connecting metal L0 and the first insulating portion 91. Along the thickness direction of the display panel, the edge of the orthographic projection of the first insulating portion 91 is located outside the edge of the orthographic projection of the first flat portion 71. The first insulating portion 91 and the first flat portion 71 form an undercut space D. For example, please refer to... Figure 6 , Figure 6 The diagram shown is an enlarged schematic of the undercut space D formed in the touch opening K2.

[0024] In the display panel provided in this disclosure, in the pixel opening K1, the first insulating portion 91 is located on the side of the first flat portion 71 away from the connecting metal L0, and the edge of the first insulating portion 91 extends beyond the edge of the first flat portion 71. Thus, the gap (or concave structure) formed between the surface of the first insulating portion 91 facing the connecting metal L0, the side of the first flat portion 71, and the surface of the connecting metal L0 facing the first flat portion 71 is the undercut space D mentioned in the embodiments of this disclosure.

[0025] In the display panel provided in this disclosure, the touch electrode 39 and the display cathode 33 are disposed on the same layer, both located on the cathode layer 30 of the display panel. This allows the cathode layer 30 to serve not only as the top electrode of the electron injection layer and the light-emitting material layer 32, but also as the touch electrode 39. The touch electrode 39 is no longer a separately manufactured film layer, but directly utilizes the conductive properties of the cathode layer 30 to achieve touch sensing functionality. The cathode layer 30 is precisely patterned so that it acts as the display cathode 33 above the pixel opening K1, and as the touch electrode 39 in the specially designed touch opening K2 area. This completely eliminates the separate touch panel and additional bonding layer required by traditional external or on-cell structures. This results in the highest integration of the display product, achieving the thinnest and lightest design, meeting the current pursuit of thinness and lightness in high-end display products. It also reduces the need for separate manufacturing of the touch panel, touch driver IC, and bonding processes between the display panel and the touch panel, simplifying the overall assembly process. Furthermore, by placing the touch electrode 39 and the display cathode 33 on the same layer, the formation of the touch electrode 39 and the manufacturing process of the cathode layer 30 are combined, which helps to improve production efficiency.

[0026] To enable the light-emitting elements to emit light, a common layer 99 may also be introduced into the display panel. It should be noted that... Figure 5 The diagram only illustrates one common layer 99 in the display panel, but does not limit the number of common layers 99. The common layer 99 may include, for example, a hole layer and an electron layer, located on the upper and lower sides of the light-emitting material layer 32, respectively. The hole layer receives holes (positive charge carriers) injected from the display anode 31 and effectively transfers them to the light-emitting material layer 32. The electron layer receives electrons (negative charge carriers) injected from the display cathode 33 and effectively transfers them to the light-emitting material layer 32. When holes and electrons enter the light-emitting material layer 32, they are attracted by electrostatic forces due to their opposite charges, forming an exciton. The exciton is in a high-energy unstable state and rapidly decays from the excited state back to the stable ground state, releasing excess energy as light. This process is called electroluminescence, and the wavelength (color) of the emitted light is determined by the energy level difference of the light-emitting material doped in the light-emitting material layer 32. Optionally, the common layer 99 may also include a hole blocking layer and / or an electron blocking layer. Their function is to prevent holes or electrons from penetrating the luminescent material layer 32 and entering the transport layer on the other side, thereby confining holes and electrons within the luminescent material layer 32 and improving luminous efficiency.

[0027] In practical applications, when depositing the common layer 99, a full-surface deposition method is typically used. This means that the common layer 99 extends beyond the pixel opening K1 into the touch opening K2. If the common layers 99 between different pixel openings K1 are continuous, short circuits or crosstalk may occur between different sub-pixels or adjacent sub-pixels, preventing independent pixel driving. Therefore, when the touch electrode 39 and the display cathode 33 are disposed on the same layer, this embodiment introduces an undercut space D formed by the first insulating portion 91, the first flat portion 71, and the connecting metal L0 in the touch opening K2. When depositing the hole layer, electron layer, and other common layers 99, due to the evaporation angle limitation of the material and the shielding effect of the undercut structure, the material cannot or is difficult to deposit below the suspended structure, thus causing the common layer 99 to be disconnected in the touch opening K2. This ensures that the common layer 99 is physically disconnected and insulated between different pixel openings K1, thereby severing the connection between sub-pixels of different pixel openings K1 and ensuring that each sub-pixel can be driven independently.

[0028] In the touch opening K2, the touch electrode 39, by overlapping the connecting metal L0 below, can draw touch signals from inside the panel, thereby realizing the in-cell touch function. The flatness of the first flat portion 71 ensures that the subsequently vapor-deposited touch electrode 39 (as part of the cathode layer 30) can form a stable, low-resistance ohmic contact. This structure ensures that the touch electrode 39 and the connecting metal L0 can reliably overlap to the undercut area. The edge of the first insulating portion 91 is located outside the edge of the first flat portion 71, forming a cantilevered or recessed undercut space D. This precise geometry can control the deposition path of the subsequent cathode layer 30 (touch electrode 39), helping to guide the cathode material to uniformly and continuously cross the step and enter the undercut area, avoiding electrode breakage or uneven deposition caused by excessively steep steps, thereby improving manufacturing yield and electrode performance.

[0029] Furthermore, in the display area, the pixel opening K1 only penetrates the pixel definition layer 60. In the area where the touch electrode 39 is located, the touch opening K2 penetrates not only the pixel definition layer 60 but also part of the planarization layer 80. Therefore, the planarization layer 80 in the display area is relatively thick. This allows the planarization layer 80 to be used to planarize the film layer where the connecting metal L0 is located, so that the subsequent display anode 31 is formed on a flat surface. This helps to avoid the anode being uneven due to the uneven structure in the area below the pixel opening K1, which in turn leads to uneven display or poor color shift.

[0030] Therefore, this embodiment of the present disclosure achieves a reliable electrical connection between the touch electrode 39 and the lower auxiliary metal by constructing a precise undercut space D within the touch opening K2. At the same time, by controlling the film thickness of the planarization layer 80 in the display area and the area where the touch electrode 39 is located, the contradiction between display uniformity and touch function integration is resolved, thus balancing display performance and touch reliability.

[0031] Please refer to Figure 5 and Figure 6 In one optional embodiment of this disclosure, the touch electrode 39 is electrically connected to the connecting metal L0 at least within the undercut space D. In this disclosure, the undercut space D is a geometric structure with a suspended, concave feature in the vertical direction. When the touch electrode 39 (cathode layer 30) is deposited by vapor deposition, the cathode material is guided and extended by controlling the evaporation angle of the material, successfully crossing the step and overlapping with the exposed connecting metal L0 at the bottom of the undercut space D. Concentrating the connection within the undercut space D ensures a stable and low-resistance electrical contact between the cathode and the connecting metal L0. In practical applications, by controlling different evaporation angles of the vapor-deposited organic material (common layer 99) and the cathode, the length of the touch electrode 39 extending into the undercut region can be greater than the extension length of other common layers 99 (such as hole layers and electron layers), thereby ensuring that the touch electrode 39 can reliably overlap with the underlying connecting metal L0 in the undercut region. This avoids problems such as impaired touch signal transmission, decreased signal-to-noise ratio, and reduced touch accuracy due to poor contact between the touch electrode 39 and the connecting metal L0.

[0032] Although the touch electrode 39 needs to be connected to the connecting metal L0, the area covered by the cathode layer 30 is very large. The presence of the undercut space D can precisely define the connection area between the touch electrode 39 and the connecting metal L0. Through the precise connection of the undercut space D, the touch electrode 39 can efficiently and stably lead the sensed charge signal to the touch driving circuit through the connecting metal L0, ensuring the quality of the touch signal.

[0033] Please continue to refer to this. Figure 5 and Figure 6In one optional embodiment of this disclosure, the width of the undercut space D along the direction parallel to the light-emitting surface of the display panel is S0, where 0.3 μm ≤ S0 ≤ 0.8 μm. S0 refers to the width of the suspended or recessed portion of the undercut structure along the direction parallel to the light-emitting surface of the display panel (i.e., the horizontal direction). This width directly determines the horizontal distance that the subsequent deposited film layer (touch electrode 39) needs to cross and the inclination angle of the step. If S0 is too large (e.g., greater than 0.8 μm), the suspended length of the undercut structure is too long, and the subsequently deposited cathode material (touch electrode 39) may become thinner, have increased resistance, or even break when crossing the step due to the shielding effect or the limitation of the deposition angle, resulting in touch signal extraction failure or excessively high resistance. If S0 is too small (e.g., less than 0.3 μm), the step formed by the undercut structure is too steep, and it may not be possible to effectively use the evaporation angle to control the overlap path of the cathode. At the same time, an excessively small undercut space D may lead to insufficient etching of the underlying planarization layer 80, affecting the uniformity of subsequent deposition. Therefore, setting the thickness to 0.3μm ≤ S0 ≤ 0.8μm allows for the formation of a suitable suspended structure and step angle, ensuring that the subsequently deposited cathode layer 30 can form a continuous and low-resistance film within the undercut space D, thereby achieving a reliable electrical connection between the touch electrode 39 and the connecting metal L0. Controlling the geometric dimensions is crucial for ensuring the reliability of the electrical connection between the touch electrode 39 and the underlying connecting metal L0. This optimizes the continuity of cathode deposition while maintaining the stability and precision of the manufacturing process. This range provides the necessary window for process operation, and together with the vertical thickness of the organic film in the undercut region, it determines the geometry of the undercut step, representing a proven best practice range for OLED panel manufacturing.

[0034] Alternatively, 0.4μm≤S0≤0.7μm, or 0.35μm≤S0≤0.65μm, etc., are not specifically limited in this disclosure.

[0035] In one optional embodiment of this disclosure, the display panel further includes the aforementioned common layer 99, such as a hole layer or an electron layer. Since the common layer 99 is typically deposited over its entire surface, it is located within the pixel opening K1 and the touch opening K2; in the touch opening K2, the thickness of the first flat portion 71 is greater than the thickness of the common layer 99. It should be noted that when the display panel includes multiple common layers 99, the thickness of the common layer 99 refers to the total thickness of the multiple common layers 99.

[0036] In In-cell OLED structures, the common layers 99 are typically deposited across the entire surface. During this process, they need to be cut off by the cantilever portion of the undercut structure to prevent them from extending into the connection area of ​​the touch electrode 39. When the thickness of the first planar portion 71 is greater than the thickness of the common layer 99, it is beneficial to form a deeper groove or a more effective shielding angle. Due to the thinness of the common layers 99, their deposition direction and angle are easily shielded by the cantilever structure of the undercut structure. The thickness difference between the common layer 99 and the first planar portion 71 ensures that the common layer 99 is completely cut off by the geometry of the undercut structure before the cathode layer 30 reaches the first planar portion 71 and completes the connection. Therefore, by ensuring that "the thickness of the first planar portion 71 is greater than the thickness of the common layer 99", even if the common layer 99 is deposited across the entire surface, the undercut structure can physically cut off or greatly weaken the continuity of the common layer 99 within the undercut space D. This ensures that the subsequently deposited cathode layer 30 can be directly and electrically connected to the underlying connection metal L0 with low resistance, thereby eliminating the interference of the common layer 99 on the touch electrical signal connection.

[0037] During deposition, the cathode (touch electrode 39) needs to cross the steps formed by the underlying film layer (such as the planarization layer 80) and the pixel definition layer 60, ultimately overlapping onto the connecting metal L0. If the thickness of the first planar portion 71 is greater than the thickness of the common layer 99, it can provide better geometric conditions for subsequent cathode deposition, such as a flatter overlapping surface or steps that are easier to be covered by the cathode. In addition, in the connection area of ​​the touch opening K2, the height of the first planar portion 71 is required to be relatively prominent. Since the thickness of the common layer 99 is thinner, the extension of the common layer 99 in the undercut space D is shorter than that of the cathode layer 30. This ensures that the common layer 99 does not form a thick and continuous film in the overlapping area, thereby not interfering with the direct and reliable electrical connection between the cathode (touch electrode 39) and the connecting metal L0, which helps to improve the connection reliability between the touch electrode 39 and the connecting metal L0.

[0038] Please continue to refer to this. Figure 5 and Figure 6 In one optional embodiment of this disclosure, the thickness of the first flat portion 71 is H1, where 0.3 μm ≤ H1 ≤ 0.6 μm.

[0039] In this disclosure, the first flat portion 71 is an insulating structure formed above the connecting metal L0. The first flat portion 71 and the first insulating portion 91 together form an undercut space D above the connecting metal L0. As a component of the undercut structure, the thickness H1 of the first flat portion 71 determines the vertical depth and step height of the undercut opening. When H1 is less than 0.3 μm, the thickness of the first flat portion 71 is too small. When the extremely thin organic film is etched to form the undercut structure, the etching selectivity and termination control become more difficult, and it is easy to etch through to the connecting metal L0, causing over-etching or distortion of the geometry of the undercut structure, affecting the accuracy of the overlap. When H1 is greater than 0.6 μm, the organic film is too thick, resulting in an excessively high vertical step and an excessively large undercut depth. The vapor-deposited cathode material (touch electrode 39) cannot continuously cross this high step by means of the evaporation angle. The thicker organic film requires a longer etching time and a stronger etching solution, narrowing the process window. This increases the risk of etching runaway and reduces manufacturing efficiency.

[0040] Therefore, this disclosure sets the thickness to 0.3μm≤H1≤0.6μm. This moderate thickness ensures that the undercut step is not too high, allowing the cathode layer 30 to continuously and with low resistance cross the step and connect to the lower connecting metal L0. This is a primary prerequisite for realizing touch function integration. Sufficient thickness (greater than or equal to 0.3μm) ensures that when the first flat portion 71 acts as an insulating layer, it can effectively isolate the cathode from the lower metal, preventing short circuits in unintended areas. This range is an optimal geometric window that has been proven in engineering, and can be combined with the horizontal width S0 (0.3μm~0.8μm) to form a structure most conducive to cathode evaporation and connection, improving the connection reliability between the touch electrode 39 and the connecting metal L0. At the same time, avoiding an excessively small thickness of the first flat portion 71 helps reduce the manufacturing difficulty of forming the undercut structure and simplifies the overall manufacturing process.

[0041] Alternatively, 0.35μm≤H1≤0.55μm, or 0.4μm≤H1≤0.5μm, etc.

[0042] Please continue to refer to this. Figure 5 and Figure 6 In one optional embodiment of this disclosure, in the undercut space D, along the thickness direction of the display panel, the contact area between the touch electrode 39 and the connecting metal L0 is greater than the overlap area between the common layer 99 and the connecting metal L0.

[0043] In the undercut space D, the larger the contact area between the touch electrode 39 and the connecting metal L0, the lower the contact resistance. By setting the contact area between the touch electrode 39 and the connecting metal L0 to be larger than the overlap area between the common layer 99 and the connecting metal L0, the effective contact area between the touch electrode 39 and the connecting metal L0 in the undercut space D is maximized. This ensures that the touch signal output path has extremely low resistance and high reliability, thereby improving the touch signal-to-noise ratio and response speed. In addition, the overlap area between the touch electrode 39 and the connecting metal L0 is larger than the overlap area between the common layer 99 and the connecting metal L0, which means that the design of the undercut structure must significantly limit the horizontal extension of the common layer 99 to minimize its overlap area with the connecting metal L0. This differentiated overlap area is a quantitative representation of the undercut structure cutting off the common layer 99. It ensures that the common layer 99 is effectively isolated, maximizing the direct contact between the cathode (touch electrode 39) and the connecting metal L0, thereby achieving functional partitioning and electrical isolation.

[0044] Furthermore, considering that a large overlap area between the common layer 99 and the connecting metal L0 in the undercut space D indicates insufficient cantilever shielding effect of the undercut and excessive extension of the common layer 99, a small overlap area between the touch electrode 39 and the connecting metal L0 may lead to failure of the touch electrode 39 to connect with the connecting metal L0 or excessively high connection resistance. Therefore, by setting the overlap area between the touch electrode 39 and the connecting metal L0 to be larger than the overlap area between the common layer 99 and the connecting metal L0, the evaporation angle of the touch electrode 39 and the undercut geometry are properly matched. While meeting the cathode connection requirements, the common layer 99 is successfully isolated, ensuring that the connection between the touch electrode 39 and the connecting metal L0 is efficient, low-resistance, and unaffected by interference from the common layer 99.

[0045] Please continue to refer to this. Figure 5 In one optional embodiment of this disclosure, the first flat portion 71 is disposed on the same layer as the flat layer 80, and the flat layer 80 further includes a second flat portion 72. Along the thickness direction of the display panel, the second flat portion 72 overlaps with the pixel opening K1 but does not overlap with the touch opening K2; the thickness of the first flat portion 71 is less than the thickness of the second flat portion 72.

[0046] In this embodiment, the second flat portion 72 overlaps with the pixel opening K1 and is located in the display area. To ensure display quality, its thickness is set to be relatively thick. The relatively thick second flat portion 72 can sufficiently flatten the step differences and unevenness caused by the underlying metal traces. This is crucial for the upper light-emitting material layer 32, eliminating uneven film thickness or light emission angle changes in the display anode 31 or light-emitting material layer 32 caused by the lower layer step differences, thereby avoiding display unevenness or color deviation in the display area. The first flat portion 71 is used to form an undercut structure, and its thickness is set to be relatively thin. The thin thickness ensures that the undercut structure has a suitable vertical height, so that the subsequently vapor-deposited cathode (touch electrode 39) can continuously and with low resistance cross the step and overlap with the underlying connecting metal L0. If the first flat portion 71 is too thick, the cathode will have difficulty crossing the step and will break, resulting in touch connection failure.

[0047] The first flat portion 71 and the second flat portion 72 of this disclosure are both located in the same flat layer 80. In practical applications, the thickness difference between the first flat portion 71 and the second flat portion 72 can be achieved in a single flat layer 80 through one or more photolithography / etching processes. This solves the problem of uneven display or poor color deviation in the display area and meets the geometric requirements of touch overlap. It successfully resolves the technical contradiction that a thicker flat layer 80 is beneficial for display but not for undercut overlap, thereby achieving a balance between display performance and touch integration.

[0048] Please continue to refer to this. Figure 5 and Figure 6 In one optional embodiment of this disclosure, the thickness of the second flat portion 72 is H2, where H2 ≥ 2.2 μm.

[0049] In OLED display panels, particularly in the pixel aperture K1 region, there are significant step differences in the metal traces below the planarization layer 80. If the thickness of the upper second planarization portion 72 is insufficient, these step differences will directly affect the uniformity of film thickness and surface flatness of the top light-emitting material layer 32 and cathode layer 30. In this embodiment, the thickness H2 of the second planarization portion 72 (the region where the pixel aperture K1 is located) is set to be no less than 2.2 μm. This thickness provides sufficient material volume and planarization capability to completely cover and flatten the complex and high metal trace step differences in the lower layer. This ensures that the film thickness of the display anode 31 and the light-emitting material layer 32 is highly uniform above the second planarization portion 72, avoiding differences in luminous intensity caused by uneven thickness of the display anode 31 or the light-emitting material layer 32, which in turn leads to display unevenness. Therefore, it is beneficial to ensure the high consistency of the light-emitting micro-cavity structure of the pixel structure, thereby ensuring the uniformity of the emitted light spectrum of each pixel and avoiding color shift.

[0050] In this disclosure, the thickness of the second flat portion 72 is the technical basis for achieving differentiated design between the thick film (high image quality) in the display area and the thin film in the touch connection area. By differentiating the thicknesses of the second flat portion 72 and the first flat portion 71, the display panel can ensure the image quality of the display area while allowing the touch area to use the required thin film structure to optimize cathode bonding, thereby resolving the contradiction between display performance and touch integration in the In-cell structure. Moreover, the thicker second flat portion 72 provides stronger mechanical support, helping to protect the underlying array layer 40 and wiring, and enhancing the structural stability and impact resistance of the panel.

[0051] Optionally, H2 ≥ 2.8 μm, or H2 ≥ 3 μm, or H2 ≥ 4 μm, can be flexibly set according to the requirements in practical applications.

[0052] The above embodiments illustrate a scheme in which only one planarization layer 80 is introduced between the array layer 40 and the pixel definition layer 60. However, this disclosure is not limited thereto. In some other embodiments of this disclosure, two planarization layers 80 may be introduced between the array layer 40 and the pixel definition layer 60, for example, please refer to Figure 7 , Figure 7 The diagram shows another film layer at the pixel opening K1 and touch opening K2 in a display panel provided in this embodiment. In an optional embodiment of this disclosure, along the thickness direction of the display panel, the planarization layer 80 includes a first planarization layer 81 and a second planarization layer 82 stacked together. The first planarization layer 81 is located between the second planarization layer 82 and the array layer 40. The touch opening K2 penetrates the pixel definition layer 60 and at least a portion of the second planarization layer 82. The first planarization portion 71 is disposed on the same layer as the second planarization layer 82. The "at least a portion of the second planarization layer 82" mentioned in this embodiment refers to at least a portion of the second planarization layer 82, that is, the touch opening K2 penetrates at least a portion of the second planarization layer 82, for example... Figure 7 In the illustrated embodiment, a second planarization layer 82 is not provided in a portion of the touch opening K2 to expose the underlying connection metal L0.

[0053] In this disclosure, the ultimate purpose of the touch opening K2 is to expose the underlying connecting metal L0 so that the touch electrodes 39 can overlap. The touch opening K2 extends through the pixel definition layer 60 and at least part of the second planarization layer 82, helping to precisely control the opening depth and ensuring that etching exposes the connecting metal L0 just right without over-etching and damaging the underlying array layer 40. During the etching of the second planarization layer 82, the sidewall slope and overhang structure of the first planar portion 71 can be achieved through photolithography design and control, providing a geometric basis for the formation of the undercut structure.

[0054] In this embodiment, the first flattened portion 71 (thin film portion, such as 0.3μm≤H1≤0.6μm) is disposed in the same layer as the second flattened layer 82. The first flattened portion 71 can be formed simultaneously during the fabrication of the second flattened layer 82, without the need to form the first flattened portion 71 through a thinning process. This helps to simplify the fabrication process of the undercut structure and improve the overall production efficiency of the display panel.

[0055] Please continue to refer to this. Figure 7 In one alternative embodiment of this disclosure, the thickness of the first planarization layer 81 is greater than the thickness of the second planarization layer 82.

[0056] In this embodiment, the thickest first planarization layer 81 is located at the bottom layer, adjacent to the complex array layer 40 and the film layer containing the connecting metal L0. The design that the thickness of the first planarization layer 81 is greater than the thickness of the second planarization layer 82 ensures that the main planarization function is undertaken by the thick first planarization layer 81. The first planarization layer 81 is responsible for completely eliminating the high step difference of the bottom layer, providing a highly flat base surface for all subsequent film layers above it, fundamentally ensuring the uniformity of film thickness in the display area, thereby eliminating display unevenness and color deviation caused by poor planarity.

[0057] A thinner second planarization layer 82 and its corresponding first planarization portion 71 (used to form an undercut) are located on the side of the first planarization layer 81 facing away from the array layer 40. Because the first planarization portion 71 is thin (e.g., thickness 0.3 μm ≤ H1 ≤ 0.6 μm), the vertical step height formed when etching the touch opening K2 is low. This allows the touch electrode 39 to continuously and with low resistance traverse the step and overlap with the underlying connection metal L0. This design ensures reliable overlap of the touch electrode 39 and avoids breakage due to excessively high steps.

[0058] Please continue to refer to this. Figure 7 In one optional embodiment of this disclosure, along the thickness direction of the display panel, the planarization layer 80 includes a first planarization layer 81 and a second planarization layer 82 stacked together. The first planarization layer 81 is located between the second planarization layer 82 and the array layer 40. The touch opening K2 penetrates the pixel definition layer 60 and at least a portion of the second planarization layer 82. The first planarization portion 71 is disposed on the same layer as the second planarization layer 82, and the thickness of the first planarization portion 71 is the same as the thickness of the second planarization layer 82.

[0059] In this embodiment, a first planarization layer 81 and a second planarization layer 82 are introduced below the pixel opening K1. Optionally, the thickness of the first planarization layer 81 is greater than the thickness of the second planarization layer 82. For example, the thickness of the first planarization layer 81 can be greater than or equal to 2.2 μm. This results in a larger thickness of the planarization layer 80 below the pixel opening K1, which can sufficiently planarize the film layer containing the metal traces below the pixel opening K1, i.e., sufficiently planarize the step differences generated by the metal traces. This allows the anode to be formed on a sufficiently flat surface, effectively avoiding the problem of uneven anode caused by uneven structures in the area below the pixel opening K1. Uneven anode can further lead to uneven display or poor color shift, which is beneficial to improving the display uniformity of the display product.

[0060] When the first planar portion 71 and the second planarization layer 82 are disposed on the same layer, the first planar portion 71 can be directly formed when the second planarization layer 82 is fabricated, without the need for photolithography thinning. This avoids the complex and high-risk process of first depositing a thick film and then etching and thinning a local area (i.e., "thinning"), effectively simplifying the photolithography and etching process and reducing manufacturing costs and time.

[0061] Please continue to refer to this. Figure 7 In one optional embodiment of this disclosure, when the second flattening layer 82 and the first flattening portion 71 are disposed in the same layer, the thickness of the first flattening layer 81 is H3, where H3 ≥ 2.2 μm, and the thickness of the second flattening layer 82 is H4, where 0.3 μm ≤ H4 ≤ 0.6 μm.

[0062] Considering that if the thickness of the first planarization layer 81 is too thin, for example, less than 2.2 μm, the total thickness of the first planarization layer 81 and the second planarization layer 82 will be insufficient, making it impossible to completely planarize the step difference caused by the metal traces below the pixel opening K1. This step difference will be transmitted to the upper light-emitting material layer 32 (e.g., the display anode 31 and the light-emitting material layer 32). Uneven thickness of the display anode 31 or the light-emitting material layer 32 will lead to uneven light emission (Mura defects), severely affecting the image quality of the product. Furthermore, uneven thickness of the light-emitting material layer 32 will also affect the consistency of the microcavity structure; changes in the microcavity length will alter the emitted light spectrum, causing color deviations between different pixels and affecting the accuracy of the displayed colors. Therefore, setting the thickness H3 of the first planarization layer 81 to be greater than or equal to 2.2 μm can effectively planarize the step difference caused by the metal traces below the pixel opening K1, ensuring the uniformity of the film thickness of the light-emitting material layer 32, and effectively eliminating Mura defects and color shift problems in the display area.

[0063] For the second planarization layer 82, since the first planarization portion 71 and the second planarization layer 82 are disposed in the same layer, i.e., fabricated in the same process, if its thickness is too small, for example less than 0.3 μm, the process window narrows when the extremely thin organic film is etched to form the undercut structure. Over-etching is likely to occur, leading to distortion of the geometry of the undercut structure and even damage to the underlying connecting metal L0. If its thickness is too large, for example greater than 0.6 μm, the vertical height of the undercut step is too large. The vapor-deposited cathode material (touch electrode 39) cannot continuously and uniformly cross this high step by means of the evaporation angle. The cathode film breaks or thins sharply at the step, resulting in an open circuit or high-resistance connection between the touch electrode 39 and the connecting metal L0, and the touch function fails. Moreover, manufacturing an excessively high step requires more precise etching and a longer deposition time, increasing the risk of process runaway and reducing manufacturing yield. Therefore, the thickness of the second flat layer 82 is set to 0.3μm≤H4≤0.6μm, which makes the vertical height of the undercut structure step moderate. This avoids the cathode (touch electrode 39) film layer breakage or high resistance connection caused by excessive step height, ensures reliable and low resistance electrical connection between touch electrode 39 and connecting metal L0, and effectively reduces the manufacturing difficulty of the undercut structure, which is conducive to improving the manufacturing yield.

[0064] Please continue to refer to this. Figure 7 In one optional embodiment of this disclosure, along the thickness direction of the display panel, the planarization layer 80 includes a first planarization layer 81 and a second planarization layer 82 stacked together. The first planarization layer 81 is located between the second planarization layer 82 and the array layer 40. The touch opening K2 also penetrates through the first planarization layer 81, and the connecting metal L0 is located on the side of the first planarization layer 81 away from the second planarization layer 82.

[0065] In this embodiment, the connecting metal L0 is disposed below the first planarization layer 81. The touch opening K2 penetrates the pixel definition layer 60, the second planarization layer 82, and the first planarization layer 81, exposing the connecting metal L0. This ensures that the subsequently deposited cathode (touch electrode 39) can directly and unobstructedly connect with the connecting metal L0. This direct connection method helps to minimize contact resistance and improve the extraction efficiency and reliability of touch signals. Disposing the connecting metal L0 below the first planarization layer 81, making it closer to the bottom array layer 40, simplifies the routing layout of the connecting metal L0, allowing it to take advantage of the bottom metal routing. At the same time, the opening depth is clear, and the connecting metal L0 can be reached as long as it penetrates all the upper organic films. Based on this, the first planarization layer 81 and the second planarization layer 82 are retained below the pixel opening K1. The total thickness of the first planarization layer 81 and the second planarization layer 82 is relatively large, providing sufficient planarization capability and ensuring the flatness of the anode and light-emitting material layer 32, thereby helping to solve the problems of display uniformity and color shift.

[0066] Figure 7The embodiment illustrates a scheme in which a touch opening K2 penetrates the pixel definition layer 60, the second planarization layer 82, and the first planarization layer 81 to expose a connection metal L0, with the connection metal L0 located on the side of the first planarization layer 81 facing away from the second planarization layer 82. However, this disclosure is not limited thereto. In some other embodiments of this disclosure, the connection metal L0 may also be disposed between the first planarization layer 81 and the second planarization layer 82. For example, please refer to... Figure 8 , Figure 8 The diagram shows another film layer at the pixel opening K1 and touch opening K2 in the display panel provided in this embodiment of the present disclosure. In an optional embodiment of the present disclosure, along the thickness direction of the display panel, the planarization layer 80 includes a first planarization layer 81 and a second planarization layer 82 stacked together. The first planarization layer 81 is located between the second planarization layer 82 and the array layer 40. The touch opening K2 penetrates the pixel definition layer 60 and at least a portion of the second planarization layer 82. The first planarization portion 71 is disposed on the same layer as the second planarization layer 82. Along the thickness direction of the display panel, the first planarization layer 81 overlaps with both the pixel opening K1 and the touch opening K2, and the thickness of the first planarization layer 81 overlapping with both the pixel opening K1 and the touch opening K2 is the same, that is, the touch opening K2 does not penetrate the first planarization layer 81. The connecting metal L0 is located between the first planarization layer 81 and the second planarization layer 82.

[0067] In this embodiment, the thicker first planarization layer 81 is located below the thinner second planarization layer 82, and a complete first planarization layer 81 is provided below both the touch opening K2 and the pixel opening K1. That is, the thickness of the first planarization layer 81 is the same and solid throughout the entire panel area. The first planarization layer 81 undertakes the main planarization function, completely eliminating the step difference caused by the metal traces below it, and providing a highly flat foundation for all the upper film layers, fundamentally solving the problems of uneven display and color shift caused by poor planarity. The connecting metal L0 is placed between the first planarization layer 81 and the second planarization layer 82, and the touch opening K2 only needs to penetrate the pixel definition layer 60 and the second planarization layer 82 to reach the connecting metal L0. This avoids deep etching and greatly reduces the risk of damage to the underlying circuitry. The height of the undercut step is determined by the thin second planarization layer 82. This ensures that the cathode (touch electrode 39) can be continuously and with low resistance, guaranteeing the reliability of the touch function.

[0068] In this embodiment, the depth of the touch opening K2 is limited to the upper pixel definition layer 60 and the second planarization layer 82. The thick first planarization layer 81 is completely preserved below it, serving as the most critical insulating and protective layer, thus avoiding the risk of damage to the array layer 40 caused by deep etching. Simultaneously, it avoids large-area openings and complex etching of the thick first planarization layer 81, simplifying the upper-layer process, improving etching accuracy and yield, and also helping to protect the underlying array layer 40 and wiring structure, enhancing the stability and reliability of the structure.

[0069] Furthermore, in this embodiment, the first flattened portion 71 and the second flattened layer 82 have the same thickness, which allows the first flattened portion 71 to be formed directly when the second flattened layer 82 is fabricated, without the need for secondary photolithography and etching, greatly simplifying the process flow.

[0070] Figure 9 The diagram shown illustrates another type of film layer at the pixel opening K1 and touch opening K2 in the display panel provided in this embodiment. Please refer to [the diagram]. Figure 9 In one optional embodiment of this disclosure, the display panel further includes a first insulating layer 90 and a display anode 31, the first insulating layer 90 and the display anode 31 being located between the planarization layer 80 and the pixel definition layer 60, and the first insulating layer 90 being located between the display anode 31 and the planarization layer 80; the first insulating layer 90 includes a second insulating portion 92, and the pixel opening K1 exposes the display anode 31; along the thickness direction of the display panel, the display anode 31 overlaps with the second insulating portion 92; the first insulating portion 91 is located in the first insulating layer 90.

[0071] In this embodiment, the first insulating layer 90 includes a first insulating portion 91 overlapping with the touch opening K2 and a second insulating portion 92 overlapping with the pixel opening K1. In the area corresponding to the pixel opening K1, the second insulating portion 92 is located below the display anode 31, acting as a buffer protective layer between the planarization layer 80 and the display anode 31, ensuring that the display anode 31 is deposited in an area covered by the second insulating portion 92, rather than directly deposited on the planarization layer 80. The pixel definition layer 60 is located above the display anode 31, with the pixel opening K1 for emitting light and the touch opening K2 for connecting the touch electrode 39 to the connecting metal L0. The first insulating portion 91 is located in the touch opening K2 and is used to form an undercut structure.

[0072] This disclosure introduces a first insulating layer 90 into the display panel. After deposition and curing, the first insulating layer 90 provides a smoother and cleaner surface than the planarization layer 80. The display anode 31 is deposited on this flatter, higher-quality surface, which improves the anode interface quality and reduces leakage current or localized resistance unevenness caused by underlying defects. The high deposition quality of the display anode 31 ensures uniform hole injection in the subsequent hole injection layer, thereby improving the electroluminescence efficiency and brightness uniformity of the OLED device.

[0073] If the second insulating portion 92 below the anode is removed, the etching process of the second insulating portion 92 may over-etch the planarization layer 80 below the anode, causing unevenness in the planarization layer 80, which in turn leads to unevenness in the anode and uneven display. In subsequent process steps, patterned etching (such as plasma etching or ashing) is required on the film layer above the first insulating layer 90 (e.g., the anode, pixel definition layer 60) or the first insulating layer 90 itself. Retaining the first insulating layer 90 (second insulating portion 92) below the anode allows the second insulating portion 92 to act as an etching stop layer or buffer layer, and its material properties differ from the thick planarization layer 80 below. If the first insulating layer 90 is missing or completely removed, the etchant will directly contact the planarization layer 80 below. Due to the lateral etching effect or etching rate difference in the etching process, the planarization layer 80 can easily be over-etched, causing minor unevenness on its surface. This unevenness is transmitted to the upper display anode 31 and light-emitting material layer 32, resulting in uneven film thickness of the light-emitting material layer 32, which ultimately leads to poor Mura or color shift. Therefore, retaining the second insulating portion 92 below the display anode 31 helps to ensure the flatness of the display anode 31 and light-emitting material layer 32, thereby avoiding display unevenness or color shift problems caused by anode unevenness.

[0074] In this disclosure, the first insulating portion 91 for forming the undercut structure is located in the first insulating layer 90. The first insulating portion 91 and the second insulating portion 92 can be formed during the fabrication of the first insulating layer 90, without the need to introduce different fabrication processes for the first insulating portion 91 and the second insulating portion 92, thus simplifying the fabrication process.

[0075] It should be noted that, Figure 9 This embodiment is illustrated using a scenario where the display panel includes a first planarization layer 81 and a second planarization layer 82, and the touch opening K2 penetrates the pixel definition layer 60 and the second planarization layer 82. In this case, a second insulating portion 92 can be retained below the display anode 31, but this is not a limitation. When the touch opening K2 penetrates the pixel definition layer 60, the second planarization layer 82, and the first planarization layer 81, the second insulating portion 92 below the display anode 31 can also be retained, for example, please refer to... Figure 7 Similarly, when the display panel consists of only one planarization layer 80, a second insulating portion 92 can also be retained below the display anode 31, for example, please refer to Figure 10 , Figure 10 The diagram shown is a schematic of another film layer at the pixel opening K1 and touch opening K2 in the display panel provided in this embodiment of the present disclosure, and is consistent with... Figure 5 The difference in the embodiments includes the introduction of a second insulating portion 92 below the display anode 31; other structures can be found elsewhere. Figure 5 The description of the embodiments will not be repeated where necessary.

[0076] Figure 11 The diagram shows one possible arrangement of the touch electrode 39 and the display cathode 33 in a display panel. It should be noted that the specific patterned structure of the cathode layer 30 provided in this embodiment can be selected according to actual conditions; the patterned structure in the accompanying drawings is for illustrative purposes only. Please refer to... Figure 11 In one optional embodiment of this disclosure, the touch electrode 39 includes a plurality of touch electrode blocks 390, and at least two touch electrode blocks 390 are electrically connected via a connecting metal L0. Specifically, one touch electrode block 390 can be electrically connected by overlapping with the connecting metal L0 in the touch opening K2, and another touch electrode block 390 can also be electrically connected by overlapping with the same connecting metal L0 in the touch opening K2, thereby realizing the electrical connection between the two touch electrode blocks 390.

[0077] For example, the touch electrode 39 (typically patterned from the OLED cathode layer 30) is divided into multiple discrete sensing units (e.g., rhomboid blocks, square blocks, etc.). At least two touch electrode blocks 390 are electrically connected via a connecting metal L0. The touch electrode block 390 (e.g., a rhomboid pattern) is the smallest unit that actually senses changes in capacitance when a human touches the object. In a mutual capacitance touch scheme, discrete electrode blocks need to be connected to form touch driving electrodes and touch sensing electrodes; that is, multiple touch electrode blocks 390 can be electrically connected to form touch driving electrodes, while other electrode blocks can be electrically connected to form touch sensing electrodes. The connecting metal L0 acts as a bridge or common trace connecting the various electrode blocks. This layered connection (touch electrode 39 on the cathode layer 30, connecting metal L0 on other film layers) enables the interleaving and cross-layer connection (bridging structure) of touch driving signals and touch sensing signals, thereby realizing the mutual capacitance touch function. Although the touch electrode 39 (cathode) is conductive, its resistivity is typically higher than that of a dedicated low-resistance connecting metal L0 (e.g., a Mo / Al / Ti alloy). Shifting long-distance or critical connection paths to the low-resistance connecting metal L0 reduces signal attenuation and ensures minimal loss of touch signals during transmission. Lower resistance reduces the impact of parasitic capacitance on the signal, improves the signal-to-noise ratio, and reduces RC delay, which is beneficial for ensuring the acquisition speed and uniformity of touch signals on large-size panels. This disclosure utilizes the existing metal layer in OLED manufacturing as a channel for touch wiring (connecting metal L0), achieving the reuse of display and touch functions. Through an undercut structure, the touch electrode block 390 (cathode) can partially overlap with the underlying connecting metal L0, allowing touch traces to be integrated parallel to display pixel traces within the panel, minimizing bezel width and panel thickness.

[0078] Therefore, using a low-resistance connecting metal L0 to pattern and connect the touch electrode blocks 390 of the cathode layer 30 not only provides the structural basis for mutual capacitance touch patterns, but also facilitates low resistance and high signal-to-noise ratio of touch signals on large-size In-cell OLED panels, thereby improving touch performance. Of course, in some other embodiments of this disclosure, the touch electrode 39 may also be embodied as a self-contained touch structure, for example, please refer to Figure 12 , Figure 12 The diagram shows another arrangement of the touch electrode 39 and display cathode 33 in the display panel. The touch electrode 39 includes multiple touch electrode blocks 391. The touch electrode 39 (part of the cathode layer 30) is divided into multiple discrete sensing units (touch electrode blocks 391), and each touch electrode block 391 is electrically connected to a different connecting metal L0. In the self-capacitive structure, each touch electrode block 391 is itself a sensing line. The touch position is determined by measuring the capacitance change of each sensing line relative to ground or to the driving source. The self-capacitive structure requires that each electrode block can be driven and acquire signals independently. "Each touch electrode block 391 is electrically connected to a different connecting metal L0" ensures that each electrode block has its own independent signal path (connecting metal L0), thereby achieving independent sensing and independent addressing. Even in the self-capacitive structure, leading the signal out through the low-resistance connecting metal L0 is much more efficient than directly using the touch electrode 39 (cathode) for long-distance transmission, thus effectively reducing the RC delay and attenuation of the signal. This is especially important for large-size OLED panels, ensuring that the weak capacitive signals collected by the touch electrode 39 can be transmitted to the driver IC at the edge of the panel for processing with high signal-to-noise ratio (SNR) and high fidelity.

[0079] Furthermore, in the self-capacitive structure, the geometry of the touch electrode block 391 is generally regular, only needing to overlap with the underlying independent connecting metal L0 locally through an undercut structure. This design allows for a relatively simple touch electrode 39 pattern (cathode), with the main complex routing work (leading independent signal lines to the edge) handled by the connecting metal L0 layer. This helps maintain the structural integrity of the pixel opening K1 area while achieving highly integrated touch functionality. Therefore, by assigning an independent connecting metal L0 to each touch electrode block 391, independent sensing functionality of the self-capacitive touch is ensured, and the low-resistance auxiliary metal guarantees the efficiency and reliability of touch signal acquisition.

[0080] It should be noted that when the connecting metal L0 is electrically connected to the touch electrode 39, the connecting metal L0 and the pixel opening K1 do not overlap along the thickness direction of the display panel. For example, please refer to... Figure 12In the planar structure, the wiring of the connecting metal L0 avoids the pixel opening K1. Considering that if the wiring of the connecting metal L0 overlaps with the pixel opening K1, the connecting metal L0 would be located on the side of the display anode 31 facing the array layer 40, potentially creating coupling capacitance between the display anode 31 and the connecting metal L0, affecting display accuracy and touch precision. Therefore, setting the connecting metal L0 to not overlap with the pixel opening K1 avoids coupling effects between the touch signal and the signal in the pixel opening K1 area. For example, it prevents the touch signal transmitted by the connecting metal L0 from coupling with the anode signal, and also prevents the anode signal from coupling with the touch signal, thereby improving display reliability and touch precision.

[0081] Please continue to refer to this. Figure 10 , Figure 11 and Figure 12 In one optional embodiment of this disclosure, when both the display cathode 33 and the touch electrode 39 are disposed on the cathode layer 30, the display cathode 33 and the touch electrode 39 are insulated from each other. The insulation in this disclosure is manifested by introducing an isolation gap F between the display cathode 33 and the touch electrode 39. That is, the display cathode 33 and the adjacent touch electrode 39 are disconnected. In practical applications, the isolation gap F can be filled with insulating material.

[0082] In this disclosure, both the display cathode 33 and the touch electrode 39 are located in the cathode layer 30 of the display panel. The display cathode 33 (light-emitting area) and the touch electrode 39 (sensing area) are horizontally insulated from each other. This insulation is typically achieved by precisely etching an isolation gap F in the cathode layer 30 and filling the isolation gap F with an insulating material (e.g., PV, RE, or other protective layer). Although both are located in the same physical layer, the insulation arrangement ensures that there is no direct electrical connection between the pixel driving current (for light emission) and the touch acquisition signal (capacitance change). During light emission, the display cathode 33 is affected by high-frequency driving signals or current fluctuations. Through insulation isolation, these driving noises are isolated in the display cathode 33 area and do not directly couple to the touch electrode 39, thereby significantly improving the touch signal-to-noise ratio.

[0083] If a separate electrode design is used (placing the touch electrode 39 on another layer), additional metal or ITO layers are required, which increases the total film thickness, manufacturing steps, and manufacturing cost. This disclosure maintains a high degree of structural integration by achieving insulating separation on the common cathode layer 30, eliminating the need for additional electrode layers. The display cathode 33 is a key component of the OLED light-emitting structure. Through this insulating arrangement, the patterning of the touch electrode 39 does not affect the working area and electrical performance of the display cathode 33, thereby ensuring the luminous efficiency and uniformity of the display area.

[0084] Therefore, this disclosure, based on the structure of a shared cathode layer 30, achieves functional independence between pixel emission and touch sensing through precise insulation isolation. This significantly improves the touch signal-to-noise ratio, solves the coupling problem of driving noise, and maintains the integration and thickness advantages of the in-cell touch structure.

[0085] It should be noted that, please refer to Figure 12 When the cathode layer 30 is patterned to form the display cathode 33 and the touch electrode 39, to ensure that the display cathode 33 can receive the cathode signal, the display cathode 33 can also be electrically connected to the connecting trace L1 by overlapping, and the cathode signal is transmitted through the connecting trace L1. At this time, the connecting trace L1 and the connecting metal L0 can be located in the same film layer, so that the connecting trace L1 and the connecting metal L0 can be formed in the same production process, and the overlapping area Q1 between the connecting trace L1 and the display cathode 33 can also avoid the pixel opening K1.

[0086] Figure 13 The diagram shown is a schematic representation of a film layer at the pixel opening K1 and touch opening K2 in a display panel provided in this embodiment of the present disclosure. Figure 14 The diagram shown illustrates another arrangement of the touch electrode 39 and the display cathode 33 in the display panel. Please refer to the diagram. Figure 13 and Figure 14 In one optional embodiment of this disclosure, when both the display cathode 33 and the touch electrode 39 are disposed on the cathode layer 30, the display cathode 33 is multiplexed as the touch electrode 39, and no isolation gap is introduced between the touch electrode 39 and the display cathode 33. When the touch electrode 39 forms a plurality of touch electrode blocks 392, in the area corresponding to the touch electrode block 392, the touch electrode block 392 is time-division multiplexed as both the touch electrode 39 and the display cathode 33. The display panel includes a display stage and a touch stage. In the display stage, the display cathode 33 transmits a common voltage signal to drive pixel light emission; in the touch stage, the display cathode 33 transmits a touch signal to sense changes in capacitance.

[0087] In this embodiment, the display cathode 33 and the touch electrode 39 are on the same physical layer, with the display cathode 33 reused as the touch electrode 39. The system switches between the display phase and the touch phase. Since the display cathode 33 and the touch electrode 39 are on the same layer, there is no need to add an additional touch electrode layer. This maintains the thinnest characteristic of the in-cell structure, avoids additional material deposition and patterning steps, and reduces manufacturing costs and process complexity.

[0088] The display phase is a high-power, high-noise phase (pixel driving), during which touch functionality is inactive. The touch phase is a low-power, low-noise phase (signal acquisition), during which the display is either off or held. By staggering operation times, severe coupling interference caused by the simultaneous operation of high-noise pixel driving signals and weak touch sensing signals is avoided, thereby improving the touch signal-to-noise ratio. The system's switching frequency (e.g., a 60Hz display frame rate) is typically much higher than the flicker frequency perceptible to the human eye. Within each frame cycle, the system allocates a very short time (e.g., a few microseconds to a few milliseconds) for touch signal acquisition. Users experience a continuous display visually and real-time touch response operationally, achieving functional compatibility.

[0089] At this point, both self-capacitive and mutual-capacitive touch structures can be implemented. When it is a self-capacitive touch structure, during the touch phase, the patterned touch electrode blocks on the cathode layer are sequentially connected to the acquisition circuit to measure their capacitance to ground. When it is a mutual-capacitive touch structure, during the touch phase, the patterned electrode blocks on the cathode layer are grouped into touch driving lines and touch sensing lines, and driving and acquisition are performed in a time-division manner.

[0090] This embodiment utilizes a time multiplexing mechanism to integrate display light emission and touch sensing functions on the same physical layer (cathode layer 30). This effectively improves the integration of the display panel and solves the key technical problem of signal interference through clever driving timing.

[0091] It should be noted that when the display cathode 33 and the touch electrode 39 are time-division multiplexed, the connecting metal L0 can also be time-division multiplexed. For example, during the display phase, the connecting metal L0 is used to transmit a common voltage signal to the display cathode 33, and during the touch phase, the connecting metal L0 is used to transmit touch signals.

[0092] Based on the same inventive concept, this disclosure also provides a display device. Figure 15 The diagram shown is a structural schematic of a display device 200 provided in an embodiment of this disclosure. Please refer to it. Figure 15 The display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in this disclosure can be any electronic device with touch and display functions, such as a display screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display device 200 provided in this disclosure has the beneficial effects of the display panel provided in this disclosure; for details, please refer to the specific descriptions of the display panel in the above embodiments, which will not be repeated here.

[0093] Understandable, Figure 15The rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it.

[0094] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0095] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: An array layer and a flat layer disposed on one side of the array layer; A pixel definition layer is located on the side of the flat layer opposite to the array layer; Multiple pixel openings and multiple touch openings are provided along the thickness direction of the display panel. The pixel openings penetrate the pixel definition layer, and the touch openings penetrate the pixel definition layer and at least a portion of the planarization layer, and expose the connecting metal. The device includes a light-emitting material layer and a cathode layer, wherein the light-emitting material layer is located at least in the pixel opening, and the cathode layer is located on the side of the light-emitting material layer opposite to the planarization layer; the cathode layer includes a display cathode and a touch electrode, wherein the touch electrode is located at least in the touch opening and is electrically connected to the connecting metal. In the touch opening, the side of the connecting metal facing the pixel definition layer includes a first flat portion and a first insulating portion. The first flat portion is located between the connecting metal and the first insulating portion. Along the thickness direction of the display panel, the edge of the orthographic projection of the first insulating portion is located outside the edge of the orthographic projection of the first flat portion. The first insulating portion and the first flat portion form an undercut space.

2. The display panel according to claim 1, characterized in that, The touch electrode is electrically connected to the connecting metal at least in the undercut space.

3. The display panel according to claim 1, characterized in that, Along the direction parallel to the light-emitting surface of the display panel, the width of the undercut space is S0, 0.3μm≤S0≤0.8μm.

4. The display panel according to claim 1, characterized in that, It also includes a common layer located in the pixel opening and the touch opening; in the touch opening, the thickness of the first flat portion is greater than the thickness of the common layer.

5. The display panel according to claim 4, characterized in that, The thickness of the first flat portion is H1, where 0.3 μm ≤ H1 ≤ 0.6 μm.

6. The display panel according to claim 4, characterized in that, In the undercut space, along the thickness direction of the display panel, the contact area between the touch electrode and the connecting metal is greater than the overlap area between the common layer and the connecting metal.

7. The display panel according to claim 1, characterized in that, The first flat portion is disposed on the same layer as the flat layer, and the flat layer further includes a second flat portion. Along the thickness direction of the display panel, the second flat portion overlaps with the pixel opening but does not overlap with the touch opening; the thickness of the first flat portion is less than the thickness of the second flat portion.

8. The display panel according to claim 7, characterized in that, The thickness of the second flat portion is H2, where H2 ≥ 2.2 μm.

9. The display panel according to claim 1, characterized in that, Along the thickness direction of the display panel, the planarization layer includes a first planarization layer and a second planarization layer stacked together. The first planarization layer is located between the second planarization layer and the array layer. The touch opening penetrates the pixel definition layer and at least a portion of the second planarization layer. The first planarization portion is disposed on the same layer as the second planarization layer.

10. The display panel according to claim 9, characterized in that, The thickness of the first flattened portion is the same as the thickness of the second flattened layer.

11. The display panel according to claim 9, characterized in that, The thickness of the first planarization layer is greater than the thickness of the second planarization layer.

12. The display panel according to claim 11, characterized in that, The thickness of the first planarization layer is H3, where H3 ≥ 2.2 μm, and the thickness of the second planarization layer is H4, where 0.3 μm ≤ H4 ≤ 0.6 μm.

13. The display panel according to claim 9, characterized in that, The touch opening also extends through the first planarization layer, and the connecting metal is located on the side of the first planarization layer opposite to the second planarization layer.

14. The display panel according to claim 9, characterized in that, Along the thickness direction of the display panel, the first planarization layer overlaps with both the pixel opening and the touch opening, and the thickness of the first planarization layer overlapping with the pixel opening and the touch opening is the same; the connecting metal is located between the first planarization layer and the second planarization layer.

15. The display panel according to claim 1, characterized in that, It also includes a first insulating layer and a display anode, the first insulating layer and the display anode being located between the planarization layer and the pixel definition layer, and the first insulating layer being located between the display anode and the planarization layer; the first insulating layer includes a second insulating portion, and the pixel opening exposes the display anode; along the thickness direction of the display panel, the display anode overlaps with the second insulating portion; the first insulating portion is located in the first insulating layer.

16. The display panel according to claim 1, characterized in that, The touch electrode includes multiple touch electrode blocks, and at least two of the touch electrode blocks are electrically connected through the connecting metal.

17. The display panel according to claim 1, characterized in that, Along the thickness direction of the display panel, the connecting metal does not overlap with the pixel opening.

18. The display panel according to claim 1, characterized in that, The display cathode is insulated from the touch electrode.

19. The display panel according to claim 1, characterized in that, The display cathode is reused as a touch electrode, and the display panel includes a display stage and a touch stage. In the display stage, the display cathode transmits a common voltage signal, and in the touch stage, the display cathode transmits a touch signal.

20. A display device, characterized in that, Includes the display panel described in any one of claims 1 to 19.

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