Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit comprises a pixel driving circuit; the plurality of unit columns comprise a plurality of first unit columns and a plurality of second unit columns, the first unit columns are odd-numbered unit columns, the second unit columns are even-numbered unit columns, or the first unit columns are even-numbered unit columns, and the second unit columns are odd-numbered unit columns; the pixel driving circuits in the first unit column are connected with at least one first signal line extending along a first direction (X), and the first signal line is configured to provide an initial signal with a first voltage to the pixel driving circuits in the first unit column; the pixel driving circuits in the second unit column are connected with at least one second signal line extending along a second direction (Y), and the second signal line is configured to provide an initial signal with a second voltage to the pixel driving circuits in the second unit column; the first voltage and the second voltage are different.

Description

Display substrate, preparation method thereof and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit; the plurality of unit columns comprises a plurality of first unit columns and a plurality of second unit columns, the first unit columns are odd unit columns, and the second unit columns are even unit columns, or the first unit columns are even unit columns, and the second unit columns are odd unit columns; the pixel driving circuit in the first unit column is connected with at least one first signal line extending along a first direction, the first signal line is configured to provide an initial signal with a first voltage to the pixel driving circuit in the first unit column; the pixel driving circuit in the second unit column is connected with at least one second signal line extending along a second direction, the second signal line is configured to provide an initial signal with a second voltage to the pixel driving circuit in the second unit column; the first direction and the second direction intersect, and the first voltage and the second voltage are different.

[0006] In an example embodiment, the at least one first signal line includes a first initial signal line configured to provide a first initial signal having a first voltage to the pixel driving circuit in the first unit column; and the at least one second signal line includes a fourth initial signal line configured to provide a first initial signal having a second voltage to the pixel driving circuit in the second unit column.

[0007] In an example embodiment, the pixel driving circuit includes at least a first reset transistor including at least a first reset active layer; the first initial signal line is connected to a first region of the first reset active layer of the pixel driving circuit in the first unit column through a first initial electrode; and the fourth initial signal line is connected to a first region of the first reset active layer of the pixel driving circuit in the second unit column through a fourth initial electrode.

[0008] In an example embodiment, one end of the first initial electrode is connected to the first initial signal line through a via, and the other end of the first initial electrode is connected to the first region of the first reset active layer of the pixel driving circuit in the first unit column through a via; one end of the fourth initial electrode is connected to the fourth initial signal line, and the other end of the fourth initial electrode is connected to the first region of the first reset active layer of the pixel driving circuit in the second unit column through a via.

[0009] In an example embodiment, the display substrate includes a plurality of conductive layers in a direction perpendicular to the display substrate; the first initial signal line and the fourth initial signal line are arranged in different conductive layers; the first initial electrode, the fourth initial electrode, and the fourth initial signal line are arranged in the same conductive layer; and in at least one second circuit unit, the fourth initial electrode and the fourth initial signal line are an integrated structure connected to each other.

[0010] In an example embodiment, at least one unit row further includes a second initial signal line extending along the first direction, the second initial signal line being configured to provide a second initial signal to the pixel driving circuit; and at least one first unit column further includes a second initial connection line extending along the second direction, the second initial connection line being connected to the second initial signal line to form a grid communication structure for transmitting the second initial signal on the display substrate.

[0011] In an example embodiment, the at least one unit row further comprises a third initial signal line extending along the first direction, the third initial signal line being configured to provide a third initial signal to the pixel driving circuit; and the at least one first unit column further comprises a third initial connection line extending along the second direction, the third initial connection line being connected with the third initial signal line, so as to form a grid communication structure for transmitting the third initial signal on the display substrate.

[0012] In an example embodiment, the second initial connection line, the fourth initial signal line, the third initial connection line and the fourth initial signal line are periodically arranged in the first direction.

[0013] In an example embodiment, the at least one first signal line comprises a second initial signal line configured to provide a second initial signal with a first voltage to the pixel driving circuit in the first unit column; and the at least one second signal line comprises a fifth initial signal line configured to provide a second initial signal with a second voltage to the pixel driving circuit in the second unit column.

[0014] In an example embodiment, the pixel driving circuit comprises at least a second reset transistor comprising a second reset active layer; the second initial signal line is connected with a first region of the second reset active layer of the pixel driving circuit in the first unit column through a second initial electrode; and the fifth initial signal line is connected with a first region of the second reset active layer of the pixel driving circuit in the second unit column through a fifth initial electrode.

[0015] In an example embodiment, one end of the second initial electrode is connected with the second initial signal line through a via, and the other end of the second initial electrode is connected with the first region of the second reset active layer of the pixel driving circuit in the first unit column through a via; one end of the fifth initial electrode is connected with the fifth initial signal line, and the other end of the fifth initial electrode is connected with the first region of the second reset active layer of the pixel driving circuit in the second unit column through a via.

[0016] In an example embodiment, in a direction perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers; the second initial signal line and the fifth initial signal line are arranged in different conductive layers, and the second initial electrode, the fifth initial electrode and the fifth initial signal line are arranged in the same conductive layer; and in the at least one second circuit unit, the fifth initial electrode and the fifth initial signal line are an integrated structure connected with each other.

[0017] In an example embodiment, the at least one unit row further comprises a first initial signal line extending along the first direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit; and the at least one first unit column further comprises a first initial connection line extending along the second direction, the first initial connection line being connected with the first initial signal line to form a grid communication structure for transmitting the first initial signal on the display substrate.

[0018] In an example embodiment, the at least one unit row further comprises a third initial signal line extending along the first direction, the third initial signal line being configured to provide a third initial signal to the pixel driving circuit; and the at least one first unit column further comprises a third initial connection line extending along the second direction, the third initial connection line being connected with the third initial signal line to form a grid communication structure for transmitting the third initial signal on the display substrate.

[0019] In an example embodiment, the first initial connection line, the fifth initial signal line, the third initial connection line and the fifth initial signal line are periodically arranged in the first direction.

[0020] In an example embodiment, the at least one first signal line comprises a third initial signal line configured to provide a third initial signal having a first voltage to the pixel driving circuit in the first unit column; and the at least one second signal line comprises a sixth initial signal line configured to provide a third initial signal having a second voltage to the pixel driving circuit in the second unit column.

[0021] In an example embodiment, the pixel driving circuit comprises at least a third reset transistor comprising at least a third reset active layer; the third initial signal line is connected with a first region of the third reset active layer of the pixel driving circuit in the first unit column through a third initial electrode; and the sixth initial signal line is connected with a first region of the third reset active layer of the pixel driving circuit in the second unit column through a sixth initial electrode.

[0022] In an example embodiment, one end of the third initial electrode is connected with the third initial signal line through a via, and the other end of the third initial electrode is connected with the first region of the third reset active layer of the pixel driving circuit in the first unit column through a via; one end of the sixth initial electrode is connected with the sixth initial signal line, and the other end of the sixth initial electrode is connected with the first region of the third reset active layer of the pixel driving circuit in the second unit column through a via.

[0023] In an exemplary embodiment, the display substrate includes a plurality of conductive layers in a direction perpendicular to the display substrate; the third initial signal line and the sixth initial signal line are disposed in different conductive layers, the third initial electrode, the sixth initial electrode and the sixth initial signal line are disposed in the same conductive layer; in at least one second circuit unit, the sixth initial electrode and the sixth initial signal line are an integrated structure connected to each other.

[0024] In an exemplary embodiment, at least one unit row further includes a first initial signal line extending along the first direction, the first initial signal line is configured to provide a first initial signal to the pixel driving circuit; at least one first unit column further includes a first initial connection line extending along the second direction, the first initial connection line is connected with the first initial signal line, forming a grid communication structure for transmitting the first initial signal on the display substrate.

[0025] In an exemplary embodiment, at least one unit row further includes a second initial signal line extending along the first direction, the second initial signal line is configured to provide a second initial signal to the pixel driving circuit; at least one first unit column further includes a second initial connection line extending along the second direction, the second initial connection line is connected with the second initial signal line, forming a grid communication structure for transmitting the second initial signal on the display substrate.

[0026] In an exemplary embodiment, the first initial connection line, the sixth initial signal line, the second initial connection line and the sixth initial signal line are periodically arranged in the first direction.

[0027] In an exemplary embodiment, the display substrate further includes a plurality of light emitting units, the plurality of light emitting units include a red light emitting unit, a blue light emitting unit, a first green light emitting unit and a second green light emitting unit, the red light emitting unit includes a red light emitting device emitting red light, the blue light emitting unit includes a blue light emitting device emitting blue light, the first green light emitting unit includes a first green light emitting device emitting green light, and the second green light emitting unit includes a second green light emitting device emitting green light; the red light emitting device and the blue light emitting device are connected with the pixel driving circuit in the first unit column, the first green light emitting device and the second green light emitting device are connected with the pixel driving circuit in the second unit column; or, the red light emitting device and the blue light emitting device are connected with the pixel driving circuit in the second unit column, and the first green light emitting device and the second green light emitting device are connected with the pixel driving circuit in the first unit column.

[0028] In another aspect, the present disclosure also provides a display device including the aforementioned display substrate.

[0029] In another aspect, the present disclosure also provides a method for manufacturing a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of unit columns comprising a plurality of first unit columns and a plurality of second unit columns, the first unit columns being odd unit columns, the second unit columns being even unit columns, or the first unit columns being even unit columns, the second unit columns being odd unit columns; the method comprising:

[0030] forming a pixel driving circuit in the circuit unit; the pixel driving circuit in the first unit column being connected with at least one first signal line extending along a first direction, the first signal line being configured to provide an initial signal with a first voltage to the pixel driving circuit in the first unit column, the pixel driving circuit in the second unit column being connected with at least one second signal line extending along a second direction, the second signal line being configured to provide an initial signal with a second voltage to the pixel driving circuit in the second unit column; the first direction and the second direction intersecting, the first voltage and the second voltage being different.

[0031] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the detailed description, serve to explain the technical solutions of the present disclosure, but do not constitute limitations on the technical solutions of the present disclosure.

[0033] FIG. 1 is a structural schematic diagram of a display device;

[0034] FIG. 2 is a plan structural schematic diagram of a display substrate;

[0035] FIG. 3 is a cross-sectional structural schematic diagram of a display substrate;

[0036] FIG. 4 is an equivalent circuit schematic diagram of a pixel driving circuit;

[0037] FIG. 5 is a plan structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0038] FIG. 6 is a structural schematic diagram of an initial signal line according to an exemplary embodiment of the present disclosure;

[0039] FIG. 7 is a schematic diagram of a display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0040] FIG. 8A and FIG. 8B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0041] FIG. 9A and FIG. 9B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0042] FIGS. 10A and 10B are schematic diagrams of a display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0043] FIGS. 11A and 11B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to the present disclosure;

[0044] FIG. 12 is a schematic diagram of a display substrate after forming a sixth insulating layer pattern according to the present disclosure;

[0045] FIGS. 13A and 13B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0046] FIG. 14 is a schematic diagram of an initial lead-out line and an initial trace according to an exemplary embodiment of the present disclosure;

[0047] FIG. 15 is a schematic diagram of another planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0048] FIG. 16 is a schematic diagram of another initial signal line according to an exemplary embodiment of the present disclosure;

[0049] FIG. 17 is a schematic diagram of a display substrate after forming a first semiconductor layer pattern according to another exemplary embodiment of the present disclosure;

[0050] FIG. 18 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to another exemplary embodiment of the present disclosure;

[0051] FIG. 19 is a schematic diagram of a display substrate after forming a second conductive layer pattern according to another exemplary embodiment of the present disclosure;

[0052] FIG. 20 is a schematic diagram of a display substrate after forming a second semiconductor layer pattern according to another exemplary embodiment of the present disclosure;

[0053] FIGS. 21A and 21B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to another exemplary embodiment of the present disclosure;

[0054] FIG. 22 is a schematic diagram of a display substrate after forming a sixth insulating layer pattern according to another exemplary embodiment of the present disclosure;

[0055] FIGS. 23A and 23B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to another exemplary embodiment of the present disclosure;

[0056] FIG. 24 is a schematic diagram of another initial lead-out line and another initial trace according to an exemplary embodiment of the present disclosure;

[0057] FIG. 25 is a schematic diagram of another planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0058] FIG. 26 is a schematic diagram of another initial signal line according to an exemplary embodiment of the present disclosure;

[0059] FIG. 27 is a schematic view of another display substrate of the present disclosure after forming a first semiconductor layer pattern;

[0060] FIG. 28 is a schematic view of another display substrate of the present disclosure after forming a first conductive layer pattern;

[0061] FIG. 29 is a schematic view of another display substrate of the present disclosure after forming a second conductive layer pattern;

[0062] FIG. 30 is a schematic view of another display substrate of the present disclosure after forming a second semiconductor layer pattern;

[0063] FIG. 31A and FIG. 31B are schematic views of another display substrate of the present disclosure after forming a third conductive layer pattern;

[0064] FIG. 32 is a schematic view of another display substrate of the present disclosure after forming a sixth insulating layer pattern;

[0065] FIG. 33A and FIG. 33B are schematic views of another display substrate of the present disclosure after forming a fourth conductive layer pattern;

[0066] FIG. 34 is a schematic view of an initial lead-out line and an initial trace according to an exemplary embodiment of the present disclosure.

[0067] Label explanation: 11-first active layer; 12-second active layer; 13-third active layer; 14-fourth active layer; 15-fifth active layer; 16-sixth active layer; 17-seventh active layer; 18-eighth active layer; 21-first scanning signal line; 22-second scanning signal line; 23-third scanning signal line; 24-fourth scanning signal line; 25-emitting signal line; 30-storage capacitor; 31-first plate; 32-second plate; 33-opening; 34-plate connecting strip; 35-shielding line; 41-first initial signal line; 42-second initial signal line; 43-third initial signal line; 44-fourth initial signal line; 45-fifth initial signal line; 46-sixth initial signal line; 51-first connecting electrode; 52-second connecting electrode; 53-third connecting electrode; 54-fourth connecting electrode; 55-fifth connecting electrode; 56-sixth connecting electrode; 57-seventh connecting electrode; 61-first initial connecting line; 62-second initial connecting line; 63-third initial connecting line; 64-first connecting strip; 65-second connecting strip; 66-third connecting strip; 71-first initial electrode; 72-second initial electrode; 73-third initial electrode; 74-fourth initial electrode; 75-fifth initial electrode; 76-sixth initial electrode; 100-display area; 101-substrate; 102-driving structure layer; 103-emitting structure layer; 104-encapsulation structure layer; 200-bonding area; 201-first initial lead-out line; 202-second initial lead-out line; 203-third initial lead-out line; 204-fourth initial lead-out line; 205-fifth initial lead-out line; 206-sixth initial lead-out line; 300-bezel area;301 - first initial wiring; 302 - second initial wiring; 303 - third initial wiring. DETAILED DESCRIPTION

[0068] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It will be easily understood by those skilled in the art that the embodiments and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other on the premise of no conflict.

[0069] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and interval of each film layer, and the width and interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0070] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided in order to avoid confusion of components, and are not intended to be limiting in terms of number.

[0071] In the present specification, in order to facilitate the description and simplify the description, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0072] In the present specification, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0073] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0074] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. In the case of using a transistor having opposite polarity or in the case where the direction of current changes in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0075] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0076] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0077] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0078] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon. There can be some small deformation due to a tolerance, a rounded corner, a curved side, or the like.

[0079] In this specification, "about" means not strictly limited to a limit, and a value within a range of a process and a measurement error is allowed.

[0080] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0081] FIG. 2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 2, a display area can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected with a scan signal line, a light-emitting signal line, and a data signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected with the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0082] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 can be a first green sub-pixel (G1) emitting green light, and the fourth sub-pixel P4 can be a second green sub-pixel (G2) emitting green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG manner.

[0083] In other example embodiments, a pixel unit can include three sub-pixels arranged in a horizontal parallel manner or a vertical parallel manner, and the present disclosure does not limit the same.

[0084] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of four sub-pixels in a display area. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display substrate can include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, and the present disclosure does not limit the same.

[0085] In an example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving structure layer 102 can include a plurality of circuit units, each of which can include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device that can include at least an anode, an organic light-emitting layer, and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulating structure layer 104 can include a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer stacked together, the first encapsulating layer and the third encapsulating layer can be made of inorganic material, and the second encapsulating layer can be made of organic material, the second encapsulating layer being arranged between the first encapsulating layer and the third encapsulating layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0086] FIG. 4 is an equivalent circuit schematic diagram of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit can include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light-emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0087] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0088] In an example embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power supply line VDD.

[0089] In an exemplary embodiment, the first transistor T1 can be referred to as a first reset transistor, the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the third node N3.

[0090] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor, the gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0091] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0092] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0093] In an exemplary embodiment, the fifth transistor T5 can be referred to as a first emission control transistor, the gate electrode of the fifth transistor T5 is connected to the emission signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0094] In an exemplary embodiment, the sixth transistor T6 can be referred to as a second emission control transistor, the gate electrode of the sixth transistor T6 is connected to the emission signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0095] In an exemplary embodiment, the seventh transistor T7 can be referred to as a second reset transistor, the gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0096] In an exemplary embodiment, the eighth transistor T8 can be referred to as a third reset transistor, the gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0097] In an example embodiment, the first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0098] In an example embodiment, the first power supply line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, the second power supply line VSS is configured to provide a constant second voltage signal to the light emitting device, and the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial voltage signal, the second initial voltage signal, and the third initial voltage signal can be constant voltage signals, which are not limited in the present disclosure.

[0099] In an example embodiment, the first transistor T1 to the eighth transistor T8 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 can include P-type transistors and N-type transistors.

[0100] In an example embodiment, the first transistor T1 to the eighth transistor T8 can be a low temperature poly-silicon transistor, or can be an oxide transistor, or can be a low temperature poly-silicon transistor and a metal oxide transistor. The active layer of the low temperature poly-silicon transistor adopts low temperature poly-silicon (LTPS), and the active layer of the metal oxide transistor adopts metal oxide semiconductor (oxide). The low temperature poly-silicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon transistor and the metal oxide transistor on one display substrate forms an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0101] In an example embodiment, the second transistor T2 can be a metal oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be low temperature poly-silicon transistors.

[0102] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary implementation, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit; the plurality of unit columns include a plurality of first unit columns and a plurality of second unit columns, the first unit columns being odd unit columns, the second unit columns being even unit columns, or, the first unit columns being even unit columns, the second unit columns being odd unit columns; the pixel driving circuit in the first unit column is connected with at least one first signal line extending along a first direction, the first signal line being configured to provide an initial signal with a first voltage to the pixel driving circuit in the first unit column; the pixel driving circuit in the second unit column is connected with at least one second signal line extending along a second direction, the second signal line being configured to provide an initial signal with a second voltage to the pixel driving circuit in the second unit column; the first direction and the second direction intersect, and the first voltage and the second voltage are different.

[0103] In an exemplary implementation, the at least one first signal line includes a first initial signal line configured to provide a first initial signal with a first voltage to the pixel driving circuit in the first unit column; and the at least one second signal line includes a fourth initial signal line configured to provide a first initial signal with a second voltage to the pixel driving circuit in the second unit column.

[0104] In an exemplary implementation, the at least one first signal line includes a second initial signal line configured to provide a second initial signal with a first voltage to the pixel driving circuit in the first unit column; and the at least one second signal line includes a fifth initial signal line configured to provide a second initial signal with a second voltage to the pixel driving circuit in the second unit column.

[0105] In an exemplary implementation, the at least one first signal line includes a third initial signal line configured to provide a third initial signal with a first voltage to the pixel driving circuit in the first unit column; and the at least one second signal line includes a sixth initial signal line configured to provide a third initial signal with a second voltage to the pixel driving circuit in the second unit column.

[0106] In an example embodiment, the display substrate further includes a plurality of light emitting units, the plurality of light emitting units including a red light emitting unit, a blue light emitting unit, a first green light emitting unit, and a second green light emitting unit, the red light emitting unit including a red light emitting device emitting red light, the blue light emitting unit including a blue light emitting device emitting blue light, the first green light emitting unit including a first green light emitting device emitting green light, and the second green light emitting unit including a second green light emitting device emitting green light; the red light emitting device and the blue light emitting device are connected with the pixel driving circuit in the first unit column, the first green light emitting device and the second green light emitting device are connected with the pixel driving circuit in the second unit column; or, the red light emitting device and the blue light emitting device are connected with the pixel driving circuit in the second unit column, the first green light emitting device and the second green light emitting device are connected with the pixel driving circuit in the first unit column.

[0107] The display substrate of the present embodiment is illustrated below by some examples.

[0108] In an example embodiment, in a direction parallel to the plane of the display substrate, the display substrate of the present disclosure can include at least a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area. In a direction perpendicular to the display substrate, the display substrate of the present disclosure can include at least a driving structure layer disposed on a substrate, a light emitting structure layer disposed on the side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light emitting structure layer away from the substrate. The driving structure layer of the display area can include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit can include a pixel driving circuit configured to output a corresponding current to the connected light emitting device. The light emitting structure layer of the display area can include a plurality of light emitting units, and at least one light emitting unit can include a light emitting device connected with the pixel driving circuit of the corresponding circuit unit, and the light emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0109] In an example embodiment, the plurality of light emitting units can include a red light emitting unit, a blue light emitting unit, a first green light emitting unit, and a second green light emitting unit, the red light emitting unit can include a red light emitting device emitting red light, the blue light emitting unit can include a blue light emitting device emitting blue light, the first green light emitting unit can include a first green light emitting device emitting green light, and the second green light emitting unit can include a second green light emitting device emitting green light.

[0110] In an example embodiment, the circuit unit in the present disclosure refers to a region divided according to a pixel driving circuit, and the light emitting unit in the present disclosure refers to a region divided according to a light emitting device. In an example embodiment, the position of the light emitting unit orthogonally projected on the substrate can correspond to the position of the circuit unit orthogonally projected on the substrate, or the position of the light emitting unit orthogonally projected on the substrate can not correspond to the position of the circuit unit orthogonally projected on the substrate.

[0111] In an example embodiment, the plurality of circuit units arranged in sequence along the first direction X can be referred to as a unit row, the plurality of circuit units arranged in sequence along the second direction Y can be referred to as a unit column, the plurality of unit rows and the plurality of unit columns form an array of circuit units arranged in an array, and the first direction X and the second direction Y intersect.

[0112] In an example embodiment, the plurality of unit columns in the display substrate can include a plurality of first unit columns and a plurality of second unit columns, the first unit columns and the second unit columns can each include a plurality of circuit units arranged in sequence along the second direction Y, and the plurality of first unit columns and the plurality of second unit columns can be alternately arranged in the first direction X.

[0113] In an example embodiment, the first unit column can be an odd unit column, and the second unit column can be an even unit column. In another example embodiment, the first unit column can be an even unit column, and the second unit column can be an odd unit column.

[0114] In an example embodiment, the plurality of pixel driving circuits in the first unit column can be respectively connected with a red light emitting device emitting red light and a blue light emitting device emitting blue light, and the plurality of pixel driving circuits in the second unit column can be respectively connected with a first green light emitting device emitting green light and a second green light emitting device emitting green light. In another example embodiment, the plurality of pixel driving circuits in the first unit column can be respectively connected with a first green light emitting device emitting green light and a second green light emitting device emitting green light, and the plurality of pixel driving circuits in the second unit column can be respectively connected with a red light emitting device emitting red light and a blue light emitting device emitting blue light.

[0115] FIG. 5 is a schematic diagram of a planar structure of a display substrate according to an example embodiment of the present disclosure, illustrating the structure of 8 circuit units (2 unit rows and 4 unit columns), the Nth unit column and the N+2th unit column are first unit columns, and the N+1th unit column and the N+3th unit column are second unit columns.

[0116] In the example embodiment, the pixel driving circuits in the two unit columns can be connected with the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41 and the third initial signal line 43 respectively, the pixel driving circuits in the first unit column are connected with the second initial signal line 42, and the pixel driving circuits in the second unit column are connected with the fifth initial signal line 45.

[0117] In the example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 can be in a linear or zigzag shape with the main part extending along the first direction X, and the fifth initial signal line 45 can be in a linear or zigzag shape with the main part extending along the second direction Y.

[0118] In the present disclosure, A extending along B direction means that A can include a main part and a secondary part connected with the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. In the following description, A extending along B direction means that the main part of A extending along B direction.

[0119] In the example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24 and the light-emitting signal line 25 are configured to provide the pixel driving circuits with the first scan signal, the second scan signal, the third scan signal, the fourth scan signal and the light-emitting control signal respectively, and the first initial signal line 41 and the third initial signal line 43 are configured to provide the pixel driving circuits with the first initial signal and the third initial signal respectively. The plurality of signal lines connected with the pixel driving circuits can be located within the corresponding circuit unit.

[0120] In the example embodiment, the pixel driving circuit can also be connected with a data signal line and a first power supply line, the data signal line is configured to provide the pixel driving circuit with a data signal, and the first power supply line is configured to provide the pixel driving circuit with a first power supply signal, which is not limited in the present disclosure.

[0121] In the example embodiment, the second initial signal line 42 extending along the first direction X can serve as the first signal line of the present disclosure, and the second initial signal line 42 is configured to provide the second initial signal with the first voltage to the pixel driving circuit in the first unit column; the fifth initial signal line 45 extending along the second direction Y can serve as the second signal line of the present disclosure, and the fifth initial signal line 45 is configured to provide the second initial signal with the second voltage to the pixel driving circuit in the second unit column, the first voltage and the second voltage being different.

[0122] In the example embodiment, in the at least one circuit unit, the fourth scan signal line 24 can be disposed on the side of the storage capacitor 30 in the opposite direction of the second direction Y, and the first scan signal line 21 can be disposed on the side of the fourth scan signal line 24 away from the storage capacitor 30. The light emission signal line 25 can be disposed on the side of the storage capacitor 30 in the second direction Y, the second scan signal line 22 can be disposed on the side of the light emission signal line 25 away from the storage capacitor 30, and the third scan signal line 23 can be disposed on the side of the second scan signal line 22 away from the storage capacitor 30.

[0123] In the example embodiment, in the at least one circuit unit, the orthographic projection of the first initial signal line 41 on the substrate at least partially overlaps the orthographic projection of the light emission signal line 25 on the substrate, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps the orthographic projection of the third scan signal line 23 on the substrate, and the orthographic projection of the second scan signal line 22 on the substrate at least partially overlaps the orthographic projection of the third initial signal line 43 on the substrate.

[0124] In the example embodiment, the at least one pixel driving circuit can include the storage capacitor 30 and a plurality of transistors. The storage capacitor can include a first plate and a second plate stacked, and the plurality of transistors can include a first transistor T1 serving as a first reset transistor, a second transistor T2 serving as a compensation transistor, a third transistor T3 serving as a driving transistor, a fourth transistor T4 serving as a data writing transistor, a fifth transistor T5 serving as a first light emission control transistor, a sixth transistor T6 serving as a second light emission control transistor, a seventh transistor T7 serving as a second reset transistor, and an eighth transistor T8 serving as a third reset transistor. Among them, the second transistor T2 can be a metal oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be low-temperature polysilicon transistors.

[0125] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line 23, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, and the first electrode of the second transistor T2 and the first plate of the storage capacitor (which is also the gate electrode of the third transistor T3) are connected. The first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected to the data signal line. The gate electrode of the fifth transistor T5 is connected to the emission signal line 25, and the first electrode of the fifth transistor T5 is connected to the first power supply line. The gate electrode of the sixth transistor T6 is connected to the emission signal line 25, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, the gate electrode of the seventh transistor T7 is connected to the second scan signal line 22, the gate electrode of the eighth transistor T8 is connected to the second scan signal line 22, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0126] In the exemplary embodiment, the first electrode of the seventh transistor T7 of the pixel driving circuit in the first unit column is connected to the second initial signal line 42, and the first electrode of the seventh transistor T7 of the pixel driving circuit in the second unit column is connected to the fifth initial signal line 45.

[0127] FIG. 6 is a schematic diagram of a structure of an initial signal line according to an exemplary embodiment of the present disclosure. As shown in FIGS. 5 and 6, at least one circuit unit in the first unit column can further include a second initial electrode 72, at least one circuit unit in the second unit column can further include a fifth initial electrode 75, and the seventh transistor T7 as the second reset transistor can include at least a seventh active layer 17 as a second reset active layer. The second initial signal line 42 can be connected to the first region of the seventh active layer 17 of the pixel driving circuit in the first unit column through the second initial electrode 72, and the fifth initial signal line 45 can be connected to the first region of the seventh active layer 17 of the pixel driving circuit in the second unit column through the fifth initial electrode 75.

[0128] In the exemplary embodiment, the second initial electrode 72 can have a strip shape extending along the second direction Y, one end of the second initial electrode 72 can be connected to the second initial signal line 42 through a via, and the other end of the second initial electrode 72 can be connected to the first region of the seventh active layer 17 of the pixel driving circuit in the first unit column through a via.

[0129] In an exemplary embodiment, the fifth initial electrode 75 can have a strip shape extending along the first direction X, one end of the fifth initial electrode 75 is directly connected to the fifth initial signal line 45, and the other end of the fifth initial electrode 75 is connected to the first region of the seventh active layer 17 of the pixel driving circuit in the second unit column through a via.

[0130] In an exemplary embodiment, the display substrate can include a plurality of conductive layers in a direction perpendicular to the display substrate. The second initial signal line 42 and the fifth initial signal line 45 can be disposed in different conductive layers, and the fifth initial signal line 45, the second initial electrode 72, and the fifth initial electrode 75 can be disposed in the same conductive layer.

[0131] In an exemplary embodiment, the fifth initial signal line 45 and the fifth initial electrode 75 can be an integrated structure connected to each other in at least one circuit unit.

[0132] In an exemplary embodiment, the first transistor T1 as the first reset transistor can include at least the first active layer 11 as the first reset active layer. In at least one unit row, the first initial signal line 41 can be connected to the first region of the first active layer 11 through the first initial electrode 71.

[0133] In an exemplary embodiment, the at least one first unit column can further include a first initial connection line 61. The first initial connection line 61 can have a straight line shape or a broken line shape with a main body portion extending along the second direction Y, and be connected to the first initial electrode 71 through the first connection strip 64, thereby achieving connection between the first initial signal line 41 and the first initial connection line 61 and forming a mesh communication structure for transmitting the first initial signal on the display substrate.

[0134] In an exemplary embodiment, the eighth transistor T8 as the third reset transistor can include at least the eighth active layer 18 as the third reset active layer. In at least one unit row, the third initial signal line 43 can be connected to the first region of the eighth active layer 18 through the third initial electrode 73.

[0135] In an exemplary embodiment, the at least one first unit column can further include a third initial connection line 63. The third initial connection line 63 can have a straight line shape or a broken line shape with a main body portion extending along the second direction Y, and be connected to the third initial electrode 73 through the third connection strip 66, thereby achieving connection between the third initial signal line 43 and the third initial connection line 63 and forming a mesh communication structure for transmitting the third initial signal on the display substrate.

[0136] In the exemplary embodiment, the first initial connection line 61, the fifth initial signal line 45, the third initial connection line 63, and the fifth initial signal line 45 can be periodically arranged in the first direction X.

[0137] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, and the like for metal materials, inorganic materials, or transparent conductive materials, and includes coating organic materials, mask exposure, and development, and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, and chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating, and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating, or other processes. If the "thin film" does not need a patterning process in the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0138] In the exemplary embodiment, taking 8 circuit units of 2 unit rows (Mth unit row and M+1th unit row) and 4 unit columns (Nth unit column to N+3th unit column) as an example, the preparation process of the display substrate can include the following operations. Among them, the Nth unit column and the N+2th unit column are the first unit column, and the N+1th unit column and the N+3th unit column are the second unit column.

[0139] (11) Forming a first semiconductor layer pattern. In the exemplary embodiment, forming the first semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a first semiconductor thin film on the substrate, patterning the first semiconductor thin film by a patterning process, forming a first insulating layer arranged on the substrate, and a first semiconductor layer pattern arranged on the first insulating layer, as shown in FIG. 7.

[0140] In the exemplary embodiment, the first semiconductor layer pattern of each circuit unit in the display substrate can include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are integrally connected, and the first active layer 11 and the eighth active layer 18 are separately provided.

[0141] In the exemplary embodiment, in the first direction X, the first active layer 11 and the sixth active layer 16 can be located on one side of the third active layer 13 in the present circuit unit, and the fourth active layer 14 and the fifth active layer 15 can be located on the other side of the third active layer 13 in the present circuit unit. In the second direction Y, the fourth active layer 14 can be located on one side of the third active layer 13 in the present circuit unit in the opposite direction of the second direction Y, and the first active layer 11, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 can be located on one side of the third active layer 13 in the present circuit unit in the second direction Y.

[0142] In the exemplary embodiment, the third active layer 13 can have an inverted "Ω" shape, the first active layer 11, the fourth active layer 14, and the fifth active layer 15 can have an "I" shape, and the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 can have an "L" shape.

[0143] In the exemplary embodiment, the first active layer 11, the third active layer 13 to the eighth active layer 18 can each include a first region, a second region, and a channel region between the first region and the second region. In the exemplary embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer can be connected to each other, and the first region 13-1 of the third active layer can simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer can be connected to each other, and the second region 13-2 of the third active layer can serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer can be separately provided.

[0144] In an example embodiment, the first active layer 11 is arranged across adjacent cell rows, a first region 11-1 of the first active layer is arranged in a current cell row, and a second region 11-2 of the first active layer is arranged in a next cell row.

[0145] In an example embodiment, in a cell row, the first active layer 11 in part of adjacent circuit units can be an integrated structure connected to each other, and the first active layer 11 in two circuit units can share a same first region 11-1 of the first active layer. For example, the fifth active layer in the Nth unit column and the first active layer in the N+1th unit column can be an integrated structure connected to each other. For another example, the fifth active layer in the N+2th unit column and the first active layer in the N+3th unit column can be an integrated structure connected to each other. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by arranging the first transistor T1 in adjacent circuit units in a mirror arrangement and sharing the first region of the first active layer. In addition, by forming the first active layer in part of adjacent circuit units into an integrated structure connected to each other, the first electrode of the first transistor T1 in part of adjacent circuit units can have the same potential, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0146] In an example embodiment, in a cell row, the fifth active layer 15 in part of adjacent circuit units can be an integrated structure connected to each other, and the fifth active layer 15 in two circuit units can share a same first region 15-1 of the fifth active layer. For example, the fifth active layer in the N-1th unit column and the fifth active layer in the Nth unit column can be an integrated structure connected to each other. For another example, the fifth active layer in the N+1th unit column and the fifth active layer in the N+2th unit column can be an integrated structure connected to each other. For another example, the fifth active layer in the N+3th unit column and the fifth active layer in the N+4th unit column can be an integrated structure connected to each other. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by arranging the fifth transistor T5 in adjacent circuit units in a mirror arrangement and sharing the first region of the fifth active layer. In addition, by forming the fifth active layer in part of adjacent circuit units into an integrated structure connected to each other, the first electrode of the fifth transistor T5 in part of adjacent circuit units can have the same potential, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0147] In the exemplary embodiments, the eighth active layers 18 in some adjacent circuit units in one unit row can be an integrated structure connected to each other, and the eighth active layers 18 in two circuit units can share the same first region 18-1 of the eighth active layer. For example, the eighth active layer of the N-1th unit column and the eighth active layer of the Nth unit column can be an integrated structure connected to each other. For another example, the eighth active layer of the N+1th unit column and the eighth active layer of the N+2th unit column can be an integrated structure connected to each other. For another example, the eighth active layer of the N+3th unit column and the eighth active layer of the N+4th unit column can be an integrated structure connected to each other. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connection electrodes, reduce the area occupied by the pixel driving circuit, and facilitate the realization of high resolution by setting the eighth transistor T8 in adjacent circuit units to be mirror-set and share the first region of the eighth active layer. In addition, since the first region 18-1 of the eighth active layer in each circuit unit is configured to be connected to the third initial signal line formed subsequently, by forming the first region 18-1 of the eighth active layer of some adjacent circuit units into an integrated structure connected to each other, the first electrode of the eighth transistor T8 in some adjacent circuit units can have the same potential, which is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0148] In the exemplary embodiments, the first semiconductor layers of adjacent unit columns can be mirror-symmetrical relative to the column boundary line. For example, the first semiconductor layer of the Nth unit column and the first semiconductor layer of the N+1th unit column can be mirror-symmetrical relative to the column boundary line. For another example, the first semiconductor layer of the N+1th unit column and the first semiconductor layer of the N+2th unit column can be mirror-symmetrical relative to the column boundary line. For another example, the first semiconductor layer of the N+2th unit column and the first semiconductor layer of the N+3th unit column can be mirror-symmetrical relative to the column boundary line. In the exemplary embodiments, the shapes of the first semiconductor layers in the plurality of unit rows can be substantially the same.

[0149] In the exemplary embodiments, the first semiconductor layer can be polycrystalline silicon (p-Si), i.e., the first transistor T1, the third transistor T3 to the eighth transistor T8 are LTPS transistors. In the exemplary embodiments, the patterning process of the first semiconductor thin film can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, dehydrogenating the amorphous silicon thin film, and crystallizing the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a first semiconductor layer pattern.

[0150] (12) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the first conductive thin film by a patterning process, forming a second insulating layer covering the first semiconductor layer pattern, and forming the first conductive layer pattern on the second insulating layer, as shown in FIGS. 8A and 8B, which is a plan view of the first conductive layer in FIG. 8A. In an exemplary embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0151] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate at least includes: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light-emitting signal line 25, and a first plate 31 of a storage capacitor.

[0152] In an exemplary embodiment, the first plate 31 can have a rectangular shape, and a corner of the rectangular shape can be chamfered. A normal projection of the first plate 31 on the substrate at least partially overlaps a normal projection of a third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first plate 31 can simultaneously serve as a lower plate of the storage capacitor and a gate electrode of the third transistor T3.

[0153] In an exemplary embodiment, the first scan signal line 21 can have a straight line shape or a broken line shape in which a main body portion extends along the first direction X. The first scan signal line 21 can be located on a side opposite to the second direction Y of the first plate 31. An area in which the first scan signal line 21 overlaps the fourth active layer can serve as a gate electrode of the fourth transistor T4, and thus the first scan signal line 21 can control on or off of the fourth transistor T4.

[0154] In an exemplary embodiment, the second scan signal line 22 can have a straight line shape or a broken line shape in which a main body portion extends along the first direction X. The second scan signal line 22 can be located on a side of the second direction Y of the first plate 31. An area in which the second scan signal line 22 overlaps the seventh active layer can serve as a gate electrode of the seventh transistor T7, and an area in which the second scan signal line 22 overlaps the eighth active layer can serve as a gate electrode of the eighth transistor T8, and thus the second scan signal line 22 can control on or off of the seventh transistor T7 and the eighth transistor T8.

[0155] In an example embodiment, the third scan signal line 23 can have a shape of a straight line or a broken line with a main body extending along the first direction X. The third scan signal line 23 can be located on a side of the second scan signal line 22 away from the first plate 31. An area of the third scan signal line 23 overlapping the first active layer can serve as a gate electrode of the first transistor T1, so that the third scan signal line 23 can control the first transistor T1 to be turned on or turned off.

[0156] In an example embodiment, the light emission signal line 25 can have a shape of a straight line or a broken line with a main body extending along the first direction X. The light emission signal line 25 can be located between the second scan signal line 22 and the first plate 31. An area of the light emission signal line 25 overlapping the fifth active layer can serve as a gate electrode of the fifth transistor T5, and an area of the light emission signal line 25 overlapping the sixth active layer can serve as a gate electrode of the sixth transistor T6, so that the light emission signal line 25 can control the fifth transistor T5 and the sixth transistor T6 to be turned on or turned off.

[0157] In an example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can have a non-equal width design, with the width being a dimension in the second direction Y. This can facilitate the layout of the pixel structure and reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0158] In an example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can include an area overlapping the first semiconductor layer and an area not overlapping the first semiconductor layer. The width of the signal line in the area overlapping the first semiconductor layer can be greater than the width of the signal line in the area not overlapping the first semiconductor layer.

[0159] In an example embodiment, the first conductive layer of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the first conductive layer of the Nth unit column and the first conductive layer of the N+1th unit column can be mirror-symmetrical with respect to the column boundary line. For another example, the first conductive layer of the N+1th unit column and the first conductive layer of the N+2th unit column can be mirror-symmetrical with respect to the column boundary line. For another example, the first conductive layer of the N+2th unit column and the first conductive layer of the N+3th unit column can be mirror-symmetrical with respect to the column boundary line. In an example embodiment, the shape of the first conductive layer in the plurality of unit rows can be substantially the same.

[0160] In the exemplary embodiments, after the first conductive layer pattern is formed, the first semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield, the first semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 and the third to eighth transistors T3 to T8, and the first semiconductor layer in the region not shielded by the first conductive layer is conductorized, i.e., the first regions and the second regions of the first active layer, the third active layer, and the third to eighth active layers are conductorized.

[0161] (13) Forming a second conductive layer pattern. In the exemplary embodiments, forming the second conductive layer pattern can include sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the second conductive thin film using a patterning process, forming a third insulating layer covering the first conductive layer, and forming the second conductive layer pattern on the third insulating layer, as shown in FIGS. 9A and 9B, which are a plan view of the second conductive layer in FIG. 9A. In the exemplary embodiments, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0162] In the exemplary embodiments, the second conductive layer pattern of each circuit unit in the display substrate at least includes a second plate 32 of a storage capacitor and a shield line 35.

[0163] In the exemplary embodiments, the second plate 32 can have a rectangular shape, and the corners of the rectangular shape can be chamfered. The orthographic projection of the second plate 32 on the substrate at least partially overlaps the orthographic projection of the first plate 31 on the substrate, and the second plate 32 can serve as the upper plate of the storage capacitor, and the first plate 31 and the second plate 32 constitute the storage capacitor of the pixel driving circuit.

[0164] In the exemplary embodiments, the second plate 32 is provided with an opening 33, and the opening 33 can have a rectangular shape and can be located in the middle of the second plate 32, so that the second plate 32 forms a ring structure. The opening 33 exposes the third insulating layer covering the first plate 31, and the orthographic projection of the first plate 31 on the substrate contains the orthographic projection of the opening 33 on the substrate. In the exemplary embodiments, the opening 33 is configured to accommodate a thirteenth via hole formed later, the thirteenth via hole is located in the opening 33 and exposes the first plate 31, so that a first connection electrode formed later is connected to the first plate 31.

[0165] In the exemplary embodiments, the second plate 32 can be provided with a plate connection strip 34. The plate connection strip 34 can have a strip shape extending along the first direction X, and the plate connection strip 34 can be arranged on one side of the second plate 32 in the first direction X or on the side opposite to the first direction X. The first end of the plate connection strip 34 is connected to the second plate 32 in the present circuit unit, and the second end of the plate connection strip 34 is connected to the second plate 32 in the adjacent circuit unit in the first direction X.

[0166] In an exemplary embodiment, the second plate 32 and the plate connecting strip 34 in at least one circuit unit can be an integrated structure connected to each other.

[0167] In an exemplary embodiment, the second plates 32 in part of two adjacent circuit units in one unit row can be an integrated structure connected to each other. For example, the second plate 32 of the N-1 unit column and the second plate 32 of the N unit column can be connected to each other through the plate connecting strip 34 to form an integrated structure connected to each other. For another example, the second plate 32 of the N+1 unit column and the second plate 32 of the N+2 unit column can be connected to each other through the plate connecting strip 34 to form an integrated structure connected to each other. For another example, the second plate 32 of the N+3 unit column and the second plate 32 of the N+4 unit column can be connected to each other through the plate connecting strip 34 to form an integrated structure connected to each other. Since the second plate 32 in each circuit unit is connected to the first power supply line formed subsequently, by forming the second plates 32 of part of the adjacent circuit units into an integrated structure connected to each other, the second plates of the integrated structure can be reused as the power supply signal line, which can ensure that the second plates of the adjacent circuit units have the same potential, and is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0168] In an exemplary embodiment, the shielding line 35 can be a straight line or a broken line extending along the first direction X in the main body part, and can be located between the first scan signal line 21 and the second plate 32. The shielding line 35 is configured as a shielding layer of the second transistor T2, shields the channel region of the second transistor T2, ensures the electrical performance of the oxide second transistor T2, and is also configured as the bottom gate electrode of the second transistor T2.

[0169] In an exemplary embodiment, the shielding line 35 can be designed to have a non-equal width, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines.

[0170] In an exemplary embodiment, the second conductive layer of the adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the second conductive layer of the N unit column and the second conductive layer of the N+1 unit column can be mirror-symmetrical with respect to the column boundary line, the second conductive layer of the N+1 unit column and the second conductive layer of the N+2 unit column can be mirror-symmetrical with respect to the column boundary line, and the second conductive layer of the N+2 unit column and the second conductive layer of the N+3 unit column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the shapes of the second conductive layers in the plurality of unit rows can be substantially the same.

[0171] (14) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a fourth insulating thin film and a second semiconductor thin film, patterning the second semiconductor thin film by a patterning process, forming a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIGS. 10A and 10B, FIG. 10B being a plan view of the second semiconductor layer in FIG. 10A.

[0172] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit in the display substrate at least includes a second active layer 12 of a second transistor T2.

[0173] In an exemplary embodiment, the second active layer 12 can have an "L" shape, and a normal projection of the second active layer 12 on the substrate at least partially overlaps a normal projection of the shield line 35 on the substrate.

[0174] In an exemplary embodiment, a first region 12-1 of the second active layer can be located on a side of the shield line 35 away from the second plate 32, and a second region 12-2 of the second active layer can be located on a side of the shield line 35 close to the second plate 32.

[0175] In an exemplary embodiment, the second semiconductor layer of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the second semiconductor layer of the Nth unit column and the second semiconductor layer of the N+1th unit column can be mirror-symmetrical with respect to the column boundary line, the second semiconductor layer of the N+1th unit column and the second semiconductor layer of the N+2th unit column can be mirror-symmetrical with respect to the column boundary line, and the second semiconductor layer of the N+2th unit column and the second semiconductor layer of the N+3th unit column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the shape of the second semiconductor layer in the plurality of unit rows can be substantially the same.

[0176] In an exemplary embodiment, the second semiconductor layer can be an oxide, i.e., the second transistor T2 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film can be indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.

[0177] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: on a substrate on which the aforementioned pattern is formed, sequentially depositing a fifth insulating thin film and a third conductive thin film, patterning the third conductive thin film by a patterning process, forming a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIGS. 11A and 11B, FIG. 11B being a plan view of the third conductive layer in FIG. 11A. In an exemplary embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0178] In the example embodiment, the third conductive layer pattern of each circuit unit in the display substrate at least includes a fourth scan signal line 24, a first initial signal line 41, a second initial signal line 42, and a third initial signal line 43.

[0179] In the example embodiment, the fourth scan signal line 24 can be in a straight line shape or a zigzag shape with a main body extending along the first direction X, the fourth scan signal line 24 can be located between the first scan signal line 21 and the second plate 32, and the area where the fourth scan signal line 24 overlaps the second active layer can serve as the gate electrode of the second transistor T2, so that the fourth scan signal line 24 can control the on or off of the second transistor T2.

[0180] In the example embodiment, the fourth scan signal line 24 and the shielding line 35 can be connected to the same signal source, so that the shielding line 35 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming the second transistor T2 in a top gate bottom gate structure.

[0181] In the example embodiment, the first initial signal line 41 can be in a straight line shape or a zigzag shape with a main body extending along the first direction X, and the first initial signal line 41 can be located between the second scan signal line 22 and the first plate 31. The fourth scan signal line 24 and the shielding line 35 can be connected to the same signal source, so that the shielding line 35 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming the second transistor T2 in a top gate bottom gate structure.

[0182] In the example embodiment, the first initial signal line 41 can be provided with a first initial connection block 41-1, and the first initial connection block 41-1 can be in a block shape (e.g., a rectangular shape). In the first direction X, the first initial connection block 41-1 can be arranged between part of the adjacent circuit units, and in the second direction Y, the first initial connection block 41-1 can be arranged on the side of the first initial signal line 41 close to the second plate 32 and connected to the first initial signal line 41. In the example embodiment, the first initial connection block 41-1 is configured to be connected to the first region of the first active layer through the first initial electrode formed subsequently.

[0183] In the example embodiment, the first initial signal line 41 and the plurality of first initial connection blocks 41-1 in one unit row can be an integrated structure connected to each other.

[0184] In the example embodiment, two circuit units that are partially adjacent in one unit row can share one same first initial connection block 41-1. For example, two circuit units in the Nth unit column and the (N+1)th unit column can share one same first initial connection block 41-1. For another example, two circuit units in the (N+2)th unit column and the (N+3)th unit column can share one same first initial connection block 41-1. The present disclosure can effectively reduce the lateral layout space, reduce the number of vias and connection electrodes, reduce the area occupied by the pixel driving circuit, and facilitate the realization of high resolution by arranging the first initial connection block 41-1 to be shared by the partially adjacent circuit units.

[0185] In the example embodiment, the second initial signal line 42 can have a shape of a straight line or a broken line with a main body extending along the first direction X, and the second initial signal line 42 can be located on the side of the second scan signal line 22 away from the second plate 32. The orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps the orthographic projection of the third scan signal line 23 on the substrate, and the second initial signal line 42 transmitting a constant voltage can shield the influence of the third scan signal line 23 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0186] In the example embodiment, the second initial signal line 42 can be provided with a second initial connection block 42-1, the second initial connection block 42-1 can have a shape of a block (e.g., a rectangle), and the second initial connection block 42-1 can be arranged on the side of the second initial signal line 42 close to the second plate 32 and connected to the second initial signal line 42. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer through the second initial electrode formed subsequently.

[0187] In the example embodiment, the second initial connection block 42-1 can be arranged in the circuit units of the first unit column. For example, the second initial connection block 42-1 can be arranged in the circuit units of the Nth unit column and the (N+2)th unit column.

[0188] In the example embodiment, the second initial signal line 42 and the plurality of second initial connection blocks 42-1 in one unit row can be an integrated structure connected to each other.

[0189] In the example embodiment, the third initial signal line 43 can have a shape of a straight line or a broken line with a main body extending along the first direction X, and the third initial signal line 43 can be located between the third scan signal line 23 and the light-emitting signal line 25. The orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps the orthographic projection of the second scan signal line 22 on the substrate, and the third initial signal line 43 transmitting a constant voltage can shield the influence of the second scan signal line 22 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0190] In an example embodiment, the third initial signal line 43 can be provided with a third initial connection block 43-1 in a block shape (e.g., a rectangular shape). In the first direction X, the third initial connection block 43-1 can be arranged between part of the adjacent circuit units. In the second direction Y, the third initial connection block 43-1 can be arranged on the side of the third initial signal line 43 away from the second electrode plate 32 and connected to the third initial signal line 43. In an example embodiment, the third initial connection block 43-1 is configured to be connected to the first region of the eighth active layer through the third initial electrode formed later.

[0191] In an example embodiment, the third initial signal line 43 and the plurality of third initial connection blocks 43-1 in one unit row can be an integrated structure connected to each other.

[0192] In an example embodiment, part of the two adjacent circuit units in one unit row can share the same third initial connection block 43-1. For example, the two circuit units in the N-1th unit column and the Nth unit column can share the same third initial connection block 43-1. For another example, the two circuit units in the N+1th unit column and the N+2th unit column can share the same third initial connection block 43-1. For another example, the two circuit units in the N+3th unit column and the N+4th unit column can share the same third initial connection block 43-1. By arranging the third initial connection block 43-1 shared by part of the adjacent circuit units, the present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution.

[0193] In an example embodiment, the third conductive layer (except the second initial connection block) of the adjacent unit columns can be mirror-symmetrical relative to the column boundary line. For example, the third conductive layer of the Nth unit column and the third conductive layer of the N+1th unit column can be mirror-symmetrical relative to the column boundary line, the third conductive layer of the N+1th unit column and the third conductive layer of the N+2th unit column can be mirror-symmetrical relative to the column boundary line, and the third conductive layer of the N+2th unit column and the third conductive layer of the N+3th unit column can be mirror-symmetrical relative to the column boundary line. In an example embodiment, the shapes of the third conductive layers in the plurality of unit rows can be substantially the same.

[0194] (16) Forming a sixth insulating layer pattern. In an example embodiment, forming the sixth insulating layer pattern can include: depositing a sixth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fifth insulating thin film by using a patterning process to form a sixth insulating layer covering the third conductive layer, the sixth insulating layer being provided with a plurality of vias, as shown in FIG. 12.

[0195] In the example embodiment, the plurality of vias of each circuit unit in the display substrate at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, and a sixteenth via V16.

[0196] In the example embodiment, the first via V1 is configured to expose the surface of the first region of the first active layer by etching away the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the first via V1, and the first via V1 is configured to connect the first initial electrode formed subsequently to the first region of the first active layer.

[0197] In the example embodiment, since the first active layers in the two adjacent circuit units are integrated and connected to each other, the two circuit units share the same first region of the first active layer, and thus the two adjacent circuit units can share the same first via V1, which can effectively reduce the lateral layout space, reduce the number of vias, reduce the area occupied by the pixel driving circuit, and facilitate the realization of high resolution.

[0198] In the example embodiment, the second via V2 is configured to expose the surface of the second region of the first active layer by etching away the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the second via V2, and the second via V2 is configured to connect the second connection electrode formed subsequently to the second region of the first active layer.

[0199] In the example embodiment, the third via V3 is configured to expose the surface of the first region of the second active layer by etching away the sixth insulating layer and the fifth insulating layer in the third via V3, and the third via V3 is configured to connect the first connection electrode formed subsequently to the first region of the second active layer.

[0200] In the example embodiment, the fourth via V4 is configured to expose the surface of the second region of the second active layer by etching away the sixth insulating layer and the fifth insulating layer in the fourth via V4, and the fourth via V4 is configured to connect the second connection electrode formed subsequently to the second region of the second active layer.

[0201] In an example embodiment, the normal projection of the fifth via V5 on the substrate is located within the normal projection of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer), and the fifth via V5 is configured to enable the fifth connection electrode formed subsequently to connect with the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the via.

[0202] In an example embodiment, the normal projection of the sixth via V6 on the substrate is located within the normal projection of the second region of the third active layer (also the first region of the sixth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away, exposing the surface of the second region of the third active layer (also the first region of the sixth active layer), and the sixth via V6 is configured to enable the second connection electrode formed subsequently to connect with the second region of the third active layer (also the first region of the sixth active layer) through the via.

[0203] In an example embodiment, the normal projection of the seventh via V7 on the substrate is located within the normal projection of the first region of the fourth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first region of the fourth active layer, and the seventh via V7 is configured to enable the third connection electrode formed subsequently to connect with the first region of the fourth active layer through the via.

[0204] In an example embodiment, the normal projection of the eighth via V8 on the substrate is located within the normal projection of the first region of the fifth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eighth via V8 are etched away, exposing the surface of the first region of the fifth active layer, and the eighth via V8 is configured to enable the fourth connection electrode formed subsequently to connect with the first region of the fifth active layer through the via.

[0205] In an example embodiment, since the fifth active layers in part of two adjacent circuit units in one unit row are an integral structure connected with each other, the two circuit units share the same first region of the fifth active layer, thus part of the adjacent circuit units can share the same eighth via V8, which can effectively reduce the lateral wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and be conducive to achieving high resolution.

[0206] In the example embodiment, the normal projection of the ninth via V9 on the substrate is located within the normal projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the ninth via V9 are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the ninth via V9 is configured to connect the sixth connection electrode formed subsequently thereto with the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0207] In the example embodiment, the normal projection of the tenth via V10 on the substrate is located within the normal projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via V10 are etched away, exposing the surface of the first region of the seventh active layer, the tenth via V10 in the first unit column is configured to connect the second initial electrode formed subsequently thereto with the first region of the seventh active layer through the via, and the tenth via V10 in the second unit column is configured to connect the fifth initial electrode formed subsequently thereto with the first region of the seventh active layer through the via.

[0208] In the example embodiment, the normal projection of the eleventh via V11 on the substrate is located within the normal projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eleventh via V11 are etched away, exposing the surface of the first region of the eighth active layer, and the eleventh via V11 is configured to connect the third initial electrode formed subsequently thereto with the first region of the eighth active layer through the via.

[0209] In the example embodiment, since the eighth active layers in part of two adjacent circuit units in one unit row are connected as an integral structure, the two circuit units share the same first region of the eighth active layer, and thus part of the adjacent circuit units can share the same eleventh via V11, which can effectively reduce the lateral wiring space, reduce the number of vias, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution.

[0210] In the example embodiment, the normal projection of the twelfth via V12 on the substrate is located within the normal projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the twelfth via V12 are etched away, exposing the surface of the second region of the eighth active layer, and the twelfth via V12 is configured to connect the fifth connection electrode formed subsequently thereto with the second region of the eighth active layer through the via.

[0211] In the example embodiment, the thirteenth via V13 is configured such that a first connection electrode formed subsequently is connected to the first plate 31 through the via. The thirteenth via V13 has a normal projection on the substrate within the normal projection on the substrate of the opening 33. The sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the thirteenth via V13 are etched away to expose the surface of the first plate 31.

[0212] In the example embodiment, the fourteenth via V14 is configured such that a seventh connection electrode formed subsequently is connected to the plate connection strip 34 through the via. The fourteenth via V14 has a normal projection on the substrate within the normal projection on the substrate of the plate connection strip 34 of the second plate 32. The sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fourteenth via V14 are etched away to expose the surface of the plate connection strip 34. In the example embodiment, since the second plates 32 of some adjacent circuit units in a unit row are connected to each other through the plate connection strip 34, the some adjacent circuit units in a unit row can share one fourteenth via V14.

[0213] In the example embodiment, the fifteenth via V15 is configured such that a first initial electrode formed subsequently is connected to the first initial connection block 41-1 through the via. The fifteenth via V15 has a normal projection on the substrate within the normal projection on the substrate of the first initial connection block 41-1 of the first initial signal line 41. The sixth insulating layer in the fifteenth via V15 is etched away to expose the surface of the first initial connection block 41-1.

[0214] In the example embodiment, since some adjacent circuit units in a unit row share the same first initial connection block 41-1, two adjacent circuit units can share the same fifteenth via V15. For example, two circuit units in the Nth unit column and the N+1th unit column can share the same fifteenth via V15. For another example, two circuit units in the N+2th unit column and the N+3th unit column can share the same fifteenth via V15. The disclosure can effectively reduce the number of vias and the area occupied by the pixel driving circuit by configuring adjacent circuit units to share the fifteenth via V15, which is conducive to achieving high resolution.

[0215] In the example embodiment, the sixteenth via V16 is configured such that a third initial electrode formed subsequently is connected to the third initial connection block 43-1 through the via. The sixteenth via V16 has a normal projection on the substrate within the normal projection on the substrate of the third initial connection block 43-1 of the third initial signal line 43. The sixth insulating layer in the sixteenth via V16 is etched away to expose the surface of the third initial connection block 43-1.

[0216] In the example embodiment, since part of the adjacent circuit units in one unit row share the same third initial connection block 43-1, part of the adjacent two circuit units can share the same sixteenth via V16. For example, two circuit units in the N-1th unit column and the Nth unit column can share the same sixteenth via V16. For another example, two circuit units in the N+1th unit column and the N+2th unit column can share the same sixteenth via V16. For another example, two circuit units in the N+3th unit column and the N+4th unit column can share the same sixteenth via V16. The present disclosure can effectively reduce the number of vias and reduce the area occupied by the pixel driving circuit by setting the adjacent circuit units to share the sixteenth via V16, which is conducive to achieving high resolution.

[0217] In the example embodiment, at least one circuit unit can further include a seventeenth via V17.

[0218] In the example embodiment, the orthogonal projection of the seventeenth via V17 on the substrate is located within the range of the orthogonal projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate. The sixth insulating layer in the seventeenth via V17 is etched away to expose the surface of the second initial connection block 42-1, and the seventeenth via V17 is configured to connect the second initial connection block 42-1 with the second initial electrode formed subsequently through the via.

[0219] In the example embodiment, the seventeenth via V17 can be arranged in the circuit units of the first unit column. For example, the seventeenth via V17 can be arranged in the circuit units of the Nth unit column and the N+2th unit column.

[0220] (17) Forming a fourth conductive layer pattern. In the example embodiment, forming the fourth conductive layer can include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film by using a patterning process to form a fourth conductive layer arranged on the sixth insulating layer, as shown in FIGS. 13A and 13B, FIG. 13B being a plan view of the fourth conductive layer in FIG. 13A. In the example embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0221] In the example embodiment, the fourth conductive layer of each circuit unit in the display substrate at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, a first initial electrode 71, and a third initial electrode 73.

[0222] In the example embodiment, the first connecting electrode 51 can have a strip shape with a main body extending along the second direction Y, a first end of the first connecting electrode 51 is connected to the first region of the second active layer through the third via V3, and a second end of the first connecting electrode 51 is connected to the first plate 31 through the thirteenth via V13 after extending along the second direction Y. In the example embodiment, since the first plate 31 also serves as the gate electrode of the third transistor T3, the first connecting electrode 51 makes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate 31 have the same potential, thereby forming the first node N1 of the pixel driving circuit.

[0223] In the example embodiment, the second connecting electrode 52 can have a strip shape with a main body extending along the second direction Y, a first end of the second connecting electrode 52 is connected to the second region of the first active layer of the current circuit unit through the second via V2, a second end of the second connecting electrode 52 is connected to the second region of the third active layer (also the first region of the sixth active layer) of the next circuit unit through the sixth via V6 after extending along the second direction Y, and a portion between the first end and the second end of the second connecting electrode 52 is connected to the second region of the second active layer of the next circuit unit through the fourth via V4. In the example embodiment, the second connecting electrode 52 makes the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential, thereby forming the third node N3 of the pixel driving circuit.

[0224] In the example embodiment, the third connecting electrode 53 can have a block shape (e.g., a rectangular shape), and the third connecting electrode 53 is connected to the first region of the fourth active layer through the seventh via V7 and is configured to be connected to the data signal line formed subsequently.

[0225] In the example embodiment, the fourth connecting electrode 54 can have a block shape (e.g., a rectangular shape), and the fourth connecting electrode 54 is connected to the first region of the fifth active layer through the eighth via V8 and is configured to be connected to the first power supply line formed subsequently.

[0226] In the example embodiment, since one eighth via V8 is shared by part of two adjacent circuit units in one unit row, part of the adjacent circuit units can share one fourth connecting electrode 54, which can effectively reduce the lateral wiring space, reduce the number of connecting electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution.

[0227] In an example embodiment, the fifth connection electrode 55 can have a shape of a strip extending along the second direction Y, a first end of the fifth connection electrode 55 is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the fifth via V5, and a second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer through the twelfth via V12. In an example embodiment, the fifth connection electrode 55 makes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 have the same potential, forming the second node N2 of the pixel driving circuit.

[0228] In an example embodiment, the sixth connection electrode 56 can have a shape of a block (e.g., a rectangle), and the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the ninth via V9. In an example embodiment, the sixth connection electrode 56 can simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 56 is configured to be connected to the anode connection electrode formed subsequently.

[0229] In an example embodiment, the seventh connection electrode 57 can have a shape of a block (e.g., a rectangle), and the seventh connection electrode 57 is connected to the plate connection strip 34 through the fourteenth via V14, and the seventh connection electrode 57 is configured to be connected to the first power line formed subsequently.

[0230] In an example embodiment, since one of the fourteenth vias V14 is shared by part of two adjacent circuit units in one unit row, part of the adjacent circuit units can share the same seventh connection electrode 57, which can effectively reduce the lateral wiring space, reduce the number of connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution.

[0231] In an example embodiment, the first initial electrode 71 can have a shape of a strip extending along the second direction Y, a first end of the first initial electrode 71 is connected to the first region of the first active layer through the first via V1, and a second end of the first initial electrode 71 is connected to the first initial connection block 41-1 through the fifteenth via V15. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal line 41 writes the first initial signal to the first region of the first active layer is realized.

[0232] In the example embodiment, since two circuit units that are partially adjacent share the first region of the same first active layer, share the same first initial connection block 41-1, and share the same fifteenth via V15, the two circuit units that are partially adjacent can share the same first initial electrode 71. For example, two circuit units in the Nth unit column and the N+1th unit column can share the same first initial electrode 71. For another example, two circuit units in the N+2th unit column and the N+3th unit column can share the same first initial electrode 71. The present disclosure can effectively reduce the number of connection electrodes and reduce the occupied area of the pixel driving circuit by arranging adjacent circuit units to share the first initial electrode 71, which is conducive to achieving high resolution.

[0233] In the example embodiment, the third initial electrode 73 can have a strip shape extending along the second direction Y, a first end of the third initial electrode 73 is connected to the first region of the eighth active layer through the eleventh via V11, and a second end of the third initial electrode 73 is connected to the third initial connection block 43-1 through the sixteenth via V16. Since the third initial connection block 43-1 is connected to the third initial signal line 43, the third initial signal line 43 writes the third initial signal to the first region of the eighth active layer is realized.

[0234] In the example embodiment, since two circuit units that are partially adjacent share the first region of the same eighth active layer, share the same third initial connection block 43-1, and share the same sixteenth via V16, the two circuit units that are partially adjacent can share the same third initial electrode 73. For example, two circuit units in the N-1th unit column and the Nth unit column can share the same third initial electrode 73. For another example, two circuit units in the N+1th unit column and the N+2th unit column can share the same third initial electrode 73. For another example, two circuit units in the N+3th unit column and the N+4th unit column can share the same third initial electrode 73. The present disclosure can effectively reduce the number of connection electrodes and reduce the occupied area of the pixel driving circuit by arranging adjacent circuit units to share the third initial electrode 73, which is conducive to achieving high resolution.

[0235] In the example embodiment, the fourth conductive layer can further include a second initial electrode 72.

[0236] In the example embodiment, the second initial electrode 72 can have a strip shape extending along the second direction Y, a first end of the second initial electrode 72 is connected to the first region of the seventh active layer through the tenth via V10, and a second end of the second initial electrode 72 is connected to the second initial connection block 42-1 through the seventeenth via V17. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the second initial signal line 42 writes the second initial signal to the first region of the seventh active layer is realized.

[0237] In an exemplary embodiment, the second initial signal line 42 can be provided in each unit row, and the second initial electrode 72 can be provided in the first unit column. For example, the second initial electrode 72 can be provided in the Nth unit column and the N+2th unit column, respectively, i.e., the seventh transistor T7 of the plurality of circuit units in the Nth unit column and the N+2th unit column (the first unit column) is provided with the second initial signal by the second initial signal line 42.

[0238] In an exemplary embodiment, the fourth conductive layer can further include the first initial connection line 61 and the first connection bar 64.

[0239] In an exemplary embodiment, the first initial connection line 61 can be in the shape of a broken line extending along the second direction Y, and can be provided on the side of the first connection electrode 51 away from the second connection electrode 52. The first connection bar 64 can be in the shape of a bar extending along the first direction X, and can be provided between the first initial connection line 61 and the first initial electrode 71. The first end of the first connection bar 64 is connected to the first initial connection line 61, and the second end of the first connection bar 64 is connected to the first initial electrode 71. Since the first initial electrode 71 is connected to the first initial signal line 41, a meshed communication structure for transmitting the first initial signal is formed by the first initial signal line 41 extending along the first direction X and the first initial connection line 61 extending along the second direction Y, which can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0240] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first connection bar 64 on the substrate at least partially overlaps the orthographic projection of the third initial signal line 43 on the substrate.

[0241] In an exemplary embodiment, in at least one circuit unit, the first initial connection line 61, the first connection bar 64, and the first initial electrode 71 can be an integrated structure connected to each other.

[0242] In an exemplary embodiment, the first initial signal line 41 can be provided in each unit row, the first initial connection line 61 can be provided in part of the first unit columns, and there can be 3 circuit units between adjacent first initial connection lines 61 along the first direction X. For example, the first initial connection line 61 can be provided in the Nth unit column. For another example, the first initial connection line 61 can be provided in the N+4th unit column.

[0243] In an exemplary embodiment, the fourth conductive layer can further include the fifth initial signal line 45 and the fifth initial electrode 75.

[0244] In an exemplary embodiment, the fifth initial signal line 45 can be in the shape of a broken line extending along the second direction Y, and can be arranged on the side of the first connection electrode 51 away from the second connection electrode 52. The fifth initial electrode 75 can be in the shape of a strip extending along the first direction X, and can be arranged on the side of the fifth initial signal line 45 close to the seventh active layer. The first end of the fifth initial electrode 75 is connected to the fifth initial signal line 45, and the second end of the fifth initial electrode 75 extends toward the seventh active layer and is connected to the first region of the seventh active layer through the tenth via V10, so that the fifth initial signal line 45 writes the second initial signal into the first region of the seventh active layer.

[0245] In an exemplary embodiment, in at least one circuit unit, the fifth initial signal line 45 and the fifth initial electrode 75 can be an integrated structure connected to each other.

[0246] In an exemplary embodiment, the fifth initial signal line 45 can be arranged in the second unit column, and there can be 1 circuit unit between adjacent fifth initial signal lines 45 in the first direction X. For example, the fifth initial signal line 45 can be arranged in the N+1th unit column and the N+3th unit column, that is, the seventh transistor T7 in the plurality of circuit units in the N+1th unit column and the N+3th unit column (the second unit column) is provided with the second initial signal by the fifth initial signal line 45.

[0247] In an exemplary embodiment, the fourth conductive layer can further include a third initial connection line 63 and a third connection strip 66.

[0248] In an exemplary embodiment, the third initial connection line 63 can be in the shape of a broken line extending along the second direction Y, and can be arranged on the side of the first connection electrode 51 away from the second connection electrode 52. The third connection strip 66 can be in the shape of a strip extending along the first direction X, and can be arranged between the third initial connection line 63 and the third initial electrode 73. The first end of the third connection strip 66 is connected to the third initial connection line 63, and the second end of the third connection strip 66 is connected to the third initial electrode 73. Since the third initial electrode 73 is connected to the third initial signal line 43, the third initial signal line 43 extending along the first direction X and the third initial connection line 63 extending along the second direction Y form a mesh-shaped networked communication structure for transmitting the third initial signal, which can effectively reduce the resistance of the third initial signal line, reduce the voltage drop of the third initial signal, effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0249] In the at least one circuit unit, the third connection strip 66 can be disposed between the second initial signal line 42 and the third initial signal line 43, and a projection of the third connection strip 66 on the base at least partially overlaps a projection of the first region of the eighth active layer on the base.

[0250] In the at least one circuit unit, the third initial connection line 63, the third connection strip 66, and the third initial electrode 73 can be an integrated structure connected to each other.

[0251] In the at least one circuit unit, the third initial signal line 43 can be disposed in each unit row, the third initial connection line 63 can be disposed in a part of the first unit columns, and 3 circuit units can be spaced between adjacent third initial connection lines 63 in the first direction X. For example, the third initial connection line 63 can be disposed in the N+2th unit column. For another example, the third initial connection line 63 can be disposed in the N+6th unit column.

[0252] In the at least one circuit unit, the third initial connection line 63, the third connection strip 66, and the third initial electrode 73 can be an integrated structure connected to each other.

[0253] In the at least one circuit unit, the third initial connection line 63, the third connection strip 66, and the third initial electrode 73 can be an integrated structure connected to each other.

[0254] In the at least one circuit unit, the third initial connection line 63, the third connection strip 66, and the third initial electrode 73 can be an integrated structure connected to each other.

[0255] In an example embodiment, the second initial signal line 42 can be provided in each unit row, the second initial electrode 72 can be provided in the first unit column, the seventh transistor T7 of the plurality of circuit units in the first unit column is provided with the second initial signal by the second initial signal line 42, the fifth initial signal line 45 and the fifth initial electrode 75 can be provided in the second unit column, the seventh transistor T7 of the plurality of circuit units in the second unit column is provided with the second initial signal by the fifth initial signal line 45, that is, the pixel driving circuit connected with the red light emitting device and the blue light emitting device is provided with the second initial signal with the first voltage by the second initial signal line 42 located in the third conductive layer (GATE3), the pixel driving circuit connected with the first green light emitting device and the second green light emitting device is provided with the second initial signal with the second voltage by the fifth initial signal line 45 located in the fourth conductive layer (SD1), and the voltage value of the first voltage and the voltage value of the second voltage are different.

[0256] In another example embodiment, the second initial signal line 42 can be provided in each unit row, the second initial electrode 72 can be provided in the second unit column, the seventh transistor T7 of the plurality of circuit units in the second unit column is provided with the second initial signal by the second initial signal line 42, the fifth initial signal line 45 and the fifth initial electrode 75 can be provided in the first unit column, the seventh transistor T7 of the plurality of circuit units in the first unit column is provided with the second initial signal by the fifth initial signal line 45, that is, the pixel driving circuit connected with the first green light emitting device and the second green light emitting device is provided with the second initial signal with the first voltage by the second initial signal line 42 located in the third conductive layer (GATE3), the pixel driving circuit connected with the red light emitting device and the blue light emitting device is provided with the second initial signal with the second voltage by the fifth initial signal line 45 located in the fourth conductive layer (SD1), and the voltage value of the first voltage and the voltage value of the second voltage are different.

[0257] In an example embodiment, the fourth conductive layer of adjacent unit columns (except the first connection bar 64, the third connection bar 66 and the fifth initial electrode 75) can be mirror symmetrical with respect to the column boundary line. For example, the fourth conductive layer of the Nth unit column and the fourth conductive layer of the N+1th unit column can be mirror symmetrical with respect to the column boundary line, the fourth conductive layer of the N+1th unit column and the fourth conductive layer of the N+2th unit column can be mirror symmetrical with respect to the column boundary line, and the fourth conductive layer of the N+2th unit column and the fourth conductive layer of the N+3th unit column can be mirror symmetrical with respect to the column boundary line. In an example embodiment, the shape of the fourth conductive layer in the plurality of unit rows can be substantially the same.

[0258] In the example embodiment, the subsequent manufacturing process can include sequentially forming a first planar layer, a fifth conductive layer (may be referred to as a second source-drain metal layer, i.e., SD2), a second planar layer, a sixth conductive layer (may be referred to as a third source-drain metal layer, i.e., SD3), and a third planar layer on the base to complete the preparation of the driving structure layer. Subsequently, the light-emitting structure layer is formed on the driving structure layer, and the encapsulation structure layer is formed on the light-emitting structure layer, which will not be described herein.

[0259] In the example embodiment, in a plane parallel to the display substrate, the driving structure layer can include a plurality of circuit units, each of which can include a pixel driving circuit. In a direction perpendicular to the display substrate, the driving structure layer can include, sequentially arranged on the base, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, a second planar layer, a sixth conductive layer, and a third planar layer. The first semiconductor layer can include at least active layers of a first transistor, a third transistor to an eighth transistor, the first conductive layer can include at least a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, and a first plate of a storage capacitor, the second conductive layer can include at least a second plate of the storage capacitor, the second semiconductor layer can include at least an active layer of a second transistor, the third conductive layer can include at least a first initial signal line, a second initial signal line, a third initial signal line, and a fourth scan signal line, and the fourth conductive layer can include at least a first initial connection line, a third initial connection line, a fifth initial signal line, and a plurality of connection electrodes.

[0260] In the example embodiment, the base can be a flexible base or can be a rigid base. The rigid base can include, but is not limited to, one or more of glass, quartz, and the flexible base can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In the example embodiment, the flexible base can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc., the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the base, the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0261] In exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The first planar layer, the second planar layer and the third planar layer can be made of an organic material, such as resin, etc.

[0262] FIG. 14 is a schematic diagram of a structure of an initial lead-out line and an initial routing line according to an exemplary embodiment of the present disclosure. As shown in FIG. 14, the display substrate can include a display area 100, a bonding area 200 located at one side of the display area 100, and a bezel area 300 located at the other side of the display area 100. In exemplary embodiments, the display area 100 can be a flat area including a plurality of sub-pixels constituting a pixel array, and the plurality of sub-pixels are configured to display dynamic pictures or static images. The display area 100 can be referred to as an active area (AA). In exemplary embodiments, the display substrate can be made of a flexible substrate, and thus the display substrate can be deformable, such as being rolled, bent, folded or rolled up.

[0263] In exemplary embodiments, the bonding area 200 can include, in sequence along a direction away from the display area, a lead-out line area, a bending area, a driving chip area and a bonding pin area. The lead-out line area is connected to the display area 100 and can include at least a plurality of data lead-out lines. The bending area is connected to the lead-out line area and can include at least a composite insulating layer provided with a recess configured to bend the bonding area to the back of the display area. The driving chip area can include an integrated circuit (IC) configured to be connected to the plurality of data lead-out lines. The bonding pin area can include a bonding pad configured to be bonded to an external flexible printed circuit (FPC).

[0264] In the example embodiment, the frame area 300 can include, in sequence along a direction away from the display area 100, a circuit area, a power line area, a crack dam area, and a cutting area. The circuit area is connected to the display area 100 and can include at least a gate driving circuit connected to a scan signal line and a light-emitting signal line in the display area 100. The power line area is connected to the circuit area and can include at least a frame power lead line extending along a direction parallel to the edge of the display area and connected to a cathode in the display area 100. The crack dam area is connected to the power line area and can include at least a plurality of cracks provided on a composite insulating layer. The cutting area is connected to the crack dam area and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut by a cutting device along the cutting groove after all film layers of the display substrate are prepared.

[0265] In the example embodiment, the binding area 200 can further include a plurality of initial lead-out lines, which can include at least a first initial lead-out line 201, a second initial lead-out line 202, a third initial lead-out line 203, and a fifth initial lead-out line 205. The frame area 300 can further include a plurality of initial wiring lines, which can include at least a first initial wiring line 301, a second initial wiring line 302, and a third initial wiring line 303.

[0266] In the example embodiment, the first initial lead-out line 201 in the binding area 200 can have a shape of a straight line or a broken line extending along the second direction Y and can be disposed on one side or both sides of the binding area 200 in the first direction X. The first initial wiring line 301 in the frame area 300 can have a shape of a straight line or a broken line extending along a direction parallel to the edge of the display area. One end of the first initial lead-out line 201 is connected to the first initial pad of the binding pin area, and the other end extends toward the display area 100 and is connected to one end of the first initial wiring line 301 in the frame area 300. The other end of the first initial wiring line 301 extends away from the binding area 200 and is connected to a plurality of first initial signal lines 41 in the display area 100 to provide first initial signals to the plurality of first initial signal lines 41.

[0267] In the exemplary embodiment, the shape of the second initial lead-out line 202 in the binding area 200 can be a straight line or a broken line extending along the second direction Y, and can be arranged on one side or both sides of the first direction X of the binding area 200. The shape of the second initial trace 302 in the frame area 300 can be a straight line or a broken line extending along a direction parallel to the edge of the display area. One end of the second initial lead-out line 202 is connected to the second initial pad of the binding pin area, and the other end is extended toward the direction close to the display area 100, and is connected to one end of the second initial trace 302 in the frame area 300. The other end of the second initial trace 302 is extended toward the direction away from the binding area 200, and is connected to the plurality of second initial signal lines 42 in the display area 100, respectively, to provide the second initial signal to the plurality of second initial signal lines 42.

[0268] In the exemplary embodiment, the shape of the third initial lead-out line 203 in the binding area 200 can be a straight line or a broken line extending along the second direction Y, and can be arranged on one side or both sides of the first direction X of the binding area 200. The shape of the third initial trace 303 in the frame area 300 can be a straight line or a broken line extending along a direction parallel to the edge of the display area. One end of the third initial lead-out line 203 is connected to the third initial pad of the binding pin area, and the other end is extended toward the direction close to the display area 100, and is connected to one end of the third initial trace 303 in the frame area 300. The other end of the third initial trace 303 is extended toward the direction away from the binding area 200, and is connected to the plurality of third initial signal lines 43 in the display area 100, respectively, to provide the third initial signal to the plurality of third initial signal lines 43.

[0269] In the exemplary embodiment, the shape of the fifth initial lead-out line 205 in the binding area 200 can be a straight line or a broken line extending along the second direction Y, and can be arranged on one side or both sides of the first direction X of the binding area 200. One end of the fifth initial lead-out line 205 is connected to the fifth initial pad of the binding pin area, and the other end is extended toward the direction close to the display area 100, and is connected to the plurality of fifth initial signal lines 45 in the display area 100 through the horizontal connection line, to provide the second initial signal to the plurality of fifth initial signal lines 45.

[0270] In the example embodiment, the shapes of the first initial signal lines 41, the second initial signal lines 42 and the third initial signal lines 43 in the display area 100 can be straight lines or broken lines extending along the first direction X, the shape of the fifth initial signal line 45 can be a straight line or a broken line extending along the second direction Y, the first initial signal lines 41 are configured to provide the first initial signals to the pixel driving circuits, the third initial signal lines 43 are configured to provide the third initial signals to the pixel driving circuits, the second initial signal lines 42 and the fifth initial signal lines 45 are configured to provide the second initial signals to the pixel driving circuits, the second initial signals provided by the second initial signal lines 42 have a first voltage, the second initial signals provided by the fifth initial signal lines 45 have a second voltage, and the voltage values of the first voltage and the second voltage are different.

[0271] In the example embodiment, the display area 100 can further include a plurality of first initial connection lines 61 and a plurality of third initial connection lines 63 extending along the second direction Y, the plurality of first initial connection lines 61 are connected with the plurality of first initial signal lines 41 to form a mesh-shaped communication structure for transmitting the first initial signals, and the plurality of third initial connection lines 63 are connected with the plurality of third initial signal lines 43 to form a mesh-shaped communication structure for transmitting the third initial signals.

[0272] The example embodiment of the present disclosure provides a display substrate, by providing a second initial signal line and a fifth initial signal line to provide a second initial signal with different voltages, the pixel driving circuits connected with the red light emitting device and the blue light emitting device are connected with the second initial signal line, and the pixel driving circuits connected with the green light emitting unit are connected with the fifth initial signal line, the voltage of the second initial signal can be adjusted according to different display requirements, not only the low gray scale light-on problem of the blue light emitting unit can be solved, but also high resolution (up to 520 PPI) and high quality display can be realized.

[0273] The example embodiment of the present disclosure can effectively reduce the layout space, reduce the number of vias and connection electrodes, and reduce the occupied area of the pixel driving circuit by adopting the pixel driving circuit mirror symmetry design and circuit node sharing, the first transistors T1 in adjacent unit columns are mirror arranged and share the first poles of the first transistors T1, and the eighth transistors T8 in adjacent unit columns are mirror arranged and share the first poles of the eighth transistors T8, which is conducive to realizing high resolution.

[0274] The embodiment of the present disclosure forms a meshed communication structure for transmitting the first initial signal on the display substrate by setting the first initial signal line extending along the first direction X and the first initial connection line extending along the second direction Y, and the first initial signal line and the first initial connection line are connected to each other, which not only can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, but also can effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0275] The embodiment of the present disclosure forms a meshed communication structure for transmitting the third initial signal on the display substrate by setting the third initial signal line extending along the first direction X and the third initial connection line extending along the second direction Y, and the third initial signal line and the third initial connection line are connected to each other, which not only can effectively reduce the resistance of the third initial signal line, reduce the voltage drop of the third initial signal, but also can effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0276] The embodiment of the present disclosure forms a meshed communication structure for transmitting the third initial signal on the display substrate by setting the third initial signal line extending along the first direction X and the third initial connection line extending along the second direction Y, and the third initial signal line and the third initial connection line are connected to each other, which not only can effectively reduce the resistance of the third initial signal line, reduce the voltage drop of the third initial signal, but also can effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0277] FIG. 15 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, the main structure of the display substrate of the present embodiment is basically the same as that of the display substrate shown in FIG. 5, except that the present embodiment adjusts the voltage of the third initial signal.

[0278] In the exemplary embodiment, the pixel driving circuits in the two unit columns can be connected to the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41 and the second initial signal line 42 respectively, the pixel driving circuits in the first unit column are connected to the third initial signal line 43, and the pixel driving circuits in the second unit column are connected to the sixth initial signal line 46. The shape of the third initial signal line 43 can be a straight line or a broken line with a main part extending along the first direction X, and the shape of the sixth initial signal line 46 can be a straight line or a broken line with a main part extending along the second direction Y.

[0279] In an exemplary embodiment, a third initial signal line 43 extending along the first direction X can serve as the first signal line of the present disclosure, the third initial signal line 43 being configured to provide a third initial signal having a first voltage to the pixel driving circuit in the first unit column, a sixth initial signal line 46 extending along the second direction Y can serve as the second signal line of the present disclosure, the sixth initial signal line 46 being configured to provide a third initial signal having a second voltage to the pixel driving circuit in the second unit column, the first voltage and the second voltage being different.

[0280] In an exemplary embodiment, the first electrode of the eighth transistor T8 of the pixel driving circuit in the first unit column is connected with the third initial signal line 43, and the first electrode of the eighth transistor T8 of the pixel driving circuit in the second unit column is connected with the sixth initial signal line 46.

[0281] FIG. 16 is a schematic diagram of the structure of another initial signal line in an exemplary embodiment of the present disclosure. As shown in FIGS. 15 and 16, at least one circuit unit in the first unit column can further include a third initial electrode 73, at least one circuit unit in the second unit column can further include a sixth initial electrode 76, and the eighth transistor T8 as the third reset transistor can include at least an eighth active layer 18 as a third reset active layer, the third initial signal line 43 can be connected with the first region of the eighth active layer 18 of the pixel driving circuit in the first unit column through the third initial electrode 73, and the sixth initial signal line 46 can be connected with the first region of the eighth active layer 18 of the pixel driving circuit in the second unit column through the sixth initial electrode 76.

[0282] In an exemplary embodiment, the third initial electrode 73 can have a strip shape extending along the second direction Y, one end of the third initial electrode 73 is connected with the third initial signal line 43 through a via, and the other end of the third initial electrode 73 is connected with the first region of the eighth active layer 18 of the pixel driving circuit in the first unit column through a via.

[0283] In an exemplary embodiment, the sixth initial electrode 76 can have a block shape (e.g., a rectangular shape), one end of the sixth initial electrode 76 is directly connected with the sixth initial signal line 46, and the other end of the sixth initial electrode 76 is connected with the first region of the eighth active layer 18 of the pixel driving circuit in the second unit column through a via.

[0284] In an exemplary embodiment, the display substrate can include a plurality of conductive layers in a direction perpendicular to the display substrate. The third initial signal line 43 and the sixth initial signal line 46 can be disposed in different conductive layers, and the sixth initial signal line 46, the third initial electrode 73, and the sixth initial electrode 76 can be disposed in the same conductive layer.

[0285] In the example embodiment, the sixth initial signal line 46 and the sixth initial electrode 76 in the at least one circuit unit can be an integrated structure connected to each other.

[0286] In the example embodiment, the first transistor T1 as the first reset transistor can at least include the first active layer 11 as the first reset active layer. In the at least one unit row, the first initial signal line 41 can be connected to the first region of the first active layer 11 through the first initial electrode 71.

[0287] In the example embodiment, the at least one first unit column can further include the first initial connection line 61. The first initial connection line 61 can be in a straight line shape or a broken line shape with a main body part extending along the second direction Y, and connected to the first initial electrode 71 through the first connection strip 64, so as to realize the connection between the first initial signal line 41 and the first initial connection line 61, and form a grid communication structure for transmitting the first initial signal on the display substrate.

[0288] In the example embodiment, the seventh transistor T7 as the second reset transistor can at least include the seventh active layer 17 as the second reset active layer. In the at least one unit row, the second initial signal line 42 can be connected to the first region of the seventh active layer 17 through the second initial electrode 72.

[0289] In the example embodiment, the at least one first unit column can further include the second initial connection line 62. The second initial connection line 62 can be in a straight line shape or a broken line shape with a main body part extending along the second direction Y, and connected to the second initial electrode 72 through the second connection strip 65, so as to realize the connection between the second initial signal line 42 and the second initial connection line 62, and form a grid communication structure for transmitting the second initial signal on the display substrate.

[0290] In the example embodiment, the first initial connection line 61, the sixth initial signal line 46, the second initial connection line 62, and the sixth initial signal line 46 can be periodically arranged in the first direction X.

[0291] In the example embodiment, taking 8 circuit units (2 unit rows and 4 unit columns) as an example, the preparation process of the display substrate can include the following operations.

[0292] (21) Forming a first semiconductor layer pattern. In the example embodiment, the process of forming the first semiconductor layer and the formed pattern can be basically the same as that of the embodiment shown in FIG. 5, except that the eighth active layer in the adjacent circuit unit is separately arranged and has a different shape, as shown in FIG. 17.

[0293] In the example embodiment, in the two circuit units that are partially adjacent, the eighth active layer 18 in one of the circuit units can have an "L" shape, the eighth active layer 18 in the other of the circuit units can have an "I" shape, and the first regions 18-1 of the eighth active layer in the two circuit units are separately provided. For example, the eighth active layer 18 in the Nth unit column and the N+2th unit column can have an "L" shape, and the eighth active layer 18 in the N+1th unit column and the N+3th unit column can have an "I" shape.

[0294] In the example embodiment, this design of the eighth active layer in the present embodiment is to adapt the first regions of the eighth active layer in the two circuit units to connect different initial signal lines.

[0295] In the example embodiment, the first semiconductor layers (except the eighth active layer) in the adjacent unit columns can be mirror-symmetrical with respect to the column boundary line, the eighth active layers in the adjacent unit columns can have substantially the same shape, and the first semiconductor layers in the plurality of unit rows can have substantially the same shape.

[0296] (22) Forming a first conductive layer pattern. In the example embodiment, the process of forming the first conductive layer and the formed pattern can be substantially the same as that in the embodiment shown in FIG. 5, as shown in FIG. 18.

[0297] (23) Forming a second conductive layer pattern. In the example embodiment, the process of forming the second conductive layer and the formed pattern can be substantially the same as that in the embodiment shown in FIG. 5, as shown in FIG. 19.

[0298] (24) Forming a second semiconductor layer pattern. In the example embodiment, the process of forming the second semiconductor layer and the formed pattern can be substantially the same as that in the embodiment shown in FIG. 5, as shown in FIG. 20.

[0299] (25) Forming a third conductive layer pattern. In the example embodiment, the process of forming the third conductive layer and the formed pattern can be substantially the same as that in the embodiment shown in FIG. 5, except that a second initial connection block 42-1 can be provided in the circuit unit of each unit column, and the second initial connection block 42-1 is configured to connect the first region of the seventh active layer in each circuit unit through a second initial electrode to be formed later, as shown in FIGS. 21A and 21B, which is a plan view of the third conductive layer in FIG. 21A.

[0300] (26) Forming a sixth insulating layer pattern. In an exemplary embodiment, the process of forming the sixth insulating layer and the formed pattern can be substantially the same as the embodiment shown in FIG. 5, except that the eleventh via V11 in each circuit unit is separately provided, the eleventh via V11 in the first unit column is configured to connect the third initial electrode formed subsequently therethrough to the first region of the eighth active layer, and the eleventh via V11 in the second unit column is configured to connect the sixth initial electrode formed subsequently therethrough to the first region of the eighth active layer, as shown in FIG. 22.

[0301] In an exemplary embodiment, the sixteenth via V16 can be provided in the circuit unit of the first unit column and configured to connect the third initial electrode formed subsequently therethrough to the third initial connection block 43-1, and the seventeenth via V17 can be provided in the circuit unit of each unit column and configured to connect the second initial electrode formed subsequently therethrough to the second initial connection block 42-1.

[0302] (27) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer can include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film by using a patterning process, to form the fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 23A and FIG. 23B, which is a plan view of the fourth conductive layer in FIG. 23A.

[0303] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, a first initial electrode 71, and a second initial electrode 72.

[0304] In an exemplary embodiment, the positions, shapes, and connection relationships of the first connection electrode 51 to the seventh connection electrode 57 and the first initial electrode 71 can be substantially the same as the embodiment shown in FIG. 5.

[0305] In an exemplary embodiment, the second initial electrode 72 can have a strip shape extending along the second direction Y, a first end of the second initial electrode 72 is connected to the first region of the seventh active layer through the tenth via V10, and a second end of the second initial electrode 72 is connected to the second initial connection block 42-1 through the seventeenth via V17, thereby realizing that the second initial signal line 42 writes the second initial signal to the first region of the seventh active layer.

[0306] In an exemplary embodiment, the fourth conductive layer can further include a third initial electrode 73.

[0307] In an exemplary embodiment, the third initial electrode 73 can be in a strip shape extending along the second direction Y, a first end of the third initial electrode 73 is connected to the first region of the eighth active layer through the eleventh via V11, and a second end of the third initial electrode 73 is connected to the third initial connection block 43-1 through the sixteenth via V16, so that the third initial signal line 43 writes the third initial signal to the first region of the eighth active layer.

[0308] In an exemplary embodiment, the third initial signal line 43 can be arranged in each unit row, and the third initial electrode 73 can be arranged in the first unit column. For example, the third initial electrode 73 can be arranged in the Nth unit column and the N+2th unit column, respectively, that is, the eighth transistor T8 of the plurality of circuit units in the Nth unit column and the N+2th unit column (the first unit column) is provided with the third initial signal by the third initial signal line 43.

[0309] In an exemplary embodiment, the fourth conductive layer can further include the first initial connection line 61 and the first connection strip 64, and the positions, shapes and connection relationships of the first initial connection line 61 and the first connection strip 64 can be substantially the same as those of the embodiment shown in FIG. 5, forming a mesh-shaped meshed communication structure for transmitting the first initial signal.

[0310] In an exemplary embodiment, the fourth conductive layer can further include the second initial connection line 62 and the second connection strip 65.

[0311] In an exemplary embodiment, the second initial connection line 62 can be in a polyline shape extending along the second direction Y and can be arranged on a side of the first connection electrode 51 away from the second connection electrode 52. The second connection strip 65 can be in a strip shape extending along the first direction X and can be arranged between the second initial connection line 62 and the second initial electrode 72. A first end of the second connection strip 65 is connected to the second initial connection line 62, and a second end of the second connection strip 65 is connected to the second initial electrode 72. Since the second initial electrode 72 is connected to the second initial signal line 42, the second initial signal line 42 extending along the first direction X and the second initial connection line 62 extending along the second direction Y form a mesh-shaped meshed communication structure for transmitting the second initial signal, which can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0312] In an exemplary embodiment, in at least one circuit unit, the second connection strip 65 can be arranged between the second initial signal line 42 and the third initial signal line 43, and the second initial connection line 62, the second connection strip 65 and the second initial electrode 72 can be an integrated structure connected to each other.

[0313] In the example embodiment, the second initial signal line 42 can be provided in each unit row, the second initial connection line 62 can be provided in the partial first unit column, and 3 circuit units can be spaced between adjacent second initial connection lines 62 in the first direction X. For example, the second initial connection line 62 can be provided in the N+2th unit column. For another example, the second initial connection line 62 can be provided in the N+6th unit column.

[0314] In the example embodiment, the fourth conductive layer can further include a sixth initial signal line 46 and a sixth initial electrode 76.

[0315] In the example embodiment, the sixth initial signal line 46 can be in a shape of a broken line extending along the second direction Y, and can be provided on a side of the first connection electrode 51 away from the second connection electrode 52. The sixth initial electrode 76 can be in a shape of a block (e.g., a rectangle), can be provided on a side of the sixth initial signal line 46 close to the eighth active layer, and can be connected with the sixth initial signal line 46. The sixth initial electrode 76 is connected with the first region of the eighth active layer through the eleventh via V11, so that the sixth initial signal line 46 writes the third initial signal into the first region of the eighth active layer.

[0316] In the example embodiment, the sixth initial signal line 46 and the sixth initial electrode 76 can be an integrated structure connected with each other in at least one circuit unit.

[0317] In the example embodiment, the sixth initial signal line 46 can be provided in the second unit column, and 1 circuit unit can be spaced between adjacent sixth initial signal lines 46 in the first direction X. For example, the sixth initial signal line 46 can be provided in the N+1th unit column and the N+3th unit column, i.e., the eighth transistor T8 of the plurality of circuit units in the N+1th unit column and the N+3th unit column (the second unit column) is provided with the third initial signal by the sixth initial signal line 46.

[0318] In an example embodiment, the first initial connection lines 61, the sixth initial signal lines 46, the second initial connection lines 62 and the sixth initial signal lines 46 can be periodically arranged in the first direction X, two sixth initial signal lines 46 and one second initial connection line 62 can be arranged between two adjacent first initial connection lines 61 in the first direction X, one first initial connection line 61 or one second initial connection line 62 can be arranged between two adjacent sixth initial signal lines 46 in the first direction X, one first initial connection line 61 and two sixth initial signal lines 46 can be arranged between two adjacent second initial connection lines 62 in the first direction X. In the first direction X, the first initial connection lines 61 can be arranged between two sixth initial signal lines 46, the sixth initial signal lines 46 can be arranged between the first initial connection lines 61 and the second initial connection lines 62, and the second initial connection lines 62 can be arranged between two sixth initial signal lines 46.

[0319] In an example embodiment, the first initial connection lines 61 and the sixth initial signal lines 46 of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line, and the second initial connection lines 62 and the sixth initial signal lines 46 of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line.

[0320] In an example embodiment, the pixel driving circuits of the plurality of circuit units in the first unit columns (the Nth unit column and the N+2th unit column) can be connected to the red light-emitting devices emitting red light and the blue light-emitting devices emitting blue light. The pixel driving circuits of the plurality of circuit units in the second unit columns (the N+1th unit column and the N+3th unit column) can be connected to the first green light-emitting devices emitting green light and the second green light-emitting devices emitting green light.

[0321] In an example embodiment, the third initial signal lines 43 can be arranged in each unit row, the third initial electrodes 73 can be arranged in the first unit columns, the eighth transistors T8 of the plurality of circuit units in the first unit columns are provided with the third initial signals by the third initial signal lines 43, the sixth initial signal lines 46 and the sixth initial electrodes 76 can be arranged in the second unit columns, the eighth transistors T8 of the plurality of circuit units in the second unit columns are provided with the third initial signals by the sixth initial signal lines 46, that is, the pixel driving circuits connected to the red light-emitting devices and the blue light-emitting devices are provided with the third initial signals with a first voltage by the third initial signal lines 43 located in the third conductive layer (GATE3), the pixel driving circuits connected to the first green light-emitting devices and the second green light-emitting devices are provided with the third initial signals with a second voltage by the sixth initial signal lines 46 located in the fourth conductive layer (SD1), and the voltage value of the first voltage and the voltage value of the second voltage are different.

[0322] In another exemplary embodiment, the third initial signal line 43 can be provided in each unit row, the third initial electrode 73 can be provided in the second unit column, the eighth transistor T8 of the plurality of circuit units in the second unit column is provided with the third initial signal by the third initial signal line 43, the sixth initial signal line 46 and the sixth initial electrode 76 can be provided in the first unit column, the eighth transistor T8 of the plurality of circuit units in the first unit column is provided with the third initial signal by the sixth initial signal line 46, that is, the pixel driving circuit connected with the first green light emitting device and the second green light emitting device is provided with the third initial signal with the first voltage by the third initial signal line 43 located in the third conductive layer (GATE3), the pixel driving circuit connected with the red light emitting device and the blue light emitting device is provided with the third initial signal with the second voltage by the sixth initial signal line 46 located in the fourth conductive layer (SD1), and the voltage value of the first voltage and the voltage value of the second voltage are different.

[0323] In the exemplary embodiment, the fourth conductive layer of the adjacent unit columns (except the first connection bar 64, the second connection bar 65 and the sixth initial electrode 76) can be mirror symmetrical relative to the column boundary line. For example, the fourth conductive layer of the Nth unit column and the fourth conductive layer of the N+1th unit column can be mirror symmetrical relative to the column boundary line, the fourth conductive layer of the N+1th unit column and the fourth conductive layer of the N+2th unit column can be mirror symmetrical relative to the column boundary line, and the fourth conductive layer of the N+2th unit column and the fourth conductive layer of the N+3th unit column can be mirror symmetrical relative to the column boundary line. In the exemplary embodiment, the shapes of the fourth conductive layers in the plurality of unit rows can be substantially the same.

[0324] In the exemplary embodiment, the structure of the driving structure layer of the present embodiment can be substantially the same as that of the embodiment shown in FIG. 5, except that the fourth conductive layer can include at least the first initial connection line, the second initial connection line, the sixth initial signal line and the plurality of connection electrodes.

[0325] FIG. 24 is a schematic diagram of another structure of the initial lead-out lines and the initial wiring lines in an exemplary embodiment of the present disclosure. As shown in FIG. 24, the binding area 200 can include at least the first initial lead-out line 201, the second initial lead-out line 202, the third initial lead-out line 203 and the sixth initial lead-out line 206, and the frame area 300 can include at least the first initial wiring line 301, the second initial wiring line 302 and the third initial wiring line 303.

[0326] In the exemplary embodiment, the structures of the first initial lead-out line 201, the second initial lead-out line 202 and the third initial lead-out line 203 in the binding area 200, and the first initial wiring line 301, the second initial wiring line 302 and the third initial wiring line 303 in the frame area 300 can be substantially the same as those of the embodiment shown in FIG. 14.

[0327] In the example embodiment, the sixth initial lead-out line 206 in the binding area 200 can be in the shape of a straight line or a broken line extending along the second direction Y, and can be arranged on one side or both sides of the first direction X of the binding area 200. One end of the sixth initial lead-out line 206 is connected to the sixth initial pad of the binding pin area, and the other end extends towards the display area 100, and is connected to the plurality of sixth initial signal lines 46 in the display area 100 through the transverse connection line, and provides the third initial signal to the plurality of sixth initial signal lines 46.

[0328] In the example embodiment, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 in the display area 100 can be in the shape of a straight line or a broken line extending along the first direction X, and the sixth initial signal line 46 can be in the shape of a straight line or a broken line extending along the second direction Y. The first initial signal line 41 is configured to provide the first initial signal to the pixel driving circuit, the second initial signal line 42 is configured to provide the second initial signal to the pixel driving circuit, the third initial signal line 43 and the sixth initial signal line 46 are configured to provide the third initial signal to the pixel driving circuit, the third initial signal provided by the third initial signal line 43 has a first voltage, and the third initial signal provided by the sixth initial signal line 46 has a second voltage. The voltage value of the first voltage and the voltage value of the second voltage are different.

[0329] In the example embodiment, the display area 100 can further include a plurality of first initial connection lines 61 and a plurality of second initial connection lines 62 extending along the second direction Y. The plurality of first initial connection lines 61 are connected to the plurality of first initial signal lines 41, forming a mesh-shaped network connection structure for transmitting the first initial signal. The plurality of second initial connection lines 62 are connected to the plurality of second initial signal lines 42, forming a mesh-shaped network connection structure for transmitting the second initial signal.

[0330] The example embodiment of the present disclosure provides a display substrate. By providing a third initial signal line and a sixth initial signal line to provide a third initial signal with different voltages, the pixel driving circuit connected to the red light emitting device and the blue light emitting device is connected to the third initial signal line, and the pixel driving circuit connected to the green light emitting unit is connected to the sixth initial signal line. The voltage of the third initial signal can be adjusted according to different display requirements, which not only reduces the black voltage, but also realizes high resolution (up to 520 PPI) and high quality display.

[0331] The embodiment of the present disclosure forms a meshed communication structure for transmitting the first initial signal on the display substrate by setting the first initial signal line extending along the first direction X and the first initial connection line extending along the second direction Y, and the first initial signal line and the first initial connection line are connected to each other, which not only can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, but also can effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0332] The embodiment of the present disclosure forms a meshed communication structure for transmitting the second initial signal on the display substrate by setting the second initial signal line extending along the first direction X and the second initial connection line extending along the second direction Y, and the second initial signal line and the second initial connection line are connected to each other, which not only can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, but also can effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0333] The embodiment of the present disclosure forms a meshed communication structure for transmitting the second initial signal on the display substrate by setting the second initial signal line extending along the first direction X and the second initial connection line extending along the second direction Y, and the second initial signal line and the second initial connection line are connected to each other, which not only can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, but also can effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0334] FIG. 25 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, the main structure of the display substrate of the present embodiment is basically the same as that of the display substrate shown in FIG. 5, except that the present embodiment adjusts the voltage of the first initial signal.

[0335] In the exemplary embodiment, the pixel driving circuits in the two unit columns can be connected to the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the second initial signal line 42 and the third initial signal line 43, respectively, the pixel driving circuits in the first unit column are connected to the first initial signal line 41, and the pixel driving circuits in the second unit column are connected to the fourth initial signal line 44. The shape of the first initial signal line 41 can be a straight line or a broken line with a main part extending along the first direction X, and the shape of the fourth initial signal line 44 can be a straight line or a broken line with a main part extending along the second direction Y.

[0336] In an example embodiment, a first initial signal line 41 extending along the first direction X can serve as a first signal line of the present disclosure, the first initial signal line 41 being configured to provide a first initial signal having a first voltage to the pixel driving circuit in the first unit column, a fourth initial signal line 44 extending along the second direction Y can serve as a second signal line of the present disclosure, the fourth initial signal line 44 being configured to provide a first initial signal having a second voltage to the pixel driving circuit in the second unit column, the first voltage and the second voltage being different.

[0337] In an example embodiment, the first electrode of the first transistor T1 of the pixel driving circuit in the first unit column is connected with the first initial signal line 41, and the first electrode of the first transistor T1 of the pixel driving circuit in the second unit column is connected with the fourth initial signal line 44.

[0338] FIG. 26 is a schematic view of another structure of an initial signal line in an example embodiment of the present disclosure. As shown in FIGS. 25 and 26, at least one circuit unit in the first unit column can further include a first initial electrode 71, at least one circuit unit in the second unit column can further include a fourth initial electrode 74, the first transistor T1 serving as a first reset transistor can include at least a first active layer 11 serving as a first reset active layer, the first initial signal line 41 can be connected with the first region of the first active layer 11 of the pixel driving circuit in the first unit column through the first initial electrode 71, and the fourth initial signal line 44 can be connected with the first region of the first active layer 11 of the pixel driving circuit in the second unit column through the fourth initial electrode 74.

[0339] In an example embodiment, the first initial electrode 71 can have a shape of a polyline extending along the second direction Y, one end of the first initial electrode 71 is connected with the first initial signal line 41 through a via, and the other end of the first initial electrode 71 is connected with the first region of the first active layer 11 of the pixel driving circuit in the first unit column through a via.

[0340] In an example embodiment, the fourth initial electrode 74 can have a shape of a polyline extending along the first direction X, one end of the fourth initial electrode 74 is directly connected with the fourth initial signal line 44, and the other end of the fourth initial electrode 74 is connected with the first region of the first active layer 11 of the pixel driving circuit in the second unit column through a via.

[0341] In an example embodiment, the display substrate can include a plurality of conductive layers in a direction perpendicular to the display substrate. The first initial signal line 41 and the fourth initial signal line 44 can be disposed in different conductive layers, and the fourth initial signal line 44, the first initial electrode 71, and the fourth initial electrode 74 can be disposed in the same conductive layer.

[0342] In the exemplary embodiment, the fourth initial signal line 44 and the fourth initial electrode 74 in at least one circuit unit can be an integrated structure connected to each other.

[0343] In the exemplary embodiment, the seventh transistor T7 as the second reset transistor can at least include a seventh active layer 17 as a second reset active layer. In at least one unit row, the second initial signal line 42 can be connected to a first region of the seventh active layer 17 through a second initial electrode 72.

[0344] In the exemplary embodiment, the at least one first unit column can further include a second initial connection line 62. The second initial connection line 62 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and be connected to the second initial electrode 72 through a second connection strip 65, thereby realizing the connection between the second initial signal line 42 and the second initial connection line 62, and forming a mesh communication structure for transmitting the second initial signal on the display substrate.

[0345] In the exemplary embodiment, the eighth transistor T8 as the third reset transistor can at least include an eighth active layer 18 as a third reset active layer. In at least one unit row, the third initial signal line 43 can be connected to a first region of the eighth active layer 18 through a third initial electrode 73.

[0346] In the exemplary embodiment, the at least one first unit column can further include a third initial connection line 63. The third initial connection line 63 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and be connected to the third initial electrode 73 through a third connection strip 66, thereby realizing the connection between the third initial signal line 43 and the third initial connection line 63, and forming a mesh communication structure for transmitting the third initial signal on the display substrate.

[0347] In the exemplary embodiment, the second initial connection line 62, the fourth initial signal line 44, the third initial connection line 63 and the fourth initial signal line 44 can be periodically arranged in the first direction X.

[0348] In the exemplary embodiment, taking 8 circuit units (2 unit rows and 4 unit columns) as an example, the preparation process of the display substrate can include the following operations.

[0349] (31) Forming a first semiconductor layer pattern. In the exemplary embodiment, the process of forming the first semiconductor layer and the formed pattern can be basically the same as that of the embodiment shown in FIG. 5, except that the first active layer in adjacent circuit units is separately arranged, as shown in FIG. 27.

[0350] In the exemplary embodiment, the first active layer 11 in each circuit unit can have an "I" shape and be separately arranged.

[0351] In an example embodiment, such design of the first active layer in the present embodiment is to adapt the first region of the first active layer in the two circuit units to connect different initial signal lines.

[0352] In an example embodiment, the first semiconductor layer of the adjacent unit columns can be mirror-symmetrical relative to the column boundary line, the shape of the first active layer of the adjacent unit columns can be substantially the same, and the shape of the first semiconductor layer in the plurality of unit rows can be substantially the same.

[0353] (32) Forming a first conductive layer pattern. In an example embodiment, the process of forming the first conductive layer and the formed pattern can be substantially the same as that of the embodiment shown in FIG. 5, as shown in FIG. 28.

[0354] (33) Forming a second conductive layer pattern. In an example embodiment, the process of forming the second conductive layer and the formed pattern can be substantially the same as that of the embodiment shown in FIG. 5, as shown in FIG. 29.

[0355] (34) Forming a second semiconductor layer pattern. In an example embodiment, the process of forming the second semiconductor layer and the formed pattern can be substantially the same as that of the embodiment shown in FIG. 5, as shown in FIG. 30.

[0356] (35) Forming a third conductive layer pattern. In an example embodiment, the process of forming the third conductive layer and the formed pattern can be substantially the same as that of the embodiment shown in FIG. 5, except that a second initial connection block 42-1 can be provided in the circuit unit of each unit column, and the second initial connection block 42-1 is configured to connect, through a second initial electrode to be formed later, the first region of the seventh active layer in each circuit unit, as shown in FIGS. 31A and 31B, which is a plan view of the third conductive layer in FIG. 31A.

[0357] (36) Forming a sixth insulating layer pattern. In an example embodiment, the process of forming the sixth insulating layer and the formed pattern can be substantially the same as that of the embodiment shown in FIG. 5, except that a first via V1 is provided in each circuit unit, and the first via V1 in the first unit column is configured to make the first region of the first active layer connect, through a first initial electrode to be formed later, the first region of the first active layer, and the first via V1 in the second unit column is configured to make the first region of the first active layer connect, through a fourth initial electrode to be formed later, the first region of the first active layer, as shown in FIG. 32.

[0358] In an example embodiment, a seventeenth via V17 can be provided in the circuit unit of each unit column, and configured to make the second initial electrode to be formed later connect the second initial connection block 42-1 through the via.

[0359] (37) forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the fourth conductive thin film using a patterning process, and forming the fourth conductive layer disposed on the sixth insulating layer, as shown in FIGS. 33A and 33B, which is a plan view of the fourth conductive layer in FIG. 33A.

[0360] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, a second initial electrode 72, and a third initial electrode 73.

[0361] In an exemplary embodiment, the positions, shapes, and connection relationships of the first connection electrode 51 to the seventh connection electrode 57 and the third initial electrode 73 can be substantially the same as those of the embodiment shown in FIG. 5.

[0362] In an exemplary embodiment, the second initial electrode 72 can have a strip shape extending along the second direction Y, a first end of the second initial electrode 72 is connected to the first region of the seventh active layer through a tenth via V10, and a second end of the second initial electrode 72 is connected to the second initial connection block 42-1 through a seventeenth via V17, thus realizing that the second initial signal line 42 writes a second initial signal to the first region of the seventh active layer.

[0363] In an exemplary embodiment, the fourth conductive layer can further include a first initial electrode 71.

[0364] In an exemplary embodiment, the first initial electrode 71 can have a strip shape extending along the second direction Y, a first end of the first initial electrode 71 is connected to the first region of the first active layer through a first via V1, and a second end of the first initial electrode 71 is connected to a first initial connection block 41-1 through a fifteenth via V15. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal line 41 writes a first initial signal to the first region of the first active layer is realized.

[0365] In an exemplary embodiment, the first initial signal line 41 can be disposed in each unit row, and the first initial electrode 71 can be disposed in the first unit column. For example, the first initial electrode 71 can be disposed in the Nth unit column and the N+2th unit column, respectively, that is, the first transistors T1 of the plurality of circuit units in the Nth unit column and the N+2th unit column (first unit column) are provided with a first initial signal by the first initial signal line 41.

[0366] In the exemplary embodiment, the fourth conductive layer can further include a second initial connection line 62 and a second connection strip 65.

[0367] In the exemplary embodiment, the second initial connection line 62 can be in a shape of a polyline extending along the second direction Y, and can be arranged on a side of the first connection electrode 51 away from the second connection electrode 52. The second connection strip 65 can be in a shape of a strip extending along the first direction X, and can be arranged between the second initial connection line 62 and the second initial electrode 72. A first end of the second connection strip 65 is connected with the second initial connection line 62, and a second end of the second connection strip 65 is connected with the second initial electrode 72. Since the second initial electrode 72 is connected with the second initial signal line 42, a meshed communication structure for transmitting the second initial signal is formed by the second initial signal line 42 extending along the first direction X and the second initial connection line 62 extending along the second direction Y, which can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0368] In the exemplary embodiment, in at least one circuit unit, the second connection strip 65 can be arranged between the second initial signal line 42 and the third initial signal line 43, and the second initial connection line 62, the second connection strip 65 and the second initial electrode 72 can be an integrated structure connected with each other.

[0369] In the exemplary embodiment, the second initial signal line 42 can be arranged in each unit row, and the second initial connection line 62 can be arranged in part of the first unit columns. There can be 3 circuit units between adjacent second initial connection lines 62 in the first direction X. For example, the second initial connection line 62 can be arranged in the Nth unit column. For another example, the second initial connection line 62 can be arranged in the N+4th unit column.

[0370] In the exemplary embodiment, the fourth conductive layer can further include a third initial connection line 63 and a third connection strip 66. The third initial connection line 63 and the third connection strip 66 can be substantially the same as the embodiment shown in FIG. 5 in position, shape and connection relationship, and form a meshed communication structure for transmitting a third initial signal.

[0371] In the exemplary embodiment, the fourth conductive layer can further include a fourth initial signal line 44 and a fourth initial electrode 74.

[0372] In the example embodiment, the fourth initial signal line 44 can be in the shape of a broken line extending along the second direction Y, and can be arranged on the side of the first connection electrode 51 away from the second connection electrode 52. The fourth initial electrode 74 can be in the shape of a strip extending along the first direction Y, and can be arranged on the side of the fourth initial signal line 44 close to the first active layer and connected to the fourth initial signal line 44. The fourth initial electrode 74 is connected to the first region of the first active layer through the first via V1, so that the fourth initial signal line 44 writes the first initial signal to the first region of the first active layer.

[0373] In the example embodiment, the fourth initial signal line 44 and the fourth initial electrode 74 can be an integrated structure connected to each other in at least one circuit unit.

[0374] In the example embodiment, the fourth initial signal line 44 can be arranged in the second unit column, and there can be 1 circuit unit between adjacent fourth initial signal lines 44 in the first direction X. For example, the fourth initial signal line 44 can be arranged in the N+1th unit column and the N+3th unit column, that is, the first transistors T1 of the plurality of circuit units in the N+1th unit column and the N+3th unit column (the second unit column) are provided with the first initial signal by the fourth initial signal line 44.

[0375] In the example embodiment, the second initial connection line 62, the fourth initial signal line 44, the third initial connection line 63, and the fourth initial signal line 44 can be periodically arranged in the first direction X. Two fourth initial signal lines 44 and one third initial connection line 63 can be arranged between two adjacent second initial connection lines 62 in the first direction X. One second initial connection line 62 or one third initial connection line 63 can be arranged between two adjacent fourth initial signal lines 44 in the first direction X. One second initial connection line 62 and two fourth initial signal lines 44 can be arranged between two adjacent third initial connection lines 63 in the first direction X. In the first direction X, the second initial connection line 62 can be arranged between two fourth initial signal lines 44. The fourth initial signal line 44 can be arranged between the second initial connection line 62 and the third initial connection line 63. The third initial connection line 63 can be arranged between two fourth initial signal lines 44.

[0376] In the example embodiment, the second initial connection line 62 and the fourth initial signal line 44 of adjacent unit columns can be mirror symmetrical with respect to the column boundary line. The third initial connection line 63 and the fourth initial signal line 44 of adjacent unit columns can be mirror symmetrical with respect to the column boundary line.

[0377] In an exemplary embodiment, the pixel driving circuit of the plurality of circuit units in the first unit column (the Nth unit column and the N+2th unit column) can be connected with the red light emitting device emitting red light and the blue light emitting device emitting blue light. The pixel driving circuit of the plurality of circuit units in the second unit column (the N+1th unit column and the N+3th unit column) can be connected with the first green light emitting device emitting green light and the second green light emitting device emitting green light.

[0378] In an exemplary embodiment, the first initial signal line 41 can be provided in each unit row, the first initial electrode 71 can be provided in the first unit column, the first transistor T1 of the plurality of circuit units in the first unit column is provided with the first initial signal by the first initial signal line 41, the fourth initial signal line 44 and the fourth initial electrode 74 can be provided in the second unit column, the first transistor T1 of the plurality of circuit units in the second unit column is provided with the first initial signal by the fourth initial signal line 44, that is, the pixel driving circuit connected with the red light emitting device and the blue light emitting device is provided with the first initial signal with the first voltage by the first initial signal line 41 located in the third conductive layer (GATE3), the pixel driving circuit connected with the first green light emitting device and the second green light emitting device is provided with the first initial signal with the second voltage by the fourth initial signal line 44 located in the fourth conductive layer (SD1), and the voltage value of the first voltage and the voltage value of the second voltage are different.

[0379] In another exemplary embodiment, the first initial signal line 41 can be provided in each unit row, the first initial electrode 71 can be provided in the second unit column, the first transistor T1 of the plurality of circuit units in the second unit column is provided with the first initial signal by the first initial signal line 41, the fourth initial signal line 44 and the fourth initial electrode 74 can be provided in the first unit column, the first transistor T1 of the plurality of circuit units in the first unit column is provided with the first initial signal by the fourth initial signal line 44, that is, the pixel driving circuit connected with the first green light emitting device and the second green light emitting device is provided with the first initial signal with the first voltage by the first initial signal line 41 located in the third conductive layer (GATE3), the pixel driving circuit connected with the red light emitting device and the blue light emitting device is provided with the first initial signal with the second voltage by the fourth initial signal line 44 located in the fourth conductive layer (SD1), and the voltage value of the first voltage and the voltage value of the second voltage are different.

[0380] In the example embodiment, the fourth conductive layer of the adjacent cell columns (except the second connection bar 65, the third connection bar 66, the first initial electrode 71 and the fourth initial electrode 74) can be mirror-symmetrical with respect to the column boundary line. For example, the fourth conductive layer of the Nth cell column and the fourth conductive layer of the N+lth cell column can be mirror-symmetrical with respect to the column boundary line, the fourth conductive layer of the N+lth cell column and the fourth conductive layer of the N+2th cell column can be mirror-symmetrical with respect to the column boundary line, and the fourth conductive layer of the N+2th cell column and the fourth conductive layer of the N+3th cell column can be mirror-symmetrical with respect to the column boundary line. In the example embodiment, the shape of the fourth conductive layer in the plurality of cell rows can be substantially the same.

[0381] In the example embodiment, the structure of the driving structure layer of the present embodiment can be substantially the same as that of the embodiment shown in FIG. 5, except that the fourth conductive layer can include at least the second initial connection line, the third initial connection line, the fourth initial signal line and the plurality of connection electrodes.

[0382] FIG. 34 is a schematic view of another structure of the initial lead-out lines and the initial traces according to an example embodiment of the present disclosure. As shown in FIG. 34, the binding area 200 can include at least the first initial lead-out line 201, the second initial lead-out line 202, the third initial lead-out line 203 and the fourth initial lead-out line 204, and the frame area 300 can include at least the first initial trace 301, the second initial trace 302 and the third initial trace 303.

[0383] In the example embodiment, the structures of the first initial lead-out line 201, the second initial lead-out line 202 and the third initial lead-out line 203 in the binding area 200, and the first initial trace 301, the second initial trace 302 and the third initial trace 303 in the frame area 300 can be substantially the same as those of the embodiment shown in FIG. 14.

[0384] In the example embodiment, the fourth initial lead-out line 204 in the binding area 200 can be in the shape of a straight line or a broken line extending along the second direction Y, and can be arranged on one side or both sides of the binding area 200 in the first direction X. One end of the fourth initial lead-out line 204 is connected to the fourth initial pad of the binding pin area, and the other end extends toward the display area 100, and is connected to the plurality of fourth initial signal lines 44 in the display area 100 through the horizontal connection line, and provides the first initial signal to the plurality of fourth initial signal lines 44.

[0385] In the example embodiment, the shapes of the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 in the display area 100 can be straight lines or broken lines with body portions extending along the first direction X, the shape of the fourth initial signal line 44 can be a straight line or a broken line extending along the second direction Y, the first initial signal line 41 and the fourth initial signal line 44 are configured to provide the first initial signal to the pixel driving circuit, the second initial signal line 42 is configured to provide the second initial signal to the pixel driving circuit, the third initial signal line 43 is configured to provide the third initial signal to the pixel driving circuit, the first initial signal provided by the first initial signal line 41 has a first voltage, the first initial signal provided by the fourth initial signal line 44 has a second voltage, and the voltage value of the first voltage is different from the voltage value of the second voltage.

[0386] In the example embodiment, the display area 100 can further include a plurality of second initial connection lines 62 and a plurality of third initial connection lines 63 extending along the second direction Y, the plurality of second initial connection lines 62 are connected with the plurality of second initial signal lines 42 to form a mesh-shaped communication structure for transmitting the second initial signal, and the plurality of third initial connection lines 63 are connected with the plurality of third initial signal lines 43 to form a mesh-shaped communication structure for transmitting the third initial signal.

[0387] The example embodiment of the present disclosure provides a display substrate, by providing a first initial signal line and a fourth initial signal line to provide a first initial signal with different voltages, connecting the pixel driving circuit connected with the red light emitting device and the blue light emitting device with the first initial signal line, and connecting the pixel driving circuit connected with the green light emitting unit with the fourth initial signal line, the voltage of the first initial signal can be adjusted according to different display requirements, and high refresh rate (up to 520 PPI) and high quality display can be achieved.

[0388] The example embodiment of the present disclosure provides a display substrate, by providing a first initial signal line and a fourth initial signal line to provide a first initial signal with different voltages, connecting the pixel driving circuit connected with the red light emitting device and the blue light emitting device with the first initial signal line, and connecting the pixel driving circuit connected with the green light emitting unit with the fourth initial signal line, the voltage of the first initial signal can be adjusted according to different display requirements, and high refresh rate (up to 520 PPI) and high quality display can be achieved.

[0389] The third initial signal lines and the third initial connection lines are connected to each other, a mesh communication structure for transmitting the third initial signal is formed on the display substrate, the resistance of the third initial signal lines can be effectively reduced, the voltage drop of the third initial signal can be reduced, the uniformity of the third initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and display performance are improved.

[0390] The first initial signal lines and the fourth initial signal lines are arranged along the first direction X and the second direction Y respectively to provide the first initial signal with different voltages, the first initial signal lines are arranged on the third conductive layer (GATE3), and the fourth initial signal lines are arranged on the fourth conductive layer (SD1), the structure is simple and reasonable, the preparation process of the display substrate can be well compatible with the existing preparation process, the process is simple to implement, the production efficiency is high, the production cost is low, and the yield is high.

[0391] The foregoing structure and the preparation process thereof are only an exemplary description, and in the exemplary embodiments, the corresponding structure can be changed, and the patterning process can be added or reduced, which is not limited in the present disclosure.

[0392] In the exemplary embodiments, the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0393] The present disclosure also provides a preparation method of a display substrate for manufacturing the display substrate provided in the above embodiments. In the exemplary embodiments, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of unit columns include a plurality of first unit columns and a plurality of second unit columns, the first unit columns are odd unit columns, and the second unit columns are even unit columns, or the first unit columns are even unit columns, and the second unit columns are odd unit columns; the preparation method can include:

[0394] The pixel driving circuit is formed in a circuit unit; the pixel driving circuit in the first unit column is connected with at least one first signal line extending along a first direction, the first signal line is configured to provide an initial signal with a first voltage to the pixel driving circuit in the first unit column, the pixel driving circuit in the second unit column is connected with at least one second signal line extending along a second direction, the second signal line is configured to provide an initial signal with a second voltage to the pixel driving circuit in the second unit column; the first direction and the second direction intersect, and the first voltage and the second voltage are different.

[0395] While the embodiments disclosed by the present disclosure are as above, it should be noted that the above embodiments are merely exemplary, but not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, and omissions can be made without departing from the scope of the present disclosure.

Claims

1. A display substrate comprising a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns, at least one circuit unit comprising a pixel driving circuit; the plurality of cell columns comprising a plurality of first cell columns and a plurality of second cell columns, wherein the first cell columns are odd-numbered cell columns and the second cell columns are even-numbered cell columns, or, the first cell columns are even-numbered cell columns and the second cell columns are odd-numbered cell columns; the pixel driving circuit in the first cell column is connected to at least one first signal line extending along a first direction, the first signal line being configured to provide an initial signal having a first voltage to the pixel driving circuit in the first cell column; The pixel driving circuit in the second cell column is connected to at least one second signal line extending along a second direction, the second signal line being configured to provide an initial signal having a second voltage to the pixel driving circuit in the second cell column; The first direction and the second direction intersect, and the first voltage and the second voltage are different.

2. The display substrate according to claim 1, wherein, The at least one first signal line includes a first initial signal line configured to provide a first initial signal having a first voltage to the pixel driving circuit in the first cell column; the at least one second signal line includes a fourth initial signal line configured to provide a first initial signal having a second voltage to the pixel driving circuit in the second cell column.

3. The display substrate according to claim 2, wherein, The pixel driving circuit includes at least a first reset transistor, and the first reset transistor includes at least a first reset active layer; the first initial signal line is connected to the first region of the first reset active layer of the pixel driving circuit in the first unit column through a first initial electrode, and the fourth initial signal line is connected to the first region of the first reset active layer of the pixel driving circuit in the second unit column through a fourth initial electrode.

4. The display substrate according to claim 3, wherein, One end of the first initial electrode is connected to the first initial signal line through a via, and the other end of the first initial electrode is connected to the first region of the first reset active layer of the pixel driving circuit in the first unit column through a via; one end of the fourth initial electrode is connected to the fourth initial signal line, and the other end of the fourth initial electrode is connected to the first region of the first reset active layer of the pixel driving circuit in the second unit column through a via.

5. The display substrate according to claim 4, wherein, In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers; the first initial signal line and the fourth initial signal line are disposed in different conductive layers, and the first initial electrode, the fourth initial electrode and the fourth initial signal line are disposed in the same conductive layer; in at least one second circuit unit, the fourth initial electrode and the fourth initial signal line are an integral structure interconnected with each other.

6. The display substrate according to claim 2, wherein, At least one cell row further includes a second initial signal line extending along the first direction, the second initial signal line being configured to provide a second initial signal to the pixel driving circuit; at least one first cell column further includes a second initial connection line extending along the second direction, the second initial connection line being connected to the second initial signal line, forming a grid-connected structure on the display substrate for transmitting the second initial signal.

7. The display substrate according to claim 6, wherein, At least one cell row further includes a third initial signal line extending along the first direction, the third initial signal line being configured to provide a third initial signal to the pixel driving circuit; at least one first cell column further includes a third initial connection line extending along the second direction, the third initial connection line being connected to the third initial signal line to form a grid-connected structure on the display substrate for transmitting the third initial signal.

8. The display substrate according to claim 7, wherein, The second initial connection line, the fourth initial signal line, the third initial connection line, and the fourth initial signal line are periodically arranged in the first direction.

9. The display substrate according to claim 1, wherein, The at least one first signal line includes a second initial signal line, the second initial signal line being configured to provide a second initial signal having a first voltage to the pixel driving circuitry in the first cell column; The at least one second signal line includes a fifth initial signal line, which is configured to provide a second initial signal having a second voltage to the pixel driving circuitry in the second cell column.

10. The display substrate according to claim 9, wherein, The pixel driving circuit includes at least a second reset transistor, and the second reset transistor includes at least a second reset active layer; the second initial signal line is connected to the first region of the second reset active layer of the pixel driving circuit in the first unit column through a second initial electrode, and the fifth initial signal line is connected to the first region of the second reset active layer of the pixel driving circuit in the second unit column through a fifth initial electrode.

11. The display substrate according to claim 10, wherein, One end of the second initial electrode is connected to the second initial signal line through a via, and the other end of the second initial electrode is connected to the first region of the second reset active layer of the pixel driving circuit in the first unit column through a via; one end of the fifth initial electrode is connected to the fifth initial signal line, and the other end of the fifth initial electrode is connected to the first region of the second reset active layer of the pixel driving circuit in the second unit column through a via.

12. The display substrate according to claim 11, wherein, In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers; the second initial signal line and the fifth initial signal line are disposed in different conductive layers, and the second initial electrode, the fifth initial electrode and the fifth initial signal line are disposed in the same conductive layer; in at least one second circuit unit, the fifth initial electrode and the fifth initial signal line are an integral structure interconnected with each other.

13. The display substrate according to claim 9, wherein, At least one cell row further includes a first initial signal line extending along the first direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit; at least one first cell column further includes a first initial connection line extending along the second direction, the first initial connection line being connected to the first initial signal line to form a grid-connected structure on the display substrate for transmitting the first initial signal.

14. The display substrate according to claim 13, wherein, At least one cell row further includes a third initial signal line extending along the first direction, the third initial signal line being configured to provide a third initial signal to the pixel driving circuit; at least one first cell column further includes a third initial connection line extending along the second direction, the third initial connection line being connected to the third initial signal line to form a grid-connected structure on the display substrate for transmitting the third initial signal.

15. The display substrate according to claim 14, wherein, The first initial connection line, the fifth initial signal line, the third initial connection line, and the fifth initial signal line are periodically arranged in the first direction.

16. The display substrate according to claim 1, wherein, The at least one first signal line includes a third initial signal line configured to provide a third initial signal having a first voltage to the pixel driving circuit in the first cell column; the at least one second signal line includes a sixth initial signal line configured to provide a third initial signal having a second voltage to the pixel driving circuit in the second cell column.

17. The display substrate according to claim 16, wherein, The pixel driving circuit includes at least a third reset transistor, and the third reset transistor includes at least a third reset active layer; the third initial signal line is connected to the first region of the third reset active layer of the pixel driving circuit in the first unit column through a third initial electrode, and the sixth initial signal line is connected to the first region of the third reset active layer of the pixel driving circuit in the second unit column through a sixth initial electrode.

18. The display substrate according to claim 17, wherein, One end of the third initial electrode is connected to the third initial signal line through a via, and the other end of the third initial electrode is connected to the first region of the third reset active layer of the pixel driving circuit in the first unit column through a via; one end of the sixth initial electrode is connected to the sixth initial signal line, and the other end of the sixth initial electrode is connected to the first region of the third reset active layer of the pixel driving circuit in the second unit column through a via.

19. The display substrate according to claim 18, wherein, In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers; the third initial signal line and the sixth initial signal line are disposed in different conductive layers, and the third initial electrode, the sixth initial electrode and the sixth initial signal line are disposed in the same conductive layer; in at least one second circuit unit, the sixth initial electrode and the sixth initial signal line are an integral structure interconnected with each other.

20. The display substrate according to claim 16, wherein, At least one cell row further includes a first initial signal line extending along the first direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit; at least one first cell column further includes a first initial connection line extending along the second direction, the first initial connection line being connected to the first initial signal line to form a grid-connected structure on the display substrate for transmitting the first initial signal.

21. The display substrate according to claim 20, wherein, At least one cell row further includes a second initial signal line extending along the first direction, the second initial signal line being configured to provide a second initial signal to the pixel driving circuit; at least one first cell column further includes a second initial connection line extending along the second direction, the second initial connection line being connected to the second initial signal line, forming a grid-connected structure on the display substrate for transmitting the second initial signal.

22. The display substrate according to claim 21, wherein, The first initial connection line, the sixth initial signal line, the second initial connection line, and the sixth initial signal line are periodically arranged in the first direction.

23. The display substrate according to claims 1 to 22, wherein, The display substrate further includes multiple light-emitting units, including a red light-emitting unit, a blue light-emitting unit, a first green light-emitting unit, and a second green light-emitting unit. The red light-emitting unit includes a red light-emitting device that emits red light, the blue light-emitting unit includes a blue light-emitting device that emits blue light, the first green light-emitting unit includes a first green light-emitting device that emits green light, and the second green light-emitting unit includes a second green light-emitting device that emits green light. The red and blue light-emitting devices are connected to the pixel driving circuit in the first unit column, and the first and second green light-emitting devices are connected to the pixel driving circuit in the second unit column; or, the red and blue light-emitting devices are connected to the pixel driving circuit in the second unit column, and the first and second green light-emitting devices are connected to the pixel driving circuit in the first unit column.

24. A display device comprising a display substrate as described in any one of claims 1 to 23.

25. A method for fabricating a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the plurality of unit columns comprising a plurality of first unit columns and a plurality of second unit columns, wherein the first unit columns are odd-numbered unit columns and the second unit columns are even-numbered unit columns, or, the first unit columns are even-numbered unit columns and the second unit columns are odd-numbered unit columns; the fabrication method comprising: A pixel driving circuit is formed in the circuit unit; The pixel driving circuit in the first unit column is connected to at least one first signal line extending along a first direction, the first signal line being configured to provide an initial signal having a first voltage to the pixel driving circuit in the first unit column; the pixel driving circuit in the second unit column is connected to at least one second signal line extending along a second direction, the second signal line being configured to provide an initial signal having a second voltage to the pixel driving circuit in the second unit column. The first direction and the second direction intersect, and the first voltage and the second voltage are different.

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