A routing path determination method, apparatus and related device

Abstract

Embodiments of the present application provide a routing path determination method and device and related equipment, wherein the method comprises: obtaining link state information of a communication link in which a current chip node is located, the link state information being used to indicate busy degrees of a previous chip node and a next chip node, an occupancy ratio of an input buffer of the current chip node, and an occupancy ratio of an output buffer of the current chip node; obtaining node state information of each computing node in the current chip node, the node state information being used to indicate busy degrees of each computing node; and adjusting a routing path of data transmission between the current chip node and other chip nodes on the communication link in which the current chip node is located based on the link state information and the node state information. Embodiments of the present application improve cross-chip data transmission efficiency.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to a routing path determination method, apparatus, and related equipment. Background Technology

[0002] With ever-increasing performance demands and soaring manufacturing costs, traditional single-chip architectures struggle to balance performance enhancement with cost control. Against this backdrop, multi-chip systems have emerged. Multi-chip systems interconnect multiple relatively independent single chips to collaboratively complete computing tasks, maintaining high performance while reducing the complexity and manufacturing cost of individual chips. However, the performance of a multi-chip system largely depends on the interconnection efficiency between chips, i.e., the efficiency of cross-chip data transfer.

[0003] Against this backdrop, how to provide a routing path determination method to improve the efficiency of cross-chip data transmission has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a routing path determination method, apparatus, and related equipment to improve the efficiency of cross-chip data transmission.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a routing path determination method applied to a multi-chip system, the multi-chip system including multiple chips, each chip including multiple computing units, wherein one chip serves as a chip node, and one computing unit serves as a computing node, the method comprising:

[0007] Obtain the link status information of the communication link where the current chip node is located. The link status information is used to indicate the busy level of the previous chip node and the next chip node, the occupancy ratio of the input buffer of the current chip node, and the occupancy ratio of the output buffer of the current chip node.

[0008] Obtain the node status information of each computing node within the current chip node; the node status information is used to indicate the busy level of each computing node.

[0009] Based on the link status information and the node status information, the routing path for data transmission between the current chip node and other chip nodes on the communication link where the current chip node is located is adjusted.

[0010] Optionally, the busy level of the computing node is determined based on a busy coefficient, wherein the busy coefficient is calculated as follows:

[0011] When a compute node sends a data packet whose destination node is the current chip node, the busy coefficient of that compute node is incremented by 1;

[0012] When a compute node receives a response from a destination node that is the current chip node, the busy factor of that compute node is reduced by 1.

[0013] The busy factor of the current chip node is the sum of the busy factors of all computing nodes in the current chip node.

[0014] Optionally, adjusting the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node resides, based on the link status information and the node status information, includes:

[0015] Based on the link status information and the node status information, the current chip node sends alarm information to other chip nodes on the communication link where the current chip node is located, so that the other chip nodes can adjust the routing path of data transmission;

[0016] Based on the link status information, the current chip node adjusts the data transmission routing path of the current chip node.

[0017] Optionally, the current chip node, based on the link status information and the node status information, sends alarm information to other chip nodes on the communication link where the current chip node is located, including:

[0018] If the current chip node's busy coefficient is greater than or equal to the first preset value, send alarm information to the previous chip node and the next chip node so that the previous chip node and the next chip node can adjust the data transmission routing path.

[0019] If the occupancy rate of the input buffer of the current chip node is greater than or equal to the second preset value, an alarm message is sent to the previous chip node so that the previous chip node can adjust the data transmission routing path.

[0020] Optionally, if the busy coefficient of the current chip node is greater than or equal to the first preset value and continues to exist, the step of sending alarm information to the previous chip node and the next chip node specifically means: sending alarm information to the previous chip node and the next chip node at a preset frequency.

[0021] If the current chip node's input buffer occupancy rate is greater than or equal to the second preset value and this condition persists, sending an alarm message to the next chip node specifically involves sending an alarm message to the next chip node at a preset frequency.

[0022] Optionally, the current chip node adjusts the data transmission routing path of the current chip node based on the link state information, including:

[0023] If the current chip node's output buffer occupancy rate is greater than or equal to the third preset value, adjust the data transmission routing path of the current chip node.

[0024] If the current chip node receives alarm information from the previous chip node and / or the next chip node, adjust the data transmission routing path of the current chip node.

[0025] Optionally, if no alarm information is received from the previous chip node and / or the next chip node within a preset time, the original routing path is restored. The data transmission efficiency of the original routing path is higher than the data transmission efficiency of the routing path adjusted by the current chip node.

[0026] Secondly, embodiments of this application provide a routing path determination device applied to a multi-chip system, the multi-chip system including multiple chips, each chip including multiple computing units, wherein one chip serves as a chip node, and one computing unit serves as a computing node, the device comprising:

[0027] The link status awareness unit is used to obtain the link status information of the communication link where the current chip node is located. The link status information is used to indicate the busy level of the previous chip node and the next chip node, the occupancy ratio of the input buffer of the current chip node, and the occupancy ratio of the output buffer of the current chip node.

[0028] The node status awareness unit is used to obtain the node status information of each computing node within the current chip node. The node status information is used to indicate the busy level of each computing node.

[0029] The adjustment unit is used to adjust the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located, based on the link status information and the node status information.

[0030] Thirdly, embodiments of this application provide an electronic device, including at least one memory and at least one processor, wherein the memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the routing path determination method as described in the first aspect above.

[0031] Fourthly, embodiments of this application provide a storage medium that stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the routing path determination method described in the first aspect above is implemented.

[0032] Fifthly, embodiments of this application provide a computer program product including one or more computer-executable instructions, which, when executed, implement the routing path determination method as described in the first aspect above.

[0033] This application provides a routing path determination method, apparatus, and related devices. The method includes: acquiring link status information of the communication link where the current chip node is located, the link status information indicating the busy level of the previous and next chip nodes, the occupancy ratio of the input buffer of the current chip node, and the occupancy ratio of the output buffer of the current chip node; acquiring node status information of each computing node within the current chip node, the node status information indicating the busy level of each computing node; and adjusting the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located, based on the link status information and the node status information.

[0034] As can be seen, the routing path determination method provided in this application obtains the link status information of the communication link where the current chip node is located, as well as the node status information of each computing node within the current chip node, and adjusts the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located based on the link status information and the node status information. This effectively avoids data transmission congestion and delay caused by busy links or computing nodes, thereby improving the efficiency of cross-chip data transmission. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of on-chip and inter-chip interconnect networks;

[0037] Figure 2 This is a schematic diagram of the on-chip network structure;

[0038] Figure 3 This is a schematic diagram of an optional structure of the multi-chip system provided in the embodiments of this application;

[0039] Figure 4 This is an optional flowchart illustrating the routing path determination method provided in an embodiment of this application;

[0040] Figure 5This is an optional flowchart of step S300 provided in the embodiments of this application;

[0041] Figure 6 This is a schematic diagram of another optional structure of the multi-chip system provided in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of an optional structure of the routing path determination device provided in the embodiments of this application;

[0043] Figure 8 This is a schematic diagram of an optional chip structure provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram of an optional structure of the edge routing unit provided in an embodiment of this application;

[0045] Figure 10 This is a schematic diagram of an optional structure of the routing decision unit provided in an embodiment of this application;

[0046] Figure 11 This is a schematic diagram of an optional structure for the interaction between the routing decision unit and each edge routing unit provided in an embodiment of this application;

[0047] Figure 12 This is an optional block diagram of the electronic device provided in the embodiments of this application. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0049] As described in the background section, with the ever-increasing performance demands and the sharp rise in manufacturing costs, traditional single-chip architectures struggle to balance performance improvement and cost control. Against this backdrop, multi-chip systems have emerged. Multi-chip systems interconnect multiple relatively independent single chips to collaboratively complete computing tasks, maintaining high performance while reducing the complexity and manufacturing cost of single chips. However, the performance of a multi-chip system largely depends on the interconnection efficiency between chips, i.e., the efficiency of cross-chip data transmission. Therefore, how to provide a routing path determination method to improve cross-chip data transmission efficiency has become a crucial technical problem that those skilled in the art urgently need to solve.

[0050] In one alternative implementation, refer to Figure 1An exemplary schematic diagram of an on-chip and inter-chip interconnection network is shown. This network includes multiple on-chip networks 40 and a control module 50 (which can be considered a control network). The multiple on-chip networks 40 are wirelessly connected, and each on-chip network 40 includes multiple enhancement routers 41. Each enhancement router 41 can determine its own network status (e.g., congestion or normal). Further, as... Figure 2 As shown, each of the enhanced routers 41 communicates with its respective service node 42, and the enhanced routers 41 are connected to each other through a local connection channel 43.

[0051] The control module 50 includes a central control node 51 and multiple levels of sub-control nodes 52. The central control node 51, the multiple levels of sub-control nodes 52, and the enhanced router 41 communicate in a tree topology. The enhanced router 41 is a leaf node in the tree topology, the sub-control nodes 52 are intermediate nodes, and the central control node 51 is the root node.

[0052] The master control node 51, sub-control nodes 52, and enhanced router 41 communicate using an adaptive round-robin mechanism. Specifically, the parent node first initializes the polling frequency of all its child nodes to an equal frequency, and then polls its child nodes in the polling order, sending polling frames. If a polled child node has network status changes, it sends an acknowledgment frame to the parent node; otherwise, it remains silent. The parent node waits for feedback from the polled child nodes. If it receives an acknowledgment frame, it updates the child node network status recorded in the storage unit, reduces the polling frequency of child nodes without network status changes based on the child node's historical feedback frequency, and specifies the optimal routing rule based on the child node's network status information.

[0053] The inventors analyzed that the routing rules in the above scheme are entirely controlled by the central control node, which will lead to the following problems: First, the access latency is affected by the polling time and the transmission time of the polling frame-response frame in the multi-layer control network. The topology is too complex, which will lead to high network latency. After the central control node receives the response frame reflecting the network status change information, it may have already updated the network status of the relevant nodes in the process of issuing new routing decisions to each child node. Second, if the central control node or the sub-control nodes experience congestion, deadlock or failure, the nodes will not be able to obtain routing information in time, which may lead to more serious congestion.

[0054] The inventors further believe that the root cause of the above problems lies in the overly complex network topology. Specifically, in this network topology, each enhanced router acts as a node, resulting in an excessive number of leaf nodes and a corresponding excessive network hierarchy. In the specific control flow, because the central control node needs to obtain state change information from each sub-control node and each enhanced router, and make corresponding routing decisions, it sequentially transmits the corresponding routing decision information based on the hierarchical structure. This causes the access latency to increase with the polling time during information transmission and the transmission time of polling frames and response frames in the control network, leading to low timeliness of routing decisions in multi-chip systems where network states change rapidly. Furthermore, if anomalies occur in information transmission at the central control node or sub-control nodes, it will lead to even more severe congestion.

[0055] In view of this, embodiments of this application provide a routing path determination method, apparatus, and related devices. The method includes: acquiring link status information of the communication link where the current chip node is located, the link status information indicating the busy levels of the previous and next chip nodes, the occupancy ratio of the input buffer of the current chip node, and the occupancy ratio of the output buffer of the current chip node; acquiring node status information of each computing node within the current chip node, the node status information indicating the busy level of each computing node; and adjusting the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located, based on the link status information and the node status information.

[0056] As can be seen, the routing path determination method provided in this application obtains the link status information of the communication link where the current chip node is located, as well as the node status information of each computing node within the current chip node, and adjusts the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located based on the link status information and the node status information. This effectively avoids data transmission congestion and delay caused by busy links or computing nodes, thereby improving the efficiency of cross-chip data transmission.

[0057] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0058] The routing path determination method provided in this application is applied to multi-chip systems. (Refer to...) Figure 3The exemplary diagram illustrates an optional structure of a multi-chip system, which includes multiple chips, such as chip 1 to chip n. Each chip includes multiple computing units, which are units within the chip used to perform actual computing tasks. These computing units can independently perform data processing, computation, and other operations, and are the foundation for the chip to realize various functions. In this application, one chip serves as a chip node, and one computing unit serves as a computing node.

[0059] It should be noted that this application is only for the purpose of... Figure 3 The chip interconnect structure shown is illustrated as an example. In other embodiments, other interconnect structures (such as tree, ring, star, etc.) can be adopted in the network architecture design. This application does not limit this.

[0060] Further reference Figure 4 , Figure 4 This is a schematic diagram of an optional flowchart of the routing path determination method provided in an embodiment of this application. For example... Figure 4 As shown, the method may include the following steps:

[0061] Step S100: Obtain the link status information of the communication link where the current chip node is located.

[0062] The link status information is used to indicate the busy levels of the previous and next chip nodes, the occupancy rate of the current chip node's input buffer, and the occupancy rate of the current chip node's output buffer. The link status information reveals the busy levels of the previous and next chip nodes. By understanding the busy status of the previous chip node, it can be determined whether the speed at which data flows from the previous chip node to the current chip node will be affected; by understanding the busy status of the next chip node, the ease with which the current chip node can send data to the next chip node can be estimated. For example, if the next chip node is busy, the data sent by the current chip node may accumulate in the output buffer, leading to increased transmission latency.

[0063] The occupancy rate of the current chip node's input buffer reflects the backlog of data received from the previous chip node. If the occupancy rate is too high, it indicates that the current chip node's input buffer is already under high load, and continuing to receive large amounts of data may affect data processing efficiency and system stability. The occupancy rate of the current chip node's output buffer reflects the amount of data the current chip node is preparing to send to the next chip node. If the occupancy rate is too high, it indicates that the current chip node's output buffer is already under high load, posing a risk of data backlog.

[0064] Step S200: Obtain the node status information of each computing node within the current chip node.

[0065] The node status information is used to indicate the workload of each computing node. This embodiment uses workload as an indicator to quantify the workload of computing nodes, thereby providing a basis for subsequent task allocation, resource scheduling, and other operations to ensure that chip resources are used rationally and efficiently.

[0066] In a specific implementation, the busy level of the computing node can be determined based on a busy coefficient, which is calculated as follows:

[0067] When a compute node sends a data packet destined for the current chip node, its busy coefficient increases by 1. When a compute node actively sends a data packet to the current chip node, it means that the compute node has data that needs to be processed or transmitted within the current chip, indicating that the compute node is actively engaging in data interaction, and its workload is increasing; therefore, its busy coefficient is increased by 1. It is understandable that when a compute unit sends a data packet, it needs to occupy its own communication resources, such as the send buffer and communication interface. Even if the data packet is sent to other compute nodes within the chip node, the occupation of these resources will still increase the workload of the compute unit. For example, the send buffer needs to store the data to be sent, and the communication interface needs to perform data encoding and modulation operations, all of which consume the compute unit's computing resources and time.

[0068] When a compute node receives a response destined for the current chip node, its busy level is reduced by 1. The response refers to feedback information returned by other chip nodes in response to data packets sent by the current chip node. When a compute node receives a response for the current chip node, it indicates that the previously initiated data transmission operation has been acknowledged, meaning that some tasks have been completed or progressed, and the workload is correspondingly reduced; therefore, its busy level is reduced by 1.

[0069] The current chip node's busy coefficient is the sum of the busy coefficients of all compute nodes within that chip node. The overall busy coefficient of the current chip node is obtained by accumulating the busy coefficients of all compute nodes within the chip node. This metric reflects the workload of the entire chip node as a whole. Measuring the workload of a chip node at a macro level helps with resource management and task scheduling at the chip level. For example, when a chip node's busy coefficient is high, the allocation of new tasks can be reduced or resources can be reallocated to ensure stable chip operation.

[0070] Step S300: Based on the link status information and the node status information, adjust the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located.

[0071] This application embodiment adjusts the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located based on the link status information and the node status information, thereby effectively avoiding data transmission congestion and delay caused by busy links or computing nodes, and thus improving the efficiency of cross-chip data transmission.

[0072] In the optional implementation, refer to Figure 5 An exemplary schematic diagram of the optional process of step S300 is shown, such as... Figure 5 As shown, step S300, based on the link status information and the node status information, adjusts the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located, which may include:

[0073] Step S301: Based on the link status information and the node status information, the current chip node sends alarm information to other chip nodes on the communication link where the current chip node is located, so that the other chip nodes can adjust the routing path of data transmission.

[0074] In a specific implementation, the current chip node sends alarm information to other chip nodes on the communication link where it is located, based on the link status information and the node status information, so that the other chip nodes can adjust the data transmission routing path. This can include the following two cases:

[0075] Scenario 1: If the current chip node's busy coefficient is greater than or equal to a first preset value, an alarm message is sent to the previous and next chip nodes to enable them to adjust their data transmission routing paths. This embodiment monitors the current chip node's busy coefficient in real time and compares it to a first preset value. The first preset value is a pre-defined threshold used to measure whether a chip node is in a busy state. If the current chip node's busy coefficient is greater than or equal to the first preset value, it indicates that the current chip node is already busy and cannot efficiently handle more data transmission tasks. In this case, the current chip node sends an alarm message to the previous and next chip nodes to notify them of the current chip node's busy status, allowing the previous and next chip nodes to adjust their routing strategies based on this information, avoiding sending large amounts of data to the currently busy chip node. The previous and next chip nodes refer to chip nodes directly connected to the current chip node on the routing path.

[0076] Understandably, while the next chip node might not send data to the current chip node based on some strategy, the overall system routing strategy is dynamic. For example, when other parts of the network experience congestion or failure, data paths that originally didn't pass through the current chip node might be replanned, causing the next chip node or chip nodes in other directions to need to send data to the current chip node. Therefore, sending alarm information to the next chip node in advance allows it to consider the current chip node's busy status during path adjustments, avoiding introducing data to an already busy current chip node.

[0077] In this embodiment, by sending alarm information to adjacent chip nodes to trigger a route update alarm, the routing path of data transmission is adjusted to avoid directing excessive data traffic to the busy current chip node, thereby alleviating the processing pressure on the current chip node and ensuring the data transmission efficiency and stability of the entire multi-chip system.

[0078] In the specific implementation, after receiving alarm information, the previous and next chip nodes will re-plan the data transmission route based on their own routing algorithms and the current network conditions. For example, they may select other relatively idle chip nodes as data relay nodes, or adjust the data transmission priority to prioritize data that does not pass through currently busy chip nodes. This application distributes data traffic to other chip nodes by adjusting the data transmission route, reducing the burden on the current chip node and ensuring that data can be transmitted efficiently and stably in the multi-chip system.

[0079] In an optional implementation, sending alarm information to the upstream and downstream chip nodes can be achieved by sending alarm shards to the upstream and downstream chip nodes. These alarm shards include information about the current chip node's workload, such as a specific workload coefficient or workload level (e.g., high, medium, low), reflecting the chip node's current workload. A shard is a commonly used data transmission unit in inter-chip communication, typically smaller than a complete data packet, and is used to carry specific control or status information.

[0080] It should be noted that the above-mentioned method of sending alarm information by sending alarm micro-chips is only an optional implementation. In actual situations, other methods (such as sending congestion signals) can also be used to send alarm information, and this application embodiment does not limit this.

[0081] Furthermore, if the current chip node's busy coefficient is greater than or equal to a first preset value and persists, sending alarm information to the next and previous chip nodes specifically involves sending alarm information to the next and previous chip nodes at a preset frequency. If the current chip node's busy coefficient is greater than or equal to the first preset value and this situation persists, it indicates that the current chip node is continuously facing high load or congestion. In this case, the current chip node can send alarm information to the next and previous chip nodes at a preset frequency so that adjacent chip nodes (i.e., the previous and next chip nodes) are aware of the current chip node's congestion status, allowing them to take appropriate measures, such as adjusting the data transmission rate or path selection, to avoid further exacerbating the current chip node's congestion. This application, by sending alarm information at a preset frequency, strikes a balance between timely notification and avoiding excessive network overhead, preventing the problem of network congestion exacerbated by excessively high sending frequencies or untimely responses due to excessively low sending frequencies.

[0082] Scenario 2: If the occupancy rate of the current chip node's input buffer is greater than or equal to a second preset value, an alarm message is sent to the previous chip node so that the previous chip node can adjust the data transmission routing path. The occupancy rate of the input buffer reflects the data receiving load of the current chip node. When the occupancy rate of the input buffer is greater than or equal to the second preset value, it indicates that the current chip node's input buffer is already under high load, and continuing to receive a large amount of data may affect data processing efficiency and system stability. At this time, an alarm message can be sent to the previous chip node so that the previous chip node is aware of the current chip node's load status and can adjust its data transmission routing path to avoid sending too much data to the currently busy chip node.

[0083] In the actual implementation, after receiving an alarm, the previous chip node can choose to send the data to other relatively idle chip nodes or adjust the data transmission rate to reduce the burden on the current chip node, based on its own routing strategy.

[0084] Furthermore, if the occupancy rate of the current chip node's input buffer is consistently greater than or equal to a second preset value, sending an alarm message to the next chip node specifically involves sending an alarm message to the next chip node at a preset frequency. If the occupancy rate of the current chip node's input buffer is greater than or equal to the second preset value, and this situation persists, it indicates that the current chip node's input buffer is continuously facing high load or is about to overflow. In this case, the current chip node can send an alarm message to the next chip node at a preset frequency so that the next chip node is aware of the status of the current chip node's input buffer, allowing the next chip node to take appropriate measures, such as adjusting the data transmission rate or path selection, thereby avoiding further increasing the load on the current chip node's input buffer. Similarly, by sending an alarm message to the next chip node at a preset frequency, a balance can be struck between timely notification and avoiding excessive network overhead, preventing network congestion from worsening due to excessively high sending frequency or untimely response due to excessively low sending frequency.

[0085] It is understandable that since a high input buffer occupancy rate is usually caused by the previous chip node sending data too quickly, if the current chip node's input buffer occupancy rate is greater than or equal to the second preset value, it is only necessary to notify the previous chip node so that the previous chip node can take appropriate measures.

[0086] refer to Figure 5 Then, proceed to step S302, whereby the current chip node adjusts the data transmission routing path of the current chip node based on the link status information.

[0087] In a specific implementation, the current chip node adjusts the data transmission routing path of the current chip node based on the link state information, which can include the following two cases:

[0088] Scenario 1: If the current chip node's output buffer occupancy rate is greater than or equal to the third preset value, adjust the data transmission routing path of the current chip node. The output buffer occupancy rate reflects the data transmission load of the current chip node. When the output buffer occupancy rate is greater than or equal to the third preset value, it indicates that the current chip node's output buffer is under high load, posing a risk of data backlog. This situation may be due to adjacent chip nodes being busy, preventing data from being transmitted from the current chip node to adjacent chip nodes in a timely manner, thus causing data accumulation in the current chip node's output buffer. In this case, to avoid further burdening the output buffer and prevent data overflow and increased transmission latency, the data transmission routing path of the current chip node can be adjusted, rerouting data originally routed to a busy adjacent chip node to other relatively idle chip nodes.

[0089] Scenario 2: If the current chip node receives alarm information from the previous and / or next chip node, adjust the data transmission routing path of the current chip node. When the current chip node receives alarm information from the previous and / or next chip node, it indicates that the previous and / or next chip node is already busy and cannot efficiently handle more data transmission tasks. In this case, to avoid continuing to send a large amount of data to the currently busy chip node, the data transmission routing path of the current chip node can be adjusted, rerouting data originally routed to adjacent chips that are already busy to other relatively idle chip nodes.

[0090] It should be noted that, in order to avoid sending large amounts of data to the currently busy chip node, the current chip node will still transmit data according to the adjusted route even if the adjusted data transmission route is not the optimal route (e.g., the path length increases, the transmission delay increases, etc.).

[0091] This application embodiment adjusts the data transmission routing path of the current chip node to reroute data to other relatively idle chip nodes, thereby bypassing chip nodes that are congested or overly busy, and thus improving data transmission efficiency.

[0092] Furthermore, if no alarm information is received from the previous chip node and / or the next chip node within a preset time, the original routing path is restored. The data transmission efficiency of the original routing path is higher than that of the adjusted routing path of the current chip node. If no alarm information is received from the previous chip node and / or the next chip node within the preset time, it indicates that the busy state of the previous chip node and / or the next chip node has been alleviated. Since the data transmission efficiency of the original routing path is higher than that of the adjusted routing path of the current chip node, the original routing path can be restored so that data can be transmitted again on an efficient path, improving data transmission efficiency and reducing data transmission latency.

[0093] Understandably, the load on a chip node is dynamic, and chip nodes may experience brief periods of high activity. By setting preset times and restoring the original routing path based on alarm information, the current chip node can dynamically adjust its routing path according to the real-time status of neighboring chip nodes to adapt to these dynamic changes. For example, in a multi-chip system, a sudden surge in data transmission at a certain moment may cause neighboring chip nodes to become busy. The current chip node may then adjust its data transmission routing path to other relatively idle chip nodes. After a period of time, the sudden data traffic decreases, the busy status of neighboring chip nodes is alleviated, and the current chip node does not receive any more alarm information within the preset time. At this point, the current chip node can restore its original routing path, enabling data transmission to proceed more efficiently.

[0094] The following example illustrates the routing path determination scheme described above. (Reference) Figure 6 An exemplary schematic diagram of another optional structure of a multi-chip system is shown, comprising eight chips, for example, chip 1, chip 2... chip 8. Assume that in the initial state, the initial routing path from chip 1 to chip 5 is 1->5. If chip 1 receives an alarm message from chip 5, this indicates a risk of congestion on the current routing path. In this case, chip 1 will adjust the next-hop route of the initial routing path, for example, changing the initial routing path from chip 1 to chip 5 to 1->2->5.

[0095] After the data packet is forwarded to chip 2, assuming the initial routing path from chip 2 to chip 5 is 2->4->5, if the busy coefficient of chip 4 is greater than or equal to a first preset value, chip 4 will send an alarm message to chip 2 via the link. Then, chip 2 will further adjust the next-hop route, for example, adjusting the initial routing path from chip 2 to chip 5 to 2->5. If chip 2 does not receive an alarm message from chip 5 at this point, it indicates that chip 2 can forward data packets to chip 5.

[0096] As can be seen, this application embodiment adjusts the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located based on the link status information and the node status information, thereby effectively avoiding data transmission congestion and delay caused by busy links or computing nodes, and thus improving the efficiency of cross-chip data transmission.

[0097] The routing path determination apparatus provided in the embodiments of this application will be described below. The routing path determination apparatus described below can be considered as a software or hardware functional module required to implement the routing path determination method provided in the embodiments of this application. The content of the routing path determination apparatus described below can be referred to in correspondence with the content of the method described above.

[0098] In an optional implementation, Figure 7 An exemplary schematic diagram of an optional structure of the routing path determination device provided in an embodiment of this application is shown. The routing path determination device is applied to a multi-chip system, which includes multiple chips, each chip including multiple computing units, wherein one chip serves as a chip node and one computing unit serves as a computing node. Figure 7 As shown, the route path determination device may include:

[0099] The link status sensing unit 11 is used to obtain the link status information of the communication link where the current chip node is located. The link status information is used to indicate the busy level of the previous chip node and the next chip node, the occupancy ratio of the input buffer of the current chip node, and the occupancy ratio of the output buffer of the current chip node.

[0100] The node status sensing unit 12 is used to obtain the node status information of each computing node in the current chip node, and the node status information is used to indicate the busy level of each computing node.

[0101] The adjustment unit 13 is used to adjust the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located, based on the link status information and the node status information.

[0102] In the specific implementation, refer to Figure 8 The exemplary schematic diagram of the optional structure of the chip shows that the chip is a single-chip system that constitutes the multi-chip system described above. The chip includes multiple computing units 100 and routing units 200 corresponding to each computing unit 100. The computing unit 100 refers to the unit in the chip used to perform actual computing tasks. It can independently perform data processing, calculation and other operations, and is the basis for the chip to realize various functions. The routing unit 200 is used to provide routing function for data transmission when the computing units interact with each other or with the outside world.

[0103] like Figure 8 As shown, the chip may further include at least one edge routing unit 300 (the figure illustrates an example of the chip including two edge routing units), and a routing decision unit 400 that interacts with the edge routing unit 300. In this application, the routing decision unit 400 inside the chip can be responsible for formulating and adjusting the routing strategy, so that after receiving an alarm message that the chip node is busy, it can make a routing adjustment decision based on the overall situation of the system.

[0104] Among them, such as Figure 9As shown, the edge routing unit 300 may include an input unit 301, a link status awareness unit 11, and an output feedback unit 302. The input unit 301 receives data from the previous chip node and introduces it to the current chip node for processing or further forwarding. The output feedback unit 302 sends data from the current chip node to the next chip node and feeds back data transmission feedback information (such as whether reception was successful) to the current chip node. The link status awareness unit 11 acquires the link status information of the communication link where the current chip node is located. This link status information indicates the busy levels of the previous and next chip nodes, the occupancy rate of the current chip node's input buffer, and the occupancy rate of the current chip node's output buffer.

[0105] This application sets the link state awareness unit 11 in the edge routing unit 300 so that the link state awareness unit 11 can obtain the occupancy ratio of the input buffer of the current chip node and the occupancy ratio of the output buffer of the current chip node.

[0106] like Figure 10 As shown, the routing decision unit 400 may include a node status awareness unit 12 and an adjustment unit 13. The node status awareness unit 12 is used to acquire node status information of each computing node within the current chip node, the node status information indicating the busy level of each computing node; the adjustment unit 13 is used to adjust the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located, based on the link status information and the node status information.

[0107] Further reference Figure 11 An exemplary schematic diagram of the optional structure for the interaction between the routing decision unit and each edge routing unit is shown, such as... Figure 11 As shown, firstly, the input unit 301 of each edge routing unit 300 initializes the input buffer size, and the output feedback unit 302 initializes the output buffer size. The routing decision unit 400 allocates and initializes routing tables for each computing unit within the current chip node, and simultaneously initializes the total busy coefficient of the current chip node. Then, the link state awareness unit 11 sets alarm thresholds for the occupancy ratios of the input and output buffers respectively, in order to monitor the occupancy status of the input and output buffers. The node state awareness unit 12 sets alarm thresholds for the busy coefficient of the current chip node, in order to monitor the busy level of the current chip node.

[0108] In an optional implementation, the current chip node can send alarm information to other chip nodes on the communication link where the current chip node is located, based on the link status information and the node status information, so that the other chip nodes can adjust the routing path of data transmission.

[0109] Specifically, if the current chip node's busy coefficient is greater than or equal to a first preset value (i.e., the alarm threshold of the current chip node's busy coefficient), an alarm message is sent to the previous chip node and the next chip node so that the previous chip node and the next chip node can adjust the data transmission routing path.

[0110] If the occupancy rate of the input buffer of the current chip node is greater than or equal to the second preset value (i.e., the alarm threshold of the occupancy rate of the input buffer), an alarm message is sent to the previous chip node so that the previous chip node can adjust the routing path of the data transmission.

[0111] In an optional implementation, if the busy coefficient of the current chip node is greater than or equal to a first preset value and continues to exist, sending alarm information to the next chip node and the next chip node specifically means sending alarm information to the next chip node and the next chip node at a preset frequency; if the occupancy ratio of the input buffer of the current chip node is greater than or equal to a second preset value and continues to exist, sending alarm information to the next chip node specifically means sending alarm information to the next chip node at a preset frequency.

[0112] In another alternative implementation, the current chip node can adjust the data transmission routing path of the current chip node based on the link state information.

[0113] Specifically, if the occupancy rate of the current chip node's output buffer is greater than or equal to a third preset value (i.e., the alarm threshold for the occupancy rate of the output buffer), the routing path for the data transmission of the current chip node is adjusted.

[0114] If the current chip node receives alarm information from the previous chip node and / or the next chip node, the data transmission routing path of the current chip node is adjusted. In an optional implementation, if no alarm information is received from the previous chip node and / or the next chip node again within a preset time, the original routing path is restored, and the data transmission efficiency of the original routing path is higher than the data transmission efficiency of the adjusted routing path of the current chip node.

[0115] This application also provides an electronic device that may include at least one memory and at least one processor. The memory stores one or more computer-executable instructions, and the processor invokes the one or more computer-executable instructions to execute the routing path determination method as described above.

[0116] As an optional implementation, refer to Figure 12 , Figure 12 This is an optional block diagram of the electronic device provided in the embodiments of this application. For example... Figure 12 As shown, the electronic device may include: at least one processor 21, at least one communication interface 22, at least one instruction memory 23 and at least one communication bus 24.

[0117] In this embodiment, the number of processor 21, communication interface 22, instruction memory 23 and communication bus 24 is at least one, and processor 21, communication interface 22 and instruction memory 23 communicate with each other through communication bus 24.

[0118] Optionally, the processor 21 may be a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural-network Processing Unit), FPGA (Field Programmable Gate Array), TPU (Tensor Processing Unit), AI chip, ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of this application.

[0119] Optionally, the communication interface 22 can be an interface for a communication module used for network communication.

[0120] Instruction memory 23 may include high-speed RAM and may also include non-volatile memory, such as at least one disk storage device. Instruction memory 23 stores one or more computer-executable instructions, which processor 21 invokes to execute the routing path determination method described above.

[0121] This application embodiment also provides a storage medium that stores one or more computer-executable instructions, which, when executed, implement the routing path determination method described above.

[0122] This application also provides a computer program product that may include one or more computer-executable instructions, which, when executed, implement the routing path determination method described above.

[0123] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0124] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for determining a routing path, characterized in that, Applied to multi-chip systems, the multi-chip system comprising multiple chips, each chip comprising multiple computing units, wherein one chip serves as a chip node and one computing unit serves as a computing node, the method includes: Obtain the link status information of the communication link where the current chip node is located. The link status information is used to indicate the busy level of the previous chip node and the next chip node, the occupancy ratio of the input buffer of the current chip node, and the occupancy ratio of the output buffer of the current chip node. Obtain the node status information of each computing node within the current chip node; the node status information is used to indicate the busy level of each computing node. Based on the link status information and the node status information, the routing path for data transmission between the current chip node and other chip nodes on the communication link where the current chip node is located is adjusted.

2. The routing path determination method according to claim 1, characterized in that, The busy level of the computing node is determined based on a busy coefficient, which is calculated as follows: When a compute node sends a data packet whose destination node is the current chip node, the busy coefficient of that compute node is incremented by 1; When a compute node receives a response from a destination node that is the current chip node, the busy factor of that compute node is reduced by 1. The busy factor of the current chip node is the sum of the busy factors of all computing nodes in the current chip node.

3. The routing path determination method according to claim 1, characterized in that, The step of adjusting the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located, based on the link status information and the node status information, includes: Based on the link status information and the node status information, the current chip node sends alarm information to other chip nodes on the communication link where the current chip node is located, so that the other chip nodes can adjust the routing path of data transmission; Based on the link status information, the current chip node adjusts the data transmission routing path of the current chip node.

4. The routing path determination method according to claim 3, characterized in that, Based on the link status information and the node status information, the current chip node sends alarm information to other chip nodes on the communication link where the current chip node is located, including: If the current chip node's busy coefficient is greater than or equal to the first preset value, send alarm information to the previous chip node and the next chip node so that the previous chip node and the next chip node can adjust the data transmission routing path. If the occupancy rate of the input buffer of the current chip node is greater than or equal to the second preset value, an alarm message is sent to the previous chip node so that the previous chip node can adjust the data transmission routing path.

5. The routing path determination method according to claim 4, characterized in that, If the busy coefficient of the current chip node is greater than or equal to the first preset value and continues to exist, the step of sending alarm information to the next chip node and the next chip node specifically means: sending alarm information to the next chip node and the next chip node at a preset frequency. If the current chip node's input buffer occupancy rate is greater than or equal to the second preset value and this condition persists, sending an alarm message to the next chip node specifically involves sending an alarm message to the next chip node at a preset frequency.

6. The routing path determination method according to claim 3, characterized in that, The current chip node adjusts the data transmission routing path of the current chip node based on the link state information, including: If the current chip node's output buffer occupancy rate is greater than or equal to the third preset value, adjust the data transmission routing path of the current chip node. If the current chip node receives alarm information from the previous chip node and / or the next chip node, adjust the data transmission routing path of the current chip node.

7. The routing path determination method according to claim 6, characterized in that, If no alarm information is received from the previous chip node and / or the next chip node within a preset time, the original routing path is restored. The data transmission efficiency of the original routing path is higher than the data transmission efficiency of the routing path adjusted by the current chip node.

8. A routing path determination device, characterized in that, Applied to multi-chip systems, the multi-chip system comprising multiple chips, each chip comprising multiple computing units, wherein one chip serves as a chip node and one computing unit serves as a computing node, the device comprises: The link status awareness unit is used to obtain the link status information of the communication link where the current chip node is located. The link status information is used to indicate the busy level of the previous chip node and the next chip node, the occupancy ratio of the input buffer of the current chip node, and the occupancy ratio of the output buffer of the current chip node. The node status awareness unit is used to obtain the node status information of each computing node within the current chip node. The node status information is used to indicate the busy level of each computing node. The adjustment unit is used to adjust the data transmission routing path between the current chip node and other chip nodes on the communication link where the current chip node is located, based on the link status information and the node status information.

9. An electronic device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer-executable instructions, the processor invoking the one or more computer-executable instructions to perform the routing path determination method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium stores one or more computer-executable instructions, which, when executed, implement the routing path determination method as described in any one of claims 1 to 7.

11. A computer program product, characterized in that, It includes one or more computer-executable instructions, which, when executed, implement the routing path determination method as described in any one of claims 1 to 7.

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