Flexible direct-current real-time digital simulation source based on AURORA protocol and working method thereof

Abstract

According to the flexible direct-current real-time digital simulation source based on the AURORA protocol and the working method of the flexible direct-current real-time digital simulation source based on the AURORA protocol, when an AURORA receiving module receives simulation data sent by a simulation system, an FPGA frames the simulation data into loopback virtual data based on communication parameters of the flexible direct-current simulation data; when the AURORA receiving module does not receive simulation data sent by a simulation system, the FPGA constructs loopback virtual data based on communication parameters of the secondary control and protection device to be tested; after receiving the loopback virtual data, the simulation system sends flexible direct current simulation data to an AURORA receiving module; the FPGA frames flexible direct current simulation data based on data framing logic and a flexible direct current transmission protocol to obtain an output message and encodes the output message based on a link layer verification mode, the code is output to the secondary control and protection device to be tested through the optical serial port sending module, and the simulation source and the RTDS simulation system have good interactivity.

Description

Technical Field

[0001] This invention belongs to the field of flexible DC technology, specifically, it relates to a flexible DC real-time digital simulation source based on the AURORA protocol and its working method. Background Technology

[0002] Since flexible DC protection and control are essentially integrated designs, and the operation of DC protection depends on the behavior of the control system, fault current and voltage need to be output during flexible DC protection testing. However, currently there is no good mathematical model for the operating voltage and current characteristics of the control system, making it difficult to test the correlation between control and protection through static testing of fault signals. Therefore, current flexible DC protection testing mainly relies on dynamic simulation software such as RTDS to simulate the current and voltage of flexible DC faults and the current and voltage signals on each side after the control system operates.

[0003] In existing technologies, the output of DC transformers in flexible DC transmission systems is only provided to control and protection equipment. Testing of flexible DC control and protection devices generally employs dynamic simulation, building a simulation device for the DC transformers to complete the overall control and protection testing. Existing flexible DC simulation test sources, when outputting analog simulation signals, use an RTDS simulation system to build a model of the flexible DC transmission system, simulating the operating state of the DC transformers in the converter station and outputting corresponding small voltage analog quantities. However, analog simulation signals cannot be directly applied to the DC transformers in the flexible DC transmission system. When outputting digital simulation signals, the RTDS simulation system, based on the Aurora link layer protocol, transmits the simulation test signal to an external system through a custom digital sampling value encapsulation format. However, the output of the RTDS simulation system is based on... The AURORA protocol's digital simulation signals cannot exchange information with DC transformers, and some RTDS simulation systems even fail to output simulation data correctly. When secondary manufacturers use proprietary digital signal conversion, the DC merging unit or DC control and protection manufacturer employs digital signal conversion technology suitable for the RTDS signal interface according to the sampling value transmission protocol requirements of the relevant secondary products. However, the dedicated digital signal conversion devices developed by different secondary manufacturers have different output protocols, and these protocols lack scalability and cannot be interchanged. Furthermore, the signal conversion delay of digital simulation signal conversion devices implemented based on embedded systems is uncontrollable. Digital simulation signal conversion devices use an open-loop sampling value reception mode and lack link loopback functionality, making them unsuitable for simulation signal output systems requiring closed-loop transmission links. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a flexible DC real-time digital simulation source based on the AURORA protocol and its operating method, which realizes information interaction between the digital simulation signal of the RTDS simulation system and the DC transformer based on the AURORA protocol.

[0005] The present invention adopts the following technical solution.

[0006] This invention proposes a flexible DC real-time digital simulation source based on the AURORA protocol, used to process the flexible DC simulation data output by the simulation system into digital sample values ​​of the DC transformer before sending them to the secondary control and protection device under test; including: The system comprises a main control module and multiple optical serial port transmitting modules. The main control module includes an FPGA and an AURORA receiving module that interact with each other via an on-chip bus. The control logic of the FPGA is connected to the control terminals of each optical serial port transmitting module. The FPGA enables or disables the optical signal output function of each optical serial port transmitting module based on the operating status of the AURORA receiving module and the operating status of the simulation system. The simulation system interacts with the FPGA via the AURORA receiving module, and the FPGA sends signals to the secondary control and protection device under test via the optical serial port transmitting modules. When the AURORA receiver module receives flexible DC simulation data sent by the simulation system, the FPGA frames the simulation data into loopback virtual data based on the communication parameters of the flexible DC simulation data. When the AURORA receiver module does not receive flexible DC simulation data sent by the simulation system, the FPGA constructs loopback virtual data based on the communication parameters of the secondary control and protection device under test. After receiving the loopback virtual data sent by the AURORA receiver module, the simulation system sends flexible DC simulation data to the AURORA receiver module. The FPGA frames the flexible DC simulation data based on the dynamically adjustable data framing logic and the flexible DC transmission protocol to obtain the output message. The output message is encoded based on the link layer verification mode, and the encoded message is output to the secondary control and protection device under test by the optical serial port transmission module.

[0007] The AURORA receiver module and the simulation system interact with each other based on the Aurora protocol. The FPGA obtains the operating status of the AURORA receiver module through the status port and interacts with the AURORA receiver module based on the AXIS protocol.

[0008] The AURORA receiver module includes a GTP transceiver and an SFP optical module; The data signal terminal of the SFP optical module is connected to the RX / TX of the GTP transceiver for data exchange; The control signals for the SFP optical module come from the FPGA. The FPGA initiates an I2C-based communication with the SFP optical module once per second to obtain the real-time operating status of the SFP optical module hardware, including: SFP optical module insertion status, abnormal received optical signal power, abnormal transmitted optical signal, SFP optical module temperature, SFP optical module operating voltage, SFP optical module transmitted optical power, and SFP optical module received optical power. At the same time, based on the operating status of the simulation system, it enables or disables the underlying optical signal output function of the SFP optical module.

[0009] The optical serial port transmission module includes an optical fiber transmitter; after the FPGA controls the optical fiber transmitter to convert the encoding of the flexible DC simulation data frame into an optical signal, the optical fiber transmitter sends the optical signal to the secondary control and protection device under test based on the flexible DC transmission protocol.

[0010] The main control module also includes: ARM; the FPGA and ARM interact via an on-chip bus; and the ARM implements human-computer interaction via an Ethernet communication module based on the TCP / IP protocol.

[0011] This invention also proposes a working method for a flexible DC real-time digital simulation source based on the AURORA protocol, including: The FPGA enables or disables the optical signal output function of each optical serial port transmitting module based on the operating status of the AURORA receiving module and the operating status of the simulation system. After the optical serial port transmitting module is enabled, when the AURORA receiving module receives the flexible DC simulation data sent by the simulation system, the FPGA frames the simulation data into loopback virtual data based on the communication parameters of the flexible DC simulation data; when the AURORA receiving module does not receive the flexible DC simulation data sent by the simulation system, the FPGA constructs loopback virtual data based on the communication parameters of the secondary control and protection device under test; after the simulation system receives the loopback virtual data sent by the AURORA receiving module, it sends the flexible DC simulation data to the AURORA receiving module. The FPGA uses dynamically adjustable data framing logic and a flexible DC transmission protocol to frame flexible DC simulation data to obtain output messages. The output messages are then encoded based on the link layer verification mode, and the encoded messages are output to the secondary control and protection device under test by the optical serial port transmission module.

[0012] After the optical serial port transmitting module is enabled, the FPGA monitors in real time whether the AURORA receiving module has received a valid AURORA data frame sent by the simulation system based on the Aurora protocol. If no valid AURORA data frame is received, the FPGA starts the loopback virtual data self-maintenance logic to obtain the loopback virtual data. If a valid AURORA data frame is received, the FPGA starts the loopback virtual data following logic to obtain the loopback virtual data.

[0013] The loopback virtual data self-maintenance logic includes: self-maintenance interruption and self-maintenance framing; among which, Self-maintenance interrupts include: determining the data transmission interrupt cycle of the AURORA receiver module under FPGA control within the transmission frequency range of the digital sampled values ​​of the DC transformer; Self-maintenance framing includes: under a determined data transmission interruption period, within the byte length range of the digital sampled values ​​of the DC transformer, determining the byte length of the data frame of the AURORA receiving module and whether to attach a sampling counter to the end of the data frame under FPGA control; adjusting the byte length sequentially according to a set step size, and combining the adjusted byte length with or without the attached sampling counter to obtain the communication parameter combination of the AURORA receiving module; based on the communication parameter combination, if the AURORA receiving module receives a valid AURORA data frame from the simulation system, the AURORA receiving module outputs loopback virtual data constructed based on the communication parameter combination according to the determined data transmission interruption period.

[0014] The loopback virtual data following logic includes: following interrupt and following frame; among which, The follow-up interrupt includes: determining the data transmission interrupt period of the AURORA receiving module under FPGA control based on the transmission frequency of valid AURORA data frames; Follow-up framing includes: using valid AURORA data frames as loopback virtual data during the determined data transmission interruption period; The AURORA receiver module outputs loopback virtual data according to the determined data transmission interrupt period.

[0015] The data framing logic includes: whether each byte of the output data frame needs to be mapped to received data, whether it needs to output fixed data, whether it needs to be a sign bit byte, whether it needs to be a sampling counter byte, and a type area and a data area with the same number of bytes as the output message. The type area defines the attributes of the bytes, and the data area defines the associated information of the bytes.

[0016] Based on the output sampling rate and output compensation delay of the flexible DC transmission protocol, the flexible DC simulation data is framed according to the data framing logic to obtain the output message; the FPGA encodes the output message based on the link layer verification mode to obtain the optical logic level; the optical logic level is output through multiple enabled optical serial port transmission modules.

[0017] The process of framing flexible DC simulation data includes: 1) The total number of bytes of flexible DC simulation data read by the FPGA; 2) The FPGA converts the flexible DC simulation data byte by byte into an output data frame. When the FPGA converts the flexible DC simulation data byte by byte... When reading bytes, read the bytes in the data frame assembly logic. Data types and data parameters; If the data framing logic contains bytes If the data type is "fixed value", then the bytes in the data framing logic will be... The data parameters are filled into the first part of the output data frame. byte; If the data framing logic contains bytes If the data type is "input mapping value", then the bytes in the data frame logic will be... Extracting byte numbers from data parameters and the first flexible DC simulation data Bytes of data are filled into the first byte of the output data frame. byte; If the data framing logic contains bytes If the data type is "sign extension bit", then the bytes in the data framing logic... Extracting byte numbers from data parameters and the first flexible DC simulation data The data sign bit of the byte is extended to a new byte and filled into the first byte of the output data frame. byte; If the data framing logic contains bytes If the data type is "sampling counter", then the sampling counter of the flexible DC simulation data will be filled into the first frame of the output data frame. byte; 3) Compare the total number of bytes of the flexible DC simulation data with the total number of bytes of the output data frame to determine whether the framing is complete; if complete, the sampling counter is incremented to obtain the output message; if not complete, repeat steps 1) and 2).

[0018] The process of encoding the output message includes: 1) Select link layer verification mode Based on the selected link layer verification mode, determine the CRC check polynomial, CRC data check block length, whether the start-of-frame character is checked, and whether the check output data is reversed; 2) After entering the link layer verification mode, select the encoding method; The encoding methods for the digital sampled values ​​output by flexible DC systems include synchronous encoding and asynchronous encoding; If synchronous encoding is selected, the Manchester encoding method is used to encode the flexible DC simulation data at the synchronous mode baud rate to obtain the optical logic level; If asynchronous encoding is selected, the UART format encoding method is used to encode the flexible DC simulation data at an asynchronous mode baud rate to obtain the optical logic level; 3) Obtain the data baud rate of the determined encoding method. The data baud rates for synchronous encoding include 2.5Mb / s, 5Mb / s, 10Mb / s, and 20Mb / s, while the data baud rates for asynchronous encoding are integer multiples of 2Mb / s.

[0019] The present invention is also a terminal, including a processor and a storage medium; the storage medium is used to store instructions; the processor is used to perform operations according to the instructions to execute the steps of the method.

[0020] The present invention is also a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method.

[0021] The beneficial effects of this invention are as follows: Compared with the prior art, the flexible DC real-time digital simulation source proposed in this invention, based on the AURORA communication protocol, possesses excellent interactivity with the digital quantities of the RTDS simulation system. Implemented through the embedded FPGA programmable logic of the ZYNQ processor, it achieves high communication stability, low data conversion latency, and controllable latency. It supports the communication link loopback function with the RTDS simulation system, supporting both self-transmission and follow-transmission modes of loopback data to meet the needs of different application scenarios. It is compatible with mainstream flexible DC system digital quantity sampling value output protocols and supports synchronous output of multiple sampling value data. It possesses good protocol scalability; the physical layer parameters of the output protocol can be customized, and the link layer data can be fully configured or mapped. Based on a general-purpose underlying output encoding architecture, it adopts a byte configuration mode to control the output data framing, realizing a complete reconstruction of the simulation source output protocol from the physical layer to the link layer, compatible with mainstream flexible DC control and protection system digital quantity sampling value protocols, and possessing good protocol scalability. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a flexible DC real-time digital simulation source based on the AURORA protocol proposed in this invention.

[0023] Figure 2 This is a schematic diagram of the AURORA receiving module in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0025] like Figure 1 As shown, the present invention provides a flexible DC real-time digital simulation source based on the AURORA protocol, including: a main control module, multiple optical serial port transmission modules, and an Ethernet communication module; wherein, the simulation system interacts with the secondary control and protection device under test through the main control module and each optical serial port transmission module, and the human-machine interface interacts with the main control module through the Ethernet communication module. like Figure 1 As shown, the main control module includes: a programmable logic array (FPGA), an ARM processor, and an AURORA receiver module; the FPGA and ARM interact via an on-chip bus, and the FPGA and the AURORA receiver module interact via an on-chip bus; as shown... Figure 1 The FPGA control logic shown by the thin dashed line is connected to the control terminals of each optical serial port transmitting module. The FPGA enables or disables the optical signal output function of each optical serial port transmitting module according to the operating status of the AURORA receiving module and the operating status of the simulation system. The simulation system interacts with the FPGA through the AURORA receiving module, and the FPGA sends signals to the secondary control and protection device under test through the optical serial port transmitting module. When the AURORA receiver module receives the flexible DC simulation data sent by the simulation system, the FPGA frames the simulation data into loopback virtual data based on the communication parameters of the flexible DC simulation data. When the AURORA receiver module does not receive the flexible DC simulation data sent by the simulation system, the FPGA constructs loopback virtual data based on the communication parameters of the secondary control and protection device under test. After receiving the loopback virtual data sent by the AURORA receiver module, the simulation system sends the flexible DC simulation data to the AURORA receiver module. The FPGA frames the flexible DC simulation data based on the byte data framing logic and encodes the flexible DC simulation data frame based on the link layer verification mode. The encoded data is output to the secondary control and protection device under test by the optical serial port transmission module.

[0026] The AURORA receiver module and the simulation system interact with each other based on the Aurora protocol. The FPGA obtains the operating status of the AURORA receiver module through the status line and interacts with the AURORA receiver module based on the AXIS protocol. Based on the AURORA communication protocol, this invention has good interactivity with the digital quantities of the RTDS simulation system. It directly obtains the native RTDS simulation data stream through the AURORA interface and synchronously converts it into the digital sample values ​​required for the testing of the flexible DC control and protection system, ensuring the reliability and real-time performance of the simulation source data.

[0027] The ARM implements human-machine interaction via Ethernet communication module based on TCP / IP protocol; the AURORA receiving module interacts with the simulation system based on Aurora protocol; the FPGA obtains the working status of AURORA receiving module through status lines and interacts with AURORA receiving module based on AXIS protocol; the optical serial port transmitting module interacts with the secondary control and protection device under test based on flexible DC transmission protocol.

[0028] In this embodiment, the main control module uses a ZYNQ system-on-a-chip, which integrates a dual-core ARM processor and an FPGA programmable logic array, and has an internal interconnect bus, programmable hardware resources, and rich peripheral interfaces. The FPGA is responsible for controlling high-speed serial AURORA data reception and multi-channel parallel optical serial port digital transmission, while the ARM is responsible for parameter configuration and other human-computer interaction functions. The FPGA and ARM communicate via an internal AXI4 high-speed bus. The optical serial port transmission module includes an optical fiber transmitter; in this embodiment, the optical serial port transmission module includes an HFBR-1414Z optical fiber transmitter controlled by an FPGA. The FPGA controls the optical fiber transmitter to convert the encoding of the flexible DC simulation data frame into an optical signal and then output it. The optical fiber transmitter supports the synchronous transmission of up to 16 channels of DC sampling digital quantities, supports a transmission rate of up to 160MBd, a transmission distance of 2.7 kilometers, and the interface type is ST interface.

[0029] like Figure 2As shown, the AURORA receiver module includes a GTP high-speed transceiver and an SFP (Small Form-factor Pluggable) optical module. The GTP high-speed transceiver is integrated into the ZYNQ platform. The data signal of the SFP optical module is connected to the RX / TX of the GTP transceiver for data interaction, realizing multiple high-speed fiber optic communication interfaces. The control signal of the SFP optical module comes from the FPGA control logic. The FPGA initiates a communication with the SFP optical module once per second based on the I2C (Inter-Integrated Circuit) protocol to obtain the real-time operating status of the SFP optical module hardware, including but not limited to: SFP optical module insertion status, connection status, etc. The system monitors and controls various optical signal output functions, including received optical signal power anomaly, transmitted optical signal anomaly, SFP optical module temperature, SFP optical module operating voltage, SFP optical module transmitted optical power, and SFP optical module received optical power. The FPGA control logic enables or disables the underlying optical signal output function of the SFP optical module based on the operating status of the AURORA receiver module and the simulation system. The TX and RX signals are connected to the GTP transceiver and SFP optical module in a differential signal configuration. Each TX transmit and RX receive data rate reaches up to 6.125 Gb / s. The reference clock for the GTP transceiver is provided by an internal 125 MHz differential crystal oscillator.

[0030] This invention is implemented through the embedded FPGA programmable logic of the ZYNQ main control module, which has high communication stability, low data conversion delay, and controllable delay. The FPGA programmable array logic completes the functions of receiving RTDS simulation data stream and converting and sending flexible DC digital sample values. The simulation source data conversion delay is fixed and controllable and can be adjusted according to application requirements.

[0031] The device communicates with external systems via an Ethernet communication module, enabling human-machine interaction for device control and simulation system data. It utilizes an Ethernet controller integrated with a ZYNQ chip ARM core, employing an RJ45 interface and dedicated communication cables.

[0032] This invention also provides a method for operating a flexible DC real-time digital simulation source based on the AURORA protocol, including: Step 1: The FPGA enables or disables the optical signal output function of each optical serial port transmitting module according to the operating status of the AURORA receiving module and the operating status of the simulation system. When both the AURORA receiver module and the simulation system are in working condition, the optical signal output function of each optical serial port transmitter module is enabled; when the AURORA receiver module and / or the simulation system are not in working condition, the optical signal output function of each optical serial port transmitter module is disabled. In this invention, enabling or disabling the optical signal output function of each optical serial port transmitting module is the initialization stage of the flexible DC real-time digital simulation source. By obtaining the operating status of the AURORA receiving module and the operating status of the simulation system, it is determined whether to execute subsequent steps, and the established communication link provides the basic conditions for the execution of subsequent steps.

[0033] Step 2: After the optical serial port transmitting module is enabled, when the AURORA receiving module receives the flexible DC simulation data sent by the simulation system based on the Aurora protocol, the FPGA frames the simulation data into loopback virtual data based on the communication parameters of the simulation data; when the AURORA receiving module does not receive the flexible DC simulation data sent by the simulation system based on the Aurora protocol, the FPGA constructs loopback virtual data based on the communication parameters of the secondary control and protection device under test; after the simulation system receives the loopback virtual data sent by the AURORA receiving module, it sends the flexible DC simulation data to the AURORA receiving module.

[0034] There are currently two application scenarios in the project: one where RTDS needs to receive loopback data before sending simulation data, and the other where RTDS can send simulation data without receiving loopback data. After the RTDS simulation system is started, it can output flexible DC simulation data normally based on the Aurora protocol. The method proposed in this invention is to ensure that RTDS can also send data in the first case. In the first scenario, when the RTDS system communicates with an external system based on the Aurora protocol, it requires consistent data communication parameters before it can output flexible DC simulation data to the external system. These parameters include, but are not limited to, data transmission interruption period, data frame byte length, and whether or not a sampling counter is appended to the data frame tail. Furthermore, the feedback technology based on the closed-loop of the Aurora communication link cannot solve the problem of missing simulation data during DC transformer testing caused by inconsistent data communication parameters. Therefore, this invention proposes a higher-level implementation method for RTDS loopback virtual data that ensures consistent data communication parameters. All RTDS simulation systems must receive the loopback virtual data sent by the main control module before sending flexible DC simulation data to the main control module. During normal operation of all RTDS simulation systems, the main control module does not need to feed back the status variables of each node in the actual system to the RTDS simulation system, but it needs to continuously output loopback virtual data to the RTDS system. This ensures that the communication frequency, data format, sampling counter, and other parameters between the main control module and the RTDS simulation system are completely consistent, allowing for long-term stable operation of Aurora communication between the two.

[0035] After the optical serial port transmitting module is enabled, the FPGA monitors in real time whether the AURORA receiving module has received a valid AURORA data frame from the simulation system. If no valid AURORA data frame is received, the FPGA starts the loopback virtual data self-maintenance logic, which constructs loopback virtual data based on the communication parameters of the secondary control and protection device under test. If a valid AURORA data frame is received, the FPGA starts the loopback virtual data following logic, which frames the simulation data into loopback virtual data based on the communication parameters of the simulation data. Specifically, the loopback virtual data self-maintenance logic includes: self-maintenance interruption and self-maintenance framing; among which, The self-maintenance interrupt includes: determining the data transmission interrupt period of the AURORA receiving module under FPGA control within the transmission frequency range of the digital sample values ​​of the DC transformer; in this embodiment, the transmission frequency range of the digital sample values ​​of the DC transformer is... When a self-maintenance interruption occurs, the transmission frequency is selected sequentially as 10kHz, 50kHz, and 100kHz, and the data transmission interruption period is determined based on the selected transmission frequency. Self-maintenance framing includes: under a determined data transmission interruption period, within the byte length range of the digital sample value of the DC transformer, determining the byte length of the data frame of the AURORA receiving module and whether to attach a sampling counter to the end of the data frame under FPGA control; in this embodiment, the byte length of the digital sample value of the DC transformer is no more than 256 bytes; adjusting the byte length sequentially according to a set step size, and combining the adjusted byte length with a 4-byte sampling counter attached to the end of the data frame, or combining the adjusted byte length with no sampling counter at the end of the data frame, to obtain the communication parameter combination of the AURORA receiving module; based on the communication parameter combination, if the AURORA receiving module receives a valid AURORA data frame from the simulation system, the AURORA receiving module outputs loopback virtual data constructed based on the communication parameter combination according to the determined data transmission interruption period; The loopback virtual data following logic includes: following interrupt and following frame; among which, The interrupt follow-up includes: determining the data transmission interrupt period of the AURORA receiving module under FPGA control based on the transmission frequency of valid AURORA data frames; in the embodiment, the main control module adjusts its own loopback virtual data transmission time according to the interval time of previously received data frames, that is, predicts the transmission interrupt period, to ensure that the virtual transmission data frames can be kept as consistent as possible with the RTDS communication data frames in terms of interval time, and to ensure the stability of long-term communication between the two. Follow-up framing includes: using valid AURORA data frames as loopback virtual data during the determined data transmission interruption period; The AURORA receiver module outputs loopback virtual data according to the determined data transmission interrupt period.

[0036] In this embodiment, after the main control module starts working, it first initiates the loopback virtual data self-maintenance logic. By gradually adjusting the data transmission interruption period and communication parameters, and monitoring in real time whether the AURORA receiving module receives a valid AURORA data frame from the simulation system, it determines whether the communication parameter adjustment is correct. When the communication parameters are adjusted correctly and the AURORA receiving module receives a valid AURORA data frame from the simulation system, the main control module switches from self-maintenance logic to follow logic, sending the valid AURORA data frame back to the RTDS system as loopback virtual data. This ensures that the communication frequency, data format, sampling counter, and other parameters of the main control module and the RTDS system are completely consistent, allowing the AURORA system between the two to operate stably for a long time. The loopback data virtual strategy of the main control module on the AURORA communication link proposed in this invention involves adjusting the transmission interruption of loopback virtual data and adjusting the content of the transmitted message. When the RTDS simulation system outputs correctly and no longer needs to continue self-maintaining the transmission of loopback data, the loopback data is adjusted from self-maintenance output to following the output of the RTDS simulation system.

[0037] After the optical serial port transmitting module is enabled, the main control module sends a virtual data frame representing the closed loop of the communication link to the RTDS simulation system via the receiving module; after receiving the virtual data frame, the RTDS simulation system outputs flexible DC simulation data.

[0038] Specifically, the AURORA communication link includes a set of serial differential receiving channels and a set of serial differential transmitting channels. The receiving and transmitting channels support full-duplex parallel independent operation. In engineering applications, to ensure data transmission reliability, the RTDS simulation system uses a closed-loop AURORA communication mode. This means the RTDS simulation system needs to continuously receive valid AURORA communication data before outputting the corresponding simulation signal's AURORA communication data. To ensure the normal operation of the RTDS simulation system, the real-time digital simulation source needs to continuously output loopback virtual data to maintain the closed-loop communication link, even if it does not need to feed back node signals such as switch states to the RTDS system. This invention features an AURORA communication link loopback function, suitable for RTDS simulation systems requiring a closed-loop transmission link. It supports the communication link loopback function with the RTDS simulation system, supporting both self-sending and follow-up sending modes of loopback data to meet the needs of different application scenarios. Furthermore, based on the AURORA communication protocol, the flexible DC real-time digital simulation source possesses good data interactivity with the RTDS simulation system.

[0039] Step 3: The FPGA uses dynamically adjustable data framing logic and flexible DC transmission protocol to frame flexible DC simulation data to obtain output messages. The output messages are then encoded based on the link layer verification mode. The encoded messages are output to the secondary control and protection device under test by the optical serial port transmission module.

[0040] Specifically, step 3 includes: Step 3.1, configure the data transmission and reception mechanism between the FPGA and the AURORA receiver module, including: 1) When the AURORA receiver module sends an AURORA data frame, the FPGA sets the tx_tvalid signal. When the AURORA receiver module's tx_tready signal is valid, the FPGA puts the data packet to be sent into the tx_data data line in each transmission clock, and sets the tx_tlast signal synchronously when the last data packet is put in, so as to notify the AURORA receiver module that the transmission of one frame of data has ended. 2) When the AURORA receiving module receives AURORA data frames, the FPGA sets the rx_tready signal to notify the AURORA module that it is ready to receive. After the AURORA receiving module sets the rx_tvalid signal, the FPGA reads data from the rx_data line in each transmission clock until it reads the rx_tlast signal, which marks the end of the reception of one frame of data by the AURORA receiving module.

[0041] To reduce data processing latency, the data transmission, reception, and conversion control of the simulation source are all handled by the FPGA.

[0042] Step 3.2, set up dynamically adjustable data framing logic; the data framing logic includes, but is not limited to: whether each byte of the output data frame needs to be mapped to received data, whether it needs to output fixed data, whether it needs to be a sign bit byte, whether it needs to be a sampling counter byte, and the type area and data area with the same number of bytes as the output message. The type area defines the attributes of the bytes, and the data area defines the associated information of the bytes.

[0043] Different manufacturers' flexible DC secondary devices use different protocols, making them incompatible with the expansion of multiple flexible DC transmission protocols during real-time data processing. For platforms using an operating system, the upper-layer processor (ARM, etc.) first obtains the received data from the lower-layer processor (FPGA, etc.), then performs application-layer framing according to the flexible DC transmission protocol to be output, and finally transmits the complete frame data back to the lower-layer processor for encoding and outputting the protocol. In this mode, due to the need for multiple data interactions, the real-time performance of the digital simulation source data processing cannot be guaranteed. For platforms without an operating system, the lower-layer processor (FPGA) directly frames the received data according to a preset flexible DC transmission protocol format and then encodes and outputs it. In this mode, the digital simulation source can only output according to a single protocol format and cannot output other flexible DC transmission protocols without changing the program. This invention addresses the issue of platforms without an operating system by setting data framing logic, enabling the digital simulation source to change the framing logic of the output data in real time. Therefore, regardless of how the data frames of the flexible DC transmission protocols from different manufacturers are framed, the corresponding protocol output can be achieved quickly and in real-time by modifying or presetting the relevant data framing logic. The data framing logic proposed in this invention, which allows for customizable conversion and minimizes conversion delay, maintains the universality and scalability of the output protocol. This enables the simulation source to be compatible with the flexible DC transmission protocols of various manufacturers and output suitable signals to secondary control and protection devices from different manufacturers. The simulation source receives the simulation sample value data stream from the RTDS simulation system via the AURORA protocol, and then converts and processes it into digital sample values ​​of the flexible DC electronic transformer according to the test requirements before outputting them to the secondary control and protection device under test.

[0044] Step 3.3: Based on the output sampling rate and output compensation delay of the flexible DC transmission protocol, frame the flexible DC simulation data according to the data framing logic to obtain the output message; In this embodiment, the data framing logic and the output sampling rate and output compensation delay of the flexible DC transmission protocol are stored in the main control module. After the simulation source is working, the FPGA of the main control module reads the data framing logic, the output sampling rate and the output compensation delay, performs framing of the flexible DC simulation data, and obtains the output message. The process of framing flexible DC simulation data includes: 1) The total number of bytes of flexible DC simulation data read by the FPGA; 2) The FPGA converts the flexible DC simulation data byte by byte into an output data frame. When the FPGA converts the flexible DC simulation data byte by byte... When reading bytes, read the bytes in the data frame assembly logic. Data types and data parameters; If the data framing logic contains bytes If the data type is "fixed value", then the bytes in the data framing logic will be... The data parameters are filled into the first part of the output data frame. byte; If the data framing logic contains bytes If the data type is "input mapping value", then the bytes in the data frame logic will be... Extracting byte numbers from data parameters and the first flexible DC simulation data Bytes of data are filled into the first byte of the output data frame. byte; If the data framing logic contains bytes If the data type is "sign extension bit", then the bytes in the data framing logic... Extracting byte numbers from data parameters and the first flexible DC simulation data The data sign bit of the byte is extended to a new byte and filled into the first byte of the output data frame. byte; If the data framing logic contains bytes If the data type is "sampling counter", then the sampling counter of the flexible DC simulation data will be filled into the first frame of the output data frame. byte; In this embodiment, when converting the first byte of flexible DC simulation data, the FPGA first reads the data type of byte 1 in the data frame logic as "fixed value," then reads the data parameter of byte 1 as 0x03, and fills 0x03 into the first byte of the output data frame; when converting the second byte of flexible DC simulation data, the FPGA reads the data type of byte 2 in the data frame logic as "input mapping value," then reads the data parameter of byte 2 as 0x05, and fills the data of the fifth byte of flexible DC simulation data into the second byte of the output data frame; when converting the third byte of flexible DC simulation data... When converting bytes, if the data type of byte 3 in the FPGA data frame reading logic is "sign extension bit", then the data parameter of byte 3 is 0x07. Therefore, the sign bit of the 7th byte of the flexible DC simulation data is extended to one byte and filled into the 3rd byte of the output data frame. When converting the 4th byte of the flexible DC simulation data, if the data type of byte 4 in the FPGA data frame reading logic is "sampling counter", then the sampling counter of the flexible DC simulation data is directly filled into the 4th byte of the output data frame. This process continues until all bytes of the flexible DC simulation data have been converted. 3) Compare the total number of bytes of the flexible DC simulation data with the total number of bytes of the output data frame to determine whether the framing is complete; if complete, the sampling counter is incremented to obtain the output message; if not complete, repeat steps 1) and 2).

[0045] Step 3.3: The FPGA encodes the output message based on the link layer verification mode to obtain the optical logic level; The link-layer check mode determines the rules for generating data frame checksums. Regardless of the encoding mode, corresponding link-layer checksums must be generated and added at a specified location on the data link, according to the specified rules.

[0046] The process of encoding the output message includes: 1) Select link layer verification mode Based on the selected link layer verification mode, determine the CRC check polynomial, CRC data check block length, whether the start-of-frame character is checked, and whether the check output data is reversed. 2) After entering the link layer verification mode, select the encoding method; The encoding methods for the digital sampled values ​​output by flexible DC systems include synchronous encoding and asynchronous encoding; If synchronous encoding is selected, the Manchester encoding method is used to encode the flexible DC simulation data at the synchronous mode baud rate to obtain the optical logic level; If asynchronous encoding is selected, the UART format encoding method is used to encode the flexible DC simulation data at an asynchronous mode baud rate to obtain the optical logic level; 3) Obtain the data baud rate of the determined encoding method and control the encoding character change cycle. The data baud rates for synchronous encoding include 2.5Mb / s, 5 Mb / s, 10 Mb / s, and 20Mb / s, while the data baud rates for asynchronous encoding are integer multiples of 2Mb / s. In this embodiment, the software uses a general-purpose encoding architecture, setting the variable factors in the encoding process as module inputs, and automatically completing the encoding of the output message in actual applications.

[0047] This invention realizes the process from flexible DC simulation data framing to encoding. The flexible DC simulation data framing is a custom framing process at the application layer. By allowing the underlying processor (FPGA) to directly output and frame the received data, this framing method is configurable and can realize the framing of any application layer data. The output message encoding is a custom encoding process at the link layer. Since the data does not need to be transmitted to the upper-layer processor (ARM, etc.) for framing, and the underlying processor (FPGA) is programmable hardware logic without software operating system, this framing method has the least latency, and the duration of each framing is fixed and controllable.

[0048] Step 3.4: The optical logic level is output through multiple enabled optical serial port transmission modules; When the optical logic level is output through the optical serial port transmission module of the physical layer, the output light is selected to be either high or low level.

[0049] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0050] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0051] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0052] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A flexible DC real-time digital simulation source based on AURORA protocol, used for processing the flexible DC simulation data output by a simulation system into digital quantity sample values of a DC mutual inductor and then sending the digital quantity sample values to a secondary control and protection device under test; characterized in that, Comprise: The master module, a plurality of optical serial port sending modules; The master module comprises FPGA and AURORA receiving module for data interaction through on-chip bus; The control logic of FPGA is connected with the control end of each optical serial port sending module, and FPGA enables or disables the optical signal output function of each optical serial port sending module according to the running state of AURORA receiving module and the running state of simulation system; The simulation system carries out data interaction with FPGA through AURORA receiving module, and FPGA sends signals to the secondary control and protection device to be tested through optical serial port sending module; When AURORA receiving module receives the flexible DC simulation data sent by the simulation system, FPGA frames the simulation data into loopback virtual data based on the communication parameters of the flexible DC simulation data; When AURORA receiving module does not receive the flexible DC simulation data sent by the simulation system, FPGA constructs loopback virtual data based on the communication parameters of the secondary control and protection device to be tested; After the simulation system receives the loopback virtual data sent by AURORA receiving module, it sends flexible DC simulation data to AURORA receiving module; FPGA frames the flexible DC simulation data based on the dynamically adjustable data framing logic and the flexible DC transmission protocol to obtain the output message, and encodes the output message based on the link layer check mode, and the encoding is output to the secondary control and protection device to be tested by the optical serial port sending module.

2. The flexible DC real-time digital simulation source based on AURORA protocol according to claim 1, wherein, AURORA receiving module and simulation system carry out data interaction based on Aurora protocol; FPGA obtains the running state of AURORA receiving module through the state port line, and carries out data interaction with AURORA receiving module based on AXIS protocol.

3. The flexible DC real-time digital simulation source based on AURORA protocol according to claim 2, wherein, AURORA receiving module comprises GTP transceiver and SFP optical module; The data signal end of SFP optical module is connected with the RX / TX of GTP transceiver for data interaction; The control signal of SFP optical module comes from FPGA, FPGA initiates communication based on I2C protocol to SFP optical module once per second to obtain the real-time running state of SFP optical module hardware, including: SFP optical module insertion state, receiving optical signal power abnormality, sending optical signal abnormality, SFP optical module temperature, SFP optical module working voltage, SFP optical module sending optical power, SFP optical module receiving optical power; At the same time, enable or disable the optical signal output function of SFP optical module bottom layer according to the running state of simulation system.

4. The flexible DC real-time digital simulation source based on AURORA protocol according to claim 1, wherein, The optical serial port sending module comprises a fiber transmitter; After FPGA controls the fiber transmitter to convert the encoding of the flexible DC simulation data frame into an optical signal, the fiber transmitter sends the optical signal to the secondary control and protection device to be tested based on the flexible DC transmission protocol.

5. The AURORA protocol-based flexible DC real-time digital simulation source of claim 1, characterized in that, The master module further comprises an ARM; the FPGA and the ARM exchange data through an on-chip bus; the ARM realizes human-computer interaction based on a TCP / IP protocol through an Ethernet communication module.

6. A method for operating an AURORA protocol based flexible DC real-time digital simulation source, adapted to the AURORA protocol based flexible DC real-time digital simulation source of any one of claims 1 to 5; characterized in that, comprising: The FPGA enables or disables the optical signal output function of each optical serial port sending module according to the running state of the AURORA receiving module and the running state of the simulation system; After the optical serial port sending module is enabled, when the AURORA receiving module receives the flexible DC simulation data sent by the simulation system, the FPGA frames the simulation data into loopback virtual data based on the communication parameters of the flexible DC simulation data; when the AURORA receiving module does not receive the flexible DC simulation data sent by the simulation system, the FPGA constructs loopback virtual data based on the communication parameters of the secondary control and protection device to be tested; After the simulation system receives the loopback virtual data sent by the AURORA receiving module, it sends flexible DC simulation data to the AURORA receiving module; The FPGA frames the flexible DC simulation data to obtain output messages based on dynamically adjustable data framing logic and flexible DC transmission protocols, encodes the output messages based on a link layer check mode, and outputs the encoded messages to the secondary control and protection device to be tested by the optical serial port sending module.

7. The working method of the AURORA protocol-based flexible DC real-time digital simulation source of claim 6, characterized in that, After the optical serial port sending module is enabled, the FPGA monitors whether the AURORA receiving module receives valid AURORA data frames sent by the simulation system based on the Aurora protocol in real time; if no valid AURORA data frames are received, the FPGA starts a loopback virtual data self-maintenance logic to obtain loopback virtual data; if valid AURORA data frames are received, the FPGA starts a loopback virtual data following logic to obtain loopback virtual data.

8. The working method of the AURORA protocol-based flexible DC real-time digital simulation source of claim 7, characterized in that, The loopback virtual data self-maintenance logic comprises a self-maintenance interrupt and a self-maintenance framing; wherein, The self-maintenance interrupt comprises determining the data sending interrupt period of the AURORA receiving module within the sending frequency range of the digital sampling value of the DC mutual inductor under the control of the FPGA. The self-maintenance framing includes: under the determined data transmission interruption period, determining whether the data frame byte length of the AURORA receiving module and the data frame tail are attached with the sampling counter in the byte length range of the digital quantity sampling value of the DC mutual inductor under the control of the FPGA; adjusting the byte length in turn according to the set step length, and combining the adjusted byte length and the data frame tail with or without the attached sampling counter to obtain the communication parameter combination of the AURORA receiving module; based on the communication parameter combination, if the AURORA receiving module receives the valid AURORA data frame sent by the simulation system, the AURORA receiving module outputs the loopback virtual data constructed based on the communication parameter combination according to the determined data transmission interruption period.

9. The working method of the AURORA protocol-based flexible DC real-time digital simulation source according to claim 7, characterized in that, The loopback virtual data following logic comprises: following interruption and following framing; wherein, The following interruption comprises: determining the data transmission interruption period of the AURORA receiving module under the control of the FPGA according to the transmission frequency of the valid AURORA data frame; The following framing comprises: taking the valid AURORA data frame as the loopback virtual data under the determined data transmission interruption period; The AURORA receiving module outputs the loopback virtual data according to the determined data transmission interruption period.

10. The working method of the AURORA protocol-based flexible DC real-time digital simulation source according to claim 6, characterized in that, The data framing logic comprises: whether each byte of the output data frame needs to map the received data, whether it needs to output fixed data, whether it needs to become a symbol bit byte, whether it needs to become a sampling counter byte, and the same byte number type area and data area of the output message, wherein the type area defines the attribute of the byte, and the data area defines the associated information of the byte.

11. The working method of the AURORA protocol-based flexible DC real-time digital simulation source according to claim 10, characterized in that, According to the output sampling rate and output compensation delay of the flexible DC transmission protocol, the flexible DC simulation data is framed based on the data framing logic to obtain the output message; the FPGA encodes the output message based on the link layer check mode to obtain the optical logic level; The optical logic level is output via a plurality of enabled optical serial sending modules.

12. The working method of the AURORA protocol-based flexible DC real-time digital simulation source according to claim 11, characterized in that, The process of framing the flexible DC simulation data comprises: 1) The FPGA reads the total number of bytes of the flexible DC simulation data; 2) FPGA converts the flexible DC simulation data into output data frame byte by byte, and when the FPGA converts the flexible DC simulation data to the first byte, the data type and data parameters of the byte in the data group framing logic are read; ​​ If the data type of the byte in the data framing logic is "fixed value", the data parameter of the byte in the data framing logic is filled into the first byte of the output data frame ; If the data type of the data in the data framing logic byte is "input mapping value", the byte number is extracted from the data parameter in the data framing logic byte , and the data in the first byte of the flexible DC simulation data is filled into the first byte of the output data frame; If the data type of the data in the byte of the data framing logic is "symbol extension bit", the byte number is extracted from the data parameter in the byte of the data framing logic, and the data symbol bit of the first byte of the flexible DC simulation data is extended to one byte to fill the first byte of the output data frame; If the data type of the byte in the data framing logic is "sample counter", the sample counter of the flexible DC simulation data is filled into the 1st byte of the output data frame; ​ 3) Comparing the total number of bytes of the flexible DC simulation data with the total number of bytes of the output data frame to determine whether the framing is completed; if yes, the output message is obtained after the sampling counter is accumulated; if not, the processes 1) and 2) are repeated.

13. The working method of the AURORA protocol-based flexible DC real-time digital simulation source according to claim 11, characterized in that, The process of encoding the output message comprises: 1) Selecting a link layer check mode Based on the selected link layer check mode, determine the CRC check polynomial, the CRC data check block length, whether the frame start symbol is checked, and whether the check output data is reversed; 2) Selecting an encoding mode after entering the link layer check mode The digital quantity sampling value encoding mode of the flexible DC system output includes synchronous encoding and asynchronous encoding; If synchronous encoding is selected, the Manchester encoding method is used to encode the flexible DC simulation data at a synchronous mode baud rate to obtain an optical logic level; If asynchronous encoding is selected, the UART format encoding method is used to encode the flexible DC simulation data at an asynchronous mode baud rate to obtain an optical logic level; 3) Obtaining the data baud rate of the determined encoding mode, wherein the data baud rate of synchronous encoding includes 2.5 Mb / s, 5 Mb / s, 10 Mb / s, and 20 Mb / s, and the data baud rate of asynchronous encoding is an integer multiple of 2 Mb / s.

14. A terminal comprising a processor and a storage medium; characterized in that: the storage medium is configured to store instructions; the processor is configured to operate according to the instructions to perform the steps of the method of any one of claims 6-13.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the steps of the method of any one of claims 6-13.

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