Implementation system and method for cache consistency of multi-core processor based on priority
By introducing priority-aware scheduling and an improved bus arbitration module into multi-core processors, the problem of high-priority tasks being blocked by low-priority tasks is solved, and cache consistency priority response of high-priority tasks is achieved, thereby improving the real-time performance of multi-core processors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-03-10
AI Technical Summary
The existing bus arbitration mechanism of multi-core processors does not associate task priorities, causing consistency requests from high-priority tasks to be blocked by low-priority tasks, which cannot meet the timeliness requirements of real-time systems.
By introducing a priority-aware scheduling module and an improved bus arbitration module into multi-core processors, and binding task priorities with consistency operations, a dynamic preemption mechanism is implemented to ensure that cache consistency operations of high-priority tasks are responded to first.
While ensuring data consistency, optimize bus resource allocation efficiency, avoid blocking of low-priority tasks, and improve the real-time performance and response efficiency of multi-core processors.
Smart Images
Figure CN121636092A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of multi-core processors, in particular to a multi-core processor cache consistency implementation system and method based on priority. BACKGROUND
[0002] In a multi-core processor chip, the bus listening protocol is the core mechanism for maintaining cache consistency - all cores broadcast consistency messages (such as invalid signals, data requests) through a shared bus, and the cache controller listens to the bus in real time and updates the cache (cache memory) data and state. However, the scheduling mechanism of the existing bus listening protocol has certain defects and cannot meet the real-time system requirements:
[0003] 1. The bus arbitration mechanism does not associate task priority: the existing bus arbitration uses "fixed polling" or "first come first served", without distinguishing the real-time priority of core tasks. The consistency request of a high-priority task may be blocked by a non-urgent request of a low-priority task, resulting in poor real-time performance.
[0004] 2. High-priority task response blocking: the "exclusivity" of the shared bus (only one consistency operation is supported at the same time) is the basis for maintaining cache consistency, but the existing protocol lacks a dynamic preemption mechanism. When a low-priority task has occupied the bus, the consistency request of a high-priority task can only passively wait for release, resulting in the problem of "low-priority blocking high-priority".
[0005] With the increasing requirements for response timeliness and data reliability in the fields of embedded real-time systems, autonomous driving, etc., the defects of the traditional cache consistency mechanism, such as "no priority awareness and no dynamic adaptation capability", are becoming more and more prominent. How to realize the deep binding of cache consistency requests and task priority while guaranteeing the consistency of MESI / MOESI protocol, and optimize the efficiency of bus resource allocation, has become a key technical challenge to improve the real-time performance of multi-core processors. SUMMARY
[0006] The present application provides a multi-core processor cache consistency implementation system and method based on priority to meet the needs and deficiencies of current technology development. By binding task priority with consistency operation, the cache consistency operation of high-priority tasks is guaranteed to be responded preferentially, ensuring real-time performance.
[0007] In the first aspect, the present application provides a multi-core processor cache consistency implementation system based on priority, which solves the above technical problems by adopting the following technical solutions:
[0008] A multi-core processor cache consistency implementation system based on priority, comprising:
[0009] CPU core module, configured to initiate a cache coherence request according to a service requirement, encapsulate the request into a request packet containing key control information, and send the request packet to the cache controller module;
[0010] The cache controller module is configured to receive the request packet sent by the CPU core module, trigger a cache coherence operation process, and forward the request packet to the priority-aware scheduling module;
[0011] The priority-aware scheduling module is configured to analyze the request packet, quantify the request priority, and complete sorting based on the request priority, and then send the priority sorting result to the improved bus arbitration module.
[0012] The improved bus arbitration module is configured to receive the priority sorting result, directly execute the coherence operation of the highest priority request, or first wait according to the priority sorting, then trigger a dynamic preemption mechanism to allocate the bus to the high-priority request, and finally execute the coherence operation of the request.
[0013] Optionally, the CPU core module involved initiates a cache coherence request according to a service requirement, encapsulates the request into a request packet containing a task priority, an operation type and a target cache address, and sends the request packet to the cache controller module.
[0014] Optionally, the priority-aware scheduling module specifically includes:
[0015] The request analysis unit is configured to receive the request packet forwarded by the cache controller module in real time, first extract the coherence operation type and the target cache address in the request packet, then compare the target cache address with the address of the cache controller module, and combine the current MOESI state of the cache line to determine whether the request type is a hit or a miss, and finally transmit the request type and the parsed task priority level to the dynamic arbitration unit.
[0016] The dynamic arbitration unit is configured to, based on the received request type and task priority level, first quantify the request priority by a calculation formula "scheduling weight = task priority level × request emergency coefficient", then sort all coherence requests to be processed based on the calculated scheduling weight, and send the final sorting result to the improved bus arbitration module; wherein the "request emergency coefficient" is set according to the request type.
[0017] Optionally, the improved bus arbitration module specifically includes:
[0018] A bus allocation unit is used to receive the consistency request priority ranking result output by the dynamic arbitration unit, and to perform the following operations: (a) when the shared bus resource is currently in an idle state, directly allocate the bus control right to the request with the highest priority, and trigger the consistency operation of the request; (b) when the shared bus resource is already occupied, add the request to the priority waiting queue, wait according to the priority ranking, and trigger the real-time monitoring function of the shared bus resource at the same time;
[0019] A conflict resolution unit is used to monitor the occupancy state of the shared bus resource in real time, and when a high-priority request arrives and a low-priority request has occupied the shared bus resource, trigger the dynamic preemption mechanism according to the execution of the low-priority request;
[0020] A preemption response unit is used to complete the transfer and subsequent recovery of the bus control right of the low-priority request according to the execution of the dynamic preemption mechanism, and realize the dynamic allocation of the bus resource.
[0021] Preferably, the execution process of the dynamic preemption mechanism is as follows:
[0022] (a) the low-priority request has not entered the "unpreemptable phase":
[0023] (a1) send a pause signal to the low-priority request, and save its current consistency operation state;
[0024] (a2) release the occupied shared bus resource, and allocate it to the high-priority request;
[0025] (a3) after the high-priority request is executed, send a recovery signal to the low-priority request, and restore its saved consistency operation state to make it continue to execute the remaining operation;
[0026] The preemption response unit is used to complete the transfer and subsequent recovery of the bus control right of the low-priority request according to the pause signal and the recovery signal sent during the execution of the dynamic preemption mechanism, and realize the dynamic allocation of the bus resource.
[0027] (b) the low-priority request has entered the "unpreemptable phase":
[0028] Wait for the execution of the priority request to be completed and release the corresponding shared bus resource, and then allocate the bus control right to the request with the highest priority in the priority waiting queue.
[0029] In a second aspect, the application provides a priority-based multi-core processor cache consistency implementation method, which solves the above technical problems by adopting the following technical solutions:
[0030] A priority-based multi-core processor cache consistency implementation method, which includes the following steps:
[0031] Step 1, the CPU core initiates a cache consistency request according to the business requirement, encapsulates the request packet containing key control information, and sends it to the cache controller;
[0032] Step 2, the cache controller receives the request packet sent by the CPU core, triggers the cache consistency operation process, and forwards the request packet to the next process;
[0033] Step 3, receiving the request packet forwarded by step 2, performing the following operations in turn: parsing the request packet, quantifying the request priority, and completing the sorting based on the request priority;
[0034] Step 4, receiving the request priority sorting result of step 3, directly executing the consistency operation of the highest priority request, or first waiting according to the priority, then triggering the dynamic preemption mechanism to allocate the bus to the high priority request, and finally executing the consistency operation of the request.
[0035] Optionally, the CPU core involved initiates a cache consistency request according to the business requirement, encapsulates the request packet containing task priority, operation type and target cache address, and sends it to the cache controller.
[0036] Optionally, step 3 is specifically performed as follows:
[0037] Step 3.1, receiving the request packet forwarded by step 2 in real time, first extracting the consistency operation type and target cache address in the request packet, then comparing the target cache address with the address of the cache controller, and combining the current MOESI state of the cache line, determining the request type as hit or miss, and finally transmitting the request type and the parsed task priority to the next process;
[0038] Step 3.2, based on the received request type and task priority, first quantifying the request priority by the calculation formula "dispatch weight = task priority × request emergency coefficient", and then sorting all pending consistency requests based on the calculated dispatch weight; wherein, "request emergency coefficient" is set according to the request type.
[0039] Optionally, step 4 is specifically performed as follows:
[0040] Step 4.1, receiving the priority sorting result of the pending consistency request, performing the following operations: (a) when the shared bus resource is currently idle, directly allocating the bus control right to the request with the highest priority, and triggering the consistency operation of the request; (b) when the shared bus resource is occupied, adding the request to the priority waiting queue, waiting according to the priority, and triggering real-time monitoring of the shared bus resource;
[0041] Step 4.2, real-time monitoring of the occupation state of the shared bus resource, when a high-priority request arrives and a low-priority request has occupied the shared bus resource, triggering a dynamic preemption mechanism according to the execution of the low-priority request;
[0042] Step 4.3, according to the execution of the dynamic preemption mechanism, completing the bus control right transfer and subsequent recovery of the low-priority request, and realizing dynamic allocation of the bus resource.
[0043] Preferably, the execution process of the dynamic preemption mechanism involved is as follows:
[0044] (a) the low-priority request has not entered the "unpreemptable phase":
[0045] (a1) sending a pause signal to the low-priority request, and saving its current consistency operation state;
[0046] (a2) releasing the occupied shared bus resource and allocating it to the high-priority request;
[0047] (a3) after the high-priority request is executed, sending a recovery signal to the low-priority request, and recovering its saved consistency operation state to make it continue to execute the remaining operation;
[0048] In this process, the bus control right transfer and subsequent recovery of the low-priority request are completed according to the pause signal and the recovery signal sent by the dynamic preemption mechanism execution process, and dynamic allocation of the bus resource is realized;
[0049] (b) the low-priority request has entered the "unpreemptable phase":
[0050] waiting for the execution of the priority request to be completed and releasing the corresponding shared bus resource, and then allocating the bus control right to the request with the highest priority in the priority waiting queue.
[0051] The priority-based multi-core processor cache consistency implementation system and method of the present application has the following beneficial effects compared with the prior art:
[0052] 1. The present application is suitable for multi-core real-time systems and can guarantee the cache consistency operation of high-priority tasks to be responded preferentially, avoiding real-time invalidation caused by low-priority task blocking;
[0053] 2、The application realizes the priority scheduling of cache consistency operation from three dimensions of request analysis and sequencing, bus dynamic allocation and conflict preemption processing through the cooperative mechanism of "priority-aware scheduling + improved bus arbitration", ensures that the cache consistency request of high-priority task is responded in priority, avoids the real-time invalidation caused by the blocking of low-priority task, and improves the real-time performance of a multi-core processor under the premise of guaranteeing the consistency and data reliability of bus listening protocols such as MOESI and MESI.
[0054] 3、The system of the application realizes the deep binding of task priority and consistency request through the priority-aware scheduling module, avoids the out-of-order preemption of high-priority request by low-priority request, guarantees the real-time performance, realizes the dynamic allocation and preemption mechanism of the improved bus arbitration module, replaces the traditional "fixed polling", dynamically allocates bus resources according to the priority, eliminates the low-efficiency problem of static allocation of bus resources, and guarantees the data consistency while solving the problem of "low-priority blocking high-priority".
[0055] 4、The application can be applied to multi-core processor chip products related to multi-core real-time systems, is suitable for multi-core processor cache control systems using bus listening protocols such as MOESI and MESI in nodes, guarantees the cache data consistency of each core in a multi-core processor, realizes the priority response of cache operation of high-priority task, and meets the task scheduling demand in real-time scenarios. BRIEF DESCRIPTION OF DRAWINGS
[0056] Figure 1 is a system architecture diagram of the application; Figure 1 Figure 2 is a method flowchart of the application.
[0057] Figure 3 is a schematic diagram of the application. Figure 2 DETAILED DESCRIPTION
[0058] In order to make the technical scheme, the solved technical problems and the technical effects of the application clearer, the technical scheme of the application is described in detail below in combination with specific embodiments.
[0059] Embodiment one:
[0060] In combination with Figure 1, Figure 1 the embodiment provides a multi-core processor cache consistency implementation system based on priority, which comprises:
[0061] A CPU core module is used for initiating a cache consistency request according to business demand, encapsulating a request packet containing task priority, operation type (read request / write request) and target cache address, and sending the request packet to a cache controller module.
[0062] The cache controller module is configured to receive a request packet sent by the CPU core module, trigger a cache consistency operation process, and forward the request packet to the priority-aware scheduling module.
[0063] The priority-aware scheduling module is configured to analyze the request packet, quantify the request priority, and complete sorting based on the request priority, and then send the priority sorting result to the improved bus arbitration module.
[0064] The improved bus arbitration module is configured to receive the priority sorting result, directly execute a consistency operation of a request with the highest priority, or first wait according to the priority sorting, then trigger a dynamic preemption mechanism to allocate the bus to a high-priority request, and finally execute a consistency operation of the request.
[0065] In this embodiment, the priority-aware scheduling module specifically includes:
[0066] The request analysis unit is configured to receive the request packet forwarded by the cache controller module in real time, first extract the consistency operation type (read request or write request) and target cache address in the request packet, then determine whether the request type is a hit or a miss by comparing the target cache address with the address of the cache controller module and combining the current MOESI state of the cache line, and finally transmit the request type and the parsed task priority level to the dynamic arbitration unit.
[0067] The dynamic arbitration unit is configured to first quantify the request priority by a calculation formula "scheduling weight = task priority level × request emergency coefficient" based on the received request type and task priority level, then sort all consistency requests to be processed based on the calculated scheduling weight, and send the final sorting result to the improved bus arbitration module; wherein the "request emergency coefficient" is set according to the request type.
[0068] In this embodiment, the improved bus arbitration module specifically includes:
[0069] The bus allocation unit is configured to receive the consistency request priority sorting result output by the dynamic arbitration unit, and perform the following operations: (a) when the shared bus resource is currently in an idle state, directly allocate the bus control right to the request with the highest priority, and trigger a consistency operation of the request; (b) when the shared bus resource is already occupied, add the request to a priority waiting queue, wait according to the priority sorting, and trigger a real-time monitoring function of the shared bus resource.
[0070] The conflict resolution unit is configured to monitor the shared bus resource occupation state in real time, and when a high-priority request arrives and a low-priority request has occupied the shared bus resource, trigger a dynamic preemption mechanism according to the execution of the low-priority request.
[0071] (a) Low-priority requests have not entered the "non-preemptive phase":
[0072] (a1) Send a pause signal to the low-priority request to stop the low-priority request from occupying the shared bus resources and save its current consistent operation state;
[0073] (a2) Release the occupied shared bus resources and allocate them to high-priority requests;
[0074] (a3) After a high-priority request is completed, a recovery signal is sent to a low-priority request, the saved state of the low-priority request is loaded, and its saved consistent operation state is restored so that it can continue to execute the remaining operations.
[0075] The preemption response unit is used to transfer bus control to a higher priority request based on the pause signal sent during the execution process of the dynamic preemption mechanism; and to return bus control based on the recovery signal sent during the execution process of the dynamic preemption mechanism, thereby realizing the dynamic allocation of bus resources.
[0076] (b) Low-priority requests have entered the "non-preemptible phase":
[0077] First, wait for the priority request to complete and release the corresponding shared bus resources. Then, allocate bus control to the highest priority request in the priority waiting queue and perform its consistency operation.
[0078] Example 2:
[0079] Combined with appendix Figure 2 This embodiment proposes a priority-based multi-core processor cache coherency implementation method, which includes the following steps:
[0080] Step 1: The CPU core initiates a cache consistency request based on business needs. The request is encapsulated into a request packet containing the task priority, operation type (read request / write request) and target cache address, and then sent to the cache controller.
[0081] Step 2: The Cache controller receives the request packet sent by the CPU core, triggers the Cache consistency operation process, and forwards the request packet to the next process.
[0082] Step 3: Receive the request packet forwarded in Step 2 and perform the following operations in sequence: parse the request packet, quantify the request priority, and sort the requests based on their priority. The specific execution flow is as follows:
[0083] Step 3.1, real-time receiving the request packet forwarded in step 2, extracting the consistency operation type (read request, write request) and the target Cache address in the request packet, comparing the target Cache address with the address of the Cache controller, and combining the current MOESI state of the Cache line to determine the request type as a hit or a miss, and finally transmitting the request type and the parsed task priority level to the next process;
[0084] Step 3.2, based on the received request type and task priority level, first quantifying the request priority by the calculation formula "scheduling weight = task priority level x request emergency coefficient", and then sorting all pending consistency requests based on the calculated scheduling weight; wherein the "request emergency coefficient" is set according to the request type.
[0085] Step 4, receiving the request priority sorting result of step 3, directly executing the consistency operation of the highest priority request, or first waiting according to the priority, then triggering the dynamic preemption mechanism to allocate the bus to the high priority request, and finally executing the consistency operation of the request; the specific execution process is as follows:
[0086] Step 4.1, receiving the priority sorting result of the pending consistency request, performing the following operations: (a) when the shared bus resource is currently idle, directly allocating the bus control right to the request with the highest priority, and triggering the consistency operation of the request; (b) when the shared bus resource is occupied, adding the request to the priority waiting queue, waiting according to the priority, and triggering real-time monitoring of the shared bus resource at the same time;
[0087] Step 4.2, real-time monitoring the occupation state of the shared bus resource, when a high priority request arrives and a low priority request has occupied the shared bus resource, triggering the dynamic preemption mechanism according to the execution of the low priority request:
[0088] (a) the low priority request has not entered the "non-preemptable phase":
[0089] (a1) sending a pause signal to the low priority request, saving its current consistency operation state;
[0090] (a2) releasing the occupied shared bus resource and allocating it to the high priority request;
[0091] (a3) after the high priority request is executed, sending a resume signal to the low priority request, and restoring its saved consistency operation state to continue executing the remaining operations;
[0092] In this process, the bus control right transfer and subsequent recovery of the low priority request are completed according to the pause signal and the resume signal sent by the dynamic preemption mechanism execution process, realizing the dynamic allocation of the bus resource;
[0093] (b) the low-priority request has entered the "non-preemptable phase":
[0094] The priority waiting queue is emptied, and the bus control right is assigned to the request with the highest priority in the priority waiting queue, and the cache coherency operation of the request is executed.
[0095] In conclusion, the cache coherency implementation system and method based on priority for multi-core processors according to the present application is suitable for multi-core real-time systems, and can guarantee that the cache coherency operation of high-priority tasks is responded preferentially, and avoid real-time invalidation caused by blocking of low-priority tasks.
[0096] The principles and implementation modes of the present application are described in detail above by using specific examples, and these examples are only used to help understand the core technical content of the present application. Based on the above specific examples of the present application, any improvement and modification of the present application made by those skilled in the art without departing from the principles of the present application shall fall within the patent protection scope of the present application.
Claims
1. A priority-based multi-core processor cache coherency implementation system, characterized in that, It comprises: CPU core module, for initiating Cache consistency request according to business requirements, encapsulating the request into a request packet containing key control information and sending it to the Cache controller module; Cache controller module, for receiving the request packet sent by the CPU core module, triggering the Cache consistency operation process, and forwarding the request packet to the priority-aware scheduling module; Priority-aware scheduling module, for parsing the request packet, quantifying the request priority and completing the sorting based on the request priority, and then sending the priority sorting result to the improved bus arbitration module; Improved bus arbitration module, for receiving the priority sorting result, directly executing the consistency operation of the highest priority request, or first waiting according to the priority sorting, then triggering the dynamic preemption mechanism to allocate the bus to the high priority request, and finally executing the consistency operation of the request.
2. The priority-based multi-core processor cache coherency implementation system according to claim 1, wherein, The CPU core module initiates Cache consistency request according to business requirements, encapsulates the request into a request packet containing task priority, operation type and target Cache address, and sends it to the Cache controller module.
3. The priority-based multi-core processor cache coherency implementation system according to claim 1, wherein, The priority-aware scheduling module specifically comprises: The request parsing unit is used for receiving the request packet forwarded by the Cache controller module in real time, extracting the consistency operation type and target Cache address in the request packet, comparing the target Cache address with the address of the Cache controller module, and combining the current MOESI state of the Cache line to determine whether the request type is hit or miss, and finally transmitting the request type and the parsed task priority level to the dynamic arbitration unit; The dynamic arbitration unit is used for quantifying the request priority by the calculation formula "scheduling weight=task priority level×request emergency coefficient" based on the received request type and task priority level, sorting all pending consistency requests based on the calculated scheduling weight, and sending the final sorting result to the improved bus arbitration module; wherein "request emergency coefficient" is set according to the request type.
4. The priority-based multi-core processor cache coherency implementation system according to claim 3, wherein, The improved bus arbitration module specifically comprises: The bus allocation unit is used for receiving the consistency request priority sorting result output by the dynamic arbitration unit, and performing the following operations: (a) when the shared bus resource is currently idle, directly allocating the bus control right to the request with the highest priority and triggering the consistency operation of the request; (b) when the shared bus resource is occupied, adding the request to the priority waiting queue, waiting according to the priority sorting, and triggering the real-time monitoring function of the shared bus resource; The conflict resolution unit is used for monitoring the occupancy state of the shared bus resource in real time, and triggering the dynamic preemption mechanism according to the execution of the low-priority request when a high-priority request arrives and a low-priority request has occupied the shared bus resource; The preemption response unit is used for completing the transfer and subsequent recovery of the bus control right of the low-priority request according to the execution of the dynamic preemption mechanism, and realizing the dynamic allocation of the bus resource.
5. The priority-based multi-core processor cache coherency implementation system according to claim 4, wherein, The execution process of the dynamic preemption mechanism is as follows: (a) the low-priority request has not entered the "non-preemptable phase": (a1) sending a pause signal to the low-priority request, saving its current consistency operation state; (a2) releasing the occupied shared bus resource and allocating it to the high-priority request; (a3) after the high-priority request is executed, sending a resume signal to the low-priority request and resuming its saved consistency operation state to continue the remaining operation; The preemption response unit is used to complete the handover of the bus control right of the low-priority request and subsequent recovery according to the pause signal and the resume signal sent by the dynamic preemption mechanism execution process, so as to realize the dynamic allocation of the bus resource. (b) the low-priority request has entered the "non-preemptible phase": waiting for the execution of the priority request and releasing the corresponding shared bus resource, and then allocating the bus control right to the request with the highest priority in the priority waiting queue to execute its consistency operation.
6. A priority-based cache coherency implementation method for a multi-core processor, the method comprising: The method comprises the following steps: Step 1: The CPU core initiates a Cache consistency request according to the business requirement, encapsulates a request packet containing key control information, and sends the request packet to the Cache controller. Step 2: The Cache controller receives the request packet sent by the CPU core, triggers the Cache consistency operation process, and forwards the request packet to the next process. Step 3: Receive the request packet forwarded by step 2, and perform the following operations in sequence: parse the request packet, quantify the request priority, and complete the sorting based on the request priority. Step 4: Receive the request priority sorting result of step 3, directly execute the consistency operation of the request with the highest priority, or first wait according to the priority, then trigger the dynamic preemption mechanism to allocate the bus to the high-priority request, and finally execute the consistency operation of the request.
7. The priority-based multi-core processor cache coherency implementation system according to claim 6, wherein, The CPU core initiates a Cache consistency request according to the business requirement, encapsulates a request packet containing task priority, operation type and target Cache address, and sends the request packet to the Cache controller.
8. The priority-based multi-core processor cache coherency implementation system according to claim 6, wherein, Step 3 specifically performs the following operations: Step 3.1: Real-time receive the request packet forwarded by step 2, first extract the consistency operation type and target Cache address in the request packet, then compare the target Cache address with the address of the Cache controller, and combine the current MOESI state of the Cache line to determine the request type as hit or miss, and finally transmit the request type and the parsed task priority to the next process; Step 3.2: Based on the received request type and task priority, first quantify the request priority by the calculation formula "dispatch weight = task priority × request emergency coefficient", and then sort all pending consistency requests based on the calculated dispatch weight; wherein the "request emergency coefficient" is set according to the request type.
9. The priority-based multi-core processor cache coherency implementation system according to claim 8, wherein, Step 4 specifically performs the following operations: Step 4.1, receiving the priority ranking result of the consistency request to be processed, performing the following operations: (a) when the shared bus resource is currently idle, directly assigning the bus control right to the request with the highest priority and triggering the consistency operation of the request; (b) when the shared bus resource is occupied, adding the request to the priority waiting queue, waiting according to the priority ranking, and triggering real-time monitoring of the shared bus resource at the same time; Step 4.2, monitoring the occupation state of the shared bus resource in real time, when a high-priority request arrives and a low-priority request has occupied the shared bus resource, triggering a dynamic preemption mechanism according to the execution of the low-priority request; Step 4.3, according to the execution of the dynamic preemption mechanism, completing the bus control right transfer and subsequent recovery of the low-priority request, and realizing the dynamic allocation of the bus resource.
10. The priority-based multi-core processor cache coherency implementation system according to claim 9, wherein, The execution process of the dynamic preemption mechanism is as follows: (a) the low-priority request has not entered the "unpreemptable phase": (a1) send a pause signal to the low-priority request and save its current consistency operation state; (a2) release the occupied shared bus resource and assign it to the high-priority request; (a3) after the execution of the high-priority request is completed, send a recovery signal to the low-priority request and restore its saved consistency operation state to make it continue to execute the remaining operation; In this process, the bus control right transfer and subsequent recovery of the low-priority request are completed according to the pause signal and the recovery signal sent by the dynamic preemption mechanism execution process, and the dynamic allocation of the bus resource is realized; (b) the low-priority request has entered the "unpreemptable phase": Wait for the execution of the priority request to be completed and release the corresponding shared bus resource, and then assign the bus control right to the request with the highest priority in the priority waiting queue and execute its consistency operation.