Driving circuit, repairing method and display device

Abstract

The invention discloses a driving circuit, a repairing method and a display device, the driving circuit comprises a gate driving unit and a gate driving repairing unit, the gate driving repairing unit is used for repairing the failed gate driving unit, an input control module of the gate driving repairing unit receives a first level signal and outputs the first level signal, and an output module receives a clock signal. And the first pull-down module outputs the repaired nth-stage gate driving signal to a scanning line corresponding to the failed nth-stage gate driving unit, the pull-down maintenance module receives the corresponding gate driving signal and the second level signal, and the first pull-down module receives the corresponding gate driving signal, the frame start signal and the second level signal. For the failed gate driving unit, the corresponding first level signal, the second level signal, the gate driving signal, the frame start signal and the clock signal are received, and the repaired gate driving signal is generated to the scanning line corresponding to the failed gate driving unit so as to realize display of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving circuit, a repair method, and a display device. Background Technology

[0002] LCD and OLED panels are created by opening scan lines one by one and sending data voltages through data lines to achieve different grayscale levels. The data lines are driven by signals output from the source driver IC; the scan lines are driven by signals output from the gate driver IC. Nowadays, to optimize costs, the function of the gate driver chip is designed and fabricated on both sides of the panel glass using TFT (thin-film transistor) technology (dual-sided driving). This part of the gate driver circuit integrated into the panel is called the GOA circuit (Gate On Array), also known as the gate driver unit or GOA unit.

[0003] Each gate signal is separated from the clock signal line input signal by a GOA circuit unit. Due to panel manufacturing yield issues, there is a possibility of one GOA unit circuit failing, resulting in a horizontal weak line. As shown in the image below, the screen is white, but because one of the GOA units on the left side has failed, the TFT gate on the left side of that row cannot open normally, while the right side is normal. Therefore, a weak line is displayed from left to right. How to repair the failed gate drive unit is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a drive circuit, repair method, and display device capable of repairing a failed gate drive unit.

[0005] This application discloses a driving circuit, which includes a gate driving unit and a gate driving repair unit. The gate driving repair unit is used to repair a failed nth-level gate driving unit. The input terminal of the input control module is connected to a first-level signal output terminal, receives a first-level signal, and controls the output of the first-level signal. The control terminal of the output module is connected to the output terminal of the input control module. The input terminal receives a clock signal, and the output terminal outputs the repaired nth-level gate driving signal to the scan line corresponding to the failed nth-level gate driving unit. The control terminal of the pull-down sustaining module is connected to the output terminal of the (n-1)th-level gate driving unit, receives the corresponding gate driving signal... The input terminal of the pull-down module is connected to the output terminal of the input control module, and the output terminal is connected to the second level signal output terminal to receive the second level signal. The control terminal of the first pull-down module is connected to the output terminal of the (n+1)th level gate drive unit and the frame start signal output terminal to receive the corresponding gate drive signal and frame start signal. The input terminal is connected to the control terminal of the pull-down maintenance module, and the output terminal is connected to the second level signal output terminal to receive the second level signal. Wherein, n is a natural number greater than or equal to 1. When the corresponding gate drive unit fails, the gate drive repair unit receives the corresponding first level signal, second level signal, gate drive signal, frame start signal and clock signal to generate a repaired gate drive signal to the scan line corresponding to the failed nth level gate drive unit to realize the display of the display panel.

[0006] Optionally, the gate drive repair unit further includes a first control module, a second control module, and a third control module. The input terminal of the output module is connected to a clock signal line via a first repair line. The input terminal of the first control module is connected to the output terminal of the (n-1)th stage gate drive unit via a second repair line to receive the corresponding gate drive signal, and its output terminal is connected to the control terminal of the pull-down sustaining module. The input terminal of the second control module is connected to the output terminal of the (n+1)th stage gate drive unit via a third repair line to receive the corresponding gate drive signal, and its output terminal is connected to the control terminal of the first pull-down module. The output terminal of the output module is connected to the output terminal of the nth stage gate drive unit via a fourth repair line. The third control module... The input terminal of the module is connected to the frame start signal output terminal via the fifth repair line to receive the corresponding frame start signal, and the output terminal is connected to the control terminal of the first pull-down module; wherein, the first repair line is connected to the clock signal line via laser, the second repair line is connected to the scan line connected to the output terminal of the (n-1)th stage gate driving unit via laser, the third repair line is connected to the scan line connected to the output terminal of the (n+1)th stage gate driving unit via laser, the fourth repair line is connected to the scan line connected to the output terminal of the nth stage gate driving unit via laser, and the fifth repair line is connected to the frame start signal line connected to the frame start signal output terminal via laser.

[0007] Optionally, the pull-down sustaining module includes a first transistor and a first storage capacitor, the output module includes a second transistor, and the first pull-down module includes a third transistor; the control terminal of the first transistor is connected to the output terminal of the (n-1)th stage gate driving unit, receives the corresponding gate driving signal, the input terminal is connected to the output terminal of the input control module, and the output terminal is connected to the second level signal output terminal, receives the second level signal, and the first storage capacitor is connected between the control terminal and the output terminal of the first transistor; the control terminal of the second transistor is connected to the output terminal of the input control module, the input terminal receives a clock signal, and the output terminal outputs the repaired nth stage gate driving signal to the scan line corresponding to the failed nth stage gate driving unit; the control terminal of the third transistor is connected to the output terminal of the (n+1)th stage gate driving unit and the frame start signal output terminal respectively, receives the corresponding gate driving signal and the frame start signal, the input terminal is connected to the control terminal of the pull-down sustaining module, and the output terminal is connected to the second level signal output terminal, receives the second level signal.

[0008] Optionally, the gate drive repair unit further includes a second pull-down module. The control terminal of the second pull-down module is connected to the control terminal of the output module, the input terminal is connected to the output terminal of the output module, and the output terminal is connected to the second level signal output terminal to receive the second level signal.

[0009] Optionally, the second pull-down module includes a fourth transistor, the control terminal of which is connected to the control terminal of the second transistor, the input terminal of which is connected to the output terminal of the second transistor, and the output terminal of which is connected to the second level signal output terminal to receive the second level signal; wherein, the first level signal is a high level signal, and the second level signal is a low level signal.

[0010] Optionally, the first control module includes a first diode, the second control module includes a second diode, the third control module includes a third diode, the input control module includes a first resistor, the input terminal of the first diode is connected to the output terminal of the (n-1)th stage gate drive unit through a first patch line to receive the corresponding gate drive signal, and the output terminal is connected to the control terminal of the pull-down sustaining module; the input terminal of the second diode is connected to the output terminal of the (n+1)th stage gate drive unit through a second patch line to receive the corresponding gate drive signal, and the output terminal is connected to the control terminal of the first pull-down module; the input terminal of the third diode is connected to the frame start signal output terminal through a third patch line to receive the corresponding frame start signal, and the output terminal is connected to the control terminal of the first pull-down module; the input terminal of the first resistor is connected to the first level signal output terminal to receive the first level signal, and the output terminal is connected to the input terminal of the pull-down sustaining module and the control terminal of the output module, respectively.

[0011] Optionally, the first control module includes a fifth transistor, the second control module includes a sixth transistor, the third control module includes a seventh transistor, and the input control module includes an eighth transistor. The input terminal of the fifth transistor is connected to the output terminal of the (n-1)th stage gate drive unit via a first repair line to receive the corresponding gate drive signal. The output terminal of the fifth transistor is connected to the control terminal of the pull-down sustaining module, and the control terminal of the fifth transistor is connected to the input terminal of the fifth transistor. The input terminal of the sixth transistor is connected to the output terminal of the (n+1)th stage gate drive unit via a second repair line to receive the corresponding gate drive signal. The output terminal of the sixth transistor... The control terminal of the first pull-down module is connected, and the control terminal of the sixth transistor is connected to the input terminal of the sixth transistor. The input terminal of the seventh transistor is connected to the frame start signal output terminal via a third repair line to receive the corresponding frame start signal. The output terminal of the seventh transistor is connected to the control terminal of the first pull-down module, and the control terminal of the seventh transistor is connected to the input terminal of the seventh transistor. The input terminal of the eighth transistor is connected to the first level signal output terminal to receive the first level signal. The output terminal of the eighth transistor is connected to the input terminal of the pull-down sustaining module and the control terminal of the output module, respectively. The control terminal of the eighth transistor is connected to the input terminal of the eighth transistor.

[0012] Optionally, the pull-down sustaining module includes a first transistor and a first storage capacitor. The control terminal of the first transistor is connected to the output terminal of the (n-1)th stage gate drive unit to receive the corresponding gate drive signal. The input terminal is connected to the output terminal of the eighth transistor, and the output terminal is connected to the second level signal output terminal to receive the second level signal. The first storage capacitor is connected between the control terminal and the output terminal of the first transistor. The channel width-to-length ratio of the eighth transistor is smaller than that of the first transistor.

[0013] This application also discloses a driving method for driving any of the driving circuits described above, the driving method comprising the steps of: The gate drive repair unit receives the corresponding first level signal, second level signal, gate drive signal corresponding to the (n-1)th level gate drive unit, gate drive signal corresponding to the (n+1)th level gate drive unit, frame start signal, and clock signal; Based on the first level signal, the second level signal, the gate drive signal corresponding to the (n-1)th level gate drive unit, the gate drive signal corresponding to the (n+1)th level gate drive unit, the frame start signal, and the clock signal, a repaired gate drive signal is generated and sent to the scan line corresponding to the failed nth level gate drive unit to realize the display of the display panel.

[0014] This application also discloses a display device, which includes a driving circuit and a display panel as described above. The driving circuit further includes a timing control module and a data driving module. The data driving module outputs data signals to the data lines of the display panel. The timing control module is used to control the timing of the gate driving signals and data signals input to the display panel to achieve orderly display in the display panel.

[0015] Compared to the approach of repairing and replacing the internal traces or devices of the gate driving unit, this application adjusts and improves the driving circuit by setting a gate driving repair unit. The gate driving repair unit is used to repair the failed nth-level gate driving unit. The input control module of the gate driving repair unit receives a first-level signal and outputs it. The output module receives a clock signal and outputs the repaired nth-level gate driving signal to the scan line corresponding to the failed nth-level gate driving unit. The pull-down sustaining module receives the corresponding gate driving signal and the second-level signal. The first pull-down module receives the corresponding gate driving signal, the frame start signal, and the second-level signal. However, when a certain gate driving unit fails, the gate driving repair unit receives the corresponding first-level signal, the second-level signal, the gate driving signal, the frame start signal, and the clock signal to generate a repaired gate driving signal to the scan line corresponding to the failed gate driving unit to realize the display panel display. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a schematic diagram of the drive circuit module of the first embodiment of this application; Figure 2 This is a schematic diagram of the drive circuit module of the second embodiment of this application. Figure 3 This is a schematic diagram of the driving circuit structure of the second embodiment of this application; Figure 4 This is a schematic diagram of the driving circuit module according to the third embodiment of this application; Figure 5 This is a schematic diagram of the driving circuit of the fourth embodiment of this application; Figure 6 This is a schematic diagram of the drive signal waveform of the fourth embodiment of this application; Figure 7 This is a schematic diagram of the driving circuit according to the fifth embodiment of this application; Figure 8 This is a schematic flowchart of the driving method according to the sixth embodiment of this application; Figure 9 This is a schematic diagram of the display device module according to the seventh embodiment of this application.

[0017] Among them, 100 is a driving circuit; 101 is a gate driving unit; 102 is a gate driving repair unit; 103 is an input control module; 104 is a first level signal output terminal; 105 is an output module; 106 is a pull-down sustaining module; 107 is a second level signal output terminal; 108 is a first pull-down module; 109 is a frame start signal output terminal; 111 is a first control module; 112 is a second control module; 113 is a third control module; 114 is a second pull-down module; 115 is a timing control module; 116 is a data driving module; 200 is a display panel; and 300 is a display device. L1 - First repair line; L2 - Second repair line; L3 - Third repair line; L4 - Fourth repair line; L0 - Fifth repair line; D1 - First diode; D2 - Second diode; D3 - Third diode; R1 - First resistor; T1 - First transistor; T2 - Second transistor; T3 - Third transistor; T4 - Fourth transistor; T5 - Fourth transistor; T6 - Sixth transistor; T7 - ​​Seventh transistor; T8 - Eighth transistor; C1 - First storage capacitor; VGH - First level signal / high level signal; CKV - Clock signal; VGL - Second level signal / low level signal; STV - Frame start signal; Gn-1 - Gate drive signal of level (n-1); Gn - Gate drive signal of level n; Gn+1 - Gate drive signal of level (n+1). Detailed Implementation

[0018] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0019] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0020] refer to Figure 1As shown, as a first embodiment of this application, a driving circuit 100 is disclosed. The driving circuit 100 includes a gate driving unit 101 and a gate driving repair unit 102. The gate driving repair unit 102 is used to repair the failed nth-level gate driving unit 101. The input terminal of the input control module 103 is connected to the first level signal output terminal 104, receives the first level signal, and controls the output of the first level signal. The control terminal of the output module 105 is connected to the output terminal of the input control module 103. The input terminal receives a clock signal, and the output terminal outputs the repaired nth-level gate driving signal to the scan line corresponding to the failed nth-level gate driving unit 101. The control terminal of the pull-down sustaining module 106 is connected to the output terminal of the (n-1)th-level gate driving unit 101, receives the corresponding gate driving signal, and repairs the failed nth-level gate driving unit 101. The input terminal of the drive signal is connected to the output terminal of the input control module 103, and the output terminal is connected to the second level signal output terminal 107 to receive the second level signal. The control terminal of the first pull-down module 108 is connected to the output terminal of the (n+1)th level gate drive unit 101 and the frame start signal output terminal 109 respectively to receive the corresponding gate drive signal and frame start signal. The input terminal is connected to the control terminal of the pull-down maintenance module 106, and the output terminal is connected to the second level signal output terminal 107 to receive the second level signal. Wherein, the first level signal is a high level signal, the second level signal is a low level signal, and n is a natural number greater than or equal to 1. When the corresponding gate drive unit 101 fails, the gate drive repair unit 102 receives the corresponding first level signal, second level signal, gate drive signal, frame start signal and clock signal to generate a repaired gate drive signal to the scan line corresponding to the failed nth level gate drive unit 101 to realize the display of the display panel 200.

[0021] When a gate drive unit 101 in a certain row fails or malfunctions, the corresponding gate drive signal cannot be output to the corresponding scan line, directly causing the corresponding row to fail to scan normally. If not repaired in time, it will cause irreversible display defects such as "dark lines" and "bright lines". This application sets up a gate drive repair unit 102, which consists of four modules, each with a clear division of labor, forming a closed-loop repair link of "signal input → pulse generation → level maintenance → abnormality suppression". Specifically, the drive signals output by the upper-level gate drive unit 101 and the lower-level gate drive unit 101 of the failed gate drive unit 101 are introduced into the signal repair circuit for repair processing, so that the repaired drive signal drives the nth scan line through the repair lines on both sides of the display area at the same time. Thus, the gate drive signal input to the nth scan line is the same as the gate drive signal output by the gate drive unit 101 when it was not failed, realizing the repair of the abnormal GOA unit. By replacing the feedback of the failed unit with the signal of the adjacent stage, the normal timing is reproduced with the clock signal, and the level is maintained by redundant pull-down. Through a three-level coordination of "input control-output-pull-down", the goal of "rapid repair + long-term stability" is achieved. It is especially suitable for high-end display panels with high resolution (such as 8K) and high refresh rate (such as 240Hz). It can effectively reduce the risk of "line scrapping" caused by GOA failure and improve product yield and reliability.

[0022] As a second embodiment of this application, it is a further refinement and improvement of the first embodiment described above, such as... Figure 2 and Figure 3As shown, the gate drive repair unit 102 is mainly mounted on the control circuit board (PCBA). It passes through the chip-on-film (COF) via corresponding traces and is then connected to the gate drive unit 101, scan lines, and frame start signal lines via repair lines. Integrating the gate drive repair circuit into the panel eliminates the cost of external PCBA circuit components. The gate drive repair unit 102 also includes a first control module 111, a second control module 112, and a third control module 113. The input terminal of the output module 105 is connected to the clock signal line via the first repair line L1, and the input terminal of the first control module 111 is connected to the (n-1)th stage gate drive unit via the second repair line L2. The output terminal of the first control module 101 receives the corresponding gate drive signal and is connected to the control terminal of the pull-down sustaining module 106; the input terminal of the second control module 112 is connected to the output terminal of the (n+1)th stage gate drive unit 101 through the third repair line L3, receives the corresponding gate drive signal, and is connected to the control terminal of the first pull-down module 108; the output terminal of the output module 105 is connected to the output terminal of the nth stage gate drive unit 101 through the fourth repair line L4; the input terminal of the third control module 113 is connected to the frame start signal output terminal 109 through the fifth repair line L0, receives the corresponding frame start signal, and is connected to the control terminal of the first pull-down module 108.

[0023] Specifically, the first repair line L1 is connected to the clock signal line via laser etching; the second repair line L2 is connected to the scan line connected to the output terminal of the (n-1)th stage gate driving unit 101 via laser etching; the third repair line L3 is connected to the scan line connected to the output terminal of the (n+1)th stage gate driving unit 101 via laser etching; the fourth repair line L4 is connected to the scan line connected to the output terminal of the nth stage gate driving unit 101 via laser etching; and the fifth repair line L0 is connected to the frame start signal line connected to the frame start signal output terminal 109 via laser etching. The laser-etched repair lines can be surface-fused in the curved area without adding extra thickness.

[0024] Generally, the pull-down sustaining module 106 includes a first transistor T1 and a first storage capacitor C1, the output module 105 includes a second transistor T2, and the first pull-down module 108 includes a third transistor T3. Typically, the first transistor T1 and the third transistor T3 are N-type MOSFETs, and the second transistor T2 is a P-type MOSFET. The control terminal of the first transistor T1 is connected to the output terminal of the (n-1)th stage gate drive unit 101 to receive the corresponding gate drive signal, the input terminal is connected to the output terminal of the input control module 103, and the output terminal is connected to the second level signal output terminal 107 to receive the second level signal. The first storage capacitor C1 is connected between the control terminal and the output terminal of the first transistor T1. The storage capacitor C1 stores the falling edge voltage of Gn-1, keeping the first transistor T1 on until the end of the current scan, preventing "floating leakage". The control terminal of the second transistor T2 is connected to the output terminal of the input control module 103. The input terminal receives the clock signal, and the output terminal outputs the repaired nth-level gate drive signal to the scan line corresponding to the failed nth-level gate drive unit 101. The control terminal of the third transistor T3 is connected to the output terminal of the (n+1)th-level gate drive unit 101 and the frame start signal output terminal 109, respectively, receiving the corresponding gate drive signal and frame start signal. The input terminal is connected to the control terminal of the pull-down sustaining module 106, and the output terminal is connected to the second level signal output terminal 107 to receive the second level signal.

[0025] In this embodiment, considering that the gate repair unit needs to directly access the original signal of the adjacent stage (n-1 / n+1), which is easily affected by the noise of the original circuit, a corresponding control module is set up to process the external signal before it is transmitted to the repair unit to reduce interference. The first control module triggers the pull-down sustaining module 106 on the falling edge of Gn-1 to achieve noise filtering and eliminate high-frequency jitter pulses. The second control module 112 aligns the rising edge of Gn+1 with the frame start signal STV to limit the input voltage to a safe range. The third control module 113 expands the narrow STV pulse into a continuous full-frame effective signal to avoid conflict with Gn+1. The first control module 111 ensures that the pull-down only occurs at the end of the scan to avoid false triggering. The second control module 112 and the third control module 113 jointly realize the dual pull-down of "subsequent stage scan + frame switching" to completely suppress crosstalk.

[0026] like Figure 4 As shown, as the third embodiment of this application, and a further refinement and improvement of the first embodiment described above, the gate drive repair unit 102 further includes a second pull-down module 114. The control terminal of the second pull-down module 114 is connected to the control terminal of the output module 105, the input terminal is connected to the output terminal of the output module 105, and the output terminal is connected to the second level signal output terminal 107 to receive the second level signal.

[0027] Generally, the second pull-down module 114 includes a fourth transistor T4. The control terminal of the fourth transistor T4 is connected to the control terminal of the second transistor T2, the input terminal is connected to the output terminal of the second transistor T2, and the output terminal is connected to the second level signal output terminal 107 to receive the second level signal. The first level signal is a high level signal, and the second level signal is a low level signal.

[0028] In this embodiment, based on the first and second embodiments, a closed-loop protection mechanism of "main output-double pull-down" is constructed by introducing a second pull-down module 114. When the failure of the nth stage gate drive unit 101 GOA is detected (such as no output or abnormal output), the input control module 103 is turned on, allowing VGH to enter the output module 105. The output module 105 converts VGH into a "high-level active" scan pulse with the clock signal CLK as the beat and outputs it to the nth stage scan line, replacing the function of the original GOA. During the scan, the output module 105 maintains a high level and selects the corresponding row pixel. After the scan is completed, the pull-down maintenance module 106 pulls the scan line low to VSS based on the signal Gn-1. When Gn+1 is triggered or STV arrives, the first pull-down module 108 strengthens the pull-down to ensure that the scan line is always at a "safe low level". Regardless of whether the output module 105 is in the "on" or "off" state, the second pull-down module 114 dynamically clamps the scan line level.

[0029] As a fourth embodiment of this application, it further refines and improves any of the above embodiments, including improvements to the first, second, and third embodiments, as well as further improvements to the embodiment formed by combining the second and third embodiments. (See reference...) Figures 2 to 6As shown, the first control module 111 includes a first diode D1, the second control module 112 includes a second diode D2, the third control module 113 includes a third diode D3, and the input control module 103 includes a first resistor. The input terminal of the first diode D1 is connected to the output terminal of the (n-1)th stage gate drive unit 101 through a first repair line L1 to receive the corresponding gate drive signal, and its output terminal is connected to the control terminal of the pull-down sustaining module 106. The input terminal of the second diode D2 is connected to the output terminal of the (n+1)th stage gate drive unit 101 through a second repair line L2 to receive the corresponding gate drive signal, and its output terminal is connected to the control terminal of the first pull-down module 108. The input terminal of the third diode D3 is connected to the frame start signal output terminal 109 through a third repair line L3 to receive the corresponding frame start signal, and its output terminal is connected to the control terminal of the first pull-down module 108. The input terminal of the first resistor is connected to the first level signal output terminal 104 to receive the first level signal, and its output terminal is connected to the input terminal of the pull-down sustaining module 106 and the control terminal of the output module 105, respectively.

[0030] In this embodiment, the gate drive repair unit 102 mainly consists of one resistor, one capacitor, one P-type MOSFET, three N-type MOSFETs, and three diodes. When a GOA unit at a certain level of the panel fails, the corresponding traces can be laser-welded together to connect the input signal required by the gate drive repair circuit and the output signal compensated by the GOA circuit to the in-plane circuit. For example, when the GOA unit at level 9 of the panel fails, the corresponding CKV1 and L0 lines at level 9 need to be laser-welded together, while G8 and L2 lines, G10 and L3 lines, and G9 and L4 lines need to be laser-welded. The welding positions are... Figure 5 The red dots (before welding, the intersecting lines in the diagram represent traces from different layers and will not short-circuit each other). Since the STV corresponding to the L1 line is identical for each panel, no selection is needed; when designing the GOA panel, an interference fit can be used directly.

[0031] The principle of the gate drive repair circuit is shown in the attached figure. Figure 5Upon power-on, the first frame STV signal (start of frame signal) arrives at a high level VGH (typically around 30V). This high level is sent to the gate of the third transistor T3 via the third diode D3, turning T3 on and setting the gate voltage of T1 to a low level VGL (typically around -10V). At this time, Vgs of T1 = 0, and T1 is in the off state. The pull-up resistor R1 makes the gate voltages of T2 and T4 VGH. The voltage difference between the gate and source of T2, Vgs = VGH (the upper end of T2 is the S terminal), so T2 is off. The Vgs of NmosT4 = VGH - VGL, so T4 is on. At this time, the output of G9 is VGL. After STV goes low, T3 is off, and C1 maintains the gate voltage of T1. G9 maintains the output VGL.

[0032] When the 8th row is scanned, the G8 signal charges C1 through diode D1. When the voltage of C1 reaches the threshold voltage Vth of T1, T1 turns on, pulling the gate of Pmos T2 low to VGL. At this time, Vgs of T2 equals VGL, which is a negative voltage, and T2 turns on. Vgs of T4 equals 0, and T4 turns off. After the 8th row is scanned, G8 goes low (VGL). Due to the unidirectional conductivity of diode D1, the gate voltage of T1 is maintained by C1, T1 and T2 remain on, and T4 remains off.

[0033] When the 9th row begins scanning, CKV1 switches to a high level (VGH) to supply the GOA9 unit. However, GOA9 is faulty and cannot generate the G9 signal, requiring a repair circuit to generate G9. The CKV1 signal, laser-welded, is transmitted back to the s pole (upper end of T2). When CKV1 becomes VGH, T2's Vgs = VGL - VGH, which is a negative voltage, and T2 remains conducting. CKV1 is sent to L4 through T2, and L4 then transmits it to G9 through the laser-welded point, thus sending the G9 signal corresponding to CKV1 into the plane.

[0034] After the 9th row scan is completed, T2 needs to be turned off to prevent the high level generated by CKV1 from being mistakenly sent to G9. After CKV1 turns low, the 9th row scan is complete, and the 10th row scan begins. G10 passes through the laser point to L3, and the G10 signal is sent to the gate of the repair circuit T3 through diode D2. The voltage difference between the source and gate of T3 is Vgs = VGH - VGL, so T3 is turned on. T3 pulls the gate voltage of T1 down to VGL, and T1 is turned off. Due to the presence of R1, when T1 is turned off, the gate of T2 will be pulled high to VGH, the P-type MOS transistor, i.e., the second transistor T2, will be turned off, and T4 will be turned on (the same as when the STV high level is sent). In this way, the subsequent CKV1 high level signal will no longer be sent to G9. T4 keeps G9 at VGL voltage to prevent in-plane coupling effects from causing G9 to go too high.

[0035] like Figure 7As shown, the fifth embodiment of this application is a further extension of the first to third embodiments described above. (Refer to...) Figures 2 to 7 As shown, unlike the fourth embodiment described above, the first control module 111 includes a fifth transistor T5, the second control module 112 includes a sixth transistor T6, the third control module 113 includes a seventh transistor T7, and the input control module 103 includes an eighth transistor T8. The input terminal of the fifth transistor T5 is connected to the output terminal of the (n-1)th stage gate drive unit 101 via a first repair line L1 to receive the corresponding gate drive signal. The output terminal of the fifth transistor T5 is connected to the control terminal of the pull-down sustaining module 106, and the control terminal of the fifth transistor T5 is connected to the input terminal of the fifth transistor T5. The input terminal of the sixth transistor T6 is connected to the output terminal of the (n+1)th stage gate drive unit 101 via a second repair line L2 to receive the corresponding gate drive signal. The output terminal of transistor T6 is connected to the control terminal of the first pull-down module 108, and the control terminal of the sixth transistor T6 is connected to the input terminal of the sixth transistor T6; the input terminal of the seventh transistor T7 is connected to the frame start signal output terminal 109 through the third repair line L3 to receive the corresponding frame start signal, the output terminal of the seventh transistor T7 is connected to the control terminal of the first pull-down module 108, and the control terminal of the seventh transistor T7 is connected to the input terminal of the seventh transistor T7; the input terminal of the eighth transistor T8 is connected to the first level signal output terminal 104 to receive the first level signal, the output terminal of the eighth transistor T8 is connected to the input terminal of the pull-down sustaining module 106 and the control terminal of the output module 105 respectively, and the control terminal of the eighth transistor T8 is connected to the input terminal of the eighth transistor T8.

[0036] Furthermore, the pull-down sustaining module 106 includes a first transistor T1 and a first storage capacitor C1. The control terminal of the first transistor T1 is connected to the output terminal of the (n-1)th stage gate driving unit 101 to receive the corresponding gate driving signal. Its input terminal is connected to the output terminal of the eighth transistor T8, and its output terminal is connected to the second level signal output terminal 107 to receive the second level signal. The first storage capacitor C1 is connected between the control terminal and the output terminal of the first transistor T1. The channel width-to-length ratio of the eighth transistor T8 is smaller than that of the first transistor T1.

[0037] Unlike the fourth embodiment described above, this embodiment designs this part of the circuit as a TFT fabricated into the panel. Since the panel is full of TFT devices, diodes and resistors cannot be directly fabricated. Therefore, D1, D2, D3 and R1 are replaced with TFTs. The figure below shows the GOA repair circuit designed with TFTs.

[0038] Generally, the channel width-to-length ratio of the eighth transistor T8 can be designed to be much smaller than that of T1. The current-carrying capacity of each transistor TFT is directly proportional to the designed width-to-length ratio, while the equivalent resistance is inversely proportional to the width-to-length ratio. When T1 is turned on, the gate voltage of T2 is obtained by voltage division between the equivalent resistances of T8 and T1. The equivalent resistance of T8 is large, and the equivalent resistance of T1 is small. After voltage division, the gate voltage of T2 will also be close to VGL. When T1 is turned off, T8 pulls the gate voltage of T2 to VGH, so T8 can act as a resistor.

[0039] like Figure 8 As shown, as a sixth embodiment of this application, a driving method is also disclosed for driving the driving circuit described in any of the above embodiments. The driving method includes the following steps: S1: The gate drive repair unit receives the corresponding first level signal, second level signal, gate drive signal corresponding to the (n-1)th level gate drive unit, gate drive signal corresponding to the (n+1)th level gate drive unit, frame start signal, and clock signal; S2: Based on the first level signal, the second level signal, the gate drive signal corresponding to the (n-1)th level gate drive unit, the gate drive signal corresponding to the (n+1)th level gate drive unit, the frame start signal, and the clock signal, a repaired gate drive signal is generated and sent to the scan line corresponding to the failed nth level gate drive unit to realize the display of the display panel.

[0040] In this embodiment, the clock signal CLK is the main component. The gate drive signals Gn-1 and Gn+1 of the upper and lower stages of the failed gate drive unit are used to reconstruct the scanning waveform that the nth stage should have. VGH / VGL provides the working voltage for the repair circuit to ensure dynamic adjustment capability. STV / CLK ensures that the repair action is strictly aligned with the refresh cycle of the display panel. Through multi-source signal fusion, intelligent timing reconstruction and closed-loop level calibration, efficient repair of the failed GOA unit is achieved, improving repair efficiency and reducing repair cost.

[0041] like Figure 9 As shown in the seventh embodiment of this application, a display device is disclosed. The display device includes a driving circuit and a display panel as described above. The driving circuit further includes a timing control module and a data driving module. The data driving module outputs data signals to the data lines of the display panel. The timing control module is used to control the timing of the gate driving signals and data signals input to the display panel to achieve orderly display in the display panel.

[0042] It should be noted that the limitations on the steps involved in this solution, without affecting the implementation of the specific solution, are not considered as limiting the order of the steps. That is, the steps listed first can be performed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the protection scope of this application. The inventive concept of this application can form many embodiments, but due to space limitations in the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. The combination of embodiments or technical features will enhance the original technical effect.

[0043] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A drive circuit comprising a gate drive unit and a gate drive repair unit for repairing a failed nth stage gate drive unit, characterized by, The gate drive repair unit comprises: an input control module, an input end of which is connected to a first level signal output end, receives a first level signal, and controls output of the first level signal; an output module, a control end of which is connected to an output end of the input control module, an input end of which receives a clock signal, and an output end of which outputs a repaired nth gate drive signal to a corresponding scan line of an nth gate drive unit that is out of order; a pull-down maintenance module, a control end of which is connected to an output end of an (n-1)th gate drive unit, an input end of which receives a corresponding gate drive signal, and an output end of which is connected to a second level signal output end and receives a second level signal; and a first pull-down module, a control end of which is connected to an output end of an (n+1)th gate drive unit and a frame start signal output end, an input end of which receives a corresponding gate drive signal and a frame start signal, and an output end of which is connected to a second level signal output end and receives a second level signal. Wherein, n is a natural number greater than or equal to 1, when a corresponding gate drive unit is out of order, the gate drive repair unit receives corresponding first level signals, second level signals, gate drive signals, frame start signals, and clock signals to generate a repaired gate drive signal to a corresponding scan line of an nth gate drive unit that is out of order to realize display of a display panel.

2. The drive circuit of claim 1, wherein The gate drive repair unit further comprises a first control module, a second control module, and a third control module, an input end of the output module is connected to a clock signal line through a first repair line, an input end of the first control module is connected to an output end of the (n-1)th gate drive unit through a second repair line, receives a corresponding gate drive signal, and an output end thereof is connected to a control end of the pull-down maintenance module; an input end of the second control module is connected to an output end of the (n+1)th gate drive unit through a third repair line, receives a corresponding gate drive signal, and an output end thereof is connected to a control end of the first pull-down module; an output end of the output module is connected to an output end of the nth gate drive unit through a fourth repair line; an input end of the third control module is connected to the frame start signal output end through a fifth repair line, receives a corresponding frame start signal, and an output end thereof is connected to a control end of the first pull-down module; Wherein, the first repair line is connected to the clock signal line by means of laser, the second repair line is connected to a scan line connected to the output end of the (n-1)th gate drive unit by means of laser, the third repair line is connected to a scan line connected to the output end of the (n+1)th gate drive unit by means of laser, the fourth repair line is connected to a scan line connected to the output end of the nth gate drive unit by means of laser, and the fifth repair line is connected to a frame start signal line connected to the frame start signal output end by means of laser.

3. The drive circuit of claim 2, wherein, The pull-down maintaining module comprises a first transistor and a first storage capacitor, the output module comprises a second transistor, and the first pull-down module comprises a third transistor; the control end of the first transistor is connected to the output end of the n-1th gate drive unit to receive a corresponding gate drive signal, the input end is connected to the output end of the input control module, and the output end is connected to the second level signal output end to receive a second level signal; the first storage capacitor is connected between the control end and the output end of the first transistor; the control end of the second transistor is connected to the output end of the input control module, the input end receives a clock signal, and the output end outputs a repaired nth gate drive signal to the corresponding scan line of the failed nth gate drive unit; the control end of the third transistor is connected to the output end of the n+1th gate drive unit and the frame start signal output end respectively to receive a corresponding gate drive signal and a frame start signal, the input end is connected to the control end of the pull-down maintaining module, and the output end is connected to the second level signal output end to receive a second level signal.

4. The drive circuit of claim 3, wherein The gate drive repairing unit further comprises a second pull-down module, the control end of the second pull-down module is connected to the control end of the output module, the input end is connected to the output end of the output module, and the output end is connected to the second level signal output end to receive a second level signal.

5. The drive circuit of claim 4, wherein, The second pull-down module comprises a fourth transistor, the control end of the fourth transistor is connected to the control end of the second transistor, the input end is connected to the output end of the second transistor, and the output end is connected to the second level signal output end to receive a second level signal. The first level signal is a high level signal, and the second level signal is a low level signal.

6. The drive circuit according to any one of claims 2 to 5, wherein The first control module comprises a first diode, the second control module comprises a second diode, the third control module comprises a third diode, the input control module comprises a first resistor, the input end of the first diode is connected to the output end of the n-1th gate drive unit through a first repair line to receive a corresponding gate drive signal, and the output end is connected to the control end of the pull-down maintaining module; the input end of the second diode is connected to the output end of the n+1th gate drive unit through a second repair line to receive a corresponding gate drive signal, and the output end is connected to the control end of the first pull-down module; the input end of the third diode is connected to the frame start signal output end through a third repair line to receive a corresponding frame start signal, and the output end is connected to the control end of the first pull-down module; the input end of the first resistor is connected to the first level signal output end to receive a first level signal, and the output end is connected to the input end of the pull-down maintaining module and the control end of the output module respectively.

7. The drive circuit according to any one of claims 2 to 5, wherein The first control module comprises a fifth transistor, the second control module comprises a sixth transistor, the third control module comprises a seventh transistor, and the input control module comprises an eighth transistor. An input end of the fifth transistor is connected to an output end of the n-1th gate drive unit through a first repair line to receive a corresponding gate drive signal. An output end of the fifth transistor is connected to a control end of the pull-down maintenance module. A control end of the fifth transistor is connected to the input end of the fifth transistor. An input end of the sixth transistor is connected to an output end of the n+1th gate drive unit through a second repair line to receive a corresponding gate drive signal. An output end of the sixth transistor is connected to a control end of the first pull-down module. A control end of the sixth transistor is connected to the input end of the sixth transistor. An input end of the seventh transistor is connected to the frame start signal output end through a third repair line to receive a corresponding frame start signal. An output end of the seventh transistor is connected to the control end of the first pull-down module. A control end of the seventh transistor is connected to the input end of the seventh transistor. An input end of the eighth transistor is connected to a first level signal output end to receive a first level signal. An output end of the eighth transistor is connected to an input end of the pull-down maintenance module and a control end of the output module. A control end of the eighth transistor is connected to the input end of the eighth transistor.

8. The drive circuit of claim 7, wherein, The pull-down maintenance module comprises a first transistor and a first storage capacitor. A control end of the first transistor is connected to an output end of the n-1th gate drive unit to receive a corresponding gate drive signal. An input end of the first transistor is connected to an output end of the eighth transistor. An output end of the first transistor is connected to a second level signal output end to receive a second level signal. The first storage capacitor is connected between the control end and the output end of the first transistor. A channel width-length ratio of the eighth transistor is smaller than a channel width-length ratio of the first transistor.

9. A repairing method of a drive circuit for the drive circuit as claimed in any one of claims 1 to 8, characterized by, The repair method comprises the following steps: The gate drive repair unit receives a corresponding first level signal, a second level signal, a corresponding gate drive signal of the n-1th gate drive unit, a corresponding gate drive signal of the n+1th gate drive unit, a frame start signal, and a clock signal. Based on the first level signal, the second level signal, the corresponding gate drive signal of the n-1th gate drive unit, the corresponding gate drive signal of the n+1th gate drive unit, the frame start signal, and the clock signal, a repaired gate drive signal is generated to the corresponding scan line of the failed nth gate drive unit to realize display of the display panel.

10. A display device, characterized by comprising: The display panel comprises the driving circuit and the display panel according to any one of claims 1-8. The driving circuit further comprises a timing control module and a data driving module. The data driving module outputs a data signal to a data line of the display panel. The timing control module is used to control timing of a gate drive signal and a data signal input to the display panel to realize ordered display in the display panel.

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