Display device

Abstract

A display device is disclosed. The display device includes: a display panel including pixels connected to scan lines; a gate driver including a plurality of stages, a stage among the plurality of stages is configured to provide a carry clock signal of the carry clock line as a carry signal to a subsequent stage among the plurality of stages and to provide a scan clock signal of the scan clock line as a scan signal to a corresponding scan line among the scan lines in response to a preceding carry signal of a preceding stage among the plurality of stages; and a clock controller connecting the scan clock line to a power line in response to the carry clock signal, the power line configured to provide a constant voltage.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0125079, filed on September 12, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to a gate driver, a display device including the gate driver, and an electronic device. Background Technology

[0003] Display devices use pixels to display images. A display device may include a gate driver for driving the pixels. Summary of the Invention

[0004] Embodiments of this disclosure may relate to a gate driver, display device, and electronic device that can shorten the fall time of a scan signal.

[0005] According to one or more embodiments of the present disclosure, a display device includes: a display panel including pixels connected to scan lines; a gate driver including a plurality of stages, one of which is configured to provide a carry clock signal of a carry clock line as a carry signal to a subsequent stage of the plurality of stages and to provide a scan clock signal of a scan clock line as a scan signal to a corresponding scan line of the scan lines in response to a previous carry signal of a previous stage of the plurality of stages; and a clock controller configured to connect the scan clock line to a power line in response to the carry clock signal, the power line being configured to provide a constant voltage.

[0006] According to an embodiment, each of the carry clock line and the scan clock line can extend from a first side of the display panel (the pad can be positioned at the first side) to a second side of the display panel, and the clock controller can be positioned adjacent to the second side of the display panel.

[0007] According to an embodiment, the gate driver may further include a dummy stage configured to provide a carry signal to a previous stage, the dummy stage not connected to a scan line, and a clock controller may be positioned adjacent to the dummy stage.

[0008] According to an embodiment, the gate driver may include a clock controller.

[0009] According to an embodiment, the stage can be configured to output a first carry clock signal of a first carry clock line as a carry signal, and the clock controller can include a first switching transistor connected between the scan clock line and the power line, the first switching transistor including a gate electrode connected to a second carry clock line.

[0010] According to an embodiment, the first switching transistor may include an oxide semiconductor.

[0011] According to an embodiment, each of the carry clock signal and the scan clock signal may include a square wave periodically having a gate on voltage and a gate off voltage, and the second carry clock signal of the second carry clock line may have a phase that is delayed by as much as the pulse width of the scan clock signal having a gate on voltage, compared to the first carry clock signal of the first carry clock line.

[0012] According to an embodiment, the power line can be configured to receive a gate cutoff voltage, and the clock controller can be configured to connect a scan clock line to the power line in response to a carry clock signal having a gate turn-on voltage, thereby shortening the fall time of each of the scan clock signal and the scan signal.

[0013] According to an embodiment, the display panel may further include: a first carry clock line to a sixth carry clock line, configured to receive the first carry clock signal to the sixth carry clock signal respectively; and a first scan clock line to a sixth scan clock line, configured to receive the first scan clock signal to the sixth scan clock signal respectively. The first carry clock signal to the sixth carry clock signal may have the same waveform and different phases. The first scan clock signal to the sixth scan clock signal may have the same waveform and have the same phase as the first carry clock signal to the sixth carry clock signal. The clock controller may be configured to: pull down the first scan clock signal in response to a third carry clock signal; pull down the second scan clock signal in response to a fourth carry clock signal; pull down the third scan clock signal in response to a fifth carry clock signal; pull down the fourth scan clock signal in response to a sixth carry clock signal; pull down the fifth scan clock signal in response to a first carry clock signal; and pull down the sixth scan clock signal in response to a second carry clock signal.

[0014] According to an embodiment, the clock controller may include: an eleventh switching transistor connected between a first scan clock line and a power line, the eleventh switching transistor including a gate electrode connected to a third carry clock line; a twelfth switching transistor connected between a second scan clock line and a power line, the twelfth switching transistor including a gate electrode connected to a fourth carry clock line; a thirteenth switching transistor connected between a third scan clock line and a power line, the thirteenth switching transistor including a gate electrode connected to a fifth carry clock line; a fourteenth switching transistor connected between a fourth scan clock line and a power line, the fourteenth switching transistor including a gate electrode connected to a sixth carry clock line; a fifteenth switching transistor connected between a fifth scan clock line and a power line, the fifteenth switching transistor including a gate electrode connected to a first carry clock line; and a sixteenth switching transistor connected between a sixth scan clock line and a power line, the sixteenth switching transistor including a gate electrode connected to a second carry clock line.

[0015] According to an embodiment, the stage can be configured to output a first carry clock signal from a first carry clock line as a carry signal. The clock controller may include a first switching transistor and a second switching transistor connected in series between the scan clock line and the power line. The gate electrode of the first switching transistor may be connected to a second carry clock line, and the gate electrode of the second switching transistor may be connected to the first carry clock line.

[0016] According to an embodiment, each of the carry clock signal and the scan clock signal may include a square wave periodically having a gate on-state voltage and a gate off-state voltage. The first carry clock signal of the first carry clock line may have the same waveform and phase as the scan clock signal, and the second carry clock signal of the second carry clock line may have a phase that is delayed by as much as the pulse width of the carry clock signal with the gate on-state voltage compared to the first carry clock signal of the first carry clock line.

[0017] According to an embodiment, the constant voltage of the power line can have a voltage level lower than the gate cutoff voltage level.

[0018] According to an embodiment, a stage may include: a first transistor, a diode connected between a previous carry line configured to receive a previous carry signal and a Q node; a second transistor connected between a carry clock line and a first output terminal configured to output a carry signal, the second transistor including a gate electrode connected to the Q node; a third transistor connected between the first output terminal and a low power line, the third transistor including a gate electrode connected to the QB node; a fourth transistor connected between a scan clock line and a second output terminal configured to output a scan signal, the fourth transistor including a gate electrode connected to the Q node; and a fifth transistor connected between the second output terminal and the low power line, the fifth transistor including a gate electrode connected to the QB node. The stage may not include a transistor that connects the second output terminal and the low power line to each other in response to a subsequent carry signal from a subsequent stage.

[0019] According to one or more embodiments of this disclosure, the gate driver includes: multiple stages; and clock control circuitry. One of the multiple stages is configured to: provide a carry clock signal from a carry clock line as a carry signal to a subsequent stage; and output a scan clock signal from a scan clock line as a scan signal in response to a previous carry signal from a previous stage. The clock control circuitry may be configured to pull the scan clock line down to a gate cutoff voltage in response to the carry clock signal.

[0020] According to an embodiment, the gate driver may further include a dummy stage configured to provide a carry signal to the previous stage and not output a scan signal. Clock control circuitry may be positioned adjacent to the dummy stage.

[0021] According to an embodiment, the stage can be configured to output a first carry clock signal of a first carry clock line as a carry signal, and the clock control circuit can include a first switching transistor connected between a scan clock line and a power line configured to provide a constant voltage, the first switching transistor including a gate electrode connected to a second carry clock line.

[0022] According to an embodiment, each of the carry clock signal and the scan clock signal may include a square wave periodically having a gate on voltage and a gate off voltage, and the second carry clock signal of the second carry clock line may have a phase that is delayed by as much as the pulse width of the scan clock signal having a gate on voltage, compared to the first carry clock signal of the first carry clock line.

[0023] According to an embodiment, the stage can be configured to output a first carry clock signal of a first carry clock line as a carry signal. The clock control circuit may include a first switching transistor and a second switching transistor connected in series between the scan clock line and a power line configured to provide a constant voltage. The gate electrode of the first switching transistor may be connected to the second carry clock line, and the gate electrode of the second switching transistor may be connected to the first carry clock line.

[0024] According to an embodiment, each of the carry clock signal and the scan clock signal may include a square wave periodically having a gate on voltage and a gate off voltage, the first carry clock signal of the first carry clock line may have the same waveform and phase as the scan clock signal, and the second carry clock signal of the second carry clock line may have a phase that is delayed by as much as the pulse width of the carry clock signal with the gate on voltage compared to the first carry clock signal of the first carry clock line.

[0025] According to one or more embodiments of the present disclosure, an electronic device includes: a processor configured to provide input image data; and a display device configured to display an image based on the input image data, and includes: a display panel including pixels connected to scan lines; a gate driver including a plurality of stages, one of which is configured to provide a carry clock signal of a carry clock line as a carry signal to a subsequent stage among the plurality of stages and, in response to a previous carry signal of a previous stage among the plurality of stages, provide a scan clock signal of a scan clock line as a scan signal to a corresponding scan line among the scan lines; and a clock controller configured to connect the scan clock line to a power line in response to the carry clock signal, the power line being configured to provide a constant voltage.

[0026] However, this disclosure is not limited to the foregoing aspects and features, and the foregoing and additional aspects and features will be set forth in part in the following detailed description with reference to the accompanying drawings, and in part may be apparent from them, or may be learned by practicing one or more of the embodiments given in this disclosure. Attached Figure Description

[0027] The above and other aspects and features of this disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings.

[0028] Figure 1 This is a diagram illustrating a display device according to some embodiments of the present disclosure.

[0029] Figure 2 It is shown that, according to an embodiment Figure 1 A diagram of the display device shown.

[0030] Figure 3 It is shown that, according to an embodiment Figure 1 A diagram of the display device shown.

[0031] Figure 4 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the clock controller in the display device shown.

[0032] Figure 5 It shows Figure 4 The waveform diagram shown illustrates the operation of the clock controller.

[0033] Figure 6 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the gate driver in the display device shown.

[0034] Figure 7 It is shown in Figure 6 The waveform diagram of the signal measured in the gate driver is shown.

[0035] Figure 8 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the clock controller in the display device shown.

[0036] Figure 9 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the clock controller in the display device shown.

[0037] Figure 10 It shows Figure 9 The waveform diagram shown illustrates the operation of the clock controller.

[0038] Figure 11 It is shown in Figure 6 The waveform diagram of the signal measured in the gate driver is shown.

[0039] Figure 12 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the clock controller in the display device shown.

[0040] Figure 13 This is a block diagram illustrating a stage included in a gate driver according to an embodiment.

[0041] Figure 14 It is shown that, according to an embodiment Figure 13 The circuit diagram of the gate driver is shown.

[0042] Figure 15 It shows Figure 14 The waveform diagram shown illustrates the operation of the gate driver.

[0043] Figure 16 It shows Figure 13 The circuit diagram shows a comparative example of the gate driver.

[0044] Figure 17 This is a graph showing the fall time of the scan signal.

[0045] Figure 18 This is a block diagram illustrating a display system according to an embodiment.

[0046] Figures 19 to 22 It is shown that according to some embodiments Figure 18 The image shows a perspective view of an application example of the display system. Detailed Implementation

[0047] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques not essential for a full understanding of the aspects and features of this disclosure by those skilled in the art may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore redundant descriptions may not be repeated.

[0048] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0049] Furthermore, given the whole of this disclosure, as will be understood by those skilled in the art, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of one another or in any suitable combination with one another.

[0050] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. For ease of interpretation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., may be used herein to describe the relationship of one element or feature as shown in the drawings to another (or other) element or feature. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “below” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0051] Furthermore, it should be anticipated that the shapes shown in the accompanying drawings may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the drawings, and should be interpreted to account for shape variations that may occur, for example, due to manufacturing processes. Thus, the shapes shown in the drawings may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0052] In the accompanying figures, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0053] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first portion described below may be designated as a second element, second component, second region, second layer, or second portion.

[0054] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, it can be directly on, directly connected to, or directly bonded to the other element or layer, or there can be one or more intermediary elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected in the presence of one or more intermediary layers, regions, or elements between them. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intermediary elements or layers.

[0055] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an (kind)” are also intended to include the plural forms. It will also be understood that, when used in this specification, the terms “comprising,” “including,” “having,” and variations thereof indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. Expressions such as “at least one (kind) of…” modify the entire list of elements when following a list of elements, without modifying the individual elements in that list. For example, the expressions “at least one of a, b and c” and “at least one of the group consisting of a, b and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0056] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent variations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the term “use” and variations thereof may be considered synonymous with the term “utilize” and variations thereof, respectively.

[0057] Some embodiments are depicted in the accompanying drawings with respect to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by logic circuits, individual components, microprocessors, hardwired circuits, memory elements, wiring connections, and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, software can be used to program and control the blocks, units, and / or modules to perform the various functions discussed in this disclosure, and they can be selectively driven by firmware and / or software. Additionally, each block, each unit, and / or each module can be implemented by dedicated hardware or by a combination of dedicated hardware for performing some functions of the block, unit, and / or module and processors (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions of the block, unit, and / or module. In some embodiments, without departing from the scope of this disclosure, blocks, units, and / or modules can be physically divided into two or more separate blocks, two or more separate units, and / or two or more separate modules. Furthermore, in some embodiments, without departing from the scope of this disclosure, blocks, units, and / or modules may be physically divided into more complex blocks, more complex units, and / or more complex modules.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0059] Figure 1 This is a diagram illustrating a display device according to some embodiments of the present disclosure.

[0060] Reference Figure 1 The display device 100 may include a display panel 110 (e.g., pixel units), a timing controller 120, a data driver 130, a gate driver 140, and a clock controller 150 (e.g., clock control circuitry). These components may be implemented as separate integrated circuits, or two or more of these components may be implemented together and integrated into a single integrated circuit. Additionally, the gate driver 140 may be formed within the display panel 110.

[0061] The display panel 110 may include pixels PX (or subpixels) connected to scan lines SL1, SL2, ..., SL1 and data lines DL1, DL2, ..., DLj, where each of i and j may be a natural number of 3 or greater.

[0062] Pixels PX can be configured with various suitable types of circuits known to those skilled in the art, and the number of scan lines connected to each of the pixels PX can be modified in various ways corresponding to the structure of the pixels PX. Additionally, each of the pixels PX can be additionally connected to an emission control line corresponding to the structure of the pixel PX.

[0063] When a scan signal is supplied to scan lines SL1 to SL1, pixels PX can be selected on a horizontal line basis (e.g., pixels PX connected to each other on the same scan line can be classified as a horizontal line (e.g., a pixel row)). A data signal can be supplied to each of the pixels PX selected by the scan signal from a data line (e.g., any one of data lines DL1 to DLj) connected to the corresponding pixel PX. Pixel PX supplied with a data signal can produce light with a brightness corresponding to the voltage of the data signal.

[0064] Data cables DL1 to DLj can extend in a first direction DR1. The first direction DR1 can be, for example, the direction in which the upper and lower sides of the display panel 110 connect to each other. As another example, the first direction DR1 can be the direction in which the left and right sides of the display panel 110 connect to each other, and is referred to as another direction.

[0065] Scan lines SL1 to SL1 can extend along a second direction DR2. The second direction DR2 can be a direction that intersects or crosses the first direction DR1. The second direction DR2 can be a direction connecting the left and right sides of the display panel 110 to each other. As another example, the second direction DR2 can be a direction connecting the upper and lower sides of the display panel 110 to each other, and is referred to as the other direction.

[0066] The timing controller 120 can receive input data Din and control signal CS from the host system via an interface. As an example, the timing controller 120 can receive input data Din and control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. Various signals, including clock signals, can be included in the control signal CS.

[0067] The timing controller 120 can generate a data drive signal DCS based on the control signal CS, and can supply the generated data drive signal DCS to the data driver 130. The timing controller 120 can readjust the input data Din to suit the specifications of the display device 100. Furthermore, the timing controller 120 can generate output data Dout by correcting the input data Din, and can supply the output data Dout to the data driver 130. In an embodiment, the timing controller 120 can correct the input data Din corresponding to the optical measurement results measured in the manufacturing process.

[0068] The timing controller 120 can provide clock signals CK_CR and CK_SC to the clock lines CKL_CR and CKL_SC for driving the gate driver 140. For example, the timing controller 120 can provide the carry clock signal CK_CR to the carry clock line CKL_CR, and can provide the scan clock signal CK_SC to the scan clock line CKL_SC. Furthermore, the timing controller 120 can provide the scan start signal SSP to the gate driver 140.

[0069] Data driver 130 can receive output data Dout and data drive signal DCS from timing controller 120. Data drive signal DCS may include sampling signals and / or timing signals for driving data driver 130. Data driver 130 can generate a data signal based on data drive signal DCS and output data Dout. In this example, data driver 130 can generate an analog data signal based on the grayscale (e.g., grayscale level or grayscale value) of output data Dout. Data driver 130 can supply the data signal to data lines DL1 to DLj for synchronization with the scan signal.

[0070] Gate driver 140 can receive scan start signal SSP from timing controller 120. Furthermore, gate driver 140 can receive clock signals CK_CR and CK_SC from timing controller 120 via clock lines CKL_CR and CKL_SC. Gate driver 140 can generate scan signals while shifting scan start signal SSP corresponding to clock signals CK_CR and CK_SC, and can sequentially supply scan signals to scan lines SL1 to SL1.

[0071] Gate driver 140 may include multiple stages connected to each of scan lines SL1 to SL1. Stage ST (e.g., see...) Figure 2This stage can be configured as a shift register and can provide the carry clock signal CK_CR as a carry signal to subsequent stages in response to the scan start signal SSP or the carry signal of the previous stage. Stage ST can provide the scan clock signal CK_SC as a scan signal to the scan lines connected to stage ST (e.g., any one of SL1 to SL1).

[0072] When a scan signal is supplied, a gate on-state voltage can be supplied to scan lines SL1 to SL1, and the transistors supplied with the scan signal are turned on under this voltage. Conversely, when no scan signal is supplied (e.g., supply is paused), a gate off-state voltage can be supplied to scan lines SL1 to SL1, and the transistors are turned off under this voltage. As an example, a low-level scan signal can be supplied to a P-type transistor, and a high-level scan signal can be supplied to an N-type transistor. In the following description, for ease of explanation, it can be described as a scan signal supplied with a high-level voltage.

[0073] In one embodiment, the gate driver 140 may be a separate integrated circuit (IC) in the display device 100. In another embodiment, the gate driver 140 may be formed together with the pixel PX during the process of forming the display panel 110. For example, the gate driver 140 may be formed in an oxide semiconductor thin-film transistor gate driver circuit (OSG) or an amorphous silicon thin-film transistor gate driver circuit (ASG) in the display panel 110.

[0074] Clock controller 150 can be connected to clock lines CKL_CR and CKL_SC, and power line PL (e.g., low power line). A constant or substantially constant voltage (e.g., low voltage VSS) can be applied to power line PL. Clock controller 150 can pull down or reset scan clock signal CK_SC to low voltage VSS in response to carry clock signal CK_CR. For example, clock controller 150 can connect scan clock line CKL_SC to power line PL in response to carry clock signal CK_CR. As described in more detail below, when a delay (e.g., RC delay) occurs in the scan signal, some parts of the scan signal may overlap each other due to the delay, data signals may not be accurately written to pixel PX, and display quality may degrade. Therefore, clock controller 150 can use carry clock signal CK_CR to pull down scan clock signal CK_SC, thereby shortening the fall time of scan clock signal CK_SC and scan signal, and reducing, minimizing, or preventing overlap of scan signals. References will follow below. Figures 4 to 12 The configuration and operation of the clock controller 150 are described in more detail.

[0075] In one embodiment, the clock controller 150 may be formed together with the pixels PX during the process of forming the display panel 110. However, this disclosure is not limited thereto.

[0076] In embodiments, the display device 100 may include a flat or substantially flat display device, a curved display device in which a portion of the display panel 110 is bent, a flexible display device in which a portion of the display panel 110 can be folded or rolled up, and a stretchable display device in which a portion of the display panel 110 can be stretched / contracted.

[0077] In embodiments, the display device 100 is a means of displaying moving images and / or still images, and may be included or implemented in a variety of suitable portable electronic devices, such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, portable multimedia players (PMPs), navigation systems, and ultra-mobile computers (UMPCs). In embodiments of this disclosure, the display device 100 may be included or implemented in a variety of suitable electronic devices, such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices.

[0078] As described above, the clock controller 150 uses the carry clock signal CK_CR to pull down the scan clock signal CK_SC, thereby shortening the fall time of each of the scan clock signal CK_SC and the scan signal.

[0079] Figure 2 It is shown that, according to an embodiment Figure 1 A diagram of the display device shown. Figure 3 It is shown that, according to an embodiment Figure 1 The diagram shows the display device. See below for reference. Figure 2 and Figure 3 Some other embodiments describing the arrangement of the clock controller 150.

[0080] Reference Figures 1 to 3 The display panel 110 may include a substrate SUB and pixels PX.

[0081] The substrate SUB may include a transparent insulating material to allow light to pass through it. The substrate SUB may be a rigid substrate or a flexible substrate.

[0082] The rigid substrate can be one of the following: glass substrate, quartz substrate, glass-ceramic substrate, and crystalline glass substrate.

[0083] The flexible substrate can be one of a membrane substrate comprising a polymeric organic material and a plastic substrate. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, this disclosure is not limited thereto.

[0084] One area of ​​the base SUB can be set as a display area DA with pixels PX, and another area of ​​the base SUB can be set as a non-display area NDA.

[0085] Line portions, pad portions (or "soldering pads") of the PX (e.g., pads) and / or built-in circuitry that can be used to drive the PX can be located in the non-display area NDA.

[0086] Clock lines CKL_CR and CKL_SC can be set in the non-display area NDA and can extend in the first direction DR1 from a first side (e.g., the lower side) of the display panel 110 where the pad PDP is located to a second side (e.g., the upper side) opposite the first side.

[0087] The gate driver 140 may be disposed in a first region A1, which is located on one side (e.g., the left side) of the display region DA in the second direction DR2.

[0088] In one embodiment, the clock controller 150 may be positioned adjacent to a second side of the display panel 110 in the first direction DR1. Reference will be made below. Figure 2 The example is described in more detail. The clock controller 150 may be located in a second region A2 positioned adjacent to the second side of the display panel 110 in the first direction DR1. Because the clock controller 150 is located in the second region A2, separated from the pad PDP, delays may occur more frequently in the clock signal as the clock signal moves further away from the pad PDP. However, this disclosure is not limited thereto. For example, the clock controller 150 may be connected to another portion (e.g., the middle portion) of each of the clock lines CKL_CR and CKL_SC, rather than to the ends of each of the clock lines CKL_CR and CKL_SC.

[0089] In an embodiment, the clock controller 150 may be disposed in a first region A1 in which the gate driver 140 is disposed, or may be included in the gate driver 140.

[0090] The following will refer to Figure 3A more detailed description of the example follows. Gate driver 140 may include a stage ST and a dummy stage ST_D, and clock controller 150 may be located in a third region A3 adjacent to the dummy stage ST_D. Stage ST may be connected to the carry clock line CKL_CR, the scan clock line CKL_SC, and the scan line SL. Dummy stage ST_D may be connected to the carry clock line CKL_CR, but may not be connected to the scan clock line CKL_SC and the scan line SL. Dummy stage ST_D may be set in gate driver 140 to receive the carry signal (e.g., see...). Figure 14 The dummy stage ST_D is provided to the previous stage (e.g., the last stage) and may not include some components for outputting the scan signal. Therefore, a third region A3 corresponding to the location where some components will be included may exist on one side of the dummy stage ST_D, and the clock controller 150 may be set in the third region A3.

[0091] The pad PDP can be positioned adjacent to one side (e.g., the lower side) of the display panel 110 in the first direction DR1, and can provide data signals to data lines DL1 to DLj, and can provide clock signals to clock lines CKL_CR and CKL_SC.

[0092] The circuit board FPCB can be connected to the display panel 110 via the pad PDP. The circuit board FPCB can be a flexible circuit board, but this disclosure is not limited thereto.

[0093] The circuit board FPCB can process various signals input from the printed circuit board and can output the processed signals toward the display panel 110. One end of the circuit board FPCB can be attached to the display panel 110, and the opposite end of the circuit board FPCB can be attached to the printed circuit board. The circuit board FPCB can be connected to each of the display panel 110 and the printed circuit board via conductive adhesive members (e.g., anisotropic conductive film).

[0094] The driver DIC can be mounted on a circuit board (FPCB). The driver DIC can be, for example, an integrated circuit (IC). The driver DIC may include a data driver 130.

[0095] As described above, in some embodiments, the clock controller 150 may be positioned adjacent to the other end of the clock lines CKL_CR and CKL_SC. Furthermore, the clock controller 150 may be included in the gate driver 140 and positioned adjacent to the dummy level ST_D.

[0096] Figure 4 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the clock controller in the display device shown. Figure 5 It shows Figure 4 The waveform diagram shown illustrates the operation of the clock controller.

[0097] Reference Figure 4 and Figure 5 The clock controller 150 may include a first switching transistor M1 (e.g., a pull-down buffer) connected between the Nth scan clock line CKL_SC[N] and the power line PL. The first switching transistor M1 may include a gate electrode connected to the N+Xth carry clock line CKL_CR[N+X]. Here, each of N and X may be a natural number of 1 or greater.

[0098] In an embodiment, the first switching transistor M1 may include an oxide semiconductor. This can reduce leakage current through the first switching transistor M1. The first switching transistor M1 may be an N-type transistor, but this disclosure is not limited thereto.

[0099] The Nth carry clock signal CK_CR[N] can be provided to the Nth carry clock line CKL_CR[N], the N+X carry clock signal CK_CR[N+X] can be provided to the N+X carry clock line CKL_CR[N+X] (e.g., the second carry clock line), and the Nth scan clock signal CK_SC[N] can be provided to the Nth scan clock line CKL_SC[N] (e.g., the first scan clock line). Each of the Nth carry clock signal CK_CR[N], the N+X carry clock signal CK_CR[N+X], and the Nth scan clock signal CK_SC[N] can be a square wave cyclically having a high level VGH (e.g., gate on-voltage) and a low level VGL (e.g., gate off-voltage). The N+X carry clock signal CK_CR[N+x] can have a phase that is delayed from the Nth carry clock signal CK_CR[N] by the width of the pulse with a high level VGH (e.g., gate on-voltage). For example, at the time point when the Nth carry clock signal CK_CR[N] changes from high level VGH to low level VGL, the N+Xth carry clock signal CK_CR[N+X] can change from low level VGL to high level VGH. The Nth carry clock signal CK_CR[N] and the Nth scan clock signal CK_SC[N] can have the same waveform and the same phase. The Nth carry clock signal CK_CR[N] and the Nth scan clock signal CK_SC[N] can be provided to the same level ST (e.g., see...). Figure 2 and Figure 3 ), and the ST stage can use the Nth carry clock signal CK_CR[N] as the Nth carry signal CR[N] (see Figure 15 The signal can be output to the Nth carry clock line CKL_CR[N], and the Nth scan clock signal CK_SC[N] can be output as the Nth scan signal SC[N] to the Nth scan line SL[N].

[0100] At the point where the Nth scan clock signal CK_SC[N] changes from high level VGH to low level VGL, the (N+X)th carry clock signal CK_CR[N+X] can change from low level VGL to high level VGH, and the first switching transistor M1 can connect the Nth scan clock line CKL_SC[N] to the power line PL in response to the (N+X)th carry clock signal CK_CR[N+X], thereby pulling the Nth scan clock signal CK_SC[N] down to the low voltage VSS of the power line PL. The voltage level of the low voltage VSS can be equal to or substantially equal to the low level VGL (e.g., the gate cutoff voltage). For example, the gate cutoff voltage can be applied to the power line PL. Therefore, the Nth scan clock signal CK_SC[N] can become connected to the gate cutoff voltage more quickly. In other words, the fall time T_F of the Nth scan clock signal CK_SC[N] can be shortened.

[0101] As described above, the clock controller 150 pulls down the Nth scan clock signal CK_SC[N] in response to the N+X carry clock signal CK_CR[N+X], thereby shortening the fall time of each of the Nth scan clock signal CK_SC[N] and the Nth scan signal SC[N].

[0102] Figure 6 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the gate driver in the display device shown. Figure 7 It is shown in Figure 6 The waveform diagram of the signal measured in the gate driver is shown. Figure 8 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the clock controller in the display device shown.

[0103] Reference Figures 6 to 8 The gate driver 140 may include stages ST1, ST2, ST3, ST4, ST5, ST6, ST7, ST8, ...

[0104] Each of stages ST1 to ST8 can be connected to the corresponding carry clock line among carry clock lines CKL_CR1 to CKL_CR6, the corresponding scan clock line among scan clock lines CKL_SC1 to CKL_SC6, and the corresponding scan line among scan lines SL1 to SL8, and is arranged along the first direction DR1. Each of stages ST1 to ST8 can output a carry signal and a scan signal in response to a scan start signal or a carry signal from a previous stage (e.g., a previous carry signal).

[0105] Carry clock lines CKL_CR1 to CKL_CR6 can extend along the first direction DR1 and can be arranged along the second direction DR2. Carry clock lines CKL_CR1 to CKL_CR6 can include a first carry clock line CKL_CR1 to which a first carry clock signal CK_CR1 is provided, a second carry clock line CKL_CR2 to which a second carry clock signal CK_CR2 is provided, a third carry clock line CKL_CR3 to which a third carry clock signal CK_CR3 is provided, a fourth carry clock line CKL_CR4 to which a fourth carry clock signal CK_CR4 is provided, a fifth carry clock line CKL_CR5 to which a fifth carry clock signal CK_CR5 is provided, and a sixth carry clock line CKL_CR6 to which a sixth carry clock signal CK_CR6 is provided. For example... Figure 7 As shown, carry clock signals CK_CR1 to CK_CR6 can have the same or substantially the same waveform. For example, carry clock signals CK_CR1 to CK_CR6 can be square waves with a high level (e.g., gate on voltage) during 1 / 3 of the cycle and a low level (e.g., gate off voltage) during 2 / 3 of the cycle. Adjacent carry clock signals among CK_CR1 to CK_CR6 can have a 60-degree phase difference (e.g., 1 / 6 of the cycle). For example, the second carry clock signal CK_CR2 can have a phase delay of 60 degrees from the first carry clock signal CK_CR1, and the third carry clock signal CK_CR3 can have a phase delay of 60 degrees from the second carry clock signal CK_CR2.

[0106] Scan clock lines CKL_SC1 to CKL_SC6 can extend along the first direction DR1 and can be arranged along the second direction DR2. Scan clock lines CKL_SC1 to CKL_SC6 may include a first scan clock line CKL_SC1 to which a first scan clock signal CK_SC1 is provided, a second scan clock line CKL_SC2 to which a second scan clock signal CK_SC2 is provided, a third scan clock line CKL_SC3 to which a third scan clock signal CK_SC3 is provided, a fourth scan clock line CKL_SC4 to which a fourth scan clock signal CK_SC4 is provided, a fifth scan clock line CKL_SC5 to which a fifth scan clock signal CK_SC5 is provided, and a sixth scan clock line CKL_SC6 to which a sixth scan clock signal CK_SC6 is provided. Figure 7As shown, the scan clock signals CK_SC1 to CK_SC6 can correspond to the carry clock signals CK_CR1 to CK_CR6, respectively. For example, the first scan clock signal CK_SC1 can have the same waveform and phase as the first carry clock signal CK_CR1, and the second scan clock signal CK_SC2 can have the same waveform and phase as the second carry clock signal CK_CR2.

[0107] The first stage ST1 can be connected to the first carry clock line CKL_CR1, the first scan clock line CKL_SC1, and the first scan line SL1. In response to the first scan start signal SSP1, the first stage ST1 can output the first carry clock signal CK_CR1 of the first carry clock line CKL_CR1 as the first carry signal CR1, and can output the first scan clock signal CK_SC1 of the first scan clock line CKL_SC1 as the first scan signal SC1 to the first scan line SL1. Furthermore, in response to the fifth carry signal CR5, the output of the first scan signal SC1 can be paused.

[0108] The second stage ST2 can be connected to the second carry clock line CKL_CR2, the second scan clock line CKL_SC2, and the second scan line SL2. In response to the second scan start signal SSP2, the second stage ST2 can output the second carry clock signal CK_CR2 of the second carry clock line CKL_CR2 as the second carry signal CR2, and can output the second scan clock signal CK_SC2 of the second scan clock line CKL_SC2 as the second scan signal SC2 to the second scan line SL2. Furthermore, in response to the sixth carry signal CR6, the output of the second scan signal SC2 can be paused.

[0109] The third stage ST3 can be connected to the third carry clock line CKL_CR3, the third scan clock line CKL_SC3, and the third scan line SL3. In response to the third scan start signal SSP3, the third stage ST3 can output the third carry clock signal CKL_CR3 as the third carry signal CR3, and can output the third scan clock signal CKL_SC3 as the third scan signal SC3 to the third scan line SL3. Furthermore, in response to the seventh carry signal CR7, the output of the third scan signal SC3 can be paused.

[0110] The fourth stage ST4 can be connected to the fourth carry clock line CKL_CR4, the fourth scan clock line CKL_SC4, and the fourth scan line SL4. In response to the fourth scan start signal SSP4, the fourth stage ST4 can output the fourth carry clock signal CKL_CR4 as the fourth carry signal CR4, and can output the fourth scan clock signal CKL_SC4 as the fourth scan signal SC4 to the fourth scan line SL4. Furthermore, in response to the eighth carry signal CR8, the output of the fourth scan signal SC4 can be paused.

[0111] The fifth stage ST5 can be connected to the fifth carry clock line CKL_CR5, the fifth scan clock line CKL_SC5, and the fifth scan line SL5. In response to the first carry signal CR1, the fifth carry clock line CKL_CR5 can output its fifth carry clock signal CK_CR5 as the fifth carry signal CR5. It can also output the fifth scan clock signal CK_SC5 from the fifth scan clock line CKL_SC5 as the fifth scan signal SC5 to the fifth scan line SL5. Furthermore, in response to the ninth carry signal CR9, the output of the fifth scan signal SC5 can be paused.

[0112] The sixth stage ST6 can be connected to the sixth carry clock line CKL_CR6, the sixth scan clock line CKL_SC6, and the sixth scan line SL6. The sixth stage ST6 can respond to the second carry signal CR2 by outputting the sixth carry clock signal CKL_CR6 as the sixth carry signal CR6, and can output the sixth scan clock signal CKL_SC6 as the sixth scan signal SC6 to the sixth scan line SL6. Furthermore, it can pause the output of the sixth scan signal SC6 in response to the tenth carry signal CR10.

[0113] The seventh stage ST7 can be connected to the first carry clock line CKL_CR1, the first scan clock line CKL_SC1, and the seventh scan line SL7. In response to the third carry signal CR3, the seventh stage ST7 can output the first carry clock signal CK_CR1 of the first carry clock line CKL_CR1 as the seventh carry signal CR7. It can also output the first scan clock signal CK_SC1 of the first scan clock line CKL_SC1 as the seventh scan signal SC7 to the seventh scan line SL7. Furthermore, in response to the eleventh carry signal CR11, it can pause the output of the seventh scan signal SC7.

[0114] The eighth stage ST8 can be connected to the second carry clock line CKL_CR2, the second scan clock line CKL_SC2, and the eighth scan line SL8. The eighth stage ST8 can respond to the fourth carry signal CR4 by outputting the second carry clock signal CK_CR2 of the second carry clock line CKL_CR2 as the eighth carry signal CR8, and can output the second scan clock signal CK_SC2 of the second scan clock line CKL_SC2 as the eighth scan signal SC8 to the eighth scan line SL8. Furthermore, it can pause the output of the eighth scan signal SC8 in response to the twelfth carry signal CR12.

[0115] The clock controller 150 may include switching transistors M11 to M16 (e.g., a first switching transistor).

[0116] The eleventh switching transistor M11 can be connected between the first scan clock line CKL_SC1 and the power line PL, and the gate electrode of the eleventh switching transistor M11 can be connected to the third carry clock line CKL_CR3. (Refer to...) Figure 7 At the point where the first scan clock signal CK_SC1 changes from high to low, the eleventh switching transistor M11 can pull the first scan clock signal CK_SC1 down to a low voltage VSS (e.g., gate cutoff voltage) in response to the high-level third carry clock signal CK_CR3. Therefore, the fall time of the first scan clock signal CK_SC1 can be shortened, and the fall time of the corresponding first scan signal SC1 can also be shortened.

[0117] The twelfth switching transistor M12 can be connected between the second scan clock line CKL_SC2 and the power line PL, and the gate electrode of the twelfth switching transistor M12 can be connected to the fourth carry clock line CKL_CR4. The twelfth switching transistor M12 can pull down the second scan clock signal CK_SC2 in response to the fourth carry clock signal CK_CR4 having a high level.

[0118] The thirteenth switching transistor M13 can be connected between the third scan clock line CKL_SC3 and the power line PL, and its gate electrode can be connected to the fifth carry clock line CKL_CR5. The fourteenth switching transistor M14 can be connected between the fourth scan clock line CKL_SC4 and the power line PL, and its gate electrode can be connected to the sixth carry clock line CKL_CR6. The fifteenth switching transistor M15 can be connected between the fifth scan clock line CKL_SC5 and the power line PL, and its gate electrode can be connected to the first carry clock line CKL_CR1. The sixteenth switching transistor M16 can be connected between the sixth scan clock line CKL_SC6 and the power line PL, and its gate electrode can be connected to the second carry clock line CKL_CR2. Each of the thirteenth, fourteenth, fifteenth, and sixteenth switching transistors M13 can pull down the corresponding scan clock signal in response to the corresponding carry clock signal.

[0119] exist Figures 6 to 8 In this embodiment, gate driver 140 uses six carry clock signals CK_CR1 to CK_CR6 and six scan clock signals CK_SC1 to CK_SC6, and clock controller 150 includes six switching transistors M11 to M16. However, this disclosure is not limited thereto. For example, the number of scan clock signals (and corresponding carry clock signals) used in gate driver 140 can be two to five or seven or more. Corresponding to the number of scan clock signals, the number of switching transistors included in clock controller 150 can be two to five or seven or more.

[0120] Figure 9 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the clock controller in the display device shown. Figure 10 It shows Figure 9 The waveform diagram shown illustrates the operation of the clock controller.

[0121] Reference Figure 4 , Figure 5 , Figure 9 and Figure 10 In addition to potentially including a second switching transistor M2, the clock controller 150_1 can be the same as or substantially the same as (or similar to) the clock controller 150 described above. Furthermore, Figure 10 The waveform shown can be compared with the one above. Figure 5 The waveforms described are the same or substantially the same (or similar). Therefore, redundant descriptions can be avoided in the following text, and the differences can be described in more detail.

[0122] The clock controller 150_1 may include a first switching transistor M1 and a second switching transistor M2 connected between the Nth scan clock line CKL_SC[N] and the power line PL. The gate electrode of the first switching transistor M1 may be connected to the N+Xth carry clock line CKL_CR[N+X], and the gate electrode of the second switching transistor M2 may be connected to the Nth carry clock line CKL_CR[N]. The first switching transistor M1 and the second switching transistor M2 may form a pull-down buffer.

[0123] When both the N+X carry clock signal CK_CR[N+X] of the N+X carry clock line CKL_CR[N] and the Nth carry clock signal CK_CR[N] of the Nth carry clock line CKL_CR[N] have a high level VGH, the first switching transistor M1 and the second switching transistor M2 can connect the Nth scan clock line CKL_SC[N] to the power line PL, and can pull down the Nth scan clock signal CK_SC[N] to the low voltage VSS of the power line PL.

[0124] Ideally, the N+X carry clock signal CK_CR[N+X] and the N carry clock signal CK_CR[N] should not overlap with each other without delay. However, the clock controller 150 can use the overlap of the N+X carry clock signal CK_CR[N+X] and the N carry clock signal CK_CR[N], which may occur due to delay, to pull down the Nth scan clock signal CK_SC[N].

[0125] During the first time period P1, the Nth scan clock signal CK_SC[N] can change from high level VGH to low level VGL, and the N+X carry clock signal CK_CR[N+X] can change from low level VGL to high level VGH. In other words, during the first time period P1, the Nth scan clock signal CK_SC[N] and the N+X carry clock signal CK_CR[N+X] can be superimposed on each other, and the Nth scan clock signal CK_SC[N] and the N+X carry clock signal CK_CR[N+X] can concurrently (e.g., simultaneously or substantially simultaneously) have a high level VGH.

[0126] During the first time period P1, the first switching transistor M1 and the second switching transistor M2 can connect the Nth scan clock line CKL_SC[N] to the power line PL, and can pull the Nth scan clock signal CK_SC[N] down to the low voltage VSS of the power line PL. For example, the voltage level of the low voltage VSS can be lower than or equal to the low level VGL (e.g., the gate cutoff voltage). The Nth scan clock signal CK_SC[N] (and the Nth scan signal SC[N]) can be faster (e.g., with...) Figure 5Compared to the embodiment shown, it becomes to have a gate cutoff voltage. In some embodiments, because the voltage level of the low voltage VSS is lower than the low level VGL, an undershoot can occur in the first time period P1 in which the voltage level of the Nth scan clock signal CK_SC[N] (and the Nth scan signal SC[N]) becomes lower than the low level VGL.

[0127] As described above, the clock controller 150_1 can pull down the Nth scan clock signal CK_SC[N] in response to the N+X carry clock signal CK_CR[N+X] and the Nth carry clock signal CK_CR[N], thereby further shortening the fall time of each of the Nth scan clock signal CK_SC[N] and the Nth scan signal SC[N].

[0128] Figure 11 It is shown in Figure 6 The waveform diagram of the signal measured in the gate driver is shown. Figure 12 It is shown that, according to the embodiments, it includes Figure 1 A diagram of the clock controller in the display device shown.

[0129] Reference Figures 6 to 8 , Figure 11 and Figure 12 In addition to including switching transistors M21 to M26, Figure 12 The clock controller 150_1 shown can be compared with the one referenced above. Figure 8 The clock controller 150 described is the same as or substantially the same as (or similar to) the clock controller described. Additionally, Figure 11 The waveforms of the clock signals CK_CR1 to CK_CR6 and CK_SC1 to CK_SC6 shown can be compared with those above. Figure 7 The waveforms of the clock signals CK_CR1 to CK_CR6 and CK_SC1 to CK_SC6 are the same or substantially the same (or similar). Therefore, redundant descriptions will not be repeated in the following text, and the differences will be described in more detail.

[0130] The clock controller 150_1 may also include switching transistors M21 to M26 (e.g., a second switching transistor).

[0131] The 21st switching transistor M21 can be connected between the first scan clock line CKL_SC1 and the power line PL, and the gate electrode of the 21st switching transistor M21 can be connected to the first carry clock line CKL_CR1. During the first time period P1, the first carry clock signal CK_CR1 and the third carry clock signal CK_CR3 can be at a high level, and the 21st switching transistor M21 and the 11th switching transistor M11 can pull the first scan clock signal CK_SC1 down to a low voltage VSS (e.g., the gate cutoff voltage).

[0132] The 22nd switching transistor M22 can be connected between the second scan clock line CKL_SC2 and the power line PL, and the gate electrode of the 22nd switching transistor M22 can be connected to the second carry clock line CKL_CR2. During the second time period P2, the 22nd switching transistor M22 and the 12th switching transistor M12 can pull down the second scan clock signal CK_SC2.

[0133] The 23rd switching transistor M23 can be connected between the third scan clock line CKL_SC3 and the power line PL, and the gate electrode of the 23rd switching transistor M23 can be connected to the third carry clock line CKL_CR3. During the third time period P3, the 23rd switching transistor M23 and the 13th switching transistor M13 can pull down the third scan clock signal CK_SC3.

[0134] The 24th switching transistor M24 can be connected between the fourth scan clock line CKL_SC4 and the power line PL, and the gate electrode of the 24th switching transistor M24 can be connected to the fourth carry clock line CKL_CR4. In the fourth time period P4, the 24th switching transistor M24 and the 14th switching transistor M14 can pull down the fourth scan clock signal CK_SC4.

[0135] The 25th switching transistor M25 can be connected to the fifth scan clock line CKL_SC5 and the power line PL, and the gate electrode of the 25th switching transistor M25 can be connected to the fifth carry clock line CKL_CR5. In the fifth period P5, the 25th switching transistor M25 and the 15th switching transistor M15 can pull down the fifth scan clock signal CK_SC5.

[0136] The 26th switching transistor M26 can be connected between the sixth scan clock line CKL_SC6 and the power line PL, and the gate electrode of the 26th switching transistor M26 can be connected to the sixth carry clock line CKL_CR6. In the sixth time period P6, the 26th switching transistor M26 and the 16th switching transistor M16 can pull down the sixth scan clock signal CK_SC6.

[0137] Figure 13 This is a block diagram illustrating a stage included in a gate driver according to an embodiment. Figure 14 It is shown that, according to an embodiment Figure 13 The circuit diagram of the gate driver is shown. Figure 15 It shows Figure 14 The waveform diagram shown illustrates the operation of the gate driver.

[0138] Reference Figures 1 to 3 , Figure 13 and Figure 14 This includes stages in the gate driver 140 (e.g., Figure 6 The levels ST1 to ST8 shown may be the same as or substantially the same as each other (or similar), therefore, the levels ST in the multiple levels will be described in more detail below as representative examples.

[0139] A level ST may include a sensing block SB, a pull-up logic block PULB, a pull-up block PUB (e.g., a pull-up buffer), a pull-down logic block PDLB, and a pull-down block PDB (e.g., a pull-down buffer).

[0140] The sensing block SB can provide a gate on-voltage to the Q node (e.g., the first control node) in response to the sensing selection signal SSS. In some embodiments, the sensing block SB can be omitted as needed or desired.

[0141] The pull-up logic block PULB can control the voltage of the Q node in response to a previous carry signal (e.g., the NXth carry signal CR[NX]). Here, N can be a natural number of 1 or greater, and is a natural number greater than X. Further reference will follow below. Figure 14 A more detailed description of the example. In this example, X can be 4. The pull-up block PUB can pull the output of stage ST high (e.g., gate on-voltage). For example, the pull-up block PUB can output the Nth carry clock signal CK_CR[N] as the Nth carry signal CR[N], and can output the Nth scan clock signal CK_SC[N] as the Nth scan signal SC[N].

[0142] The pull-down logic block PDLB can control the voltage of the QB node (e.g., the second control node) in response to a subsequent carry signal (e.g., the N+Xth carry signal CR[N+X]). The pull-down block PDB can also pull the output of stage ST low (e.g., the gate cutoff voltage) in response to the voltage of the QB node. For example, the pull-down block PDB can pull the Nth carry signal CR[N] down to a second low voltage VSS2 and can pull the Nth scan signal SC[N] down to a first low voltage VSS1.

[0143] The Nth level ST[N], located on the Nth horizontal line or connected to the Nth scan line, may include transistors T1 to T14 and a first capacitor C1.

[0144] The first transistor T1 may be diode-connected between the first carry input terminal (e.g., the previous carry line) to which the NX carry signal CR[NX] is provided and the Q node. The first transistor T1 may include a first electrode connected to the first carry input terminal, a second electrode connected to the Q node, and a gate electrode connected to the first carry input terminal. The first transistor T1 may be included in a pull-up logic block PULB.

[0145] In an embodiment, the first transistor T1 may include a first-1 transistor T1-1 and a first-2 transistor T1-2 connected in series between the first carry input terminal and the Q node. The first electrode of the first-1 transistor T1-1 and the second electrode of the first-2 transistor T1-2 may be connected to the first node N1. In other words, the first transistor T1 may be implemented as a dual-gate transistor.

[0146] The second transistor T2 may include a first electrode connected to a carry clock terminal (e.g., a carry clock line) to which the Nth carry clock signal CK_CR[N] is provided, a second electrode connected to a first output terminal (e.g., a carry line) for outputting the Nth carry signal CR[N], and a gate electrode connected to the Q node.

[0147] The third transistor T3 may include a first electrode connected to a first output terminal, a second electrode connected to a second power input terminal (e.g., a second low power line) supplied to it by a second low voltage VSS2, and a gate electrode connected to a QB node. The voltage level of the second low voltage VSS2 may be higher than the voltage level of the first low voltage VSS1, but this disclosure is not limited thereto.

[0148] The fourth transistor T4 may include a first electrode connected to a scan clock terminal (e.g., a scan clock line) to which the Nth scan clock signal CK_SC[N] is provided, a second electrode connected to a second output terminal (e.g., a scan line) for outputting the Nth scan signal SC[N], and a gate electrode connected to the Q node.

[0149] The first capacitor C1 can be connected between the gate electrode of the fourth transistor T4 and the second output terminal.

[0150] The fifth transistor T5 may include a first electrode connected to the second output terminal, a second electrode connected to the first power input terminal (e.g., the first low power line) provided to it by the first low voltage VSS1, and a gate electrode connected to the QB node.

[0151] The second transistor T2, the fourth transistor T4, and the first capacitor C1 may be included in the pull-up block PUB, and the third transistor T3 and the fifth transistor T5 may be included in the pull-down block PDB.

[0152] The sixth transistor T6 may include a first electrode connected to the Q node, a second electrode connected to the second low-power terminal, and a gate electrode connected to the second carry input terminal (e.g., a subsequent carry line) to which the N+X carry signal CR[N+X] is applied.

[0153] In an embodiment, the sixth transistor T6 may include a 6-1 transistor T6-1 and a 6-2 transistor T6-2 connected in series between the Q node and the second low-power terminal. The second electrode of the 6-1 transistor T6-1 and the first electrode of the 6-2 transistor T6-2 may be connected to the first node N1.

[0154] The seventh transistor T7 can be diode-connected between a first control terminal (e.g., a first scan control line) to which the first scan control signal S1 is provided and the second node N2. The seventh transistor T7 may include a first electrode connected to the first control terminal, a second electrode connected to the second node N2, and a gate electrode connected to the first control terminal. The first scan control signal S1 may have a gate on-state voltage.

[0155] In an embodiment, the seventh transistor T7 may include a 7-1 transistor T7-1 and a 7-2 transistor T7-2 connected in series between the first control terminal and the second node N2.

[0156] The eighth transistor T8 may include a first electrode connected to the first control terminal, a second electrode connected to the QB node, and a gate electrode connected to the second node N2.

[0157] The ninth transistor T9 may include a first electrode connected to the second node N2, a second electrode connected to a third power input terminal (e.g., a third low power line) supplied to it by a third low voltage VSS3, and a gate electrode connected to the Q node. The voltage level of the third low voltage VSS3 may be equal to or substantially equal to the voltage level of the first low voltage VSS1, but this disclosure is not limited thereto.

[0158] The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be included in the pull-down logic block PDLB.

[0159] The tenth transistor T10 may include a first electrode connected to the second power input terminal, a second electrode connected to the QB node, and a gate electrode connected to the Q node.

[0160] The eleventh transistor T11 may include a first electrode connected to the Q node, a second electrode connected to the second power input terminal, and a gate electrode connected to the QB node. In an embodiment, the eleventh transistor T11 may include a 11-1 transistor T11-1 and a 11-2 transistor T11-2 connected in series between the Q node and the second power input terminal. The second electrode of the 11-1 transistor T11-1 and the first electrode of the 11-2 transistor T11-2 may be connected to the first node N1.

[0161] The twelfth transistor T12 may include a first electrode connected to a second power input terminal, a second electrode connected to a QB node, and a gate electrode connected to a first carry input terminal.

[0162] The thirteenth transistor T13 may include a first electrode connected to the Q node, a second electrode connected to the second power input terminal, and a gate electrode connected to the reset terminal to which the scan start signal SSP is provided. In an embodiment, the thirteenth transistor T13 may include a 13-1 transistor T13-1 and a 13-2 transistor T13-2 connected in series between the Q node and the second power input terminal. The second electrode of the 13-1 transistor T13-1 and the first electrode of the 13-2 transistor T13-2 may be connected to the first node N1.

[0163] The fourteenth transistor T14 may include a first electrode connected to a second control terminal (e.g., a second scan control line) to which the second scan control signal S2 is provided, a second electrode connected to a first node N1, and a gate electrode connected to a Q node. When the second scan control signal S2 has a gate on-state voltage, the fourteenth transistor T14 may provide a gate on-state voltage to the first node N1 in response to the voltage of the Q node, and the leakage current of the transistor connected to the first node N1 may be reduced. In an embodiment, the fourteenth transistor T14 may include a 14-1 transistor T14-1 and a 14-2 transistor T14-2 connected in series between the second control terminal and the first node N1.

[0164] In some embodiments, the Nth stage ST[N] may also include a fifteenth transistor T15, a sixteenth transistor T16, and a second capacitor C2.

[0165] The fifteenth transistor T15 may include a first electrode connected to a sensing clock terminal (e.g., a sensing clock line) to which the Nth sensing clock signal CK_SS[N] is provided, a second electrode connected to a third output terminal (e.g., a sensing line) for outputting the Nth sensing signal SS[N], and a gate electrode connected to the Q node.

[0166] The second capacitor C2 can be connected between the gate electrode of the fifteenth transistor T15 and the third output terminal.

[0167] The sixteenth transistor T16 may include a first electrode connected to a third output terminal, a second electrode connected to a first power input terminal supplied to it by a first low voltage VSS1, and a gate electrode connected to a QB node.

[0168] Each of transistors T1 to T16 may comprise silicon semiconductor and may be an N-type transistor. However, this disclosure is not limited thereto.

[0169] Reference Figure 15 At the first time point TP1, the NX carry signal CR[NX] can be high. The first transistor T1 can be turned on, and the high-level NX carry signal CR[NX] can be provided to the Q node, and the voltage of the Q node can change from low to high. The second transistor T2 and the fourth transistor T4 can be turned on in response to the voltage of the Q node. However, because the Nth carry clock signal CK_CR[N] is low, the Nth carry signal CR[N] can also be low. Because the Nth scan clock signal CK_SC[N] is low, the Nth scan signal SC[N] can also be low. In addition, when the tenth transistor T10 is turned on in response to the voltage of the Q node, the second low voltage VSS2 can be provided to the QB node, and the voltage of the QB node can change from high to low.

[0170] At the second time point TP2, the Nth carry clock signal CK_CR[N] and the Nth scan clock signal CK_SC[N] can be at a high level. Each of the Nth carry signal CR[N] and the Nth scan signal SC[N] can change from low to high. Because the first capacitor C1 can bootstrap the Q node based on the Nth scan signal SC[N], the voltage of the Q node can increase to a level higher than high. The Nth carry signal CR[N] and the Nth scan signal SC[N] can change to high level more quickly.

[0171] At the third time point TP3, the Nth carry clock signal CK_CR[N] and the Nth scan clock signal CK_SC[N] can be at a low level. Each of the Nth carry signal CR[N] and the Nth scan signal SC[N] can change from a high level to a low level.

[0172] However, when only the Nth scan clock signal CK_SC[N] is used to pull down the Nth scan signal SC[N] due to the load provided to its scan line by the Nth scan signal SC[N], the fall time of the Nth scan signal SC[N] may be prolonged. (Refer to the above...) Figures 4 to 12 As described, in some embodiments, the clock controller 150 pulls down the Nth scan clock signal CK_SC[N], so the fall time of the Nth scan signal SC[N] can be shortened.

[0173] At the fourth time point TP4, the sixth transistor T6 can be turned on in response to the N+X carry signal CR[N+X], the second low voltage VSS2 can be provided to the Q node, and the voltage of the Q node can change from high to low. The second transistor T2 and the fourth transistor T4 can be turned off in response to the voltage of the Q node. In other words, the output of each of the Nth carry signal CR[N] and the Nth scan signal SC[N] can be paused.

[0174] Furthermore, at the fourth time point TP4, the ninth transistor T9 can be turned off in response to the voltage of the Q node, the first scan control signal S1 can be provided to the QB node through the seventh transistor T7 and the eighth transistor T8, and the voltage of the QB node can change from low to high. The third transistor T3 and the fifth transistor T5 can be turned on in response to the voltage of the QB node, and each of the Nth carry signal CR[N] and the Nth scan signal SC[N] can remain or substantially remain at a low level.

[0175] Figure 16 It shows Figure 13 The circuit diagram shows a comparative example of the gate driver. Figure 17 This is a graph showing the fall time of the scan signal.

[0176] First, refer to Figures 14 to 16 In addition to the seventeenth transistor T17, Figure 16 The Nth level ST[N]_C shown can be compared with Figure 14 The Nth level ST[N] shown is the same or substantially the same (or similar). Therefore, redundant descriptions can be avoided in the following text, and the differences can be described in more detail.

[0177] The Nth stage ST[N]_C can also include the seventeenth transistor T17.

[0178] The seventeenth transistor T17 may include a first electrode connected to a second output terminal (e.g., a scan line) for outputting the Nth scan signal SC[N], a second electrode connected to a first power input terminal (e.g., a first low power line) provided thereto by a first low voltage VSS1, and a gate electrode connected to a third carry input terminal (e.g., a subsequent carry line) to which the N+Y carry signal CR[N+Y] is applied. Here, Y can be a positive integer less than X. For example, X can be 4, and Y can be 2.

[0179] The seventeenth transistor T17 can pull down the Nth scan signal SC[N] to the first low voltage VSS1 in response to the N+Y carry signal CR[N+Y]. Therefore, the Nth scan signal SC[N] can quickly change from high level to low level.

[0180] Reference Figure 17 The first curve, CURVE1, represents the area including... Figure 14 The Nth level ST[N] shown Figure 1 The fall time of the scan signal measured in scan lines SL1 to SL1 of the display device 100 shown. For example, i in SL1 could be 2160 relative to 4K resolution. (Refer to...) Figure 2 and Figure 17 The number of scan lines can increase as they move further away from the pad PDP. As the scan signal moves further away from the pad PDP, the fall time of the scan signal increases from approximately 25 μs to approximately 43 μs.

[0181] The second curve, CURVE2, indicates that, according to including... Figure 16 The Nth level ST[N]_C shown is not included. Figure 1 The clock controller 150 shown is a comparative example of the display device's scan line, measuring the fall time of the scan signal. As the scan signal moves further away from the pad PDP, the fall time increases from approximately 25 μs to approximately 42 μs. This is relative to the scan line further away from the pad PDP. Figure 1 The fall time in the display device 100 shown may be about 1 μs longer than the fall time in the display device according to the comparative example, but the difference is about 2.5%. In other words, in terms of shortening the fall time, Figure 1 The display device 100 shown can have a similar effect to the display device according to the comparative example.

[0182] The display device according to the comparative example includes a seventeenth transistor T17 for each stage. For example, relative to 4K resolution, the display device according to the comparative example would include an additional 2160 transistors due to the inclusion of the seventeenth transistor T17. However, Figure 1 The display device 100 (and gate driver 140) shown includes a clock controller 150 (e.g., as a circuit shared by multiple stages, including, for example, reference). Figure 8 (Six transistors), excluding the seventeenth transistor T17. Therefore, it is possible to reduce... Figure 2 and Figure 3 The first region A1 shown (for example, it can be called an invalid region).

[0183] As described above, the display device 100 (and gate driver 140) according to some embodiments of the present disclosure may not include a seventeenth transistor T17 for pulling down the scan signal for each stage, thus reducing invalid areas.

[0184] Figure 18This is a block diagram illustrating a display system according to an embodiment.

[0185] Reference Figure 18 The display system 1000 (e.g., an electronic device) may include a processor 1100 and a display device 1200.

[0186] Processor 1100 can perform a variety of suitable tasks and calculations. In some embodiments, processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, and / or a central processing unit (CPU), etc. Processor 1100 can be connected to other components of display system 1000 via a bus system to control the components of display system 1000.

[0187] Processor 1100 can transmit image data IMG and control signal CTRL to display device 1200. Display device 1200 can display an image based on image data IMG and control signal CTRL. Display device 1200 can be configured to... (refer to above) Figure 1 The described display device 100 is the same as or substantially the same. Image data IMG and control signal CTRL can be provided separately as... Figure 1 The input data Din and control signal CS are shown in the figure.

[0188] Display system 1000 may include a computing system for providing image display functionality, such as a smartwatch, mobile phone, smartphone, portable computer, tablet PC, watch phone, car display, smart glasses, portable multimedia player (PMP), navigation system, or ultra-mobile computer (UMPC). Display system 1000 may include at least one of head-mounted display (HMD) device, virtual reality (VR) device, mixed reality (MR) device, and augmented reality (AR) device.

[0189] Figures 19 to 22 It is shown that according to some embodiments Figure 18 The image shows a perspective view of an application example of the display system.

[0190] Reference Figure 19 , Figure 18 The display system 1000 shown can be applied to a smartwatch 2000, which includes a display unit 2100 and a strap unit 2200.

[0191] The smartwatch 2000 can be a wearable electronic device. For example, the smartwatch 2000 may have a structure in which the strap 2200 is mounted on the user's wrist. The display system 1000 and / or the display device 1200 may be applied to the display 2100, so that image data including time information can be provided to the user.

[0192] Reference Figure 20 , Figure 18 The display system 1000 shown can be applied to an automotive display system 3000. The automotive display system 3000 may include a computing system disposed inside / outside the vehicle to provide image data.

[0193] For example, the display system 1000 and / or display device 1200 can be applied to at least one of the infotainment panel 3100, instrument panel 3200, passenger display 3300, head-up display 3400, side mirror display 3500 and rear seat display 3600 provided in the vehicle.

[0194] Reference Figure 21 , Figure 18 The display system 1000 shown can be applied to smart glasses 4000. Smart glasses 4000 can be a wearable electronic device that can be worn on a user's face. For example, smart glasses 4000 can be a wearable device for augmented reality (AR).

[0195] The smart glasses 4000 may include a frame 4100 and a lens 4200. The frame 4100 may include a housing 4110 for supporting the lens 4200 and temples 4120 for allowing a user to wear the smart glasses 4000. The temples 4120 may be hinged to the housing 4110 to fold or unfold relative to the housing 4110.

[0196] The battery, touchpad, microphone, camera, etc., can be built into the frame 4100. In addition, the projector for outputting light, the processor for controlling the light signal, etc., can be built into the frame 4100.

[0197] The lens portion 4200 can be an optical component that allows light to be transmitted through the lens portion 4200 or to be reflected by the lens portion 4200. For example, the lens portion 4200 may include glass, transparent synthetic resin, etc.

[0198] To enable the user's eyes to recognize visual information, the lens section 4200 allows the image caused by the light signal transmitted from the projector of the frame 4100 to be reflected by the rear surface of the lens section 4200 (e.g., the surface facing the user's eyes). For example, the user can recognize information displayed on the lens section 4200, including time, data, etc. The projector and / or lens section 4200 can be a display device. The display device 1200 can be applied to the projector and / or lens section 4200.

[0199] Reference Figure 22 , Figure 18 The display system 1000 shown can be applied to a head-mounted display device 5000.

[0200] The head-mounted display device 5000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 can be a wearable device for virtual reality (VR) or mixed reality (MR).

[0201] The head-mounted display device 5000 may include a headband 5100 and a display housing 5200. The headband 5100 may be connected to the display housing 5200. The headband 5100 may include a horizontal and / or vertical strap for securing the head-mounted display device 5000 to a user's head. The horizontal strap may be configured to surround a side portion of the user's head (e.g., around the periphery of a side portion of the user's head), and the vertical strap may be configured to surround an upper portion of the user's head (e.g., around the periphery of the upper portion of the user's head). However, this disclosure is not limited thereto. For example, the headband 5100 may be implemented as an eyeglass frame, a helmet, etc.

[0202] The display housing 5200 can accommodate the display system 1000 and / or the display device 1200.

[0203] According to some embodiments of this disclosure, the gate driver and display device may include a clock controller, and the clock controller may use a carry clock signal to pull down the scan clock signal. Therefore, the fall time of the scan signal corresponding to the scan clock signal can be shortened.

[0204] According to some embodiments of this disclosure, the gate driver and display device may exclude transistors for pull-down scan signals in each stage, thereby reducing invalid areas.

[0205] The foregoing is a description of some embodiments of this disclosure and is not to be construed as limiting it. While some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be apparent to those skilled in the art that, unless specifically stated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it will be understood that the foregoing is a description of various exemplary embodiments and is not to be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display device, the display device comprising: Display panel, including pixels connected to scan lines; A gate driver includes multiple stages, one of which is configured to: provide a carry clock signal of a carry clock line as a carry signal to a subsequent stage among the multiple stages; and provide a scan clock signal of a scan clock line as a scan signal to a corresponding scan line among the scan lines in response to a previous carry signal of a previous stage among the multiple stages. as well as A clock controller is configured to connect the scan clock line to a power line in response to the carry clock signal, the power line being configured to provide a constant voltage.

2. The display device according to claim 1, wherein, Each of the carry clock line and the scan clock line extends from a first side of the positioning pad on the display panel to a second side of the display panel. The clock controller is positioned adjacent to the second side of the display panel. The gate driver further includes a dummy stage configured to provide a carry signal to a previous stage, the dummy stage being unconnected to the scan line. The clock controller is positioned adjacent to the dummy level, and The gate driver includes the clock controller.

3. The display device according to claim 1, wherein, The stage is configured to output the first carry clock signal of the first carry clock line in the carry clock lines as the carry signal, and The clock controller includes a first switching transistor connected between the scan clock line and the power line, the first switching transistor including a gate electrode connected to a second carry clock line in the carry clock line, and The first switching transistor comprises an oxide semiconductor.

4. The display device according to claim 3, wherein, Each of the carry clock signal and the scan clock signal includes a square wave periodically having a gate on voltage and a gate off voltage. Specifically, compared to the first carry clock signal of the first carry clock line, the second carry clock signal of the second carry clock line has a phase delay equal to the pulse width of the scan clock signal having the gate on-voltage. The power line is configured to receive the gate cutoff voltage, and The clock controller is configured to connect the scan clock line to the power line in response to the carry clock signal having the gate on voltage, thereby shortening the fall time of each of the scan clock signal and the scan signal.

5. The display device according to claim 1, wherein, The display panel also includes: The first carry clock line, second carry clock line, third carry clock line, fourth carry clock line, fifth carry clock line, and sixth carry clock line are configured to receive the first carry clock signal, the second carry clock signal, the third carry clock signal, the fourth carry clock signal, the fifth carry clock signal, and the sixth carry clock signal, respectively; and The first, second, third, fourth, fifth, and sixth scan clock lines are configured to receive the first, second, third, fourth, fifth, and sixth scan clock signals, respectively. The first carry clock signal to the sixth carry clock signal have the same waveform but different phases. Wherein, the first scan clock signal to the sixth scan clock signal have the same waveform as each other, and each has the same phase as the first carry clock signal to the sixth carry clock signal, and The clock controller is configured to: pull down the first scan clock signal in response to the third carry clock signal; pull down the second scan clock signal in response to the fourth carry clock signal; pull down the third scan clock signal in response to the fifth carry clock signal; pull down the fourth scan clock signal in response to the sixth carry clock signal; pull down the fifth scan clock signal in response to the first carry clock signal; and pull down the sixth scan clock signal in response to the second carry clock signal.

6. The display device according to claim 5, wherein, The clock controller includes: An eleventh switching transistor is connected between the first scan clock line and the power line, and the eleventh switching transistor includes a gate electrode connected to the third carry clock line; A twelfth switching transistor is connected between the second scan clock line and the power line, the twelfth switching transistor including a gate electrode connected to the fourth carry clock line; A thirteenth switching transistor is connected between the third scan clock line and the power line, the thirteenth switching transistor including a gate electrode connected to the fifth carry clock line; A fourteenth switching transistor is connected between the fourth scan clock line and the power line, the fourteenth switching transistor including a gate electrode connected to the sixth carry clock line; A fifteenth switching transistor, connected between the fifth scan clock line and the power line, the fifteenth switching transistor including a gate electrode connected to the first carry clock line; and A sixteenth switching transistor is connected between the sixth scan clock line and the power line, the sixteenth switching transistor including a gate electrode connected to the second carry clock line.

7. The display device according to claim 1, wherein, The stage is configured to output the first carry clock signal of the first carry clock line in the carry clock lines as the carry signal. The clock controller includes a first switching transistor and a second switching transistor connected in series between the scan clock line and the power line. Wherein, the gate electrode of the first switching transistor is connected to the second carry clock line in the carry clock line, and The gate electrode of the second switching transistor is connected to the first carry clock line.

8. The display device according to claim 7, wherein, Each of the carry clock signal and the scan clock signal includes a square wave periodically having a gate on voltage and a gate off voltage. Wherein, the first carry clock signal of the first carry clock line has the same waveform and phase as the scan clock signal, and Wherein, compared with the first carry clock signal of the first carry clock line, the second carry clock signal of the second carry clock line has a phase that is delayed by the pulse width of the carry clock signal having the gate on voltage.

9. The display device according to claim 8, wherein, The constant voltage of the power line has a voltage level lower than the voltage level of the gate cutoff voltage.

10. The display device according to claim 1, wherein, The level includes: The first transistor, a diode, is connected between the carry line configured to receive the carry signal and the Q node; A second transistor is connected between the carry clock line and a first output terminal configured to output the carry signal, the second transistor including a gate electrode connected to the Q node; A third transistor is connected between the first output terminal and the low power line, the third transistor including a gate electrode connected to the QB node; A fourth transistor, connected between the scan clock line and a second output terminal configured to output the scan signal, the fourth transistor including a gate electrode connected to the Q node; and A fifth transistor, connected between the second output terminal and the low power line, includes a gate electrode connected to the QB node, and The stage does not include a transistor that connects the second output terminal and the low power line to each other in response to a subsequent carry signal from a subsequent stage.

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