A gallium nitride device stack structure and a method of manufacturing the same

Abstract

This invention relates to the field of MOS semiconductor technology and discloses a gallium nitride (GaN) device stacking structure and its manufacturing method, comprising a bottom GaN base structure and a top GaN top structure. The bottom GaN base structure, from bottom to top, comprises: a base substrate, a base buffer layer, a base GaN layer, and a base AlGaN layer. The bottom GaN base structure also includes: a base source, a base drain, a base gate, a base dielectric layer, a lower P-GaN layer, and an upper P-GaN layer. This invention integrates multiple AlGaN / GaN heterojunction channels within a single device through a vertical stacking design, achieving a significant reduction in on-resistance. While maintaining the same breakdown voltage and chip area, this structure conducts electricity through multiple parallel two-dimensional electron gas channels, reducing the overall on-resistance to approximately one-third of that of traditional planar structures, effectively overcoming the inherent contradiction in traditional GaN HEMT devices where on-resistance increases with increasing breakdown voltage.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a gallium nitride device stacking structure and its manufacturing method. Background Technology

[0002] With the development of microelectronics technology, gallium nitride high electron mobility transistors (HEMTs), as representatives of power semiconductor devices, have enormous market potential in high-frequency applications. GaN, a wide-bandgap semiconductor material, possesses an ultra-high critical breakdown electric field, nearly 10 times higher than that of silicon (Si), and the heterojunction composed of AlGaN and GaN exhibits a strong two-dimensional electron gas. Therefore, under the same voltage withstand conditions, GaN power devices have an on-resistance nearly three orders of magnitude lower than Si devices, significantly reducing chip area and the weight of the drive circuit. Furthermore, gallium nitride (GaN) material has excellent thermal conductivity, making it highly valuable for applications in high-temperature power electronic devices. In the future, GaN-based power electronics are highly likely to become a replacement for Si-based power devices and play a crucial role in emerging industries such as smart grids, hybrid vehicles, aerospace, and high-speed rail.

[0003] However, as a new generation of power devices, GaNHEMT devices inevitably face the problem of increased on-resistance during their development. In current GaNHEMT device structures (such as the gallium nitride device disclosed in publication number CN117637819A), the distance between the source and drain determines the maximum breakdown voltage when the device is turned off. This means that the higher the breakdown voltage of a GaNHEMT device, the greater its on-resistance. Summary of the Invention

[0004] This invention provides a gallium nitride (GaN) device stacking structure and its manufacturing method to solve existing technical problems, thereby addressing the issue that the on-resistance of traditional GaN HEMT devices increases with increasing breakdown voltage.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically a gallium nitride device stacking structure, including a bottom layer gallium nitride structure and a top layer gallium nitride structure.

[0006] The gallium nitride (GaN) base structure comprises, from bottom to top: a base substrate, a base buffer layer, a base GaN layer, and a base AlGaN layer; the gallium nitride base structure also includes: a base source, a base drain, a base gate, a base dielectric layer, a lower P-GaN layer, and an upper P-GaN layer.

[0007] The top gallium nitride structure includes, from bottom to top, a lower AlGaN layer, a top GaN layer, and an upper AlGaN layer; the top gallium nitride structure also includes a top source, a top drain, a top gate, a top dielectric layer, and a top P-GaN layer.

[0008] Furthermore, the base source and base drain are located on the top left and right sides of the base AlGaN layer, respectively, the base gate is located between the base source and base drain, and the upper P-GaN layer and lower P-GaN layer are located on the upper and lower sides of the base gate, respectively.

[0009] Furthermore, the base gate is located near the base source, and the distance between the base gate and the base source is in the range of .-µm;

[0010] The space between the base source and the base gate, and between the base drain and the base gate, is filled with a base dielectric layer (the material of the base dielectric layer is SiO).

[0011] Furthermore, the top-layer source and top-layer drain are located on the top left and right sides of the top AlGaN layer, respectively, the top-layer gate is located between the top-layer source and top-layer drain, and the top layer is located at the bottom of the base layer gate.

[0012] Furthermore, the top gate is located near the top source, and the distance between the top gate and the top source is 0.5-1µm;

[0013] The top source and top gate, and the top drain and top gate are filled with a top dielectric layer (the material of the top dielectric layer is SiO).

[0014] A method for manufacturing a gallium nitride device stack structure includes the following steps:

[0015] S1. Provide a base substrate, and form a base buffer layer, a base GaN layer and a base AlGaN layer sequentially on the base substrate according to conventional processes to form a substrate structure.

[0016] S2. Perform the following sub-steps sequentially on the base structure:

[0017] S201, deposit a P-GaN layer under the substrate and perform patterned etching;

[0018] S202, deposit the base medium layer and perform patterned etching;

[0019] S203, deposit the base layer source electrode and base layer drain electrode, and perform annealing treatment;

[0020] S204. The substrate dielectric layer in the region above the P-GaN layer under the substrate is etched to form a first etch groove;

[0021] S205. Deposit the base gate in the first etching tank and perform annealing treatment;

[0022] S3. After completing step S2, deposit a base gate P-GaN layer on the structural surface and perform chemical mechanical polishing to planarize it to form a base gallium nitride structure.

[0023] S4. Sequentially deposit the lower AlGaN layer, the top GaN layer, and the upper AlGaN layer on the polished gallium nitride base structure to form an AlGaN / GaN / AlGaN sandwich structure, wherein the deposition crystal orientation of the AlGaN layer and the GaN layer is controlled to form a two-dimensional electron gas.

[0024] S5. On the AlGaN layer on the top layer, repeat steps S201 to S205 to form a top layer source, a top layer drain, a top layer gate, a top layer dielectric layer and a top layer P-GaN layer to form at least one stacked top layer gallium nitride structure.

[0025] S6. Repeat steps S3 to S5 at least once to form a gallium nitride device structure with multi-level stacking.

[0026] A method for manufacturing a gallium nitride device stack structure includes the following steps:

[0027] S1. Provide a base substrate, and form a base buffer layer, a base GaN layer and a base AlGaN layer sequentially on the base substrate according to conventional processes to form a substrate structure.

[0028] S2. A P-GaN layer under the substrate and a substrate gate are sequentially deposited on the substrate structure.

[0029] S3. On the base gate, a P-GaN layer on the base layer, an AlGaN layer below the top layer, a GaN layer on the top layer, an AlGaN layer on the top layer, a P-GaN layer on the top layer and a top gate are deposited sequentially to form a multilayer stacked structure.

[0030] Among them, when depositing the P-GaN layer on the base layer, the AlGaN layer below the top layer, the GaN layer on the top layer and the AlGaN layer on the top layer, the deposition crystal orientation is controlled to ensure the formation of a two-dimensional electron gas;

[0031] S4. The multilayer stacked structure is patterned to form a second etch trench and expose the base gate and the top gate;

[0032] S5. By selective etching, a portion of the P-GaN layer on the substrate and the top P-GaN layer are removed via the second etching trench to form a third etching trench, thereby exposing the underlying AlGaN layer and the top AlGaN layer below.

[0033] S6. A portion of the base dielectric layer and the top dielectric layer are deposited and formed on the AlGaN layer below the top layer and the AlGaN layer above the top layer exposed by the second and third etch trenches.

[0034] S7. Repeat steps S5 to S6 to form the fourth and fifth etching tanks, and deposit another part of the base dielectric layer and top dielectric layer in the fifth etching tank. Then perform patterned etching of the excess or rough base dielectric layer and top dielectric layer.

[0035] S8. Deposit source metal (base source and top source) and drain metal (base drain and top drain) in the patterned etched area to form an electrical connection.

[0036] Furthermore, in step S3, controlling the deposition crystal orientation includes controlling the growth direction of each layer of material, so that a lattice-matched interface is formed between the top GaN layer and the upper and lower AlGaN layers on the top and bottom sides.

[0037] The present invention provides a gallium nitride device stacking structure and its manufacturing method. Compared with the prior art, the advantages achieved by this method are as follows:

[0038] 1. This invention integrates multiple AlGaN / GaN heterojunction channels within a single device through a vertical stacking design, achieving a significant reduction in on-resistance. While maintaining the same breakdown voltage and chip area, this structure conducts electricity through multiple parallel two-dimensional electron gas channels, reducing the overall on-resistance to approximately one-third of that of traditional planar structures. This effectively overcomes the inherent contradiction in traditional GaNHEMT devices where on-resistance increases with increasing breakdown voltage.

[0039] 2. The stacking structure provided by this invention exhibits excellent process compatibility and scalability. The number of stacking layers can be flexibly adjusted according to the process capabilities of different chip manufacturers. This provides a path for leading manufacturers to achieve higher stacking numbers and obtain better performance, while also enabling manufacturers with relatively limited process capabilities to enter this technology field with fewer stacking layers, thus broadening the applicable scenarios and industrialization potential of this structure.

[0040] 3. The stacked structure in this invention not only improves device performance but also brings significant advantages in production capacity and cost. Within the same chip area, multiple conductive channels are integrated by vertical stacking, which greatly improves the current density and power handling capability of the device. This means that a unit wafer can produce a device with stronger performance, or reduce the chip area while meeting the same performance requirements, thereby improving production efficiency and reducing the cost per wafer, and enhancing the competitiveness of the product in the power semiconductor market.

[0041] 4. This invention provides a novel structural paradigm and technical approach for the development of GaN-based power devices. By moving from planar to three-dimensional stacking, it breaks the traditional constraints of balancing on-resistance, voltage withstand capability, and chip area in device structures. This opens up new research directions for the design and application of future high-frequency, high-power, and high-density integrated GaN devices, and helps promote the wider application of GaN technology in high-end fields such as smart grids, new energy vehicles, and aerospace. Attached Figure Description

[0042] Figures 1-8 This is a flowchart of the method for manufacturing a gallium nitride device stacked structure in Embodiment 2 of the present invention;

[0043] Figure 9 This is a schematic diagram of the gallium nitride device stacking structure in this invention;

[0044] Figures 10-23 This is a flowchart of the method for manufacturing a gallium nitride device stacked structure in Embodiment 3 of the present invention.

[0045] In the figure: 1. Base layer gallium nitride structure; 2. Top layer gallium nitride structure; 101. Base layer substrate; 102. Base layer buffer layer; 103. Base layer GaN layer; 104. Base layer AlGaN layer; 105. Base layer source; 106. Base layer drain; 107. Base layer gate; 108. Base layer dielectric layer; 109. Lower P-GaN layer; 110. Upper P-GaN layer; 111. First etch trench; 112. Second etch trench; 113. Photoresist; 114. Third etch trench; 115. Fourth etch trench; 116. Fifth etch trench; 201. Lower AlGaN layer; 202. Top layer GaN layer; 203. Upper AlGaN layer; 204. Top layer source; 205. Top layer drain; 206. Top layer gate; 207. Top layer dielectric layer; 208. Top layer P-GaN layer. Detailed Implementation

[0046] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Example 1

[0048] like Figure 9 , 23 As shown, a gallium nitride device stacking structure includes a bottom gallium nitride structure 1 and a top gallium nitride structure 2.

[0049] The gallium nitride (GaN) base structure 1 includes, from bottom to top, a base substrate 101, a base buffer layer 102, a base GaN layer 103, and a base AlGaN layer 104. The GaN base structure 1 also includes a base source 105, a base drain 106, a base gate 107, a base dielectric layer 108, a lower P-GaN layer 109, and an upper P-GaN layer 110. The base source 105 and the base drain 106 are located on the top left and right sides of the base AlGaN layer 104, respectively. The base gate 107 is located between the base source 105 and the base drain 106. The upper P-GaN layer 110 and the lower P-GaN layer 109 are located on the top and bottom sides of the base gate 107, respectively. The base gate 107 is located near the base source 105, and the distance between the base gate 107 and the base source 105 is 0.5-1um; the base dielectric layer 108 (the material of the base dielectric layer 108 is SiO2) is filled between the base source 105 and the base gate 107 and between the base drain 106 and the base gate 107.

[0050] The top-layer gallium nitride structure 2, from bottom to top, includes: a lower AlGaN layer 201, a top GaN layer 202, and an upper AlGaN layer 203. The top-layer gallium nitride structure 2 also includes: a top-layer source 204, a top-layer drain 205, a top-layer gate 206, a top-layer dielectric layer 207, and a top-layer P-GaN layer 208. The top-layer source 204 and top-layer drain 205 are located on the left and right sides of the top of the upper AlGaN layer 203, respectively. The top-layer gate 206 is located between the top-layer source 204 and the top-layer drain 205, with the top layer located at the bottom of the base gate 107. The top-layer gate 206 is located close to the top-layer source 204, and the distance between the top-layer gate 206 and the top-layer source 204 is 0.5-1 μm. The space between the top-layer source 204 and the top-layer gate 206, and between the top-layer drain 205 and the top-layer gate 206, is filled with the top-layer dielectric layer 207 (made of SiO2).

[0051] By stacking multiple GaN / AlGaN heterojunction channels vertically, a significant reduction in on-resistance is achieved. Specifically, in the base gallium nitride structure 1, a first two-dimensional electron gas channel is formed between the base GaN layer 103 and the base AlGaN layer 104; in the top gallium nitride structure 2, the top GaN layer 202 forms a second and a third two-dimensional electron gas channel between the top AlGaN layer 201 and the top AlGaN layer 203, respectively. Through this "sandwich" design (AlGaN / GaN / AlGaN), the originally single conductive channel is expanded into three parallel channels, which is equivalent to converting the on-resistance into three resistors in parallel. Thus, while maintaining the same breakdown voltage and source area, the overall on-resistance is reduced to about 33% of that of the conventional structure. In addition, the dielectric layers (such as the base dielectric layer 108 and the top dielectric layer 207) are made of SiO2 material with high breakdown field strength, which can withstand higher drain-gate voltages in the device blocking state, further ensuring the reliability and breakdown voltage capability of the stacked structure.

[0052] This technology, through the integration of multiple AlGaN / GaN heterojunctions (such as a combination of a base AlGaN layer 104, a lower top AlGaN layer 201, an upper top AlGaN layer 203, and corresponding GaN layers), achieves multi-channel parallel conduction within a single device, overcoming the limitations imposed by the on-resistance and breakdown voltage of traditional planar structures. This structure not only reduces on-resistance by nearly 70% but also provides a new technical path for improving the performance of GaN HEMTs. The number of stacked layers can be flexibly adjusted according to process capabilities, exhibiting good process compatibility and scalability. Simultaneously, it achieves higher current density and production efficiency within the same chip area, providing crucial technical support for the development of GaN devices in high-frequency, high-power applications.

[0053] Example 2

[0054] A method for manufacturing a gallium nitride device stack structure includes the following steps:

[0055] Step 1, such as Figure 1 As shown, a base substrate 101 is provided, and a base buffer layer 102, a base GaN layer 103 and a base AlGaN layer 104 are sequentially formed on the base substrate 101 according to conventional processes to form a substrate structure.

[0056] This step constructs a standard substrate structure for GaN HEMT devices by providing a base substrate 101 and sequentially forming a base buffer layer 102, a base GaN layer 103, and a base AlGaN layer 104. The base buffer layer 102 alleviates lattice mismatch between the substrate and the GaN layer, while the base GaN layer 103 and the base AlGaN layer 104 form the first two-dimensional electron gas channel, providing a foundation for subsequent stacking. This step utilizes conventional epitaxial processes, does not rely on complex equipment, and is easily implemented by various chip manufacturers, lowering the technical entry barrier.

[0057] Step 2: Perform the following sub-steps sequentially on the base structure:

[0058] 1) such as Figure 2 As shown, a P-GaN layer 109 is deposited under the substrate and then patterned and etched. The deposition and patterning of the P-GaN layer 109 under the substrate aims to form the under-gate region of the device, used to modulate channel carriers and enhance the device's breakdown voltage. Patterning etching allows for precise control of the shape and position of the P-GaN layer, avoiding any impact on the surrounding structure. This method employs standard photolithography and etching processes, requires no special equipment, and is suitable for production lines with limited process capabilities, improving manufacturing feasibility and consistency.

[0059] 2) For example Figure 3 As shown, a base dielectric layer 108 is deposited and patterned. The deposited and patterned base dielectric layer 108 (typically SiO2) serves to isolate the gate and source / drain electrodes, preventing short circuits, while also utilizing the high breakdown field strength of SiO2 to improve the device's breakdown voltage. Patterning etching allows for precise windowing, reserving positions for subsequent gate deposition. This process is mature, highly controllable, and suitable for most semiconductor production lines, helping to ensure device reliability and reduce process development costs.

[0060] 3) For example Figure 4 As shown, a base source electrode 105 and a base drain electrode 106 are deposited and then annealed. This deposition and annealing aims to form a low-resistance ohmic contact, ensuring efficient current injection and extraction. Annealing optimizes the contact characteristics of the metal-semiconductor interface and reduces contact resistance. This step employs conventional metal deposition and annealing processes, offering a wide process window, good repeatability, and ease of integration into existing production lines, thus improving manufacturing yield and electrical performance consistency.

[0061] 4) For example Figure 5As shown, the substrate dielectric layer 108 above the P-GaN layer 109 under the substrate is etched to form a first etch trench 111; the substrate dielectric layer 108 above the P-GaN layer 109 under the substrate is etched to form the first etch trench 111, providing space for subsequent gate metal embedding. This etching step is achieved through a selective etching process, which can precisely control the trench depth and sidewall morphology, avoiding damage to the underlying AlGaN / GaN heterojunction channel. This method is simple, has low equipment requirements, and is beneficial for ensuring the morphology quality of the gate region and device performance.

[0062] 5) For example Figure 6 As shown, a base gate 107 is deposited in the first etch trench 111 and then annealed to form the gate control structure of the device. The gate metal is embedded in the dielectric layer, achieving good gate isolation and electric field modulation. The annealing process helps improve the interface characteristics between the gate metal and the dielectric layer and the underlying semiconductor. This step uses conventional metal filling and heat treatment techniques, which are mature, easy to control, and suitable for large-scale manufacturing, helping to improve the uniformity and stability of the device's threshold voltage.

[0063] Step 3, as follows Figure 7 As shown, a base gate P-GaN layer 110 is deposited on the surface of the structure after step two is completed, and chemical mechanical polishing is performed to planarize it to form a base gallium nitride structure 1.

[0064] After completing the base device structure, a P-GaN layer 110 is deposited on the base layer and chemically mechanically polished (CMP) is performed to planarize the surface and provide a flat substrate for subsequent stacking. The CMP process effectively removes surface undulations, ensuring the quality of the upper epitaxial layers. This step employs a planarization technique from standard semiconductor manufacturing, offering strong process control and facilitating the achievement of interface quality and interlayer electrical isolation in multilayer stacked structures, while reducing performance fluctuations caused by surface roughness.

[0065] Step 4, as follows Figure 8 As shown, a lower AlGaN layer 201, a top GaN layer 202, and an upper AlGaN layer 203 are sequentially deposited on the polished base gallium nitride structure 1 to form an AlGaN / GaN / AlGaN sandwich structure, wherein the deposition crystal orientation of the AlGaN layer and the GaN layer is controlled to form a two-dimensional electron gas.

[0066] On the polished substrate structure, a lower AlGaN layer 201, a top GaN layer 202, and an upper AlGaN layer 203 are sequentially deposited to form an "AlGaN / GaN / AlGaN" sandwich structure. By controlling the deposition crystal orientation, two high-quality two-dimensional electron gas channels can be formed between the top GaN layer 202 and the upper and lower AlGaN layers. This step uses epitaxial growth technology, and the process conditions are compatible with the substrate growth, eliminating the need to develop a completely new process. This facilitates the integration of multi-layer channels on existing production lines and significantly improves current conduction capability.

[0067] Step 5, as follows Figure 9 As shown, on the top AlGaN layer 203, steps S201 to S205 are repeatedly performed to form a top source 204, a top drain 205, a top gate 206, a top dielectric layer 207 and a top P-GaN layer 208 to form at least one stacked top gallium nitride structure 2.

[0068] Steps S201 to S205 are repeated on the top AlGaN layer 203 to form the top source 204, top drain 205, top gate 206, top dielectric layer 207, and top P-GaN layer 208, completing the construction of the top gallium nitride structure 2. This step achieves vertical replication of the device structure and independent integration of electrical functions. It uses the same process module as the base layer, greatly simplifying the manufacturing process design, reducing process development difficulty and cost, and making mass production of multi-level stacked structures possible.

[0069] Step Six: Repeat steps Three through Five at least once to form a multi-level stacked gallium nitride (GaN) device structure. Repeating steps Three through Five forms a multi-level stacked GaN device structure. This iterative method allows for flexible increases in the number of stacked layers according to design requirements, thereby further reducing on-resistance and increasing current density. The entire manufacturing process employs modular and cyclical process steps, with relatively relaxed requirements on production line process capabilities. This provides chip manufacturers with different technical levels with a scalable performance improvement path while maintaining good process compatibility and controllable manufacturing costs.

[0070] Example 3

[0071] A method for manufacturing a gallium nitride device stack structure includes the following steps:

[0072] Step 1, such as Figure 10 As shown, a base substrate 101 is provided, and a base buffer layer 102, a base GaN layer 103 and a base AlGaN layer 104 are sequentially formed on the base substrate 101 according to conventional processes to form a substrate structure.

[0073] A standard GaN HEMT substrate structure was constructed by providing a base substrate 101 and sequentially forming a base buffer layer 102, a base GaN layer 103, and a base AlGaN layer 104. The base buffer layer 102 alleviates lattice mismatch, and the base GaN layer 103 and the base AlGaN layer 104 form the first two-dimensional electron gas channel. This step employs conventional epitaxial processes, providing a reliable and process-compatible starting platform for subsequent high-efficiency stacking.

[0074] Step 2: Sequentially deposit a P-GaN layer 109 (e.g., under the substrate structure) on the substrate structure. Figure 11 (as shown) and base gate 107 (as shown) Figure 12 (as shown)

[0075] A sublayer P-GaN layer 109 and a base gate 107 are sequentially deposited on the substrate structure to directly construct the bottom gate-controlled cell. The sublayer P-GaN layer 109 is used to modulate the channel and enhance the breakdown voltage, while the base gate 107 controls the channel of this layer. This step deposits multiple functional layers in one go, simplifying the process flow, reducing intermediate patterning steps, making it suitable for production lines with strong process control capabilities, and improving manufacturing efficiency.

[0076] Step 3: On the base gate 107, a P-GaN layer 110 (e.g., ...) is sequentially deposited. Figure 13 As shown), the AlGaN layer 201 below the top layer (as shown) Figure 14 As shown), top GaN layer 202 (as shown) Figure 15 As shown), the top AlGaN layer 203 (as shown) Figure 16 As shown), the top P-GaN layer 208 (as shown) Figure 17 (as shown) and top gate 206 (as shown) Figure 18 (as shown), to form a multi-layer stacked structure;

[0077] Among them, when depositing a P-GaN layer 110 on the base layer, an AlGaN layer 201 below the top layer, a GaN layer 202 on the top layer and an AlGaN layer 203 on the top layer, the deposition crystal orientation is controlled to ensure the formation of a two-dimensional electron gas.

[0078] A P-GaN layer 110 on the base layer, an AlGaN layer 201 below the top layer, a GaN layer 202 on the top layer, an AlGaN layer 203 on the top layer, a P-GaN layer 208 on the top layer, and a top gate 206 are successively deposited on the base gate 107 to form a complete vertical stacked prototype. By precisely controlling the deposition crystal orientation of each layer (especially the AlGaN and GaN layers), high-quality two-dimensional electron gases are ensured to be formed at both the upper and lower interfaces of the top GaN layer 202. This step achieves "one-step forming" of the multilayer structure, greatly reducing the number of interlayer pauses, polishing, and patterning in traditional methods, and significantly shortening the process cycle, but it places higher demands on the crystal epitaxial quality and thickness control.

[0079] Step 4: Pattern the multi-layer stacked structure to form the second etch groove 112 (e.g., Figure 19 (As shown) and exposes the base gate 107 and the top gate 206;

[0080] The multilayer stacked structure is patterned to form a second etch trench 112, exposing the base gate 107 and the top gate 206. This step defines the contact windows of the gates in the multilayer structure through a single photolithography and etching process. This method avoids the complexity of layer-by-layer alignment and etching, improves process integration and alignment accuracy, and is suitable for production lines with advanced photolithography and deep trench etching capabilities.

[0081] Step 5: Using a selective etching process, a portion of the P-GaN layer 110 on the base layer and the top P-GaN layer 208 are removed via the second etch trench 112 to form the third etch trench 114 (e.g., ...). Figure 20 As shown), the lower AlGaN layer 201 and the upper AlGaN layer 203 are exposed through the third etch trench 114;

[0082] By selectively etching a portion of the P-GaN layer 110 on the base layer and the top P-GaN layer 208 via the second etch trench 112, a third etch trench 114 is formed, thereby exposing the underlying AlGaN layer 201 below the top layer and the AlGaN layer 203 above the top layer. This step utilizes the selective etching characteristics of the material to precisely create trenches in the P-GaN layer without damaging the critical AlGaN / GaN heterojunction channel, creating space for subsequent dielectric layer filling and source / drain contact fabrication.

[0083] Step Six: On the AlGaN layer 201 below the top layer and AlGaN layer 203 above the top layer exposed in the second etch trench 112 and the third etch trench 114, a portion of the base dielectric layer 108 and the top dielectric layer 207 (e.g., Figure 21 (as shown)

[0084] On the exposed AlGaN layer surfaces of the second etch trench 112 and the third etch trench 114, a portion of the base dielectric layer 108 and the top dielectric layer 207 are deposited and formed. This step utilizes a single deposition process to form an insulating dielectric on multiple exposed sidewalls and trench bottoms, achieving effective isolation between the gate and channel, as well as between different layers. This method simplifies the dielectric layer coverage process and improves the uniformity and reliability of insulation protection.

[0085] Step 7: Repeat steps S5 to S6, as follows. Figure 22As shown, a fourth etching tank 115 and a fifth etching tank 116 are formed, and another part of the base dielectric layer 108 and the top dielectric layer 207 are deposited in the fifth etching tank 116. Then, the excess or rough base dielectric layer 108 and the top dielectric layer 207 are patterned and etched.

[0086] Selective etching and dielectric layer deposition steps are repeated to form a fourth etch trench 115 and a fifth etch trench 116. Another portion of the dielectric layer is deposited in the fifth etch trench 116, followed by patterning etching to planarize it. This step, through an iterative etching-fill process, gradually constructs a complex three-dimensional isolation structure, ensuring the electrical isolation and structural integrity of the device in the source and drain regions, while optimizing the morphology quality of the dielectric layer.

[0087] Step 8, as Figure 23 As shown, source metal (base source 105 and top source 204) and drain metal (base drain 106 and top drain 205) are deposited in the patterned etched area to form an electrical connection.

[0088] In step three, controlling the deposition crystal orientation includes controlling the growth direction of each layer of material, so that a lattice-matched interface is formed between the top GaN layer 2 and the upper AlGaN layer 203 and the lower AlGaN layer 201 on the top and bottom sides.

[0089] After patterning and etching, source metal (forming the base source 105 and the top source 204) and drain metal (forming the base drain 106 and the top drain 205) are deposited in the area to complete the final electrical connection. This step forms the source and drain electrodes of all layers at once, achieving parallel conduction in the vertical direction. This method avoids the tedious process of fabricating electrodes for each layer individually, greatly simplifies the subsequent metallization process, reduces manufacturing costs and time, and ensures the consistency of the current collection path for each channel.

[0090] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A gallium nitride device stack structure, characterized by, It includes a bottom-layer gallium nitride structure (1) and a top-layer gallium nitride structure (2). The interior of the gallium nitride base structure (1) includes, from bottom to top: a base substrate (101), a base buffer layer (102), a base GaN layer (103), and a base AlGaN layer (104); the gallium nitride base structure (1) also includes: a base source (105), a base drain (106), a base gate (107), a base dielectric layer (108), a lower P-GaN layer (109), and an upper P-GaN layer (110). The base source (105) and base drain (106) are located on the top left and right sides of the base AlGaN layer (104), respectively. The base gate (107) is located between the base source (105) and the base drain (106). The upper P-GaN layer (110) and the lower P-GaN layer (109) are located on the upper and lower sides of the base gate (107), respectively. The top gallium nitride structure (2) includes, from bottom to top, the following layers in sequence: a lower AlGaN layer (201), a top GaN layer (202), and an upper AlGaN layer (203); the top gallium nitride structure (2) also includes: a top source (204), a top drain (205), a top gate (206), a top dielectric layer (207), and a top P-GaN layer (208). The top source (204) and top drain (205) are located on the top left and right sides of the top AlGaN layer (203), respectively. The top gate (206) is located between the top source (204) and the top drain (205). The top P-GaN layer (208) is located below the top gate (206).

2. The gallium nitride device stack of claim 1, wherein: The base gate (107) is located near the base source (105), and the distance between the base gate (107) and the base source (105) is 0.5-1 μm; A base dielectric layer (108) is filled between the base source (105) and the base gate (107), and between the base drain (106) and the base gate (107).

3. The gallium nitride device stack of claim 1, wherein: The top gate (206) is located near the top source (204), and the distance between the top gate (206) and the top source (204) is 0.5-1um; The top layer dielectric layer (207) is filled between the top source (204) and the top gate (206), and between the top drain (205) and the top gate (206).

4. A method of fabricating a gallium nitride device stack structure, characterized by, The gallium nitride device stacking structure described in any one of claims 1-3, wherein the method for manufacturing the gallium nitride device stacking structure comprises the following steps: S1. Provide a base substrate (101), and form a base buffer layer (102), a base GaN layer (103), and a base AlGaN layer (104) sequentially on the base substrate (101) according to conventional processes to form a substrate structure; S2. Perform the following sub-steps sequentially on the base structure: S201, deposit a P-GaN layer (109) under the substrate and perform patterned etching; S202, deposit the base medium layer (108) and perform patterned etching; S203, deposit the base layer source electrode (105) and base layer drain electrode (106), and perform annealing treatment; S204. The substrate dielectric layer (108) above the P-GaN layer (109) under the substrate is etched to form a first etch groove (111). S205, deposit the base gate (107) in the first etching tank (111) and perform annealing treatment; S3. After completing step S2, deposit a P-GaN layer (110) on the substrate on the structural surface and perform chemical mechanical polishing to planarize it to form a base gallium nitride structure (1). S4. Sequentially deposit the lower AlGaN layer (201), the top GaN layer (202), and the upper AlGaN layer (203) on the polished base gallium nitride structure (1). S5. On the AlGaN layer (203) on the top layer, repeat steps S201 to S205 to form a top layer source (204), a top layer drain (205), a top layer gate (206), a top layer dielectric layer (207) and a top layer P-GaN layer (208) to form at least one stacked top layer gallium nitride structure (2). S6. Repeat steps S3 to S5 at least once to form a gallium nitride device structure with multi-level stacking.

5. A method of fabricating a gallium nitride device stack structure, characterized by, The gallium nitride device stacking structure described in any one of claims 1-3, wherein the method for manufacturing the gallium nitride device stacking structure comprises the following steps: S1. Provide a base substrate (101), and form a base buffer layer (102), a base GaN layer (103), and a base AlGaN layer (104) sequentially on the base substrate (101) according to conventional processes to form a substrate structure; S2. A P-GaN layer (109) and a base gate (107) are sequentially deposited on the substrate structure. S3. On the base gate (107), a P-GaN layer (110), a lower AlGaN layer (201), a top GaN layer (202), an upper AlGaN layer (203), a top P-GaN layer (208), and a top gate (206) are sequentially deposited to form a multilayer stacked structure. In the process of depositing the P-GaN layer (110) on the base layer, the AlGaN layer (201) under the top layer, the GaN layer (202) on the top layer and the AlGaN layer (203) on the top layer, the deposition crystal orientation is controlled to ensure the formation of a two-dimensional electron gas; S4. The multilayer stacked structure is patterned to form a second etch trench (112) and expose the base gate (107) and the top gate (206). S5. By selective etching, a portion of the P-GaN layer (110) on the base layer and the top P-GaN layer (208) are removed via the second etching tank (112) to form a third etching tank (114), through which the lower top AlGaN layer (201) and the upper top AlGaN layer (203) are exposed. S6. On the AlGaN layer (201) under the top layer and the AlGaN layer (203) exposed in the second etch trench (112) and the third etch trench (114), a portion of the base dielectric layer (108) and the top dielectric layer (207) are deposited and formed. S7. Repeat steps S5 to S6 to form the fourth etching tank (115) and the fifth etching tank (116), and deposit another part of the base dielectric layer (108) and the top dielectric layer (207) in the fifth etching tank (116), and then perform patterned etching of the excess or rough base dielectric layer (108) and the top dielectric layer (207). S8. Deposit source and drain metals in the patterned etched area to form an electrical connection.

6. The method of fabricating a gallium nitride device stack structure according to claim 5, wherein: In step S3, controlling the deposition crystal orientation includes controlling the growth direction of each layer of material so that the top GaN layer (202) forms a lattice-matched interface with the top AlGaN layer (203) and the bottom AlGaN layer (201) on the upper and lower sides.

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