Integrated circuit performing loopback operation and method of operating same
By introducing loopback operation into the integrated circuit to generate multiphase clock and data, and using delay circuits and terminals for data sampling and gating, the problem of verifying accuracy during memory data reception is solved, and the stability and accuracy of data reception are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2026-03-24
AI Technical Summary
During the data reception process in memory, existing technologies struggle to effectively verify the accuracy of data reception operations, especially during the write data reception process, where errors are prone to occur.
By introducing loopback operation into the integrated circuit, multiphase clock and data are generated using components such as loopback clock terminal, loopback data terminal, data receiver and delay circuit, data sampling and delay processing are performed to ensure the accuracy of data during the loopback process, and stable data loopback is achieved by using loopback data terminal and clock terminal to select data and clock.
This improves the accuracy of the data reception process, reduces errors in the loopback process, ensures that the memory controller can effectively verify the correctness of data reception, and reduces the difficulty of error detection.
Smart Images
Figure CN121723947A_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This application claims priority to Korean Patent Application No. 10-2024-0128858, filed on September 24, 2024, which is incorporated herein by reference in its entirety. Technical Field
[0003] Various embodiments of this disclosure relate to integrated circuits, and more specifically, to techniques for verifying the receiving operation of integrated circuits. Background Technology
[0004] The memory stores the data written from the memory controller and provides the stored data as read data. If an error occurs during the data writing process, all memory operations will fail. Therefore, verifying the memory's data receiving circuitry is crucial.
[0005] One method for verifying data reception operations from memory is to use a loopback operation. A loopback operation involves sending data received from memory back to the memory controller and verifying the transmitted data. Summary of the Invention
[0006] According to one embodiment of this disclosure, an integrated circuit may include: a loopback clock terminal; a loopback data terminal; a first data terminal; a second data terminal configured to be further away from the loopback data terminal than the first data terminal; a first data receiver configured to receive first data through the first data terminal; a second data receiver configured to receive second data through the second data terminal; a first sampler configured to sample the first data received by the first data receiver based on a multiphase clock to generate multiphase first data; a second sampler configured to sample the second data received by the second data receiver based on a multiphase clock to generate multiphase second data; and a first delay. The circuit is configured to delay one of the multiphase first data; a second delay circuit is configured to delay one of the multiphase second data, the second delay circuit having a larger delay value than the first delay circuit; a clock delay circuit is configured to delay one of the multiphase clocks; a loopback data sampler is configured to sample one of the data delayed by the first delay circuit and the data delayed by the second delay circuit based on a clock delayed by the clock delay circuit; a loopback data transmitter is configured to transmit the data sampled by the loopback data sampler to a loopback data terminal; and a loopback clock transmitter is configured to transmit a clock delayed by the clock delay circuit to a loopback clock terminal.
[0007] According to one embodiment of this disclosure, an integrated circuit may include: a first to Nth data receiving circuit configured to: receive first to Nth data via first to Nth data terminals based on a multiphase clock to generate first to Nth multiphase data respectively, wherein "N" is an integer equal to or greater than 2; a first to Nth delay circuit configured to delay the first to Nth data having a selected phase in the first to Nth multiphase data respectively; a clock delay circuit configured to delay the clock having a selected phase in the multiphase clock; and a loopback circuit configured to: transmit the clock delayed by the clock delay circuit to a loopback clock terminal, and transmit one of the first to Nth data having a selected phase delayed by the first to Nth delay circuit to the loopback data terminal based on the clock delayed by the clock delay circuit.
[0008] According to an embodiment of this disclosure, a method of operating an integrated circuit may include: receiving first to Nth data through first to Nth data terminals based on a multiphase clock to generate first to Nth multiphase data respectively, wherein N is an integer equal to or greater than 2; delaying first to Nth data having selected phases in the first to Nth multiphase data respectively; delaying a clock having selected phase in the multiphase clock; transmitting the delayed clock to a loopback clock terminal, and transmitting one of the delayed first to Nth data having selected phases to the loopback data terminal based on the delayed clock. Attached Figure Description
[0009] Figure 1 This is a block diagram illustrating a memory according to an embodiment of the present disclosure.
[0010] Figure 2 It is shown Figure 1 A block diagram of an embodiment of the multiphase clock generation circuit shown.
[0011] Figure 3 It is shown Figure 1 A block diagram of an embodiment of the data receiving circuit shown.
[0012] Figure 4 This is a timing diagram illustrating the operation of a data receiving circuit according to an embodiment of the present disclosure.
[0013] Figure 5 It is shown Figure 1 A block diagram of an embodiment of the loopback circuit shown. Detailed Implementation
[0014] Various embodiments of this disclosure relate to techniques for stable loopback operation of integrated circuits.
[0015] According to embodiments of this disclosure, a loopback operation can be performed based on the position of the data terminals of the integrated circuit, and skew differences can be compensated.
[0016] Hereinafter, various embodiments based on the technical essence of this disclosure will be described with reference to the accompanying drawings.
[0017] Figure 1 This is a block diagram illustrating a memory 100 according to an embodiment of the present disclosure. Figure 1 The portion of memory 100 related to loopback operation is shown.
[0018] refer to Figure 1 The memory 100 may include a data terminal DQ. <0> To DQ <m>The circuit includes a data clock terminal WCK, a loopback clock terminal LBDQS, a loopback data terminal LBDQ, data receiving circuits 110_0 to 110_M, delay circuits 120_0 to 120_M, a multiphase clock generation circuit 130, a clock delay circuit 140, a loopback circuit 150, data phase selectors 111_0 to 111_M, a clock phase selector 131, and a data terminal selector 151.
[0019] Data terminal DQ <0> To DQ <m>This is the terminal through which data is input to and output from memory 100, where "M" is an integer equal to or greater than 1. Data terminal DQ <0> To DQ <m>It can be physically positioned near and away from the loopback circuit 150 and the loopback clock terminal LBDQS. Here, the data terminal DQ <0> The data terminal furthest from the loopback circuit is 150, while the data terminal DQ <m>This is the data terminal closest to the loopback circuit 150.
[0020] The data clock terminal WCK is used to select the input to the data terminal DQ. <0> To DQ <m>The data clock is input to the DQ terminal. Data is input to the DQ terminal on both the rising and falling edges of the data clock. <0> To DQ <m>Each of these. Here, a data clock terminal WCK is shown, but the data clock can be a differential signal, and the data clock terminal WCK can be configured with two terminals for receiving differential signals.
[0021] The loopback data terminal LBDQ is the terminal to which data looped back from memory 100 is output. It also has a data terminal DQ. <0> To DQ <m>The selected phase data from the selected data terminal is output to the loopback data terminal LBDQ. The data rate of the data output to the loopback data terminal LBDQ can be the same as the data rate input to the data terminal DQ. <0> To DQ <m>The data rate is 1 / 4 of the data rate. Because the data rate of data looped back via the LBDQ loopback data terminal is low, the possibility of errors occurring during loopback is low. That is, errors occurring during data loopback can be detected while eliminating the possibility of errors occurring during data reception. The LBDQ loopback data terminal may include a dedicated terminal for outputting loopback data, while data terminals not used for loopback operation can be used as loopback data terminals. For example, in the verification data terminal DQ... <0> To DQ <7> During loopback operation, data terminal DQ <8> It can be used as the loopback data terminal LBDQ, while it is used for the verification data terminal DQ. <8> To DQ <15> During loopback operation, data terminal DQ <7> It can be used as a loopback data terminal LBDQ. A loopback data terminal LBDQ can refer to a dedicated terminal used only for loopback operations or a data terminal used for loopback operations.
[0022] The loopback clock terminal LBDQS is the terminal to which the loopback clock is output, used to select the data output to the loopback data terminal LBDQ. Because the loopback clock is used to select the data, it is also called the loopback data strobe signal. The loopback clock terminal LBDQS can include a dedicated terminal for outputting the loopback clock, while the read data strobe signal terminal RDQS, used for outputting the read data strobe signal, can be used as the loopback clock terminal LBDQS. The loopback clock terminal LBDQS can refer to a dedicated terminal used only for loopback operation or the read data strobe signal terminal RDQS used to output the loopback clock.
[0023] The multiphase clock generation circuit 130 can use the data clock input to the data clock terminal WCK to generate multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270. The frequencies of the multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 are half the frequency of the data clock, and the phases of the multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 can differ by 90°.
[0024] Data receiving circuits 110_0 to 110_M can use multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 to transmit data via the DQ terminal. <0> To DQ <m>Data reception. The data receiving circuit 110_0 can use multi-phase clocks WCK_0, WCK_90, WCK_180, and WCK_270 to receive data from the data terminal DQ. <0> The data, and generate the first multiphase data DATA. <0> _0、DATA <0> _90、DATA <0> _180 and DATA <0> _270. The data receiving circuit 110_1 can use multi-phase clocks WCK_0, WCK_90, WCK_180 and WCK_270 to receive data from the DQ terminal. <1> The data, and generate the second multiphase data DATA. <1> _0、DATA <1> _90、DATA <1> _180 and DATA <1> _270. Similarly, the data receiving circuit 110_M can use multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 to receive data from the data terminal DQ. <m>The data is used to generate the (M+1)th multiphase data DATA. <m>_0、DATA <m>_90、DATA <m>_180 and DATA <m>_270.
[0025] Data phase selectors 111_0 to 111_M can receive multiphase data DATA received by data receiving circuits 110_0 to 110_M. <0> _0 to DATA <0> _270、DATA <1> _0 to DATA <1> _270 and DATA <m>_0 to DATA <m>_270 selects data with the phase selected by the phase selection information PHASE_SEL. For example, the data phase selector 111_1 can select and output multiphase data DATA generated by the data receiving circuit 110_1 according to the phase selection information PHASE_SEL. <1> _0、DATA <1> _90、DATA <1> _180 and DATA <1> _One of 270.
[0026] Delay circuits 120_0 to 120_M can delay data DATA with a selected phase. <0> _SP、DATA <1> _SP and DATA <m>The delay circuits 120_0 to 120_M can have different delay values and are connected to the data terminal DQ. <0> To DQ <m>The delay circuit corresponding to the terminal closer to the loopback clock terminal LBDQS can have a larger delay value. That is, delay circuit 120_M can have the largest delay value, while delay circuit 120_M-1 can have the second largest delay value. Furthermore, delay circuit 120_1 can have the second smallest delay value, while delay circuit 120_0 can have the smallest delay value. By design, the delay value of delay circuit 120_0 can be designed to be essentially "0". That is, delay circuit 120_0 can be omitted.
[0027] Clock phase selector 131 can select and output one of the multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 generated by multiphase clock generation circuit 130 according to phase selection information PHASE_SEL. Since clock phase selector 131 and data phase selectors 111_0 to 111_M operate in response to the same phase selection information PHASE_SEL, the phase selected by data phase selectors 111_0 to 111_M can be the same as the phase selected by clock phase selector 131. For example, when data phase selector 111_0 selects data DATA... <0> When the clock phase selector is _180, the clock phase selector 131 can select the clock WCK_180.
[0028] Clock delay circuit 140 can delay a clock WCK_SP having a phase selected by clock phase selector 131. The delay value of clock delay circuit 140 can be set to match the data from data terminal DQ. <0> To DQ <m>The data terminal DQ furthest from the loopback clock terminal LBDQS <0> The value corresponding to the delay value of the path through which the transmission reaches the loop circuit 150.
[0029] Data terminal selector 151 can select data DATA obtained by delaying the data through delay circuits 120_0 to 120_M according to data terminal selection information DQ_SEL. <0> _SPD、DATA <1> _SPD and DATA <m>One of the SPDs. Data terminal selection information DQ_SEL is used to select the data terminal to be used for loopback operation. The data selected through data terminal selection information DQ_SEL and phase selection information PHASE_SEL is the target for loopback operation. For example, when phase 270 is selected through phase selection information PHASE_SEL and data terminal DQ is selected through data terminal selection information DQ_SEL... <0> At that time, it is connected to the data terminal DQ. <0> The data corresponding to phase 270 <0> _270 becomes the target for loopback operations.
[0030] The loopback circuit 150 can transmit the clock WCK_SPD obtained by delaying the clock through the clock delay circuit 140 to the loopback clock terminal LBDQS, and use the clock WCK_SPD obtained by delaying the clock through the clock delay circuit 140 to transmit the data DATA_SEL_SPD selected by the data terminal selector 151 to the loopback data terminal LBDQ.
[0031] Figure 2 for Figure 1 A block diagram of an embodiment of the multiphase clock generation circuit 130 shown.
[0032] See Figure 2 The multiphase clock generation circuit 130 may include a data clock receiver 210 and a frequency divider 220.
[0033] The data clock receiver 210 can receive the data clock from the data clock terminal WCK. As mentioned above, the data clock can be a differential signal, and the number of data clock terminals WCK can be two. Therefore, the data clock receiver 210 can be a differential receiver.
[0034] Frequency divider 220 can divide the data clock received by data clock receiver 210 and generate multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270. The frequencies of multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 can be half the frequency of the data clock, and the phases of multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 can differ by 90°.
[0035] Figure 3 It is shown Figure 1 A block diagram of an embodiment of the data receiving circuit 110_0 shown.
[0036] See Figure 3 The data receiving circuit 110_0 may include a data receiver 310 and a sampler 320.
[0037] The data receiver 310 can be connected via the data terminal DQ <0> Receive data.
[0038] Sampler 320 can sample data received by data receiver 310 using multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270. Sampler 320 may include D flip-flops 321 to 324. Each of D flip-flops 321 to 324 can sample data on the rising edge of the corresponding multiphase clock in WCK_0, WCK_90, WCK_180, and WCK_270. For example, D flip-flop 321 can sample data on the rising edge of multiphase clock WCK_0 to generate first multiphase data DATA. <0> _0, while the D flip-flop 324 can sample data on the rising edge of the multiphase clock WCL_270 to generate the first multiphase data DATA. <0> _270.
[0039] Figure 4 This is a timing diagram illustrating the operation of the data receiving circuit 110_0 according to an embodiment of the present disclosure. (See reference...) Figure 4 This shows the relationship between the data clock WCK and the multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270, as well as the data pad DQ. <0> The data is the same as the first multiphase data DATA generated by sampler 320. <0> _0、DATA <0> _90、DATA <0> _180 and DATA <0> The relationship between _270.
[0040] Although Figure 3 Only data receiving circuit 110_0 is shown, but other data receiving circuits 110_1 to 110_M can also be used in conjunction with it. Figure 3 Configure it in the same way as shown.
[0041] Figure 5 It is shown Figure 1 A block diagram of an embodiment of the loopback circuit 150 shown.
[0042] See Figure 5 The loopback circuit 150 may include a loopback data sampler 510, a loopback data transmitter 520, and a loopback clock transmitter 530.
[0043] The loopback data sampler 510 can sample the data DATA_SEL_SPD selected by the data terminal selector 151 using a clock WCK_SPD obtained through a delay of the clock delay circuit 140. The loopback data sampler 510 may include a D flip-flop that samples the data DATA_SEL_SPD on the rising edge of the clock WCK_SPD obtained through the delay of the clock delay circuit 140.
[0044] The loopback data transmitter 520 can transmit data obtained by sampling through the loopback data sampler 510 to the loopback data terminal LBDQ.
[0045] The loopback clock transmitter 530 can transmit the clock WCK_SPD (i.e., the clock WCK_SPD obtained by delay through the clock delay circuit 140) used during the sampling operation of the loopback data sampler 510 to the loopback clock terminal LBDQS.
[0046] Return to reference Figures 1 to 5 This describes the loopback operation of memory 100.
[0047] The multiphase clock generation circuit 130 can generate multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 using the data clock received from the data clock terminal WCK. The multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270 are transmitted to data receiving circuits 110_0 to 110_M, which can then receive data from the data terminal DQ using the multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270. <0> To DQ <m>The data.
[0048] The multiphase data DATA generated by data receiving circuits 110_0 to 110_M respectively <0> _0 to DATA <0> _270、DATA <1> _0 to DATA <1> _270 and DATA <m>_0 to DATA <m>In _270, there is data DATA containing the phase selected by the phase selection information PHASE_SEL. <0> _SP to DATA <m>The data (_SP) is transmitted to the loopback circuit 150 via delay circuits 120_0 to 120_M. Although the distances between the data receiving circuits 110_0 to 110_M and the loopback circuit 150 are different, this difference in distance is compensated for by the different delay values of the delay circuits 120_0 to 120_M. That is, the time it takes for data to be transmitted from the farthest data receiving circuit 110_0 to the loopback circuit 150 can be the same as the time it takes for data to be transmitted from the other data receiving circuits 110_1 to 110_M to the loopback circuit 150.
[0049] In the multiphase clocks WCK_0, WCK_90, WCK_180, and WCK_270, the clock WCK_SP with the phase selected by the phase selection information PHASE_SEL is delayed by the clock delay circuit 140. Therefore, the same delay time as the time taken for data to be transmitted from the data receiving circuit to the loopback circuit can be reflected in the clock WCK_SP.
[0050] Data terminal selector 151 can select data DATA obtained by delaying the data through delay circuits 120_0 to 120_M according to data terminal selection information DQ_SEL. <0> _SPD to DATA <m>The loopback data sampler 510 of the loopback circuit 150 can sample the data DATA SEL SPD selected by the data terminal selector 151 with the clock WCK SPD obtained by the delay of the clock delay circuit 140. The data obtained by the sampling of the loopback data sampler 510 is output to the loopback data terminal LBDQ by the loopback data transmitter 520, and the clock WCK SPD is output to the loopback clock terminal LBDQS by the loopback clock transmitter 530.
[0051] Thus, the data selected by the data terminal selection information DQ SEL and the phase selection information PHASE SEL is looped back to the memory controller through the loopback data terminal LBDQ, and the clock for gating the loopback data is looped back to the memory controller through the loopback clock terminal LBDQS. The memory controller can check whether the memory 100 correctly receives the data by checking the data and the clock to be looped back. Since the data rate of the loopback data is 1 / 4 of the data rate of the data received by the memory 100, the possibility of error occurrence is small. Therefore, the memory controller can check the loopback data reflecting only the error occurring in the data reception process, not including the error occurring during the loopback process.
[0052] Although the loopback operation in the memory is described according to the above-described embodiments, it should be understood that the embodiments are not only applicable to the memory, but also can be used to verify the data reception operation of general integrated circuits.
[0053] Although the technical essence of the present disclosure has been described above according to the embodiments, this is only for describing the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above-described embodiments. Those skilled in the art to which the present disclosure belongs can apply various embodiments within the scope of the technical essence of the present disclosure. In addition, the embodiments can be combined to form additional embodiments.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m>
Claims
1. An integrated circuit, comprising: Loopback clock terminal; Loopback data terminal; First data terminal; The second data terminal is configured to be farther from the loopback data terminal than the first data terminal; A first data receiver receives first data through the first data terminal; The second data receiver receives the second data through the second data terminal; A first sampler samples the first data received by the first data receiver based on a multiphase clock to generate multiphase first data; The second sampler samples the second data received by the second data receiver based on the multiphase clock to generate multiphase second data; A first delay circuit delays one of the multiphase first data; A second delay circuit delays one of the multi-phase second data, and the second delay circuit has a larger delay value than the first delay circuit. A clock delay circuit that delays one of the multiphase clocks; A loopback data sampler, which: samples one of the data delayed by the first delay circuit and the data delayed by the second delay circuit based on a clock delayed by the clock delay circuit; A loopback data transmitter that transmits data sampled by the loopback data sampler to the loopback data terminal; and A loopback clock transmitter that transmits the clock, delayed by the clock delay circuit, to the loopback clock terminal.
2. The integrated circuit according to claim 1, further comprising: Data clock terminal; A data clock receiver that receives a data clock through the data clock terminal; as well as A frequency divider divides the data clock received by the data clock receiver to generate the multiphase clock.
3. The integrated circuit according to claim 1, further comprising: A first phase selector selects first data having a selected phase from the multi-phase first data to provide the selected first data to the first delay circuit; A second phase selector, wherein: a second data having the selected phase is selected from the multi-phase second data, to provide the selected second data to the second delay circuit; and A clock selector that selects a clock having the selected phase from the multiphase clocks to provide the selected clock to the clock delay circuit.
4. The integrated circuit of claim 3, further comprising a data selector that selects one of the data delayed by the first delay circuit and the data delayed by the second delay circuit to provide the selected data to the loopback data sampler.
5. The integrated circuit according to claim 1, further comprising a third data terminal to an Nth data terminal, wherein N is an integer equal to or greater than 4. in, The delay value of the clock delay circuit corresponds to the delay value of the path from the data terminal furthest from the loopback clock terminal among the first data terminal to the Nth data terminal to the loopback data sampler.
6. The integrated circuit according to claim 1, wherein, The data rate of the loopback data terminal is 1 / 4 of the data rates of the first data terminal and the second data terminal.
7. The integrated circuit according to claim 2, wherein, The number of multiphase clocks is 4, the frequency of the multiphase clocks is 1 / 2 of the frequency of the received clock, and the multiphase clocks have a 90-degree phase difference with each other.
8. An integrated circuit, comprising: The first data receiving circuit to the Nth data receiving circuit, based on a multi-phase clock, receives first data to Nth data through the first data terminal to the Nth data terminal to generate first multi-phase data to Nth multi-phase data respectively, where N is an integer equal to or greater than 2; The first to Nth delay circuits respectively delay the first multiphase data to the first to Nth data having a selected phase in the Nth multiphase data; A clock delay circuit that delays a clock in the multiphase clock having the selected phase; and A loopback circuit, which: transmits a clock delayed by the clock delay circuit to a loopback clock terminal, and, based on the clock delayed by the clock delay circuit, transmits one of the first to Nth data having the selected phase, delayed by the first to Nth delay circuits, to a loopback data terminal.
9. The integrated circuit according to claim 8, wherein, The first to the Nth delay circuits have different delay values.
10. The integrated circuit according to claim 9, wherein, The delay circuit in the first to the Nth delay circuits that corresponds to the data terminal closest to the loopback clock terminal in the first to the Nth data terminals has the largest delay value.
11. The integrated circuit according to claim 10, wherein, The delay value of the clock delay circuit corresponds to the delay value of the path from the data terminal furthest from the loopback clock terminal among the first data terminal to the Nth data terminal to the loopback circuit.
12. The integrated circuit according to claim 8, wherein, Each of the first to Nth data receiving circuits includes: Data receiver; and A sampler that samples the data received by the data receiver based on the multiphase clock.
13. The integrated circuit according to claim 8, wherein, The loopback circuit includes: A loopback clock transmitter that transmits the clock, which will be delayed by the clock delay circuit, to the loopback clock terminal; A loopback data sampler, which: samples one of first to Nth data having the selected phase, delayed by the first to Nth delay circuits, based on the clock delayed by the clock delay circuit; and A loopback data transmitter that transmits the data sampled by the loopback data sampler to the loopback data terminal.
14. The integrated circuit according to claim 8, wherein, The data rate of the loopback data terminal is 1 / 4 of the data rate of the first data terminal to the Nth data terminal.
15. The integrated circuit according to claim 8, further comprising: Data clock terminal; A data clock receiver that receives a data clock through the data clock terminal; as well as A frequency divider divides the data clock received by the data clock receiver to generate the multiphase clock.
16. The integrated circuit according to claim 15, wherein, The number of multiphase clocks is 4, the frequency of the multiphase clocks is 1 / 2 of the frequency of the received clock, and the multiphase clocks have a 90-degree phase difference with each other.
17. A method of operating an integrated circuit, the method comprising: Based on a multi-phase clock, data from the first data terminal to the Nth data terminal is received to generate data from the first multi-phase data terminal to the Nth multi-phase data terminal respectively, where N is an integer equal to or greater than 2. Delay the first multiphase data to the first to Nth data of the Nth multiphase data, respectively, for each of the selected phases. Delay the clock in the multiphase clock that has the selected phase; as well as The delayed clock is transmitted to the loopback clock terminal, and based on the delayed clock, one of the delayed data from the first to the Nth data with the selected phase is transmitted to the loopback data terminal.
18. The method according to claim 17, wherein, Delaying the first data to the Nth data having the selected phase includes: delaying the first data to the Nth data having the selected phase by different delay values.
19. The method of claim 17, wherein, The transmission includes: The delayed clock is transmitted to the loopback clock terminal; Based on the clock delay, sample one of the first to Nth data points having the selected phase; and The sampled data is transmitted to the loopback data terminal.
20. The method of claim 17, further comprising: Receive data clock via data clock terminal; as well as The received data clock is divided to generate the multiphase clock.
Citation Information
Patent Citations
A connection sealing device having a lithographic apparatus, an illumination system, and a protective shield
KR1020240128858A