Nonvolatile memory data read operation test method and hardware equipment

Abstract

The embodiment of the invention provides a nonvolatile memory data read operation test method and hardware equipment, after test data are burnt to a memory, a system can automatically execute read and comparison operations of the test data, and an expected value is determined based on a comparison result, so that the test efficiency is improved. According to the invention, the system can adaptively adjust the range of the clock period for initially and stably reading the data so as to accurately capture the critical clock period for successfully reading the data, so that the access time of the memory can be efficiently calculated. The method significantly improves the test coverage, has high implementation flexibility, can be conveniently applied to various test platforms or carriers, and realizes accurate measurement of the reading speed of the target memory.

Description

Technical Field

[0001] The embodiments of this application belong to the field of read operation testing technology, and particularly relate to a method and hardware device for testing data read operations of non-volatile memory. Background Technology

[0002] Memory is a core component of integrated circuits, and measuring memory read speed is not only a crucial step in performance verification but also an important basis for reliability analysis, system optimization, standard certification, and new technology development. Accurate read speed measurement methods can help engineers optimize designs, improve yield, reduce power consumption, and ensure stable chip operation in complex application environments. However, these methods are complex, and memory cells are susceptible to process deviations, noise, and aging, leading to read / write errors. Traditional testing methods rely on external testing equipment, such as applying test vectors via ATE (Automatic Test Equipment), which is time-consuming, costly, and unable to monitor internal data in real time. When comparing read speeds with expected values, fixed test patterns struggle to cover real-world scenarios, resulting in inaccurate read speed measurements.

[0003] While the Chinese patent with publication number CN 111696617 A provides a memory testing scheme, its static testing method based on preset fixed comparison data has significant shortcomings: First, this method cannot adapt to the testing needs of dynamic data scenarios, and its testing mode is singular and lacks flexibility; second, its address path requires strict timing balance, which is difficult to ensure timing consistency in actual chip manufacturing due to environmental factors such as process deviations and temperature changes, resulting in deviations in read speed measurement results. This makes it difficult to meet the requirements of modern memory for high-precision performance testing, especially in high-frequency, high-precision application scenarios where the reliability of test results will be severely compromised; in addition, relying on manual clock adjustment not only increases the inaccuracy of measurement but also introduces additional time costs. Summary of the Invention

[0004] To address or mitigate the problems in the prior art, in a first aspect, embodiments of this application provide a method for testing data read operations in non-volatile memory, including:

[0005] Configure test parameters;

[0006] Test data is generated based on the test parameters and burned into the memory. When the readback data is consistent with the test data, the test data is stored as the expected value.

[0007] Determine the clock cycle range for initially stable data readout;

[0008] A mapping relationship between read requests and address information is generated, and the test data burned into the memory is read according to the mapping relationship and the clock cycle range.

[0009] The test data obtained from all the read operations are compared with the expected value read to determine the critical clock cycle.

[0010] As a preferred embodiment of this application, determining the clock cycle range of the initially stable readout data includes:

[0011] The test data burned into the memory is read according to the initial minimum frequency of the clock.

[0012] If the test data read by the initial minimum frequency of the clock is consistent with the expected value, the first test is passed, and the clock period corresponding to the initial minimum frequency is the lower limit of the clock period range for initially stable data reading.

[0013] Based on the initial minimum frequency, the clock frequency is gradually increased to perform the next test in sequence until the test data read by the memory fails according to the gradually increasing clock frequency. Then, the clock period corresponding to the previous clock frequency of the current clock frequency is the upper limit of the clock period range for initially stabilizing data reading.

[0014] As a preferred embodiment of this application, the step of generating a mapping relationship between read requests and address information, and the step of performing a read operation on the test data burned into the memory according to the mapping relationship and the clock cycle range, includes:

[0015] Address information is generated using the falling edge of the same clock signal, and read requests are generated using the rising edge; or, address information is generated using the rising edge of the same clock signal, and read requests are generated using the falling edge, and then a mapping relationship between read requests and address information is generated based on multiple clock signals.

[0016] Once a read request is generated, the first sampling clock cycle corresponding to the read request begins to read the test data burned into the memory.

[0017] As a preferred embodiment of this application, the step of generating a mapping relationship between read requests and address information, and the step of performing a read operation on the test data burned into the memory according to the mapping relationship and the clock cycle range, includes:

[0018] The rising edge of the clock signal is used to alternately generate read requests and address information, and then a mapping relationship between read requests and address information is generated based on multiple clock signals;

[0019] After a read request is generated, the test data burned into the memory will be read starting from the second first sampling clock cycle at the beginning of the clock cycle corresponding to the read request.

[0020] In a preferred embodiment of this application, the test data acquired by all the read operations is compared with the expected value to determine the critical clock cycle, including:

[0021] The test data burned into the memory is read according to the first sampling clock to obtain the sampled data, and the sampled data is stored.

[0022] The expected value is read from the memory according to the second sampling clock in order to obtain the expected value;

[0023] Each sampled data is compared with the expected value. If the sampled data matches the expected value, it is determined that the clock cycle range of the initially stable readout data can be read back normally. In this case, the clock cycle in the clock cycle range of the initially stable readout data has not yet reached the critical clock cycle.

[0024] As a preferred embodiment of this application, after the clock cycle range of the initially stabilized readout data is sufficient for normal data readback, the process includes:

[0025] Return to the step of determining the clock cycle range for initially stable data readout, increase the clock frequency to read the test data burned into the memory and perform another test to determine the critical clock cycle.

[0026] In a preferred embodiment of this application, if the current sampled data is inconsistent with the expected value when compared with the expected value, then when the current test fails, the clock cycle in the previous test is determined to be the critical clock cycle.

[0027] As a preferred embodiment of this application, the configuration test parameters include selecting a clock source, configuring a clock frequency range, configuring a clock frequency step value, configuring test data type parameters, and configuring a test address range.

[0028] Secondly, embodiments of this application provide a hardware device, characterized in that it is used to perform the method described in any one of the first aspects.

[0029] Compared with existing technologies, this application provides a method and hardware device for testing non-volatile memory data read operations. After the test data is burned into the memory, the system can automatically perform test data read and comparison operations. Based on the comparison results to determine the expected value, the system can adaptively adjust the clock cycle range for initially stabilizing data reads to accurately capture the critical clock cycle for successful data reads. Therefore, the memory access time can be efficiently calculated. This method significantly improves test coverage and has high implementation flexibility, allowing for convenient application to various test platforms or carriers to achieve accurate measurement of the target memory read speed. Attached Figure Description

[0030] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0031] Figure 1 This is a schematic diagram and flowchart of a non-volatile memory data read operation test method provided in an embodiment of this application;

[0032] Figure 2 This is a timing diagram for the first read request implementation in step S4;

[0033] Figure 3 This is a timing diagram for the second read request implementation in step S4. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0035] This application provides a method for testing data read operations of non-volatile memory to solve the problems of low efficiency, poor flexibility and high cost of existing measurement techniques.

[0036] This application provides a measurement method for testing memory read speed, without limiting the carrier, which can be ASIC, FPGA, IP, etc. that can generate the process described in this invention. This application can provide a flexible and configurable test architecture, such as supporting the rapid development of dedicated FPGA test equipment or ASIC test chips, or it can be integrated into the target IC as a configurable IP core, significantly improving the practicality and deployment efficiency of the test solution.

[0037] The technical solution of this application is described in detail below:

[0038] like Figure 1 As shown, this application provides a method for testing non-volatile memory data read operations, including:

[0039] Step S1: Configure test parameters;

[0040] Specifically, the first step is to configure the test parameters. Key parameters include: clock, data type, and address range, as detailed below: Select the clock source CLK_s, configure the clock frequency range [fmin, fmax], configure the clock frequency step value fstep, configure the data type parameter data_type, and configure the test address range [Addr_min, Addr_max]. These parameters are used in subsequent steps.

[0041] In the embodiment of the application, memory data read operation testing is implemented using a Field Programmable Gate Array (FPGA). To achieve read speed testing, a read speed measurement IP needs to be implemented on the FPGA. The main test signals between the FPGA and the memory, including the basic read signal interface READ, the address signal interface ADDR, and the data output interface DOUT, are then connected.

[0042] Additionally, the test address space needs to be defined: ADDR0 to ADDR_max.

[0043] Step S2: Generate test data according to the test parameters and burn the test data into the memory. When the readback data is consistent with the test data, store the test data as the expected value.

[0044] It should be noted that this step generates test data based on the configured test data type parameter `data_type` and writes it to the memory. This step includes:

[0045] Test data De1, De2, De3, ..., Den are generated based on the configured test data type parameter data_type. Specifically, this includes retrieving the test data type parameter data_type from the configuration unit using get_data_config().

[0046] The three types of data are obtained or generated sequentially using get_user_data(), get_built_in_data(), and generate_random_data().

[0047] get_user_data(): Directly uses the user-configured data as test data;

[0048] `get_built_in_data()`: Uses built-in data as test data. Built-in data has the characteristics of adjacent data not being equal, and the data is complementary in the form of bits, bytes, half words, etc.

[0049] generate_random_data(): Generates random data as test data.

[0050] Select data based on the test data type parameter data_type.

[0051] The test data is written to the memory. This step can be done by reusing the memory controller or by directly generating a write operation.

[0052] The system performs a self-check for data integrity during the programming process. First, it reads back the test data from memory and then compares the read-back data with the generated test data. This ensures the correctness of the initial test data. Specifically, the system automatically reads back the test data Dr1, Dr2, Dr3, ..., Drrn.

[0053] If the system self-test confirms (De1=Dr1, De2=Dr2, De3=Dr3, ..., Den=Drn), then if yes, use the test data that has passed the integrity test as the expected value, that is, store De1, De2, De3, ..., Den as the expected value.

[0054] Step S3: Determine the clock cycle range for initially stable data readout;

[0055] Step S3 specifically includes:

[0056] The test data burned into the memory is read according to the initial minimum frequency of the clock.

[0057] If the test data read by the initial minimum frequency of the clock is consistent with the expected value, the first test is passed, and the clock period corresponding to the initial minimum frequency is the lower limit of the clock period range for initially stable data reading.

[0058] Based on the initial minimum frequency, the clock frequency is gradually increased to perform the next test in sequence until the test data read by the memory fails according to the gradually increasing clock frequency. Then, the clock period corresponding to the previous clock frequency of the current clock frequency is the upper limit of the clock period range for initially stabilizing data reading.

[0059] It should be noted that clock-related parameters are obtained from the configuration unit through the functions get_clk_source(), get_clk_freq_range(), and get_clk_step(). The system passes parameters such as the clock source CLK_s, clock frequency range [fmin, fmax], and frequency step value fstep to the clock generation unit. The clock generation unit outputs a clock with a frequency of f = fmin + fstep * n. The system automatically sets the frequency of the clock CLK. The initial minimum frequency fmin is relatively low, and the clock period corresponding to the initial minimum frequency fmin is much larger than the rated stable data readout minimum time TAA. This clock serves as the clock source for the test circuit, and the entire test circuit is tested with reference to this clock. The clock CLK can usually be generated by a phase-locked loop. After this round of testing is completed, the system automatically determines whether the test passes. If it passes, it means that the read request period generated by this clock period can still meet the rated stable data readout minimum time TAA. The system will further increase the clock frequency for the next test, and so on. As the clock frequency increases, the read request period will continuously approach the rated stable data readout minimum time TAA.

[0060] Step S4: Generate a mapping relationship between read requests and address information, and perform read operations on the test data burned into the memory according to the mapping relationship and the clock cycle range;

[0061] Step S4 can be implemented in two ways:

[0062] The first type:

[0063] Address information is generated using the falling edge of the same clock signal, and read requests are generated using the rising edge; or, address information is generated using the rising edge of the same clock signal, and read requests are generated using the falling edge, and then a mapping relationship between read requests and address information is generated based on multiple clock signals.

[0064] Once a read request is generated, the first sampling clock cycle corresponding to the read request begins to read the test data burned into the memory.

[0065] It should be noted that the READ request and ADDR address signal pairs are generated synchronously with the clock CLK. There are typically two implementation methods: 1) Using both the rising and falling edges of CLK simultaneously, such as generating ADDR on the falling edge and READ on the rising edge. This method reduces the clock frequency requirement but requires additional logic to use both the rising and falling edges of a single clock cycle to generate max+1 sets of READ and ADDR signal pairs based on the address space ADDR0 to ADDRmax.

[0066] After a read request is generated, synchronous sampling begins. The sampling clock varies depending on the implementation method described above. Corresponding to the above method: 1) Sampling begins at the next sampling clock after the read request clock, such as... Figure 2 The SAMPLE_CLK signal in the system.

[0067] The second type:

[0068] The rising edge of the clock signal is used to alternately generate read requests and address information, and then a mapping relationship between read requests and address information is generated based on multiple clock signals;

[0069] After a read request is generated, the test data burned into the memory will be read starting from the second first sampling clock cycle at the beginning of the clock cycle corresponding to the read request.

[0070] It should be noted that both methods use the rising edge of the clock CLK to alternately update READ and ADDR. The rising edge of the previous clock cycle generates READ, and the rising edge of the next clock cycle generates ADDR. This method simplifies the implementation logic, but requires an additional clock frequency to achieve the same effect as the previous method. Based on the address space ADDR0 to ADDRmax, max+1 sets of READ and ADDR signal pairs are generated.

[0071] After a read request is generated, synchronous sampling begins. The sampling clock varies depending on the implementation method described above. Corresponding to the above method: 2) Sampling begins at the second sampling clock corresponding to the read request, such as... Figure 3 The SAMPLE_CLK signal is shown. Data D1, D2, ..., Dn are sequentially acquired and read back.

[0072] Step S5: Compare the test data obtained from all the read operations with the expected value read to determine the critical clock cycle.

[0073] Step S5 specifically includes:

[0074] The test data burned into the memory is read according to the first sampling clock to obtain the sampled data, and the sampled data is stored.

[0075] The expected value is read from the memory according to the second sampling clock in order to obtain the expected value;

[0076] Each sampled data is compared with the expected value. If the sampled data matches the expected value, it is determined that the clock cycle range of the initially stable readout data can be read back normally. In this case, the clock cycle in the clock cycle range of the initially stable readout data has not yet reached the critical clock cycle.

[0077] The method further includes: after the clock cycle range of the initially stabilized read data can be read back normally, including:

[0078] Return to the step of determining the clock cycle range for initially stable data readout, increase the clock frequency to read the test data burned into the memory and perform another test to determine the critical clock cycle.

[0079] It should be noted that test data comparison can take several forms: 1) One is to store the data first and then compare it; 2) Real-time comparison, that is, real-time comparison begins at the next clock cycle after the sampling clock. Data equality is used as the comparison method to check the test data. If all current test data comparisons pass, it means that the clock cycle range for initially stable data reading determined in step S3 can be read back normally, i.e., the critical clock cycle has not yet been reached. At this time, return to step S3 to increase the clock frequency and measure again to adjust the clock cycle.

[0080] The method further includes: if the current sampled data is inconsistent with the expected value when compared with the expected value, then when the current test fails, the clock cycle in the previous test is determined to be the critical clock cycle.

[0081] It should be noted that if the local test fails, the clock cycle from the previous test is used as the critical period T. The minimum time TAA for stable data readout is calculated according to the two different implementation methods in step S4: Method 1) TAA = T + Td - Tr. Method 2) TAA = 2T + Td – Tr. Where Tr is the delay time of the read request signal READ from the read request generation unit to the memory port; Td is the delay time of the output test data D from the target memory port DOUT to the data acquisition unit; and T is the clock cycle.

[0082] In other words, the program jumps based on the results of the test data comparison. If the test fails, the clock cycle from the previous test is used as the critical clock cycle T. The minimum time TAA for stable data reading is calculated: TAA = 2T + Td – Tr. If the test passes, the program jumps to step S3 to determine the initial stable data reading clock cycle range and continues testing.

[0083] This application utilizes the rising and falling edges of the same clock cycle, or alternating rising edges, to generate read request signals. It then derives that the minimum time (TAA) for stable data readout is a multiple of either 1 or 2 times the clock cycle T, but the multiple is not limited to different methods of generating the read request signal. Furthermore, this application's automatic measurement method for non-volatile memory data read speed allows for automatic clock adjustment and closed-loop feedback for automatic acquisition and comparison of test data.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for testing data read operations of non-volatile memory, characterized in that, include: Configure test parameters; Test data is generated based on the test parameters and burned into the memory. When the readback data is consistent with the test data, the test data is stored as the expected value. Determine the clock cycle range for initially stable data readout; A mapping relationship between read requests and address information is generated, and the test data burned into the memory is read according to the mapping relationship and the clock cycle range. The test data obtained from all the read operations are compared with the expected value read to determine the critical clock cycle.

2. The method for testing data read operations of a non-volatile memory as described in claim 1, characterized in that, The determination of the clock cycle range for initially stable readout data includes: The test data burned into the memory is read according to the initial minimum frequency of the clock. If the test data read by the initial minimum frequency of the clock is consistent with the expected value, the first test is passed, and the clock period corresponding to the initial minimum frequency is the lower limit of the clock period range for initially stable data reading. Based on the initial minimum frequency, the clock frequency is gradually increased to perform the next test in sequence until the test data read by the memory fails according to the gradually increasing clock frequency. Then, the clock period corresponding to the previous clock frequency of the current clock frequency is the upper limit of the clock period range for initially stabilizing data reading.

3. The method for testing data read operations of non-volatile memory as described in claim 1, characterized in that, The process of generating a mapping relationship between read requests and address information, and performing read operations on the test data burned into the memory based on the mapping relationship and the clock cycle range, includes: Address information is generated using the falling edge of the same clock signal, and read requests are generated using the rising edge; or, address information is generated using the rising edge of the same clock signal, and read requests are generated using the falling edge, and then a mapping relationship between read requests and address information is generated based on multiple clock signals. Once a read request is generated, the first sampling clock cycle corresponding to the read request begins to read the test data burned into the memory.

4. The method for testing data read operations of a non-volatile memory as described in claim 1, characterized in that, The process of generating a mapping relationship between read requests and address information, and performing read operations on the test data burned into the memory based on the mapping relationship and the clock cycle range, includes: The rising edge of the clock signal is used to alternately generate read requests and address information, and then a mapping relationship between read requests and address information is generated based on multiple clock signals; After a read request is generated, the test data burned into the memory will be read starting from the second first sampling clock cycle at the beginning of the clock cycle corresponding to the read request.

5. The method for testing data read operations of a non-volatile memory as described in claim 1, characterized in that, Compare the test data acquired by all the read operations with the expected value to determine the critical clock cycle, including: The test data burned into the memory is read according to the first sampling clock to obtain the sampled data, and the sampled data is stored. The expected value is read from the memory according to the second sampling clock in order to obtain the expected value; Each sampled data is compared with the expected value. If the sampled data matches the expected value, it is determined that the clock cycle range of the initially stable readout data can be read back normally. In this case, the clock cycle in the clock cycle range of the initially stable readout data has not yet reached the critical clock cycle.

6. The method for testing data read operations of a non-volatile memory as described in claim 5, characterized in that, After the clock cycle range of the initially stabilized readout data is sufficient for normal data readback, the following is included: Return to the step of determining the clock cycle range for initially stable data readout, increase the clock frequency to read the test data burned into the memory and perform another test to determine the critical clock cycle.

7. The method for testing data read operations of a non-volatile memory as described in claim 5, characterized in that, If the current sampled data is inconsistent with the expected value when compared with the expected value, then if the current test fails, the clock cycle in the previous test is determined to be the critical clock cycle.

8. The method for testing data read operations of a non-volatile memory as described in claim 1, characterized in that, The configuration test parameters include selecting a clock source, configuring the clock frequency range, configuring the clock frequency step value, configuring test data type parameters, and configuring the test address range.

9. A hardware device, characterized in that, Used to perform the method as described in any one of claims 1 to 8.

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