A waveform recording and playback-based interface verification method and device
By using an interface verification method based on waveform recording and playback, the problems of low simulation efficiency and insufficient timing fidelity in DPI interface verification are solved, achieving efficient interface verification and restoration of timing details in real-world scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CIX TECH (SHANGHAI) CO LTD
- Filing Date
- 2026-03-03
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies suffer from low simulation efficiency and insufficient timing fidelity in DPI interface verification, especially at high resolutions where signal timing margin and signal integrity requirements are stringent and conventional methods are difficult to meet.
An interface verification method based on waveform recording and playback is adopted. Timing files are obtained by matching the recording method, and playback is performed based on multi-dimensional parameters to identify and process the back voltage signal, thereby improving simulation efficiency and timing fidelity.
It significantly reduces the number of simulation events, improves simulation efficiency, can reproduce the timing details in real-world scenarios, and enables efficient interface verification.
Smart Images
Figure CN121765982B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of simulation interface verification technology, and more specifically, to an interface verification method and apparatus based on waveform recording and playback. Background Technology
[0002] As display resolutions continue to increase, DPI interface verification also faces challenges. At high resolutions, pixel clock frequencies increase significantly, placing more stringent demands on signal timing margins and signal integrity.
[0003] Currently, conventional interface verification employs two approaches: full-system simulation and independent BFM stimulus methods. In full-system simulation, the Design Under Test (DUT) and upstream / downstream IPs are integrated into a unified verification platform (such as UVM). Stimuli are generated using transaction-level drivers, and responses are collected by a monitor. This requires the complete compilation of all relevant modules, and the number of simulation events increases exponentially with the design size. In contrast, the independent BFM stimulus method develops a Bus Function Model (BFM) for the target interface and generates transaction-level stimuli through predefined test sequences.
[0004] However, the full system simulation method requires loading the complete DUT and associated IP, which results in a large amount of simulation memory usage and single test case runtime for large SoC projects, leading to low simulation efficiency; while the independent BFM stimulus method is difficult to reproduce the timing details in real-world scenarios and lacks timing fidelity. Summary of the Invention
[0005] In view of this, the purpose of this application is to provide an interface verification method and apparatus based on waveform recording and playback. The method acquires timing files through a matching recording method, plays back the timing files based on multi-dimensional parameters, determines whether a back voltage signal is detected during playback, performs corresponding processing, and performs interface verification after processing. The number of simulation events is greatly reduced, the simulation efficiency is improved, the timing details in the real scene can be restored, and the timing fidelity is reflected.
[0006] In a first aspect, embodiments of this application provide an interface verification method based on waveform recording and playback, the method comprising:
[0007] In response to the start of the timing recording phase, the simulation results of the simulation waveform file in the target format are matched with the corresponding recording method, and the timing file is obtained based on the recording method; wherein, the recording method is a waveform extraction method or a log extraction method;
[0008] In response to the start of the timing playback phase, the timing file is loaded and multi-dimensional parameters are configured. The timing file is then played back based on the multi-dimensional parameters, and it is determined whether a back pressure signal is detected during the playback process.
[0009] When a back pressure signal is detected, back pressure injection is activated, and the corresponding first processing method is executed. After the processing is completed, verification is performed based on the preset interface signal drive until the verification is completed.
[0010] If no reverse pressure signal is detected, the timing sequence is continuously replayed and verification is performed based on the interface signal drive until the verification is completed.
[0011] In one possible implementation, the simulation results based on the target format simulation waveform file are matched with a corresponding recording method, and a timing file is obtained based on the recording method, including:
[0012] If the simulation result of the simulation waveform file contains a waveform, then the corresponding recording method is determined to be the waveform extraction method;
[0013] Based on the preset configuration information of the waveform extraction engine, the preset waveform reading library is called to read the simulation waveform file, extract the corresponding waveform information, and generate the corresponding timing file based on the waveform information.
[0014] In one possible implementation, the simulation results based on the target format simulation waveform file are matched with a corresponding recording method, and a timing file is obtained based on the recording method, including:
[0015] If the simulation result of the simulation waveform file does not contain a waveform, then the corresponding recording method is determined to be the log extraction method;
[0016] Based on a preset log analysis library, a log extraction tool is obtained. Based on the log extraction tool, a preset time-series packaging library is called to extract BFM transaction logs, and a corresponding time-series file is generated based on the BFM transaction logs.
[0017] In one possible implementation, reading the simulation waveform file includes:
[0018] Based on the waveform extraction engine, all target signals that undergo transitions are monitored and recorded in each clock cycle; wherein, each clock cycle includes a rising edge and a falling edge;
[0019] For each clock cycle's rising / falling edge, the waveform extraction engine captures all target signals that undergo transitions within that clock cycle, and for each target signal, records the transition information.
[0020] In one possible implementation, generating the corresponding timing file includes:
[0021] Differential encoding is performed on the transition information to obtain compressed transition information;
[0022] The compressed transition information and preset metadata are packaged together to obtain a time-series file; wherein, the metadata represents user-defined tags.
[0023] In one possible implementation, the log analysis library includes a constructed target syntax tree; the extraction of BFM transaction logs includes:
[0024] Analyze the log format of the BFM transaction log;
[0025] Based on the target syntax tree, corresponding syntax rules are defined according to the log format of the BFM transaction log to extract the BFM transaction log.
[0026] In one possible implementation, generating the corresponding timing file includes:
[0027] The BFM transaction log is parsed based on the syntax rules to convert the text lines of the BFM transaction log into structured data objects, thereby obtaining the corresponding log parsing information;
[0028] Based on the log parsing information and in accordance with the timing rules of the preset target bus protocol, the corresponding signal level transition sequence is reconstructed, and the signal level transition sequence is encapsulated and output as a timing file in a unified target format.
[0029] Secondly, embodiments of this application also provide an interface verification device based on waveform recording and playback, the device comprising:
[0030] The recording module is used to respond to the start of the timing recording phase by matching the simulation results of the simulation waveform file in the target format with the corresponding recording method, and obtaining the timing file based on the recording method; wherein, the recording method is a waveform extraction method or a log extraction method;
[0031] The playback module is used to load the timing file and configure multi-dimensional parameters in response to the start timing playback stage, and to perform timing playback on the timing file based on the multi-dimensional parameters, and to determine whether a back pressure signal is detected during the playback process.
[0032] The first verification module is used to activate back pressure injection and execute the corresponding first processing method when a back pressure signal is detected, and to perform verification based on a preset interface signal after the processing is completed, until the verification is completed.
[0033] The second verification module is used to continuously replay the timing sequence and perform verification based on the interface signal drive when no reverse pressure signal is detected, until the verification is completed.
[0034] In one possible implementation, the recording module is specifically used for:
[0035] If the simulation result of the simulation waveform file contains a waveform, then the corresponding recording method is determined to be the waveform extraction method;
[0036] Based on the preset configuration information of the waveform extraction engine, the preset waveform reading library is called to read the simulation waveform file, extract the corresponding waveform information, and generate the corresponding timing file based on the waveform information.
[0037] In one possible implementation, the recording module is specifically used for:
[0038] If the simulation result of the simulation waveform file does not contain a waveform, then the corresponding recording method is determined to be the log extraction method;
[0039] Based on a preset log analysis library, a log extraction tool is obtained. Based on the log extraction tool, a preset time-series packaging library is called to extract BFM transaction logs, and a corresponding time-series file is generated based on the BFM transaction logs.
[0040] In one possible implementation, the recording module is specifically used for:
[0041] Based on the waveform extraction engine, all target signals that undergo transitions are monitored and recorded in each clock cycle; wherein, each clock cycle includes a rising edge and a falling edge;
[0042] For each clock cycle's rising / falling edge, the waveform extraction engine captures all target signals that undergo transitions within that clock cycle, and for each target signal, records the transition information.
[0043] In one possible implementation, the recording module is specifically used for:
[0044] Differential encoding is performed on the transition information to obtain compressed transition information;
[0045] The compressed transition information and preset metadata are packaged together to obtain a time-series file; wherein, the metadata represents user-defined tags.
[0046] In one possible implementation, the log analysis library includes a constructed target syntax tree; the recording module is specifically used for:
[0047] Analyze the log format of the BFM transaction log;
[0048] Based on the target syntax tree, corresponding syntax rules are defined according to the log format of the BFM transaction log to extract the BFM transaction log.
[0049] In one possible implementation, the recording module is specifically used for:
[0050] The BFM transaction log is parsed based on the syntax rules to convert the text lines of the BFM transaction log into structured data objects, thereby obtaining the corresponding log parsing information;
[0051] Based on the log parsing information and in accordance with the timing rules of the preset target bus protocol, the corresponding signal level transition sequence is reconstructed, and the signal level transition sequence is encapsulated and output as a timing file in a unified target format.
[0052] Thirdly, embodiments of this application provide an electronic device, including: a processor, a storage medium, and a bus. The storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the interface verification method based on waveform recording and playback as described in any of the first aspects.
[0053] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, performs the steps of the interface verification method based on waveform recording and playback as described in any one of the first aspects.
[0054] This application provides an interface verification method and apparatus based on waveform recording and playback. In response to the start of timing recording, a corresponding recording method is matched based on the simulation results of a target format simulation waveform file, and a timing file is obtained based on the recording method. In response to the start of timing playback, the timing file is loaded and multi-dimensional parameters are configured. Timing playback is performed on the timing file based on these multi-dimensional parameters, and it is determined whether a back pressure signal is detected during playback. If a back pressure signal is detected, back pressure injection is activated, and a corresponding first processing method is executed. After processing, verification is performed based on a preset interface signal until verification is complete. If no back pressure signal is detected, timing playback continues, and verification is performed based on the interface signal until verification is complete. This application obtains timing files through a matched recording method, plays back the timing files based on multi-dimensional parameters, determines whether a back pressure signal is detected during playback, performs corresponding processing, and performs interface verification after processing. This significantly reduces the number of simulation events, improves simulation efficiency, and can reproduce timing details in real-world scenarios, demonstrating high timing fidelity.
[0055] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0056] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0057] Figure 1 This is a flowchart of an interface verification method based on waveform recording and playback provided in an embodiment of this application;
[0058] Figure 2 This is a schematic diagram of the timing recording process;
[0059] Figure 3 This is a schematic diagram of the timing playback process;
[0060] Figure 4 This is a schematic diagram of the timing playback process using MIPI-DPI2 as an example;
[0061] Figure 5 This is a schematic diagram of the structure of an interface verification device based on waveform recording and playback provided in the embodiments of this application;
[0062] Figure 6 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.
[0064] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0065] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.
[0066] As display resolutions continue to increase, DPI interface verification also faces challenges. At high resolutions, pixel clock frequencies increase significantly, placing more stringent demands on signal timing margins and signal integrity.
[0067] Currently, conventional interface verification employs two approaches: full-system simulation and independent BFM stimulus methods. In full-system simulation, the Design Under Test (DUT) and upstream / downstream IPs are integrated into a unified verification platform (such as UVM). Stimuli are generated using transaction-level drivers, and responses are collected by a monitor. This requires the complete compilation of all relevant modules, and the number of simulation events increases exponentially with the design size. In contrast, the independent BFM stimulus method develops a Bus Function Model (BFM) for the target interface and generates transaction-level stimuli through predefined test sequences.
[0068] However, the full system simulation method requires loading the complete DUT and associated IP, which results in a large amount of simulation memory usage and single test case runtime for large SoC projects, leading to low simulation efficiency; while the independent BFM stimulus method is difficult to reproduce the timing details in real-world scenarios and lacks timing fidelity.
[0069] To address this issue, this application provides an interface verification method and apparatus based on waveform recording and playback. The method acquires timing files through a matched recording method, plays back the timing files based on multi-dimensional parameters, determines whether a back voltage signal is detected during playback, and performs corresponding processing. After processing, interface verification is performed. The number of simulation events is greatly reduced, simulation efficiency is improved, and timing details in real-world scenarios can be reproduced, demonstrating timing fidelity.
[0070] Figure 1 This is a flowchart of an interface verification method based on waveform recording and playback provided in an embodiment of this application. Figure 1 As shown, the interface verification method based on waveform recording and playback in this application embodiment may specifically include:
[0071] S101. In response to the start of the timing recording phase, the simulation results of the simulation waveform file in the target format are matched with the corresponding recording method, and the timing file is obtained based on the recording method.
[0072] S102. In response to the start of the timing playback phase, load the timing file and configure multi-dimensional parameters, perform timing playback on the timing file based on the multi-dimensional parameters, and determine whether a back pressure signal is detected during the playback process.
[0073] S103. When a back pressure signal is detected, back pressure injection is activated, and the corresponding first processing method is executed. After the processing is completed, verification is performed based on the preset interface signal drive until the verification is completed.
[0074] S104. If no reverse voltage signal is detected, the timing sequence will be continuously replayed and verified based on the interface signal drive until the verification is completed.
[0075] In the above-mentioned interface verification method based on waveform recording and playback, timing files are obtained by matching the recording method, and the timing files are played back based on multi-dimensional parameters. It is determined whether a back voltage signal is detected during the playback process and corresponding processing is performed. After the processing is completed, interface verification is performed. The number of simulation events is greatly reduced, the simulation efficiency is improved, the timing details in the real scene can be restored, and the timing fidelity is reflected.
[0076] The exemplary steps described above in the embodiments of this application are illustrated below with specific examples:
[0077] S101, in response to the start of the timing recording phase, matches the simulation results of the simulation waveform file in the target format with the corresponding recording method, and obtains the timing file based on the recording method; the recording method is either waveform extraction method or log extraction method.
[0078] In this embodiment, the target format can be FSDB, VCD, or similar formats. The recording method represents the data extraction method required for timing recording. The recording method can be either waveform extraction or log extraction. The timing file is a .timerec timing file. At the start of the timing recording phase, the recording method is matched based on the simulation results of the simulation waveform file in FSDB or VCD formats, and a timing file is generated under that recording method for subsequent processing. For example, as... Figure 2 As shown.
[0079] In some implementations, in response to the presence of waveforms in the simulation results of the simulation waveform file, the corresponding recording method is determined to be a waveform extraction method. Based on the input of preset waveform extraction engine configuration information, the simulation waveform file is read by calling a preset waveform reading library, the corresponding waveform information is extracted, and a corresponding timing file is generated based on the waveform information. The configuration information includes at least a standardized description file, HDL signal path, and time window settings; the waveform reading library is a Python waveform reading library provided by an EDA vendor or an open-source library.
[0080] Specifically, when the simulation result of the simulation waveform file contains a waveform, waveform extraction is performed. This involves using the waveform extraction engine to call the waveform reading library to read the simulation waveform file based on the input standardized description file, HDL signal path, and time window settings. The waveform information is then extracted and a .timerec timing file is generated based on this information. For example, ... Figure 2 As shown.
[0081] Optionally, the waveform extraction engine monitors and records all target signals that toggle in each clock cycle; for each clock cycle's rising / falling edge, the waveform extraction engine captures all target signals that toggle within that clock cycle, and for each target signal, records the toggle information. The toggle information includes at least the toggle value and the delay time of the toggle event relative to the clock rising edge. Each clock cycle includes a rising edge and a falling edge.
[0082] It should be noted that this application does not sample all signals in full for each clock cycle, but only monitors and records signals that toggle. For each rising / falling edge of the clock, all signals that toggle within that clock cycle are captured. For each toggle signal, its toggle value and the delay time of the toggle event relative to the rising edge of the clock are recorded precisely.
[0083] Thus, since static and unchanging signals are not recorded, extremely high data compression is achieved while perfectly preserving key digital timing characteristics.
[0084] Optionally, when generating the corresponding time series file, the transition information is differentially encoded (Delta Encoding) to obtain compressed transition information; the compressed transition information and preset metadata are then packaged together to obtain the time series file. The metadata represents user-defined tags and includes at least one of a signal mapping table and a timestamp index.
[0085] Specifically, transition information refers to signal transition timing data, which includes timestamps, signal identifiers, transition values, relative delays, etc. After further compression using differential encoding, it is packaged together with metadata (such as signal mapping tables and timestamp indexes) to generate a .timrec timing file. Finally, the data is serialized into a custom, efficient binary format and typically uses gzip for lossless compression to generate the final .timrec timing record file.
[0086] In some implementations, in response to the absence of waveforms in the simulation results of the simulation waveform file, the corresponding recording method is determined to be the log extraction method; a log extraction tool is obtained based on a preset log analysis library, a preset timing packaging library is called based on the log extraction tool to extract BFM transaction logs, and a corresponding timing file is generated based on the BFM transaction logs.
[0087] The log analysis library includes a constructed target syntax tree, such as a BNF (Backkos-Noor Normal Form) syntax tree. Additionally, this application provides a Python-based log analysis library for the general and flexible extraction of key information from unstructured log text, the core of which is the constructed BNF syntax tree.
[0088] Specifically, if the simulation waveform file does not contain a waveform, log extraction is performed. This involves obtaining a log extraction tool (e.g., a log extraction script) from a log analysis library, using this tool to call a time-series packaging library to capture BFM transaction logs, and generating a .timerec time-series file based on the BFM transaction logs. For example, ... Figure 2 As shown, a log extraction script is constructed that is responsible for executing and capturing the transaction logs printed by BFM (usually written in SystemVerilog) via $display or a similar function.
[0089] Optionally, when extracting BFM transaction logs, the log format of the BFM transaction logs is analyzed; and based on the target syntax tree, corresponding syntax rules are defined to extract the BFM transaction logs.
[0090] Specifically, we first analyze the format of the BFM transaction log. For example, an AXI write address channel log might look like this: [AXI_AW] TIME=100ns, ADDR=0x4000_0000, ID=1, LEN=7.
[0091] Optionally, when generating the corresponding timing file, the BFM transaction log is parsed based on syntax rules to convert the text lines of the BFM transaction log into structured data objects, obtaining the corresponding log parsing information. Based on the log parsing information and according to the timing rules of the preset target bus protocol, the corresponding signal level transition sequence is reconstructed, and the signal level transition sequence is encapsulated and output as a timing file in a unified target format. The log parsing information includes at least the transaction type, timestamp, and data value.
[0092] Therefore, this method allows for the rapid definition of syntax rules for a specific log format, transforming text lines into structured data objects. Based on the parsed transaction type, timestamp, and data value, the corresponding signal level transition sequences are reconstructed according to the timing rules of the target bus protocol. Finally, these reconstructed signal transition sequences are encapsulated and output as a unified .timrec timing file for playback.
[0093] It should be noted that if the simulation results of the simulation waveform file lack both waveforms and logs, the corresponding recording method will be either waveform extraction or log extraction. In short, when the simulation results of the simulation waveform file lack both waveforms and logs, either waveform extraction or log extraction can be used.
[0094] S102, in response to the start of timing playback phase, loads timing file and configures multi-dimensional parameters, performs timing playback on timing file based on multi-dimensional parameters, and determines whether a back voltage signal is detected during playback.
[0095] The multi-dimensional parameters include at least clock frequency, reverse voltage recognition enable, and BFM mode. The BFM mode includes at least independent drive, single-drive monitoring closed loop, and dual-drive monitoring closed loop, as shown in Table 1 below:
[0096] Table 1
[0097]
[0098] In this embodiment of the application, after obtaining the timing file through timing recording, during the timing playback stage, the timing file obtained in step S101 is loaded and multi-dimensional parameters such as clock frequency, backvoltage recognition enable, and BFM mode are configured. The timing file is then played back to determine whether a backvoltage signal is detected during playback, in order to perform subsequent processing. For example, as... Figure 3 As shown.
[0099] S103, when a back pressure signal is detected, back pressure injection is activated and the corresponding first processing method is executed. After the processing is completed, verification is performed based on the preset interface signal drive until the verification is completed.
[0100] In this embodiment, the first processing method includes at least pausing data transmission, inserting a wait period, and maintaining the signal state. When a backpressure signal is detected in step S102, backpressure injection is activated, and the corresponding first processing method is executed. After processing, interface signal-driven verification is performed until verification is complete. For example, such as Figure 3 As shown.
[0101] S104: When no reverse voltage signal is detected, the timing sequence is continuously played back and verification is performed based on the interface signal drive until the verification is completed.
[0102] In this embodiment of the application, if no reverse voltage signal is detected in step S102, the timing sequence is continuously replayed, and verification is performed based on interface signal drive until verification is completed. For example, as Figure 3 As shown.
[0103] The interface verification method based on waveform recording and playback provided in this application, in response to the start timing recording stage, matches the simulation results of the target format simulation waveform file with the corresponding recording method, and obtains the timing file based on the recording method. In response to the start timing playback stage, loads the timing file and configures multi-dimensional parameters, and performs timing playback on the timing file based on the multi-dimensional parameters. It also determines whether a back pressure signal is detected during playback. If a back pressure signal is detected, back pressure injection is activated, and the corresponding first processing method is executed. After processing, verification is performed based on a preset interface signal driver until verification is complete. If no back pressure signal is detected, timing playback continues, and verification is performed based on the interface signal driver until verification is complete. The interface verification method based on waveform recording and playback of this application obtains the timing file through the matched recording method, plays back the timing file based on multi-dimensional parameters, determines whether a back pressure signal is detected during playback, performs corresponding processing, and performs interface verification after processing. This greatly reduces the number of simulation events, improves simulation efficiency, can restore the timing details in the real scene, and reflects timing fidelity.
[0104] Furthermore, a timing file is recorded in a preset recording environment and played back in a preset playback environment, and then verified in the selected BFM mode. For example, a configuration file is recorded in a SoC environment and the timing file is played back in a preset DSI-IP environment for verification in the BFM mode.
[0105] For example, taking MIPI-DPI2 as an example, during waveform extraction, the DPU-DPI interface output is recorded in the SoC environment, specifically the recorded signals: vsync, hsync, pix_valid, pix_ready, pix_data[29:0]. The example configuration file is read, and a timing file is finally generated. Then, the timing is replayed in the DSI-IP environment, specifically by mounting Replay-BFM to the DSI input port, for example, as shown... Figure 4 As shown.
[0106] In summary, this application has the following technical effects:
[0107] 1. Significantly improved simulation efficiency: Compared to full-system simulation, the number of events is reduced, and memory usage is decreased. Furthermore, playback within the DSI-IP small environment further enhances simulation efficiency.
[0108] 2. Timing fidelity: Improved signal transition accuracy reduces resource consumption and enhances the reliability of subsystem simulation results.
[0109] 3. Cross-project reuse: The DPU-DPI timing of SoC-1 can be directly used to verify the DSI-IP of SoC-2 (supporting simulation without delay back-annotation), that is, the timing file recorded on one SoC can verify another SoC, realizing cross-project reuse.
[0110] 4. Back pressure intelligent response: Activate back pressure injection after detecting a back pressure signal.
[0111] 5. Storage cost optimization: Differential coding compression compresses the simulation waveform into a smaller time-series file.
[0112] 6. High interface compatibility: The standardized bus description file in the input configuration supports automatic identification of bus protocols such as AXI / AHB / MIPI from standard bus configuration files.
[0113] Figure 5 This is a schematic diagram of the interface verification device based on waveform recording and playback provided in the embodiments of this application; as shown below. Figure 5 As shown, the interface verification device 500 based on waveform recording and playback in this embodiment of the application may specifically include:
[0114] The recording module 501 is used to respond to the start of the timing recording stage by matching the simulation results of the simulation waveform file in the target format with the corresponding recording method, and to obtain the timing file based on the recording method; wherein, the recording method is either waveform extraction method or log extraction method.
[0115] The playback module 502 is used to load the timing file and configure multi-dimensional parameters in response to the start timing playback stage, and to perform timing playback on the timing file based on the multi-dimensional parameters, and to determine whether a back voltage signal is detected during the playback process.
[0116] The first verification module 503 is used to activate back pressure injection when a back pressure signal is detected, execute the corresponding first processing method, and perform verification based on a preset interface signal after the processing is completed, until the verification is completed.
[0117] The second verification module 504 is used to continuously replay the timing sequence and perform verification based on the interface signal drive when no reverse voltage signal is detected, until the verification is completed.
[0118] In one possible implementation, the recording module is specifically used for:
[0119] If the simulation result of the simulation waveform file contains a waveform, then the corresponding recording method is determined to be the waveform extraction method;
[0120] Based on the preset configuration information of the waveform extraction engine, the preset waveform reading library is called to read the simulation waveform file, extract the corresponding waveform information, and generate the corresponding timing file based on the waveform information.
[0121] In one possible implementation, the recording module is specifically used for:
[0122] If the simulation result of the simulation waveform file does not contain a waveform, then the corresponding recording method is determined to be the log extraction method;
[0123] The system obtains a log extraction tool based on a pre-defined log analysis library, then uses the log extraction tool to call a pre-defined time-series packaging library to extract BFM transaction logs, and finally generates corresponding time-series files based on the BFM transaction logs.
[0124] In one possible implementation, the recording module is specifically used for:
[0125] The waveform extraction engine monitors and records all target signals that undergo transitions in each clock cycle; each clock cycle includes a rising edge and a falling edge.
[0126] For each clock cycle's rising / falling edge, the waveform extraction engine captures all target signals that transition within that clock cycle, and records the transition information for each target signal.
[0127] In one possible implementation, the recording module is specifically used for:
[0128] Differential encoding is performed on the transition information to obtain compressed transition information;
[0129] The compressed transition information and preset metadata are packaged together to obtain a time series file; the metadata represents user-defined tags.
[0130] In one possible implementation, the log analysis library includes a constructed target syntax tree; and a recording module, specifically used for:
[0131] Analyze the log format of the BFM transaction log;
[0132] Based on the target syntax tree, corresponding syntax rules are defined according to the log format of the BFM transaction log to extract the BFM transaction log.
[0133] In one possible implementation, the recording module is specifically used for:
[0134] The BFM transaction log is parsed based on syntax rules to convert the text lines of the BFM transaction log into structured data objects and obtain the corresponding log parsing information.
[0135] Based on log parsing information and according to the timing rules of the preset target bus protocol, the corresponding signal level transition sequence is reconstructed, and the signal level transition sequence is encapsulated and output as a timing file in a unified target format.
[0136] The interface verification device based on waveform recording and playback provided in this application, in response to the start of timing recording, matches the simulation results of the target format simulation waveform file with the corresponding recording method, and obtains the timing file based on the recording method. In response to the start of timing playback, it loads the timing file and configures multi-dimensional parameters, and performs timing playback on the timing file based on the multi-dimensional parameters. It also determines whether a back pressure signal is detected during playback. If a back pressure signal is detected, back pressure injection is activated, and the corresponding first processing method is executed. After processing, verification is performed based on a preset interface signal drive until verification is completed. If no back pressure signal is detected, timing playback continues, and verification is performed based on the interface signal drive until verification is completed. The interface verification device based on waveform recording and playback of this application obtains the timing file through a matched recording method, plays back the timing file based on multi-dimensional parameters, determines whether a back pressure signal is detected during playback, performs corresponding processing, and performs interface verification after processing. This greatly reduces the number of simulation events, improves simulation efficiency, can restore the timing details in the real scene, and reflects timing fidelity.
[0137] like Figure 6As shown in the embodiment of this application, an electronic device 600 includes a processor 601, a memory 602, and a bus. The memory 602 stores machine-readable instructions that can be executed by the processor 601. When the electronic device is running, the processor 601 communicates with the memory 602 via the bus. The processor 601 executes the machine-readable instructions to perform the steps of the interface verification method based on waveform recording and playback as described above.
[0138] Specifically, the memory 602 and processor 601 mentioned above can be general-purpose memory and processor, without any specific limitations. When the processor 601 runs the computer program stored in the memory 602, it can execute the interface verification method based on waveform recording and playback.
[0139] Corresponding to the above-described interface verification method based on waveform recording and playback, this application embodiment also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the above-described interface verification method based on waveform recording and playback.
[0140] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and devices described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces; the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.
[0141] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0142] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0143] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the deployment methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, external hard drives, ROM, RAM, magnetic disks, or optical disks.
[0144] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. An interface verification method based on waveform recording and playback, characterized in that, The method includes: In response to the start of the timing recording phase, the simulation results of the simulation waveform file in the target format are matched with the corresponding recording method, and the timing file is obtained based on the recording method; wherein, the recording method is a waveform extraction method or a log extraction method; In response to the start of the timing playback phase, the timing file is loaded and multi-dimensional parameters are configured. The timing file is then played back based on the multi-dimensional parameters, and it is determined whether a back pressure signal is detected during the playback process. When a back pressure signal is detected, back pressure injection is activated, and the corresponding first processing method is executed. After the processing is completed, verification is performed based on the preset interface signal drive until the verification is completed. If no reverse pressure signal is detected, the timing sequence is continuously replayed and verification is performed based on the interface signal drive until the verification is completed.
2. The method according to claim 1, characterized in that, The simulation results based on the target format simulation waveform file are matched with the corresponding recording method, and a timing file is obtained based on the recording method, including: If the simulation result of the simulation waveform file contains a waveform, then the corresponding recording method is determined to be the waveform extraction method; Based on the preset configuration information of the waveform extraction engine, the preset waveform reading library is called to read the simulation waveform file, extract the corresponding waveform information, and generate the corresponding timing file based on the waveform information.
3. The method according to claim 1, characterized in that, The simulation results based on the target format simulation waveform file are matched with the corresponding recording method, and a timing file is obtained based on the recording method, including: If the simulation result of the simulation waveform file does not contain a waveform, then the corresponding recording method is determined to be the log extraction method; Based on a preset log analysis library, a log extraction tool is obtained. Based on the log extraction tool, a preset time-series packaging library is called to extract BFM transaction logs, and a corresponding time-series file is generated based on the BFM transaction logs.
4. The method according to claim 2, characterized in that, The reading of the simulation waveform file includes: Based on the waveform extraction engine, all target signals that undergo transitions are monitored and recorded in each clock cycle; wherein, each clock cycle includes a rising edge and a falling edge; For each clock cycle's rising / falling edge, the waveform extraction engine captures all target signals that undergo transitions within that clock cycle, and for each target signal, records the transition information.
5. The method according to claim 4, characterized in that, The generation of the corresponding timing file includes: Differential encoding is performed on the transition information to obtain compressed transition information; The compressed transition information and preset metadata are packaged together to obtain a time-series file; wherein, the metadata represents user-defined tags.
6. The method according to claim 3, characterized in that, The log analysis library includes the constructed target syntax tree; The extraction of BFM transaction logs includes: Analyze the log format of the BFM transaction log; Based on the target syntax tree, corresponding syntax rules are defined according to the log format of the BFM transaction log to extract the BFM transaction log.
7. The method according to claim 6, characterized in that, The generation of the corresponding timing file includes: The BFM transaction log is parsed based on the syntax rules to convert the text lines of the BFM transaction log into structured data objects, thereby obtaining the corresponding log parsing information; Based on the log parsing information and in accordance with the timing rules of the preset target bus protocol, the corresponding signal level transition sequence is reconstructed, and the signal level transition sequence is encapsulated and output as a timing file in a unified target format.
8. An interface verification device based on waveform recording and playback, characterized in that, The device includes: The recording module is used to respond to the start of the timing recording phase by matching the simulation results of the simulation waveform file in the target format with the corresponding recording method, and obtaining the timing file based on the recording method; wherein, the recording method is a waveform extraction method or a log extraction method; The playback module is used to load the timing file and configure multi-dimensional parameters in response to the start timing playback stage, and to perform timing playback on the timing file based on the multi-dimensional parameters, and to determine whether a back pressure signal is detected during the playback process. The first verification module is used to activate back pressure injection and execute the corresponding first processing method when a back pressure signal is detected, and to perform verification based on a preset interface signal after the processing is completed, until the verification is completed. The second verification module is used to continuously replay the timing sequence and perform verification based on the interface signal drive when no reverse pressure signal is detected, until the verification is completed.
9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of the interface verification method based on waveform recording and playback as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the interface verification method based on waveform recording and playback as described in any one of claims 1 to 7.