Deadlock detection and elimination of mesh networks for processor-based systems

Abstract

Systems and methods for detecting deadlocks in cyclic dependencies between a set of multiple nodes in a mesh network are disclosed. In some aspects, each of the nodes has a stagnation detection circuit. The stagnation detection circuit of each of the nodes operates by providing a stagnation output that is asserted not only when the linked input and output pipeline circuits are stagnated, but also when a stagnation input from an upstream node indicates that the upstream node is stagnated. The stagnation output is provided as a stagnation input to a downstream node. In this manner, the stagnation output of the stagnation detection circuit is stable and asserted when there is a deadlock in cyclic dependence between closed loops of nodes in the mesh network.

Description

Technical Field

[0001] This disclosure generally relates to systems and methods for detecting deadlocks in mesh networks. Background Technology

[0002] The cores in a System-on-a-Chip (SoC) typically communicate via a mesh network of routers. The routers receive input and output data from the cores (or other peripheral circuitry) and then transmit the data to other cores or peripheral circuitry within the mesh network. For the SoC to operate efficiently, these mesh networks need to transmit data in an effective manner.

[0003] Transport deadlock occurs when circular dependencies arise in an interconnected network. This problem is particularly complex in mesh networks because numerous potential loops can form between nodes, and monitoring all loops is a significant challenge. Furthermore, since deadlock is a catastrophic failure, it is highly desirable to avoid any false deadlock detections. Therefore, accurate deadlock detection is challenging, as false detections can waste substantial resources in a mesh network. Summary of the Invention

[0004] The aspects disclosed herein include deadlock detection and elimination for mesh interconnects in processor-based systems. Deadlock detection includes detecting deadlocks in cyclic dependencies among a set of multiple nodes in a mesh network. A node is a routing circuit configured to route data within the mesh network. As part of establishing a routing path in the network, each node's input is coupled to a corresponding output of an upstream node. As part of the network, each node's output is coupled to the inputs of multiple downstream nodes. Each node in a mesh interconnect (“mesh network”) includes multiple input and output pipelines configured to couple to its inputs and outputs to provide different routing paths through the node. However, nodes in a mesh network may form cyclic deadlocks depending on how a node's input and output pipelines are routed to other nodes. It is desirable to be able to detect and resolve such cyclic deadlocks. In this regard, in some aspects, each node in a mesh network includes stagnation detection circuitry. The stagnation detection circuitry of each node is configured to detect that the node is part of a cyclic deadlock in the mesh interconnect network. A stall detection circuit is configured to detect if its node is part of a cyclic deadlock by generating a stall output. This stall output is asserted not only when the linked input and output pipelines are deadlocked, but also when an upstream node coupled to the input pipeline is deadlocked. This stall output is provided as a stall input to downstream nodes in the mesh network. In this way, the stall output of the stall detection circuit is stable and asserted when a deadlock exists in a cyclic dependency between closed loops of nodes in the mesh network. In this way, a single node in the mesh network can detect a cyclic deadlock by the stalling of its inputs and outputs.

[0005] In some embodiments, a mesh network includes: a plurality of nodes configured to form a mesh network, each node including: a plurality of input pipeline circuits; a plurality of output storage pipeline circuits; and a plurality of arbitrator circuits, each of the plurality of arbitrator circuits being configured to arbitrate data traffic between an input pipeline circuit in the plurality of input pipeline circuits and an output pipeline circuit in the plurality of output pipeline circuits; and a stall detection circuit including: a stall input coupled to an upstream stall output of an upstream node in the plurality of nodes; and a stall output coupled to a downstream stall input of a downstream node in the plurality of nodes; wherein the stall detection circuit is configured to detect deadlock in a circular dependency among a set of plurality of nodes including nodes in response to: a stall input indicating an upstream stall output indicating that an upstream node is stalled; and a stall output indicating that a node is stalled. In some embodiments, the stall detection circuit is configured to provide a stall output in response to the following, such that the stall output indicating node is stalled: one input pipeline circuit of a plurality of input pipeline circuits is stalled, wherein the stalled input pipeline circuit of the plurality of input pipeline circuits corresponds to a stalled input; one output pipeline circuit of a plurality of output pipeline circuits is stalled; and an arbitrator circuit of an arbitrator circuit links the stalled input pipeline circuit of the plurality of input pipeline circuits to the stalled output pipeline circuit of the plurality of output pipeline circuits. In some embodiments, the stall output corresponds to the stalled output pipeline circuit of the output pipeline circuit. In some embodiments, the stall input is a first stall input; the upstream stall output is a first upstream stall output; the stall output is a first stall output; the downstream stall input is a first downstream stall input; and the stall detection circuit further includes: a plurality of stall inputs, including the first stall input, each stall input coupled to a different upstream stall output of a plurality of upstream stall outputs of an upstream node, the plurality of upstream stall outputs including the first upstream stall output, each input pipeline circuit in the input pipeline circuit corresponding to a different stall input; and a plurality of stall outputs, including the first stall output, each stall output coupled to a different downstream stall input of a plurality of downstream stall inputs of a downstream node, the plurality of downstream stall inputs including the first downstream stall input, each output pipeline circuit in the output pipeline circuit corresponding to a different stall output. In some embodiments, the stall detection circuit is configured to detect deadlock in a circular dependency between a plurality of nodes, including a node, in response to: any stall output indicating that a node is stalled; and any arbitrator circuit in the arbitrator circuit having linked any stall input indicating that the corresponding upstream stall output is stalled to at least one stall output indicating that a node is stalled.In some embodiments, the stall detection circuit is configured to provide any one of the stall outputs to indicate that a node is stalled in response to: one input pipeline circuit of a plurality of input pipeline circuits being stalled, wherein the stalled input pipeline circuit of the plurality of input pipeline circuits corresponds to a stall input indicating that an upstream node is stalled; one output pipeline circuit of a plurality of output pipeline circuits being stalled; and any one of the arbitrator circuits linking the stalled input pipeline circuit of the plurality of input pipeline circuits to the stalled output pipeline circuit of the plurality of output pipeline circuits. In some embodiments, each stall output corresponds to a different output pipeline circuit of the output pipeline circuits. In some embodiments, the stall detection circuit further includes: an input pipeline input configured to indicate whether an input pipeline circuit among a plurality of input pipeline circuits is stalled; an output pipeline input configured to indicate whether an output pipeline circuit among a plurality of output pipeline circuits is stalled; and wherein the stall detection circuit of each node is configured to generate a stall output in response to: at least one arbitrator circuit in the arbitrator circuit has linked the input pipeline circuit to the output pipeline circuit; the input pipeline input indicates that the input pipeline circuit is stalled, wherein the stall input corresponds to the input pipeline circuit; and the output pipeline input indicates that the output pipeline circuit is stalled, wherein the stall output corresponds to the output pipeline circuit. In some embodiments, the stall detection circuit includes an input AND gate and an output AND gate, wherein: the input AND gate has a first AND input coupled to a stall input and a second AND input coupled to an input pipeline input, the first AND output of the input AND gate serving as an intermediate stall input; and the output AND gate has a third AND input operatively associated with the intermediate stall input via at least one arbiter circuit in an arbiter circuit and a fourth stall input coupled to an output pipeline input, wherein the output AND gate has a stall output. In some embodiments, the stall detection circuit further includes an output pipe OR gate, wherein: the output pipe OR gate has a first OR input operatively associated with the intermediate stall input and a second OR input coupled to a deadlock initiation input, the output pipe OR gate having an output pipe OR output; and the third AND input coupled to the output pipe OR output. In some embodiments, the mesh network further includes a controller configured to assert the deadlock initiation input to initiate a deadlock detection test.In some embodiments, the stall input is a first stall input; the upstream stall output is a first upstream stall output; the stall output is a first stall output; the downstream stall input is a first downstream stall input; the stall detection circuit of each node further includes: a plurality of stall inputs, including the first stall input, each stall input being coupled to a different upstream stall output of a plurality of upstream stall outputs of the upstream node, the plurality of upstream stall outputs including the first upstream stall output, each input pipeline circuit in the input pipeline circuit corresponding to a different stall input; and a plurality of stall outputs, including the first stall output, each stall output being coupled to a different downstream stall input of a plurality of downstream stall inputs of the downstream node, the plurality of downstream stall inputs including the first downstream stall input, each output pipeline circuit in the output pipeline circuit corresponding to a different stall output; a plurality of input AND gates, each input AND gate corresponding to a different input pipeline circuit in the input pipeline circuit, wherein each input AND gate has a first AND input and AND gate coupled to a different stall input. A second AND input is coupled to a different input pipelining input in the input pipeline, wherein each input AND gate in the input pipeline has an intermediate stag input; a plurality of output pipes or gates, each output pipe or gate corresponding to a different output pipeline circuit in the output pipeline circuit, wherein each output pipe or gate has a first OR input, the first OR input being operatively associated with an intermediate stag input of an input AND gate in an input pipeline circuit that has been linked to an output pipe or gate, the second OR... The input is coupled to a deadlock initiation input, and an output pipe or output; and a plurality of output AND gates, each of which corresponds to a different output pipeline circuit in the output pipeline circuit, each of which has a third AND input coupled to the output pipe or output, the output pipe or output having linked an input pipeline circuit in the input pipeline circuit to the corresponding output pipeline circuit of the output AND gate, and a fourth stall input coupled to the output pipeline input of the corresponding output pipeline circuit, wherein the output AND gate has a different stall output among the stall outputs. In some embodiments, the stall detection circuit of each node in the node further includes a deadlock OR gate, the deadlock OR gate including a plurality of deadlock OR inputs and deadlock OR outputs, each of the deadlock OR inputs coupled to a different stall output among the stall outputs. In some embodiments, the mesh network further includes a controller coupled to the deadlock initiation input. In some embodiments, the mesh network further includes an OR gate network configured to perform OR operation on the deadlock OR outputs from the stall detection circuit of each node in the node, and provide a global deadlock output, wherein the controller is also coupled to the global deadlock output.In some embodiments, the controller is configured to: assert a deadlock initiation input during a first time period; cancel the assertion of the deadlock initiation input during a second time period; and sample the overall deadlock output after the deadlock initiation input is canceled during the second time period to determine whether any node in the nodes is stalled. In some embodiments, the controller is also configured to declare that a deadlock has been detected in response to an assertion of the overall deadlock output. In some embodiments, the mesh network also includes a plurality of cores, each core being operatively associated with a different node in the nodes, and wherein each node in the nodes is a router for the corresponding core. In some embodiments, the mesh network is provided in a system-on-a-chip (SoC).

[0006] In some embodiments, a method for detecting deadlock in a circular dependency among a group of multiple nodes in a mesh network, each node having a stagnation detection circuit, the method comprising: asserting a deadlock initiation input of each stagnation detection circuit in the stagnation detection circuit during a first time period; canceling the assertion of the deadlock initiation input of each stagnation detection circuit during a second time period; detecting a stagnation input of the stagnation detection circuit indicating that an upstream stagnation output indicates that an upstream node is stagnant; detecting whether a stagnation output of the stagnation detection circuit indicates that a node is stagnant; performing an OR operation on the stagnation output from each node in the nodes to determine whether a total deadlock output is asserted, wherein the stagnation output includes a stagnation output; and sampling the total deadlock output to determine whether any node in the nodes is stagnant.

[0007] In some embodiments, a mesh network includes: a plurality of nodes configured to form a mesh network, each node including: a plurality of input pipeline circuits; a plurality of output storage pipeline circuits; a plurality of arbitrator circuits, each of the arbitrator circuits being configured to arbitrate data traffic between an input pipeline circuit in the plurality of input pipeline circuits and an output pipeline circuit in the plurality of output pipeline circuits; and a stall detection circuit including: a stall input coupled to an upstream stall output of an upstream node in the plurality of nodes, the stall input corresponding to an input pipeline circuit in the input pipeline circuits; and a stall output coupled to a downstream stall input of a downstream node in the plurality of nodes, the stall output corresponding to an output pipeline circuit in the output pipeline circuits; and wherein the stall detection circuit is configured to detect deadlock in a circular dependency between a set of nodes including nodes in response to: the stall input indicating that an upstream node is stalled; an arbitrator circuit in the arbitrator circuits linking an input pipeline circuit in the input pipeline circuits to an output pipeline circuit in the output pipeline circuits; and the stall output indicating that a node is stalled.

[0008] Those skilled in the art will understand the scope of this disclosure and recognize its additional aspects after reading the following detailed description of preferred aspects in conjunction with the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] Figure 1 It is an integrated circuit (IC) chip with nodes in a mesh network based on some aspects;

[0011] Figure 2 It is a system component with a set of nodes based on some aspects, where the nodes form a closed loop with cyclic dependencies;

[0012] Figure 3 It is a system component that includes nodes for a mesh interconnection network (“mesh network”) according to some aspects, wherein the nodes include a stagnation detection circuit configured to detect whether the node is involved in a cyclic deadlock;

[0013] Figure 4 The diagram illustrates a system component with a set of nodes, where each node has input and output pipeline circuitry, and a stall detection circuit is configured to detect whether a node is involved in a cyclic deadlock.

[0014] Figure 5 It is a stagnation detection circuit with input and output pipes, which is used to generate stagnation output based on deadlock in a cyclic dependency between a set of nodes;

[0015] Figure 6 It is a mesh network of nodes based on some aspects, including a stagnation detection controller and an OR gate network based on deadlock signals received from each node indicating whether a node is involved in a cyclic deadlock.

[0016] Figure 7 The flowchart illustrates a method for detecting deadlocks in circular dependencies among a group of multiple nodes in a mesh network, where each node has a stagnation detection circuit; and

[0017] Figure 8 This is a block diagram of an exemplary processor-based system that may include any of the mesh networks described above, based on some aspects. Detailed Implementation

[0018] The aspects disclosed herein include deadlock detection and elimination for mesh networks in processor-based systems. Deadlock detection includes detecting deadlocks in cyclic dependencies among a set of multiple nodes in a mesh network. A node is a routing circuit configured to route data within the mesh network. As part of establishing a routing path in the network, each node's input is coupled to a corresponding output of an upstream node. As part of the network, each node's output is coupled to the inputs of multiple downstream nodes. Each node in a mesh interconnect network (“mesh network”) includes multiple input and output pipelines configured to couple to its inputs and outputs to provide different routing paths through the node. However, nodes in a mesh network may form cyclic deadlocks depending on how a node's input and output pipelines are routed to other nodes. It is desirable to be able to detect and resolve such cyclic deadlocks. In this regard, in some aspects, each node in a mesh network includes stagnation detection circuitry. The stagnation detection circuitry of each node is configured to detect that the node is part of a cyclic deadlock in the mesh network. A stall detection circuit is configured to detect if its node is part of a cyclic deadlock by generating a stall output. This stall output is asserted not only when the linked input and output pipelines are deadlocked, but also when an upstream node coupled to the input pipeline is deadlocked. This stall output is provided as a stall input to downstream nodes in the mesh network. In this way, the stall output of the stall detection circuit is stable and asserted when a deadlock exists in a cyclic dependency between closed loops of nodes in the mesh network. In this way, a single node in the mesh network can detect a cyclic deadlock by the stalling of its inputs and outputs.

[0019] in this regard, Figure 1 This refers to an integrated circuit (IC) chip 100. The IC chip 100, which may be a system-on-a-chip (SOC), may include a number of processing circuits (not shown here, but for example, a core), each coupled to one of a plurality of nodes 102(0) to 102(X) (collectively referred to as (a plurality of) nodes 102) in a mesh network 104. Nodes 102 are coupled to each other via segments 106 of the mesh network 104. Nodes 102 are configured to send and receive data such that data is routed to different nodes 102 in the mesh network 104. Data is then sent and received between nodes 102 and system components (not shown here) on the IC chip 100. In some aspects, nodes 102 are routers configured to route data between different nodes 102, and thus allow routing between different system components coupled to the nodes. Data transmission is typically synchronized by a system clock (not explicitly shown), which is used for timing circuitry in the IC chip 100.

[0020] In one example, different cores ( Figure 1 Each node (not shown) is coupled to Node 102. Different cores are configured to implement computer-executable instructions to perform a specified function on input data, thereby generating output data. Output data from one core can then be transmitted through Node 102 to become input data for another core that implements computer-executable instructions on its input data. For a computer program to proceed efficiently, data should be transmitted through Node 102. Unfortunately, data transmission between Nodes 102 can sometimes slow down or even stop, causing data congestion in the interconnect structure formed by Nodes 102. This congestion can sometimes prevent transmitting Node 102 from transmitting data to receiving Node 102 until the data in the receiving node is passed to another node. Interdependencies between data transmissions of Nodes 102 can sometimes prevent data transmission from progressing, resulting in data transmission failures.

[0021] For example, a deadlock occurs in the mesh network 104 when a group of nodes 102 forms a circular dependency, where no node 102 in the group can move forward. When nodes 102 have a circular dependency, data transfers between nodes 102 result in a closed loop in the group of nodes 102. In other words, if any node 102 in the group of nodes 102 is chosen as the starting node 102 for data transfer, data transfers between different nodes 102 will eventually return to the starting node 102. Deadlock occurs in the interconnected nodes whenever a group of nodes 102 forms a circular dependency, where no node 102 in the group can move forward. When nodes 102 have a circular dependency, data transfers of one node 102 depend on data transfers of the next node 102. If data transfers of one node 102 are prevented from moving forward, data transfers of the next node 102 are also prevented from moving forward. Since data transfers between nodes 102 with a circular dependency always loop back to the same node 102, all nodes 102 in the group are prevented from moving forward. In this case, ideally a deadlock should be detected, allowing for a proper reset of the core and node 102. To detect deadlocks in circular dependencies, each node in the node group includes a stall detection circuit 105. Note that only one node in node 102 is shown with a stall detection circuit 105, but it should be noted that in this example, every node in node 102 includes a stall detection circuit 105. See below for further details. Figure 3 To begin a more detailed discussion, the stagnation detection circuit 105 in each of nodes 102 is configured to detect that node 102 is part of a cyclic deadlock in the mesh network 104.

[0022] Figure 2 It is a system component 200 having a set of nodes (specifically referred to as nodes 102(0) to 102(3) and collectively referred to as node 102) based on some aspects, these nodes in Figure 1 In the mesh network 104, node 102 has a circular dependency.

[0023] In this example, four nodes 102(0) through 102(3) are shown as having a circular dependency. However, in other respects, any number of nodes 102, more than two, can have a circular dependency.

[0024] like Figure 2 As shown, node 102(0) transmits output data to node 102(1). The output data of node 102(0) is the input data of node 102(1). System components operatively associated with node 102(1) are configured to process the input data and generate output data. Node 102(1) is configured to transmit output data as input data to node 102(2). System components operatively associated with node 102(2) are configured to process the input data and generate output data. Node 102(2) is configured to transmit output data as input data to node 102(3). System components operatively associated with node 102(3) are configured to process the input data and generate output data. Node 102(3) is configured to transmit output data as input data to node 102(0). System components operatively associated with node 102(0) are configured to process the input data and generate output data. Node 102(0) is configured to transmit output data as input data to node 102(1). Therefore, as shown, node 102 has a cyclic dependency in the clockwise direction because node 102 transmits data to each other in a closed loop in the clockwise direction.

[0025] In some respects, each node 102 has multiple input pipeline circuits and multiple output pipeline circuits. Data transfers between the input pipeline circuits and output pipeline circuits within each node 102 are arbitrated by an arbitrator circuit (explained in more detail below). Thus, node 102 (0) transfers output data to node 102 (3). The output data of node 102 (0) is the input data of node 102 (3). System components operatively associated with node 102 (3) are configured to process the input data and generate output data. Node 102 (3) is configured to transfer output data as input data to node 102 (2). System components operatively associated with node 102 (2) are configured to process the input data and generate output data. Node 102 (2) is configured to transfer output data as input data to node 102 (1). System components operatively associated with node 102 (1) are configured to process the input data and generate output data. Node 102(1) is configured to transmit output data as input data to node 102(0). System components operatively associated with node 102(0) are configured to process the input data and generate output data. Node 102(0) is configured to transmit output data as input data to node 102(3). Thus, as shown, node 102 has a cyclic dependency in the counterclockwise direction because node 102 transmits data to each other in a closed loop in the counterclockwise direction.

[0026] In this example, it is assumed that clockwise data transmission is independent of counterclockwise data transmission. Regarding the clockwise direction, if any node in node 102 cannot transmit data to the next node 102 in the clockwise direction, then the next node 102 in the sequence cannot transmit data to the next node 102 in the clockwise direction. This will continue in a clockwise loop through node 102. For example, if data is prevented from being transmitted from node 102(0) to node 102(1), then node 102(1) cannot transmit new data to node 102(2). This, in turn, prevents node 102(2) from transmitting new data to node 102(3). Therefore, node 102(3) cannot transmit new data to node 102(0). In this case, a deadlock exists in the clockwise direction within the group of nodes 102 because no node 102 in the group can advance. Therefore, while data transfer between nodes 102 may be in progress in the counter-clockwise direction, nodes cannot advance in the clockwise direction, resulting in a deadlock in the clockwise direction. The same applies to the counter-clockwise direction; deadlock may occur in the counter-clockwise direction, but not in the clockwise direction. A deadlock will occur as soon as one closed-loop path between nodes 102 advances. Deadlock is a catastrophic data event, sometimes requiring a complete system reset in the SoC (e.g., ...). Figure 1The SoC 100 in the system may drop packets. Therefore, accurate deadlock detection is important because false detections can lead to inefficient operation of the SoC. Figure 2 Each of nodes 102(0) to 102(3) includes a stagnation detection circuit 105 (in Figure 1 (As shown in the image).

[0027] in this regard, Figure 3 It is a system component 300 including node 302, which includes a stagnation detection circuit 312, similar to Figure 1 The stagnation detection circuit 105 in the middle. (See the following text from...) Figure 3 To begin a more detailed discussion, the stagnation detection circuit 312 in each of nodes 302 is configured to detect that node 302 is part of a cyclic deadlock in the mesh network. The stagnation detection circuit 312 is configured to detect that its node 302 is part of a cyclic deadlock by generating a stagnation output, which is asserted not only when the linked input and output pipeline circuits are deadlocked, but also when an upstream node coupled to the input pipeline circuit is deadlocked. This stagnation output is provided as a stagnation input to downstream nodes in the mesh network. In this way, the stagnation output of the stagnation detection circuit 312 is stable and asserted when a deadlock exists in a cyclic dependency among the closed loops of nodes 302 in mesh network 104. In this way, a single node 302 in the mesh network can detect a cyclic deadlock by the stagnation of its inputs and outputs.

[0028] Node 302 can be Figure 1 Any node in node 102, or Figure 2 Any node in node 102. Node 302 can be provided in a mesh network, such as... Figure 1 Mesh networks 104. In some respects, Figure 1 Each node in node 102 is associated with Figure 3 Node 302 is provided in the same way. Figure 3 In this context, node 302 is operatively associated with core 304. Core 304 may include a finite state machine. Core 304 is configured to receive input data from node 302. Core 304 processes the input data and generates output data. Core 304 then provides the output data to node 302, which transmits the output data to the mesh network (e.g., ...). Figure 1 Another node in the mesh network (104).

[0029] Node 302 includes input pipeline circuitry (specifically referred to as input pipeline circuitry 306(0) to 306(N-1) and collectively as (a plurality of) input pipeline circuits 306). Figure 3There are N input pipeline circuits 306. The indices between parentheses () start from 0, so the final value of the index for the input pipeline circuit 306 ends in N-1. In this respect, N is greater than or equal to 4. However, in other respects, the number of input pipeline circuits 306 is N, where N is greater than or equal to 1.

[0030] Each input pipeline circuit in input pipeline circuit 306 includes a set of registers. If n represents the index of input pipeline circuit 306, then the registers of input pipeline circuit 306(n) are connected to the input terminal Input[n]. For example, if the index n=0, then the registers of input pipeline circuit 306(0) are connected to the input terminal Input[0]. Input data is received at the input terminal Input[n] from the output pipeline circuit of the upstream node (or, in some cases, from circuitry outside the mesh network in the SoC). The input data is then stored in the registers of input pipeline circuit 306(n). For example, input data is received at the input terminal Input[0] and stored in the registers of input pipeline circuit 306(0). In some cases, the input data in the registers of input pipeline circuit 306 is provided to core 304, which processes the input data to generate output data. In other cases, the input data is routed for transmission to the mesh network (e.g., Figure 1 The downstream node in the mesh network (104).

[0031] Node 302 includes output pipeline circuitry (specifically referred to as output pipeline circuitry 308(0) to 308(M-1) and collectively as output (multiple) pipeline circuits 308). Figure 3 In the given information, there are M output pipeline circuits 308. The indices between parentheses () start from 0, so the final value of the index for each output pipeline circuit 308 ends in M-1. In this respect, M is equal to or greater than 4. However, in other respects, the number of output pipeline circuits 308 is M, where M is greater than or equal to 1. In some respects, M is equal to N. In other respects, M is not equal to N.

[0032] Each output pipeline circuit in the output pipeline circuit 308 includes a set of registers. If m represents the index of the output pipeline circuit 308, then the registers of the output pipeline circuit 308(m) are connected to the output terminal Output[m]. For example, if the index n=0, then the registers of the output pipeline circuit 308(0) are connected to the output terminal Output[0]. Output data is transmitted from the registers in the output pipeline circuit 308(m) to the output terminal Output[m]. The output terminal Output[m] is coupled to the input pipeline circuit of the downstream node (or, in some cases, to circuitry outside the mesh network in the SoC). For example, output data stored in the registers of the output pipeline circuit 308(0) is sent from the output terminal Output[0]. In some cases, the output data in the registers of the output pipeline circuit 308 originates from core 304. In other respects, the output data is routed between the input pipeline circuit 306 and the output pipeline circuit 308 by the arbitrator circuit (specifically referred to as arbitrator circuits 310(0) to 310(M-1) and collectively as arbitrator circuit 310).

[0033] Node 302 includes arbitrator circuitry 310 to arbitrate data traffic between input pipelines 306 and output pipelines 308. Figure 3 In this configuration, each arbiter circuit in arbiter circuit 310 is connected to only one output pipeline circuit in output pipeline circuit 308. Therefore, there are M arbiter circuits 310. If m represents the index of output pipeline circuit 308, then for each arbiter circuit 310, arbiter circuit 310(m) is coupled to output pipeline circuit 308(m). Figure 3 In this configuration, the output pipeline circuit 308(m) receives data traffic only from the arbitrator circuit 310(m). However, in other respects, one or more arbitrator circuits in the arbitrator circuit 310 are coupled to more than one output pipeline circuit in the output pipeline circuit 308.

[0034] If n represents the index of the input pipeline circuit 306, and m represents the index of the arbiter circuit 310 and the output pipeline circuit 308, then each arbiter circuit 310 is coupled to each input pipeline circuit 306, except for the input pipeline circuit 306 when n=m. For example, arbiter circuit 310(0) is coupled to input pipeline circuits 306(1) through 306(N-1), but not to input pipeline circuit 306(0). The reason why each arbiter circuit 310 is not coupled to the input pipeline circuit 306 when m=n is related to the connection scheme between nodes, in which the input-to-output path does not loop back to the same core 304. This is explained below. Figure 4This will become more apparent in the explanation. It should be noted that, in other respects, the arbitrator circuit 310 is also coupled to each input pipeline circuit 306, including the input pipeline circuit 306 when n=m. Any other coupling scheme between the arbitrator circuit 310 and the input pipeline circuit 306 is within the scope of this disclosure.

[0035] exist Figure 3 In this configuration, each arbiter circuit 310 is configured to determine which input pipeline circuit (coupled to a specific arbiter circuit 310) in the input pipeline circuits 306 will pass data to the output pipeline circuit 308 (coupled to a specific arbiter circuit). In this way, each arbiter circuit 310 links one input pipeline circuit from the input pipeline circuits 306 to the output pipeline circuit 308 to which the arbiter circuit 310 is coupled. This creates a data traffic path between the selected input pipeline circuit 306 and the output pipeline circuit 308 to which the arbiter circuit 310 is coupled. For example, arbiter circuit 310(0) can link input pipeline circuit 306(1) to output pipeline circuit 308(0), thereby creating a data traffic path between input pipeline circuit 306(1) and output pipeline circuit 308(0).

[0036] Node 302 is considered stalled when any data service path in the data service path created by arbitrator circuit 310 is stalled. Therefore, although other data service paths created by arbitrator circuit 310 in node 302 may be open for data services, node 302 is considered stalled if one of the data service paths is stalled. If there is a circular dependency between a set of nodes (see...), then node 302 is considered stalled. Figure 2 If the stalled data path in node 302 is connected to a downstream data path in another node, that downstream path will also stall. Due to the circular dependency between nodes, the stalling of the data path will continue until the beginning of the closed loop, resulting in a catastrophic deadlock.

[0037] Node 302 includes a stall detection circuit 312. The stall detection circuit 312 is... Figure 1An example of a stall detection circuit 105. Stall detection circuit 312 is configured to detect deadlocks in cyclic dependencies between a set of multiple nodes including node 302. Stall detection circuit 312 includes multiple stall inputs (specifically referred to as stall inputs 314(0) to 314(N-1) and collectively as stall inputs 314). Each stall input in stall input 314 corresponds to one input pipeline circuit in input pipeline circuit 306. In this respect, each stall input 314(n) corresponds to input pipeline circuit 306(n) if n represents the index of input pipeline circuit 306. Stall detection circuit 312 includes multiple stall outputs (specifically referred to as stall outputs 316(0) to 316(M-1) and collectively as stall outputs 316). Each stall output in stall output 316 corresponds to one output pipeline circuit in output pipeline circuit 308. In this respect, if m represents the index of the output pipeline circuit 308, then each stall output 316(m) corresponds to the output pipeline circuit 308(m).

[0038] Each stag input in stag input 314 is connected to an upstream stag output. Each stag input in stag input 314 indicates whether the upstream stag output indicates that an upstream node is stagnant. In other words, since each stag input in stag input 314 corresponds to a specific input pipeline circuit in input pipeline circuit 306, each stag input in stag input 314 indicates whether the corresponding input pipeline circuit 306 is coupled to a stagnant data service path in the upstream node. For example, stag input 314(0) indicates whether input pipeline circuit 306 is coupled to a stagnant upstream data service path in the upstream node.

[0039] Each stag output in stag output 316 is coupled to a downstream stag input of a downstream node. Each stag output in stag output 316 indicates whether a node is stagnant. In other words, since each stag output in stag output 316 corresponds to a specific output pipeline circuit in output pipeline circuit 308, each stag output in stag output 314 indicates whether the corresponding output pipeline circuit 308 is part of a stagnant data service path in node 302. For example, stag output 314(0) indicates whether output pipeline circuit 308(0) is part of a stagnant data service path in node 302. Thus, this indicates to the downstream stag input corresponding to the input pipeline circuit of the downstream node whether that input pipeline circuit is coupled to a stagnant data service path in node 302.

[0040] When the input pipeline circuit 306 corresponding to stag input 314 is linked to the output pipeline circuit 308 corresponding to stag output 308 by one of the arbitrator circuits 310, stag input 314 and stag output 316 are linked to each other by one of the arbitrator circuits 310. Stagnation detection circuit 312 is configured to detect deadlock in a cyclic dependency between a group of nodes including node 302 in response to any of the following: any stag input in stag input 314 indicating that an upstream stag output indicates that an upstream node is stagnant, and any of the stag outputs 316 indicating that node 302 is stagnant, wherein the stag input 314 indicating that the upstream stag output indicates that the upstream node is stagnant is linked to the stag output 316 indicating that node 302 is stagnant. Therefore, this indicates that the data traffic path in the upstream node is stagnant, and the data traffic path in the node is stagnant, and is indicating to the downstream node that its data path is stagnant. Assuming that sufficient time has been given to stabilize the stall detection circuits (e.g., stall detection circuit 312) throughout the mesh network, this situation can only occur if there is a deadlock in a circular dependency among a group of multiple nodes including node 302.

[0041] To cause a stagnation output indicating node 302 in stagnation output 316 to be stagnant, one input pipeline circuit in a plurality of input pipeline circuits 306 is stagnant, wherein the stagnant input pipeline circuit in the plurality of input pipeline circuits 306 corresponds to a stagnation input indicating that an upstream node is stagnant, one output pipeline circuit in a plurality of output pipeline circuits 308 is stagnant, and an arbitrator circuit in arbitrator circuit 310 links the stagnant input pipeline circuit in the plurality of input pipeline circuits 306 to the stagnant output pipeline circuit in the output pipeline circuit 308. For example, stagnation input 314(0) corresponds to input pipeline circuit 306(0). For illustrative purposes, assume that stagnation input 314(0) indicates that an upstream node is stagnant. Stagnation detection circuit 312 also detects that input pipeline circuit 306(0) is stagnant. Assume that the arbiter circuit 310 (1) has linked the input pipeline circuit 306 (0) to the output pipeline circuit 308 (1), and also detects that the output pipeline circuit 308 (1) is stalled. In this example, the stalled output 316 (1) corresponds to the output pipeline circuit 308 (1). Therefore, since 1) the stalled input 314 (0) indicates that the upstream node is stalled, 2) the input pipeline circuit 306 (0) corresponding to the stalled input 314 (0) is stalled, 3) the input pipeline circuit 306 (0) is linked to the output pipeline circuit 308 (1) by one of the arbiter circuits in the arbiter circuit 310 (1), and 4) the output pipeline circuit 308 (1) is stalled, the stall detection circuit 312 is configured to provide the stalled output 316 (1) corresponding to the stalled output pipeline circuit 308 (1) as an indication that node 302 is stalled. This is because the data service path between the input pipeline circuit 306(0) and the output pipeline circuit 308(1) is stalled, and connected to the upstream data flow path that is also stalled.

[0042] Other data service paths (e.g., from input pipeline 306(1) to output pipeline 308(2) if they are linked together) may not be stalled. Therefore, the stall output 308 of the output pipeline 308 corresponding to a stalled data service path will not indicate that node 302 is stalled. Furthermore, if the data service paths of input pipeline 306(0) and output pipeline 308(1) are stalled, but the stall input 314(0) does not indicate that the upstream node is stalled, then the stall output 316(0) will not indicate that node 302 is stalled to the downstream node. It should also be noted that if more than one data service path is stalled, and the stall input 314 of the input pipeline 306 corresponding to the stalled data service path also indicates that the upstream node is stalled, then more than one stall output in the stall output 308(0) may indicate that node 302 is stalled. Therefore, the stagnation detection circuit 312 is configured to detect deadlock in a cyclic dependency among a group of nodes including node 302 in response to: any stagnation output in stagnation output 316 indicating that a node is stagnant, and any arbitrator circuit in arbitrator circuit 310 having linked any stagnation input in stagnation input 314 indicating that the corresponding upstream stagnation output is stagnant to at least one stagnation output in stagnation output 316 indicating that node 302 is stagnant.

[0043] In this respect, the stall detection circuit 312 is configured to receive a set of input pipeline inputs 320 indicating whether any input pipeline circuit in the input pipeline circuit 306 is stalled. For an input pipeline circuit 306 to stall, all registers of that input pipeline circuit 306 must be full, and no more data can be received unless the data in the registers can be sent externally. In response to a stall in an input pipeline circuit 306, an input pipeline input 320 corresponding to the stalled input pipeline circuit 306 indicates that the stalled input pipeline circuit 306 is stalled. In this way, the stall detection circuit 312 is configured to detect whether any input pipeline circuit in the input pipeline circuit 306 is stalled.

[0044] In this respect, the stall detection circuit 312 is configured to receive a set of output pipeline inputs 322 indicating whether any output pipeline circuit in the output pipeline circuit 308 is stalled. For an output pipeline circuit in the output pipeline circuit 308 to stall, all registers of that output pipeline circuit 308 must be full, and no more data can be received unless the data in the registers can be sent externally. In response to a stall in the output pipeline circuit 308, one of the output pipeline inputs 322 corresponding to the stalled output pipeline circuit 308 indicates that the stalled output pipeline circuit 308 is stalled. In this way, the stall detection circuit 312 is configured to detect whether any output pipeline circuit in the output pipeline circuit 308 is stalled.

[0045] Stasis detection circuit 312 includes deadlock initiation input 324, which is coupled to controller ( Figure 3 (Not shown in the image) to initiate a deadlock detection test. The function of the deadlock initiation input 324 will be explained further below. The stall detection circuit 312 also includes a deadlock output 326. As explained in further detail below, the stall detection circuit 312 is configured to perform an OR operation on all stall outputs 316, such that the deadlock output 326 indicates whether any of the stall outputs 316 indicates that node 302 is stalled.

[0046] Figure 4 The diagram illustrates a system component 400 having a group of nodes (specifically referred to as nodes 402(1) to 402(4) and collectively referred to as node 402).

[0047] Each node in node 402 can be Figure 1 Any of the nodes shown in node 102. In some respects, node 402(0) corresponds to Figure 2 Node 102(0) in the diagram. In some respects, node 402(1) corresponds to... Figure 2 Node 102(1) in the diagram. In some respects, node 402(2) corresponds to... Figure 2 Node 102(2) in the middle. In some respects, node 402(3) corresponds to Figure 2 Node 102 (3) in the middle.

[0048] Each node in node 402 is associated with Figure 3Node 302 is provided in the same manner, where M=4 and N=4. In other respects, M can be equal to any other integer, and node N can be equal to any other number. In some embodiments, the values ​​of M and N depend on the type of chip. Within some SoCs, M and N can be in the range of 2 to 10, but in other embodiments, M and N can be higher. The values ​​of M and N are application-dependent. For example, SoCs in some components used in data centers typically have 64 to 128 cores plus other additional devices (e.g., PCIe and memory).

[0049] like Figure 3 Similar to the aspects of node 302 shown, each node in node 402 is operatively associated with a different core (specifically referred to as cores 404(0) to 404(3) and collectively as core 404). Each core in core 404 is configured to receive input data from the input pipeline circuit 306 of node 402 operatively associated with core 404. Each core in core 404 is configured to transmit output data to the output pipeline circuit 308 of node 402 operatively associated with core 404. In this respect, output data in the output pipeline circuit 308 of one core in core 404 can be routed as input data through node 402 to an input pipeline circuit 306 of the input pipeline circuit of another core 404.

[0050] More specifically, let i denote the index of one of the nodes in node 402, where the field of i is [0 to N-1], which is [0 to 4] in this example. For example, if i equals 1, it indicates node 402(1). Furthermore, let o denote the index of another node 402, where the value of o is in the range [0 to N-1], which is [0 to 4] in this example, and where o is not equal to i. Therefore, in the example above, o cannot be equal to 1 when i = 1. Thus, node 402(o) can represent any node in node 402 other than node 402(i). This merely illustrates that node 402(i) and node 402(o) are different nodes.

[0051] The connection scheme between the input terminals [Input[0], Input[1], Input[2], Input[3]] and the output terminals [Output[0], Output[1], Output[2], Output[3]] of a node 402(i) is described by a simple rule. The rule is as follows: the input terminal Input[o] of node 402(i) is coupled to the output terminal Output[i] of node 402(o). This means that the input pipeline circuit 306(o) of node 402(i) is receiving the output data of the output pipeline circuit 308(i) of node 402(o) as input data.

[0052] For example, the input terminal Input[1] of node 402(0) is coupled to the output terminal Output[0]. This means that the input pipeline circuit 306(1) of node 402(0) is receiving the output data of the output pipeline circuit 308(0) of node 402(1) as input data. Note that for all nodes 402, the input terminal Input[i] and the output terminal Output[i] of node 402[i] are not connected. For example, the input terminal Input[0] and the output terminal Output[0] of node 402(0) remain unconnected. This is because, given the rules of the connection scheme, the input terminal Input[i] and the output terminal Output[i] of node 402[i] would imply that data would cycle back to the same node 402(i). In this example, data cycling back to the same node 402 is not allowed. However, alternatively, data cycling back to the same node can be allowed. Furthermore, alternatively, the input terminal Input[i], input pipeline circuit 306(i), arbitrator circuit 310(i), output pipeline circuit 308(i), and output terminal Output[i] of node 402[i] may simply not be provided. It should be noted that these are merely exemplary connection schemes for the nodes. Any suitable connection scheme for transmitting data services between nodes 402 is within the scope of this disclosure.

[0053] like Figure 4 As shown, node 402 forms part of mesh network 406. Data services can be received and transmitted between any node 402. Arbitrator circuit 310 in each node 402 determines how data services are transmitted between nodes in mesh network 406.

[0054] The mesh network 406 also includes a stagnation detection controller 408. The stagnation detection controller 408 is operatively associated with each stagnation detection circuit in the stagnation detection circuit 312 in each node of node 402. Figure 3Regarding node 302, in order for any stall output in the stall detection circuit 312 to indicate that node 402 is stalled, not only must the input pipeline circuit 306 and output pipeline circuit 308 linked within node 402 (by one of the arbitrator circuits 310) be stalled, but the stall input 314 corresponding to the stalled input pipeline circuit 306 must also indicate that the upstream node 402 is stalled. However, at circuit startup, given the cyclic dependency between nodes 402, even if all data traffic paths in nodes 402 (linked input pipeline circuits 306 and output pipeline circuits 308) are connected and stalled, no stall input 314 indicates that a previous node 402 is stalled. Therefore, the stall output 316 of the stall detection circuit 312 for all nodes 402 cannot indicate that any node in node 402 is stalled.

[0055] For example, consider the following circular dependency. The input pipeline circuit 306(0) is linked to the output pipeline circuit 308(2) by the arbitrator circuit 310(2) in node 402(1), and both are stalled. However, the stalled output 316(2) cannot indicate that node 402(1) is stalled unless the stalled input 306(0) indicates that node 402(0) is stalled.

[0056] The input pipeline circuit 306(1) is linked to the output pipeline circuit 308(3) by the arbitrator circuit 310(3) in node 402(1), and both are stalled. However, the stalled output 316(3) cannot indicate that node 402(2) is stalled unless the stalled input 306(1) indicates that node 402(1) is stalled.

[0057] The input pipeline circuit 306(2) is linked to the output pipeline circuit 308(0) by the arbitrator circuit 310(0) in node 402(3), and both are stalled. However, the stalled output 316(0) cannot indicate that node 402(3) is stalled unless the stalled input 306(2) indicates that node 402(2) is stalled.

[0058] The input pipeline circuit 306(3) is linked to the output pipeline circuit 308(1) by the arbitrator circuit 310(1) in node 402(0), and both are stalled. However, the stalled output 316(1) cannot indicate that node 402(0) is stalled unless the stalled input 306(3) indicates that node 402(3) is stalled.

[0059] Since the stall input 314 in any node 402 does not initially indicate a stall, the stall output 316 cannot indicate a stall either. Therefore, to initialize the operational deadlock detection test, the stall detection controller 408 asserts a deadlock initiation input 324 for each stall detection circuit in the stall detection circuit 312 of each node in 402. In response to the deadlock initiation input 324 being asserted, the dependence of the stall output 316 on the stall input 312 and the stall of the input pipeline circuit 306 is broken. In other words, the stall output 316 of each node in 402 is allowed to simply indicate that node 402 is stalled only in response to the stall of the output pipeline circuit 308 corresponding to the stall output 316.

[0060] Regarding the example given above, in response to the deadlock initiation input 324 of node 402(1) being asserted, the stall output 316(2) of node 402(1) indicates that node 402(1) is stalled because the output pipeline circuit 308(2) is stalled. In response, the stall input 314(1) of the stall detection circuit 312 of node 402(2) indicates that node 402(1) is stalled.

[0061] In response to the deadlock initiation input 324 of node 402(2) being asserted, the stall output 316(3) of node 402(2) indicates that node 402(2) is stalled because the output pipeline circuit 308(3) is stalled. In response, the stall input 314(2) of the stall detection circuit 312 of node 402(3) indicates that node 402(2) is stalled.

[0062] In response to the deadlock initiation input 324 of node 402(3) being asserted, the stall output 316(0) of node 402(3) indicates that node 402(3) is stalled because the output pipeline circuit 308(0) is stalled. In response, the stall input 314(3) of the stall detection circuit 312 of node 402(0) indicates that node 402(3) is stalled.

[0063] In response to the deadlock initiation input 324 of node 402(0) being asserted, the stall output 316(1) of node 402(0) indicates that node 402(0) is stalled because the output pipeline circuit 308(1) is stalled. In response, the stall input 314(0) of the stall detection circuit 312 of node 402(1) indicates that node 402(0) is stalled.

[0064] Stasis detection controller 408 is configured to assert the deadlock initiation input 324 of the stagnation detection circuit 312 of each node in node 402 during a first time period. The first time period should be sufficient to allow the stagnation input 314 and stagnation output 316 of each stagnation detection circuit in the stagnation detection circuit 312 of each node in node 402 to stabilize. Therefore, the first time period depends on the maximum propagation delay between nodes 402 when the deadlock initiation input 324 of each node in the node is asserted.

[0065] After the first period, the stall detection circuit 408 is configured to cancel the assertion of the deadlock initiation input 324 of the stall detection circuit 312 for each node in 402. In response to the cancellation of the assertion of the deadlock initiation input 324 of the stall detection circuit 312 for each node in 402, the stall output 316 of the stall detection circuit 312 for each node in 402 again depends on the stall input 314 and the stall of the linked input pipeline circuit.

[0066] Similarly, the input pipeline circuit 306(0) is linked to the output pipeline circuit 308(2) by the arbitrator circuit 310(2) in node 402(1), and both are stalled. However, in response to the deadlock initiation input 324 in node 402(1) being canceled after the first time period, the stall output 316(2) indicates that node 402(1) is stalled because the stall input 306(0) indicates that node 402(0) is stalled and the input pipeline circuit 306(0) is linked to the output pipeline circuit 308(2), both of which are stalled.

[0067] Similarly, the input pipeline circuit 306(1) is linked to the output pipeline circuit 308(3) by the arbitrator circuit 310(3) in node 402(1), and both are stalled. However, in response to the deadlock initiation input 324 in node 402(1) being canceled after the first time period, the stall output 316(3) indicates that node 402(2) is stalled because the stall input 306(1) indicates that node 402(1) is stalled and the input pipeline circuit 306(1) is linked to the output pipeline circuit 308(3), both of which are stalled.

[0068] Similarly, the input pipeline circuit 306(2) is linked to the output pipeline circuit 308(0) by the arbitrator circuit 310(0) in node 402(3), and both are stalled. However, in response to the deadlock initiation input 324 in node 402(1) being canceled after the first time period, the stall output 316(0) indicates that node 402(3) is stalled because the stall input 306(2) indicates that node 402(2) is stalled and the input pipeline circuit 306(2) is linked to the output pipeline circuit 308(0), both of which are stalled.

[0069] Similarly, the input pipeline circuit 306(3) is linked to the output pipeline circuit 308(1) by the arbitrator circuit 310(1) in node 402(0), and both are stalled. However, in response to the deadlock initiation input 324 in node 402(1) being canceled after the first time period, the stall output 316(1) indicates that node 402(0) is stalled because the stall input 306(3) indicates that node 402(3) is stalled and the input pipeline circuit 306(3) is linked to the output pipeline circuit 308(1) by the arbitrator circuit 310(1) in node 402(0), and both are stalled.

[0070] Stasis detection controller 408 is configured to cancel the assertion of deadlock initiation input 324 of stagnation detection circuit 312 for each node in 402 during a second time period. The second time period should be sufficient to allow stagnation input 314 and stagnation output 316 of each stagnation detection circuit in stagnation detection circuit 312 of each node in 402 to stabilize. Therefore, the second time period depends on the maximum propagation delay between nodes 402 when the deadlock initiation input 324 of each node in the node is canceled.

[0071] Following the second time period, the stagnation detection controller 408 is configured to sample the deadlock output 326 of each stagnation detection circuit in the stagnation detection circuit 312 of each node in 402. Since at least one stagnation output 316 in each node in 402 indicates that node 402 is stagnant, the deadlock output 326 of each stagnation detection circuit in the stagnation detection circuit 312 of each node in 402 is asserted. The stagnation detection controller 408 is coupled to the deadlock output 326 of each stagnation detection circuit in the stagnation detection circuit 312 of each node in 402. The stagnation detection controller 408 is configured to detect a deadlock because at least one deadlock output 326 is asserted. In response, the stagnation detection controller 408 initiates a reset operation. Alternatively, in response to none of the deadlock outputs 326 from each stagnation detection circuit 312 being asserted, the stagnation detection controller 408 does not initiate a reset operation for all deadlock outputs 326 from each stagnation detection circuit 312.

[0072] Figure 5 It is based on some aspects of the stagnation detection circuit 500.

[0073] According to some aspects, Figure 3 The stagnation detection circuit 312 in the middle is connected with Figure 5 The stagnation detection circuit 500 is provided in the same manner. Furthermore, according to some aspects, Figure 4The stagnation detection circuit 312 of each node in the middle node 402 is connected with Figure 5 The same manner is provided for each of the stall detection circuits 500. It should be noted that the stall detection circuit 500 is merely exemplary, and according to some aspects... Figure 3 and Figure 4 The stall detection circuit 312 in the middle can be provided in other configurations.

[0074] exist Figure 5 In the diagram, the stall detection circuit 500 includes N (where N is as defined above) input pipes, M arbitrators or gates, and M (where M is as defined above) output pipes. There are also N stall inputs 314 and M stall outputs 316. Only the input pipes Input Pipe[n] (where index n is as defined above) are shown. Only the arbitrators or gates Arb[m] are shown. It should be noted that each arbitrator or gate is provided in the same manner as Arb[m]. Furthermore, only the output pipes Output Pipe[m] (where m is an index as defined above) are shown. It should be noted that each input pipe in the input pipes is provided in the same manner as Input Pipe[n]. Furthermore, each output pipe in the output pipes is provided in the same manner as Output Pipe[m].

[0075] Each stagnant input in stagnant input 314 corresponds to a different input pipeline circuit in input pipeline circuit 306 (see [link]). Figure 3 Therefore, the stagnant inputs 314(n) correspond to the input pipeline circuit 306(n). Each input pipe in the input pipeline corresponds to a different input pipeline circuit in the input pipeline circuit 306 (see...). Figure 3 Therefore, the input pipe [n] corresponds to the input pipeline circuit 306(n). In some respects, each arbiter or gate in the arbiter or gate is provided by the corresponding arbiter circuit 310 (see...). Figure 3 Therefore, in some respects, the arbiter or gate Arb[m] is provided by the corresponding arbiter circuit 310(m). Thus, each arbiter or gate corresponds to a different output pipeline circuit in the output pipeline circuit 308 (see...). Figure 3 Therefore, the arbiter or gate Arb[m] corresponds to the output pipeline circuit 308(m). Each output pipe in the output pipeline corresponds to a different output pipeline circuit in the output pipeline circuit 308. Therefore, the output pipe Output Pipe[m] corresponds to the output pipeline circuit 308(m). Each stall output in the stall output 316 corresponds to a different output pipeline circuit in the output pipeline circuit 308. Therefore, the stall output 316(m) corresponds to the output pipeline circuit 308(m).

[0076] The input pipe (n) includes an input AND gate 502 (n). The input AND gate 502 (n) includes an AND input coupled to the stagnant input 314 (n). The input AND gate 502 (n) includes an AND input coupled to the input pipelined input InPipeStalled (n). The input pipelined input InPipeStalled (n) indicates the corresponding input pipelined circuit 306 (n) (see...). Figure 3 The output of AND gate 502(m) is the intermediate stalled input InterStalled(n). AND gate 502(n) asserts the intermediate stalled input InterStalled(n) in response to stalled input 314(n) being asserted (indicating that the upstream node is stalled) and pipelined input InPipeStalled(n) being asserted (indicating that the corresponding pipelined input 306(n) is stalled). Otherwise, AND gate 502(n) cancels the assertion of the intermediate stalled input InterStalled(n) in response to stalled input 314(n) being deasserted (indicating that the upstream node is not stalled) or pipelined input InPipeStalled(n) being deasserted (indicating that the corresponding pipelined input 306(n) is not stalled).

[0077] Arbitrator gatekeeper AND gate 507(n) has an AND input coupled to InterStalled(n) and another AND input coupled to the valid data input DV. Arbitrator gatekeeper AND gate 507(n) corresponds to a specific input pipeline circuit in input pipeline circuit 306(n). As mentioned above, each of arbitrators 310(m) is associated with a specific output pipeline circuit in output pipeline circuit 308(m). If input pipeline circuit 306(n) does not select to pass data to the arbitrator 310(m) associated with output pipeline circuit 308(m), the valid data input DV is not asserted. Therefore, the AND output of arbitrator gatekeeper AND gate 507(n) does not pass InterStalled(n) to the AND output of arbitrator gatekeeper AND gate 507(n). However, if the input pipeline circuit 306(n) has been selected to pass data to the arbitrator 310(m) associated with the output pipeline circuit 308(m), then the valid data input DV is asserted. Therefore, the AND output of the arbitrator gatekeeper AND gate 507(n) is set to pass InterStalled(n). In this way, InterStalled(n) is passed to the output pipes[m] corresponding to the output pipeline circuit 308(m) selected for data transmission.

[0078] Arbiter OR gate Arb(m) has an OR input connected to the AND output of each of the arbiter gate AND gates 507(n). However, one or more valid data inputs DV can be asserted, while the remaining valid data inputs DV are deasserted. Arbiter OR gate Arb(m) performs an OR operation on all AND outputs from all arbiter gate AND gates 507 corresponding to each input pipeline circuit in input pipeline circuit 306, and generates arbiter OR output ArbO[m]. Therefore, arbiter OR output ArbO[m] is set according to all InterStalled(n) corresponding to the asserted valid data input DV. In this way, arbiter OR output ArbO[m] is set according to InterStalled(n) corresponding to the input pipeline circuit 306(n) providing data transmission.

[0079] The Output Pipe (m) includes an Output Pipe OR gate 510 (m), an Output AND gate 512 (m), and a flip-flop 514 (m). The Output Pipe OR gate 510 (m) has an output pipe or input coupled to the arbiter or output ArbO (m). The Output Pipe OR gate 510 (m) has another output pipe or input serving as a deadlock initiation input 324. The Output Pipe OR gate 510 (m) has an output pipe or output OPO. Therefore, in response to the deadlock initiation input 324 being deasserted, the output pipe or output OPO (m) simply follows the arbiter or output ArbO. However, in response to the deadlock initiation input 324 being asserted, the connection of the Output Pipe [m] is broken due to the assertion of the output pipe or output OPO (m).

[0080] Output AND gate 512(m) includes an AND input coupled to stagnant input 314(n). Output AND gate 512(m) includes an AND input coupled to output pipe or output OPO(m). Output AND gate 512(m) includes another AND input coupled to output pipeline input OutPipeStalled(m). Output pipeline input OutPipeStalled(m) indicates whether the corresponding output pipeline circuit 308(m) is stalled. Output AND gate 512(m) has an output, namely stagnant output 316(m). Output AND gate 512(m) stalls output 316(m) in response to both output pipe or output OPO(m) being asserted (thus indicating that both linked stagnant input 314(n) and linked input pipeline circuit 306(n) indicate stalling, or a deadlock test is being initiated) and output pipeline input OutPipeStalled(m) being asserted (thus indicating that the corresponding output pipeline circuit 308(m) is stalled). Otherwise, output AND gate 512(m) cancels the assertion on the stalled output 316(m) in response to the output pipe or output OPO(m) being canceled (thus indicating that the upstream node is not stalled or the linked input pipeline circuit 306(n) is not stalled) or output pipeline input OutPipeStalled(m) (thus indicating that the corresponding output pipeline circuit 308(m) is not stalled).

[0081] Trigger 514 has a trigger input D connected to receive the stall output 316(m) before driving the stall output 316(m) to downstream nodes in the structure. In some respects, additional trigger stages can be added as needed to disable timing. It is recommended to utilize trigger 514 to help prevent the formation of combinational loops.

[0082] A stalled output 316 from each of the output pipes is provided as input to an OR gate 516. The OR gate 516 performs an OR operation on each stalled output 316 from the output pipes. The output of the OR gate 516 is a deadlock output 326. Therefore, if any stalled output 316 is asserted, the deadlock output 326 is asserted, indicating that node 500 is stalled.

[0083] Figure 6 It is a mesh network 600 based on some aspects of node 602.

[0084] Figure 6 Each node in node 602 can be Figure 1 Any node in node 102. According to some aspects, Figure 6 Each node in node 602 can be associated with Figure 3Node 302 in the same manner is provided. According to some aspects, each node in node 602 can be provided in accordance with... Figure 4 Similar connection schemes are used to connect the components.

[0085] The mesh network 600 also includes a stall detection controller 604. In some aspects, the stall detection controller 604 is compatible with... Figure 4 The same method is provided for the stagnation detection controller 408 in the middle.

[0086] The mesh network 600 has nodes 602 organized in rows [R0, R1, R2] and columns [C0, C1, C2]. In this respect, there are nodes 602 with three rows [R0, R1, R2] and three columns [C0, C1, C2]. Other aspects can have nodes 602 with any number of rows and columns.

[0087] The stagnation detection controller 604 is configured to assert a deadlock control output dlockTestEn on the deadlock initiation input 324 connected to each node in node 602. In this way, the stagnation detection controller 604 is configured to initiate a deadlock detection test, as explained above. Each node in node 602 has a deadlock output 326, as explained above.

[0088] The mesh network 600 includes a network of OR gates 606. The network of OR gates 606 is configured to detect stagnation from each node in node 602 via a stagnation detection circuit 312 (see [link to circuit 312]). Figure 3 The controller 604 performs an OR operation on the deadlock output 324 and provides a global deadlock output Odlock. The controller 604 is also coupled to the global deadlock output Odlock. In this way, the controller 604 is configured to sample the global deadlock output Odlock and determine whether any node in node 602 is deadlocked. In response to the global deadlock output Odlock being asserted, the controller 604 is configured to implement a reset procedure that reinitializes node 602 to a known state.

[0089] Regarding node 602 in the initial row R0, there is no OR gate 606 in row R0. However, an OR gate 606 is provided for each of the OR gates 606 in row R1. Regarding the OR gates 606 in row R1, each node 602 in row R1 corresponds to a different OR gate 606. For each OR gate 606 in row R1, a first OR input is coupled to the deadlock output 326 of the node 602 in row R1 corresponding to that OR gate 606. A second OR input of the OR gate 606 is coupled to the deadlock output 326 of the node 602 in the same column [either C0, C1, C2] but in the previous row R0.

[0090] Regarding OR gate 606 in row R2, each node in node 602 of row R2 corresponds to a different OR gate 606. For each OR gate 606 in row R2, the first OR input is coupled to the deadlock output 326 of the node 602 in row R2 corresponding to that OR gate 606. The second OR input of OR gate 606 is coupled to the OR output of OR gate 606 in the same column [either C0, C1, C2] but in the previous row R1.

[0091] The OR outputs of OR gate 606 in row R2 are each coupled as distinct OR inputs to the last OR gate in OR gate 606 outside the row and column. The OR output of the last OR gate 606 is the overall deadlock output Odlock. Stasis detection controller 604 is coupled to the overall deadlock output Odlock.

[0092] In some respects, there may be an additional 602 rows of nodes, thus allowing for an OR gate. Figure 6 Row R3 shown is the configuration of the last row. However, if an additional intermediate row is provided between a row configured in the same way as row R2 (the row after the initial row) and a row configured in the same way as row R3 (the configuration of the last row), the OR input will be configured in the same way as row R3, because OR gate 606 will receive one OR input from the OR output of an OR gate in the same column but a previous row, and another OR input from its associated node 602. The OR output of OR gate 606 in the additional intermediate row will be provided in the same way as OR gate 606 in row 2, because that OR output will be the OR input of OR gate 606 in a subsequent row. These and other configurations of OR gate 606 and node 606 are all within the scope of this disclosure.

[0093] Figure 7 The flowchart 700 is a method for detecting deadlocks in circular dependencies among a group of multiple nodes in a mesh network based on some aspects of the diagram, wherein each node in the network has a stagnation detection circuit.

[0094] Flowchart 700 includes processes 702 to 712. In some respects, the mesh network executing processes 702 to 712 is Figure 1 The mesh network 100 shown Figure 4 Mesh network 406 or Figure 6 The mesh network shown is 600. Examples of nodes include... Figure 1 Node 102 in Figure 2 Node 102 in Figure 3 Node 302 in Figure 4 Node 402 and Figure 6 Node 602 in the diagram. An example of a stall detection circuit is... Figure 1 The stagnation detection circuit 105 in the middle Figure 3 and Figure 4The stagnation detection circuit 302 and Figure 5 The stall detection circuit 500 is used in the process. The process begins at process 702.

[0095] In process 702, a deadlock initiation input is asserted for each stall detection circuit in the stall detection circuit during a first time period. In some aspects, process 702 is executed by a stall detection controller. In some aspects, the stall detection controller is... Figure 4 The stagnation detection controller 408 or Figure 5 The stall detection controller 604 is described. In some aspects, the first time period should be sufficient to allow the stall input and stall output of each stall detection circuit in each node of the node to stabilize. In some aspects, the first time period therefore depends on the maximum propagation delay between nodes when the deadlock initiation input of each node in the node is asserted. In some aspects, the stall input is... Figure 3 , Figure 4 and Figure 5 The stagnant input is 314. In some respects, the stagnant output is... Figure 3 , Figure 4 and Figure 5 The stagnant output is 316.

[0096] In some respects, the deadlock initiation input is asserted after a timer expires. Therefore, after a certain period, the stall detection controller initiates a stall detection test to ensure no deadlock occurs. In other respects, the stall detection controller is configured to monitor certain parameters related to the operation of the core and / or mesh network. In response to parameters indicating inefficient operation of the core and / or mesh network, the stall detection circuitry initiates a stall detection test by asserting the deadlock initiation input. The process then proceeds to process 704.

[0097] In process 704, assertions on the deadlock initiation inputs of each deadlock detection circuit in the deadlock detection circuits are cancelled during the second time period. In some respects, the second time period should be sufficient to allow the deadlock inputs and deadlock outputs of each deadlock detection circuit in each node to stabilize. The second time period therefore depends on the maximum propagation delay between nodes when the deadlock initiation inputs of each node in the node are cancelled. The process then proceeds to process 706.

[0098] In process 706, the stall input of the stall detection circuit is detected as indicating an upstream stall, and the output indicates that the upstream node is stalled. The process then proceeds to process 708.

[0099] In process 708, the stall output of the stall detection circuit is detected as an indication that the node is stalled. The process then proceeds to block 710.

[0100] In process 710, an OR operation is performed on the stagnant output from each of the nodes to determine whether a global deadlock output is asserted, where stagnant outputs include stagnant outputs. In some respects, the OR operation is performed by... Figure 5 OR gate 516 and / or Figure 6 The OR gate 606 is executed. The process then proceeds to box 712.

[0101] In process 712, the overall deadlock output is sampled to determine if any node in the cluster is stalled. In some respects, the overall deadlock output is Figure 6 The overall deadlock output is Odlock. In some cases, if a deadlock is detected, the mesh network is reset. In other cases, if no deadlock is detected, the mesh network is reconfigured to continue normal operation.

[0102] Figure 8 This is an exemplary block diagram of a processor-based system 800, which includes a processor 802 configured to execute computer instructions for execution. The processor-based system also includes a memory system 804 comprising one or more memory arrays, each including multiple memory banks, and including integrated serialization and / or deserialization circuitry. The integrated serialization circuitry is configured to convert a parallel data stream of read data received from individually switched memory banks into a single serialized read data stream to be provided on an output bus in burst read mode. The deserialization circuitry is configured to convert a serialized write data stream received on an input bus for write operations into a single parallel write data stream to be written to memory banks simultaneously in burst write mode. The memory system 804 in this example includes an instruction cache 806, a data cache 808, and system memory 810.

[0103] Continue to refer to Figure 8The processor-based system 800 may be circuitry or circuitry included in electronic boards (such as printed circuit boards (PCBs), servers, personal computers, desktop computers, laptop computers, personal digital assistants (PDAs), computing tablets, mobile devices, or any other devices), and may represent, for example, a server or user computer. The processor 802 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc. The processor 802 includes instruction processing circuitry 809, configured to execute processing logic in computer instructions for performing the operations and steps discussed herein. The processor 802 also includes an instruction cache 806 for temporary fast access memory storage of instructions. Instructions fetched or prefetched from memory (such as system memory 810 via system bus 812) are stored in the instruction cache 806. The processor 802 also includes a data cache 808 for temporary fast access memory-stored data from system memory 810 via system bus 812. In some aspects, the processor 802 has a core that communicates via a mesh network, such as... Figure 1 The mesh network 100 shown Figure 4 Mesh network 406 or Figure 6 The mesh network shown is 600.

[0104] Processor 802 and system memory 810 are coupled to system bus 812 and can be mutually coupled to peripheral devices included in processor-based system 800. Processor 802 is known to communicate with these other devices by exchanging address, control, and data information on system bus 812. For example, processor 802 can send bus transaction requests to memory controller 814 in system memory 810, as an example of a slave device. Although in Figure 8 Not shown, but multiple system buses 812 may be provided, each forming a different architecture. In this example, the memory controller 814 is configured to provide memory access requests to the memory array 816 in the system memory 810. The memory array 816 consists of an array of storage bit cells for storing data. The system memory 810 may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM), etc.), and static memory (e.g., flash memory, static random access memory (SRAM), etc.), as a non-limiting example.

[0105] Other devices can be connected to system bus 812. For example... Figure 8As illustrated, these devices, by way of example, may include system memory 810, one or more input devices 818, one or more output devices 820, modem 822, and one or more display controllers 824. The input devices 818 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 820 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 822 may be any device configured to allow data exchange to and from network 826. Network 826 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. Modem 822 may be configured to support any type of desired communication protocol. Processor 802 may also be configured to access display controllers 824 via system bus 812 to control information sent to one or more displays 828. The (multiple) displays 828 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0106] Figure 8 The processor-based system 800 may include a set of instructions 830 that, when executed by a processor (such as processor 802), perform serialization of read data from memory system 804 by converting a parallel data stream of read data received from separately switched memory banks into a single serialized read data stream to be provided on the output bus in burst read mode, and / or perform deserialization of write data delivered to memory system 804 for writing by converting a serialized write data stream received on the input bus for write operations into a single parallel write data stream to be written to memory banks simultaneously in burst write mode. Instructions 830 may be stored in system memory 810, processor 802, and / or instruction cache 806, as an example of a non-transitory computer-readable medium 832. Instructions 830 may also reside wholly or at least partially within system memory 810 and / or processor 802 during their execution. Instructions 830 may also be transmitted or received via a network 826 via a modem 822, such that network 826 includes the non-transitory computer-readable medium 832, or an input device 818 as another example.

[0107] Although the non-transitory computer-readable medium 832 is shown as a single medium in the exemplary respect, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device and causing the processing device to perform any one or more methods of the aspects disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0108] The aspects disclosed herein include various steps. These steps may be formed by hardware components or may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with those instructions to perform these steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0109] The aspects disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to the aspects disclosed herein. Machine-readable media include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include: machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.); and so on.

[0110] Unless otherwise stated and as is apparent from the preceding discussion, it should be understood that throughout this specification, discussions using terms such as “processing,” “calculating,” “determining,” and “displaying” refer to the actions and processes of a computer system or similar electronic computing device that manipulates and converts data and memory in the computer system’s registers, which are represented as physical (electronic) quantities, into other data that are similarly represented as physical quantities in the computer system’s memory or registers or other such information storage, transmission, or display devices.

[0111] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used in conjunction with the programs based on the teachings herein, or it can be demonstrated that constructing more specialized devices to perform the required method steps is convenient. The required structures for various such systems will emerge from the above description. Furthermore, the aspects described herein are not referred to in any particular programming language. It should be understood that the teachings of the aspects described herein can be implemented using various programming languages.

[0112] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. The component systems described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip, as an example. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their functionality. How this functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this aspect.

[0113] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or performed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0114] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0115] It should also be noted that the operational steps described in any exemplary aspect of this document are described as being for the purpose of example and discussion. The described operations can be performed in many different sequences besides those illustrated. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. Those skilled in the art will also understand that information and signals can be represented using any of the various techniques and skills available. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0116] Unless otherwise expressly stated, it is not intended to interpret any method described herein as requiring its steps to be performed in a particular order. Therefore, no particular order is intended to be inferred where the method claims do not actually describe the order in which the steps are to be followed, or where the claims or description do not otherwise specifically specify that these steps are limited to a particular order.

[0117] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed aspects that encompass the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

Claims

1. A mesh network (104, 406, 600), comprising: Multiple nodes (102, 302, 402, 602), the multiple nodes being configured to form the mesh network, each node comprising: Multiple input pipeline circuit (306); Multiple output storage pipeline circuits (308); and Multiple arbiter circuits (310), each configured to arbitrate data traffic between an input pipeline circuit of the multiple input pipeline circuits and an output pipeline circuit of the multiple output pipeline circuits; and The stall detection circuit (312, 500) includes: Stagnant input (314), said stagnant input being coupled to the upstream stagnant output (316) of the upstream node (102) of the plurality of nodes; and Stagnant output (316), the stagnant output being coupled to the downstream stagnant input (314) of the downstream node (102) of the plurality of nodes. The stagnation detection circuit is configured to detect deadlocks in a cyclic dependency between a group of nodes, including the node, in response to the following: The stagnation input indicates that the upstream stagnation output indicates that the upstream node is stagnant; and The stall output indicates that the node is stalled.

2. The mesh network of claim 1, wherein the stall detection circuit is configured to provide the stall output in response to any of the following, such that the stall output indicates that the node is stalled: One of the plurality of input pipeline circuits is stalled, wherein the stalled input pipeline circuit corresponds to the stalled input. One of the multiple output pipeline circuits is stopped; as well as One of the arbitrator circuits in the arbitrator circuit links the stalled one of the plurality of input pipeline circuits to the stalled one of the output pipeline circuits.

3. The mesh network of claim 2, wherein the stalled output corresponds to the stalled output pipeline circuit in the output pipeline circuit.

4. The mesh network according to claim 1, wherein: The stag input is the first stag input (314(0) in 402(1)); The upstream stall output is the first upstream stall output (316(1) in 402(0)); The stalled output is the first stalled output (316(2) in 402(1)); The downstream stag input is the first downstream stag input (314(1) in 402(2)); as well as The stall detection circuit also includes: Multiple stagnant inputs (314 in 402(1)), the multiple stagnant inputs including the first stagnant input, each of the stagnant inputs being coupled to a different upstream stagnant output of a plurality of upstream stagnant outputs of the upstream node, the plurality of upstream stagnant outputs including the first upstream stagnant output, each of the input pipeline circuits corresponding to a different stagnant input; as well as Multiple stall outputs (316 in 402(1)), the multiple stall outputs including the first stall output, each of the stall outputs being coupled to a different downstream stall input of a plurality of downstream stall inputs of the downstream node, the plurality of downstream stall inputs including the first downstream stall input, each of the output pipeline circuits corresponding to a different stall output of the stall outputs.

5. The mesh network of claim 4, wherein the stall detection circuit is configured to detect deadlock in the circular dependency among the plurality of nodes including the node in response to: Any of the stalled outputs indicates that the node is stalled; and Any of the arbitrator circuits in the arbitrator circuits has linked any one of the stag inputs in the stag inputs that indicates that the corresponding upstream stag output is stagnant to at least one stag output in the stag outputs that indicates that the node is stagnant.

6. The mesh network of claim 5, wherein the stagnation detection circuit is configured to provide any one of the stagnation outputs indicating that the node is stagnant in response to any of the following: One of the input pipeline circuits (306 (0) in 402 (1)) is stalled, wherein the stalled input pipeline circuit corresponds to one of the stalled inputs that indicates that the upstream node is stalled; One of the output pipeline circuits (308(2) in 402(1)) is stalled; and Any one of the arbitrator circuits (310 (2) in 402 (1)) links the stalled input pipeline circuit in the plurality of input pipeline circuits to the stalled output pipeline circuit in the output pipeline circuit.

7. The mesh network of claim 6, wherein each of the stagnant outputs (316 in 402 (1)) corresponds to a different output pipeline circuit in the output pipeline circuit (308 in 402 (1)).

8. The mesh network of claim 1, wherein the stagnation detection circuit further comprises: An input pipeline input (INPUT PIPE [n]) is configured to indicate whether one of the plurality of input pipeline circuits is stalled; An output pipeline input (OUTPUT PIPE [m]) configured to indicate whether one of the plurality of output pipeline circuits is stalled; and The stagnation detection circuit of each of the nodes is configured to generate the stagnation output (316(m)) in response to the following, such that the stagnation output indicates that the node is stagnant: At least one of the arbitrator circuits in the arbitrator circuit (310) has linked the input pipeline circuit to the output pipeline circuit; The input pipeline input indicates that the input pipeline circuit (306) is stalled, wherein the stall input corresponds to the input pipeline circuit; as well as The output pipeline input indicates that the output pipeline circuit (308) is stalled, wherein the stalled output corresponds to the output pipeline circuit.

9. The mesh network of claim 8, wherein the stagnation detection circuit comprises an input AND gate (502(n)) and an output AND gate (512(m)), wherein: The input AND gate has a first AND input coupled to the stagnant input and a second AND input coupled to the input pipeline input, the first AND output of the input AND gate serving as an intermediate stagnant input (INTERSTALLED(n)); and The output AND gate has a third AND input operatively associated with the intermediate stall input via at least one arbiter circuit in the arbiter circuit, and a fourth stall input coupled to the output pipeline input, wherein the output AND gate has the stall output (316(m)).

10. The mesh network of claim 9, wherein the stagnation detection circuit further comprises an output conduit or gate (510(m)), wherein: The output pipe or gate has a first OR input operatively associated with the intermediate stall input and a second OR input coupled to the deadlock initiation input (324), and the output pipe or gate has an output pipe or output (OPO(m)); and The third is coupled to the output pipe or output.

11. The mesh network of claim 10, further comprising a controller (604) configured to assert the deadlock initiation input in order to initiate a deadlock detection test.

12. The mesh network according to claim 1, wherein: The stag input is the first stag input (314(0) in 402(1)); The upstream stall output is the first upstream stall output (316(1) in 402(0)); The stalled output is the first stalled output (316(2) in 402(1)); The downstream stag input is the first downstream stag input (314(1) in 402(2)); The stagnation detection circuit for each of the nodes further includes: Multiple stagnant inputs (314 in 402(1)), the multiple stagnant inputs including the first stagnant input, each of the stagnant inputs being coupled to a different upstream stagnant output of a plurality of upstream stagnant outputs of the upstream node, the plurality of upstream stagnant outputs including the first upstream stagnant output, each of the input pipeline circuits corresponding to a different stagnant input; as well as Multiple stall outputs (316 in 402(1)), the multiple stall outputs including the first stall output, each of the stall outputs being coupled to a different downstream stall input of a plurality of downstream stall inputs of the downstream node, the plurality of downstream stall inputs including the first downstream stall input, each of the output pipeline circuits corresponding to a different stall output of the stall outputs; Multiple input AND gates (502(n)), each of the input AND gates corresponding to a different input pipeline circuit in the input pipeline circuit, wherein each of the input AND gates has a first AND input coupled to a different stag input and a second AND input coupled to a different input pipeline input in the input pipeline circuit, wherein each of the input AND gates has an intermediate stag input; Multiple output pipes or gates (510(m)), each of which corresponds to a different output pipeline circuit in the output pipeline circuit, wherein each of the output pipes or gates has a first OR input, the first OR input being operatively associated with the intermediate stall input (INTERSTALLED(n)) of an input AND gate corresponding to an input pipeline circuit linked to the output pipe or gate in the input pipeline circuit, a second OR input being coupled to a deadlock initiation input (324), and an output pipe or output; and Multiple output AND gates (512(m)), each of the output AND gates corresponding to a different output pipeline circuit in the output pipeline circuit, each of the output AND gates having a third AND input and a fourth stag input coupled to the output pipe or output, the output pipe or output having linked the one input pipeline circuit in the input pipeline circuit to the corresponding output pipeline circuit of the output AND gate, the fourth stag input being coupled to the output pipeline input of the corresponding output pipeline circuit, wherein the output AND gate has a different stag output among the stag outputs.

13. The mesh network of claim 12, wherein the stall detection circuit of each of the nodes further comprises a deadlock or gate (516), the deadlock or gate comprising a plurality of deadlock or inputs and deadlock or outputs (326), each of the deadlock or inputs being coupled to a different stall output of the stall outputs (316(m)).

14. The mesh network of claim 13, further comprising a controller (604) coupled to the deadlock initiation input (324).

15. The mesh network of claim 14, further comprising an OR gate network (606) configured to perform an OR operation on the deadlock OR output (326) of the stall detection circuit from each of the nodes, and to provide a total deadlock output (ODLOCK), wherein the controller is also coupled to the total deadlock output.

16. The mesh network of claim 15, wherein the controller is configured to: Assert the deadlock initiation input during the first time period; Cancel the assertion that initiated the deadlock input during the second time period; and After the deadlock initiation input is canceled assertion during the second time period, the overall deadlock output is sampled to determine whether any node in the node is stalled.

17. The mesh network of claim 16, wherein the controller is further configured to declare that a deadlock has been detected in response to an assertion of the overall deadlock output.

18. The mesh network of claim 1 further includes a plurality of cores (304), each core being operatively associated with a different node among the nodes, and wherein each node among the nodes is a router (402) for the corresponding core.

19. A method (700) for detecting deadlock in a circular dependency among a group of multiple nodes in a mesh network, each node having a stagnation detection circuit, the method comprising: During the first time period, assert the deadlock initiation input of each of the deadlock detection circuits in the said deadlock detection circuits (702). During the second time period, cancel the assertion (704) of the deadlock initiation input for each of the deadlock detection circuits in the deadlock detection circuits. The stagnation detection circuit in the stagnation detection circuit detects the stagnation input indicating that the upstream stagnation output indicates that the upstream node is stagnant (706). Detect whether the stall output of the stall detection circuit indicates that the node is stalled (708); Perform an OR operation on the stagnant output from each of the nodes to determine whether the overall deadlock output is asserted, wherein the stagnant output includes the stagnant output (710). as well as The overall deadlock output is sampled to determine whether any node in the node is stalled (712).

20. A mesh network (104,406,600), comprising: Multiple nodes (102, 302, 402, 602), the multiple nodes being configured to form the mesh network, each node comprising: Multiple input pipeline circuit (306); Multiple output storage pipeline circuits (308); Multiple arbitrator circuits (310), each of which is configured to arbitrate data traffic between an input pipeline circuit in the multiple input pipeline circuits and an output pipeline circuit in the multiple output pipeline circuits; The stall detection circuit (312, 500) includes: A stagnant input (314), said stagnant input being coupled to an upstream stagnant output (316) of an upstream node (102) among the plurality of nodes, said stagnant input corresponding to an input pipeline circuit in the input pipeline circuit; and A stagnant output (316), said stagnant output being coupled to a downstream stagnant input (314) of a downstream node (102) among the plurality of nodes, said stagnant output corresponding to an output pipeline circuit in the output pipeline circuit; and The stagnation detection circuit is configured to detect deadlocks in a cyclic dependency between a group of nodes, including the node, in response to the following: The stall input indicates that the upstream node is stalled; An arbitrator circuit in the arbitrator circuit links one of the input pipeline circuits in the input pipeline circuit to one of the output pipeline circuits in the output pipeline circuit; and The stall output indicates that the node is stalled.

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