Power conversion device

Abstract

This power conversion device is provided with: a plurality of switching elements arranged along a low-potential wiring; and a drive circuit that simultaneously supplies a gate voltage to each of the plurality of switching elements via a gate wiring having a predetermined gate resistance. The wiring inductance generated in the low-potential wiring to which the plurality of switching elements are connected is smaller than the wiring inductance at a merging site where the currents output from the plurality of switching elements to the low-potential wiring merge, and the wiring inductance is smaller than the wiring inductance at a merging site where the currents output from the plurality of switching elements to the low-potential wiring merge. The gate resistance of the gate wiring connected to the switching element is set to a larger resistance value.

Description

Technical Field

[0001] This invention relates to an electric power conversion device. Background Technology

[0002] Power conversion devices use inverter circuits with switching elements configured as upper and lower arms to perform switching operations, converting direct current (DC) power into alternating current (AC). Furthermore, sometimes multiple switching elements are connected in parallel, utilizing each phase formed by the upper and lower arms of the inverter circuit. In this case, when the switching elements are connected in parallel along the wiring, the wiring inductance generated in the wiring to each switching element is different. Due to the difference in wiring inductance, differences in switching speed occur, and the current flowing through each switching element becomes unbalanced.

[0003] Patent Document 1 discloses a power conversion device, which includes a gate drive circuit for turning on / off each semiconductor module and a first gate wiring for each semiconductor module and connecting the semiconductor module to the gate drive circuit or other semiconductor modules during disconnection. The semiconductor module with the lower gate threshold voltage is connected to the gate drive circuit or other semiconductor modules through the first gate wiring with the lower impedance, so that the gate current of each semiconductor module is the same during disconnection.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-156304 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] In the technology described in Patent Document 1, the imbalance of current flowing through multiple switching elements due to differences in wiring inductance cannot be suppressed.

[0009] Methods for solving problems

[0010] The power conversion device of the present invention includes: a plurality of switching elements arranged along a low-potential wiring; and a drive circuit that simultaneously supplies a gate voltage to each of the plurality of switching elements via a gate wiring having a predetermined gate resistance. For a switching element that has a smaller wiring inductance generated in the low-potential wiring connected to the plurality of switching elements, and a smaller wiring inductance up to the point where the currents output from the plurality of switching elements to the low-potential wiring converge, the gate resistance of the gate wiring connected to that switching element is set to a larger resistance value.

[0011] The effects of the invention

[0012] According to the present invention, it is possible to suppress the imbalance of current flowing through multiple switching elements caused by differences in wiring inductance. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of the power conversion device according to the first embodiment.

[0014] Figure 2 (A) and (B) are top views of the first and second layers of a multilayer wiring board on which the inverter circuit of the power conversion device of the first embodiment is arranged.

[0015] Figure 3 (A) and (B) are top views of the third and fourth layers of the multilayer wiring board on which the inverter circuit of the power conversion device of the first embodiment is arranged.

[0016] Figure 4 Figures (A) to (E) show the switching elements of the power conversion device according to the first embodiment.

[0017] Figure 5 This is a circuit diagram of the power conversion device according to the second embodiment.

[0018] Figure 6 This is a top view of the first layer of a multilayer wiring board on which the inverter circuit of the power conversion device of the second embodiment is configured.

[0019] Figure 7 This is a circuit diagram of the power conversion device according to the third embodiment.

[0020] Figure 8 This is a top view of the first layer of a multilayer wiring board on which the inverter circuit of the power conversion device of the third embodiment is configured. Detailed Implementation

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following description and drawings are examples for illustrating the present invention; appropriate omissions and simplifications have been made for clarity of explanation. The present invention may also be implemented in various other ways. Unless otherwise specified, each constituent element may be a single element or a plurality of elements.

[0022] The positions, sizes, shapes, and extents of the constituent elements shown in the accompanying drawings are sometimes not representations of actual positions, sizes, shapes, or extents for ease of understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and extents disclosed in the accompanying drawings.

[0023] [First Implementation Method]

[0024] Figure 1This is a circuit diagram of a power conversion device 100 according to a first embodiment of the present invention. The power conversion device 100 includes an inverter circuit 200 and a drive circuit 300.

[0025] Inverter circuit 200 drives, for example, an electric motor mounted on an electric vehicle. The electric motor has, for example, three-phase coils, and in this case, inverter circuit 200 has upper and lower arms for applying a predetermined energizing mode to the three-phase coils. Furthermore, four switching elements are connected in parallel to form each phase of the inverter circuit 200, which is formed by the upper and lower arms. Figure 1 This refers to the upper and lower arms of one phase. Specifically, the upper arm is constructed by connecting four switching elements P1, P2, P3, and P4 in parallel, and the lower arm is constructed by connecting four switching elements N1, N2, N3, and N4 in parallel. Furthermore, the following explanation uses the case of four switching elements connected in parallel as an example, but it is not limited to four; the invention can also be applied to the case of multiple switching elements connected in parallel.

[0026] The switching elements P1, P2, P3, P4 in the upper arm and N1, N2, N3, N4 in the lower arm use power semiconductor devices such as IGBTs, Si-MOSFETs, and GaN-HEMTs. Additionally, in Figure 1 The diagram shows an example where switching elements P1, P2, P3, P4 and switching elements N1, N2, N3, N4 use MOSFETs. In the case where each switching element P1, P2, P3, P4, N1, N2, N3, N4 is a MOSFET, a freewheeling diode is connected in anti-parallel.

[0027] The drain terminals of the upper arm switching elements P1, P2, P3, and P4 are connected to the high-potential wiring PL. The source terminals of the upper arm switching elements P1, P2, P3, and P4 are connected to the AC wiring AL. The drain terminals of the lower arm switching elements N1, N2, N3, and N4 are connected to the AC wiring AL. The source terminals of the lower arm switching elements N1, N2, N3, and N4 are connected to the low-potential wiring NL. Furthermore, when considering the lower arm switching elements N1, N2, N3, and N4, the AC wiring AL is sometimes referred to as the high-potential wiring. Conversely, when considering the upper arm switching elements P1, P2, P3, and P4, the AC wiring AL is sometimes referred to as the low-potential wiring.

[0028] The high-potential wiring PL is connected to the positive terminal of the DC power supply (not shown) via the high-potential terminal P, and the low-potential wiring NL is connected to the negative terminal of the DC power supply via the low-potential terminal N. The AC wiring AL is connected to the load via the AC terminal AC. The load is, for example, a winding of one phase of a motor.

[0029] On the gate terminals of the switching elements P1, P2, P3, and P4 in the upper arm, the gate wiring GLP is connected from the drive circuit 300. In the source terminals of the switching elements P1, P2, P3, and P4, the source terminal for applying the gate voltage between the gate and the source is connected to the source wiring PSL in the upper arm.

[0030] The drive circuit 300 simultaneously supplies a gate voltage between the source wiring PSL and the gate wiring GLP of the upper arm, turning on the switching elements P1, P2, P3, and P4. Conversely, by stopping the supply of the gate voltage, the switching elements P1, P2, P3, and P4 are turned off.

[0031] On the gate terminals of the switching elements N1, N2, N3, and N4 in the lower arm, gate wiring GLN is connected from the drive circuit 300. In the source terminals of the switching elements N1, N2, N3, and N4, the source terminal for applying the gate voltage between the gate and source is connected to the source wiring NSL in the lower arm.

[0032] The drive circuit 300 simultaneously supplies a gate voltage between the lower arm source wiring NSL and the gate wiring GLN, turning on the switching elements N1, N2, N3, and N4. Conversely, by stopping the supply of the gate voltage, the switching elements N1, N2, N3, and N4 are turned off.

[0033] The drive circuit 300 controls the switching elements P1, P2, P3, P4 of the upper arm and the switching elements N1, N2, N3, N4 of the lower arm to turn on / off according to the drive command input from the control circuit (not shown). Thus, the inverter circuit 200 converts the DC power supplied by the DC power source into AC power, and outputs the converted AC power to loads such as motors.

[0034] like Figure 1 As shown, multiple switching elements are connected in parallel on one phase of the upper and lower arms of the inverter circuit 200. For details in this case, please refer to [reference needed]. Figure 2 As will be described later, since the switching elements are connected in parallel along the low-potential wiring NL, the wiring inductance varies from the point where each switching element connects to the low-potential wiring NL to the point A where the currents from each switching element to the low-potential wiring NL converge. Specifically, wiring inductance L2 is generated from the connection point of switching element N1 and low-potential wiring NL to the connection point of switching element N2 and low-potential wiring NL. Wiring inductance L3 is generated from the connection point of switching element N2 and low-potential wiring NL to the connection point of switching element N3 and low-potential wiring NL. Wiring inductance L4 is generated from the connection point of switching element N3 and low-potential wiring NL to the connection point of switching element N4 and low-potential wiring NL.

[0035] Without applying this embodiment, the switching speed of a switching element with small wiring inductances L2, L3, and L4 increases, and the drain-source current of the switching element increases. For example, when comparing the drain-source currents of switching element N1 and switching element N4, the drain-source current of switching element N1 is larger than that of switching element N4 because of the wiring inductances L2+L3+L4 present in switching element N4.

[0036] In this embodiment, for switching elements with smaller wiring inductances L2, L3, and L4 up to the confluence point A where the currents from each of the multiple switching elements N1 to N4 converge to the low-potential wiring NL, the gate resistance of the gate wiring GL connected to that switching element is set to a larger resistance value. Specifically, as follows... Figure 1 As shown, the resistance values ​​of the gate resistors R1 to R4 of each switching element N1 to N4 are set to R1 > R2 > R3 > R4. Therefore, by adjusting the difference in switching speed caused by the difference in wiring inductances L2, L3, and L4 using the gate resistors, the imbalance of current flowing through the switching elements can be suppressed. If the current imbalance can be suppressed, the deviation in losses of each switching element can be suppressed, and the output density of the power conversion device 100 can be improved.

[0037] Figure 2 (A) Figure 2 (B) Figure 3 (A) Figure 3 (B) is a top view of the multilayer wiring board 400 on which the inverter circuit 200 of the power conversion device 100 of this embodiment is configured. Figure 2 (A) represents the first layer. Figure 2 (B) indicates the second layer. Figure 3 (A) represents the third layer. Figure 3 (B) indicates the fourth layer. In addition, the example is a 4-layer multilayer wiring board 400, but it is not limited to 4 layers. A multilayer wiring board 400 with any number of layers can be used. It will be referred to as wiring board 400 below.

[0038] In addition, Figure 2 (A) Figure 2 (B) Figure 3 (A) Figure 3 In (B), an example of arranging one phase of the inverter circuit 200 on the wiring board 400 is given, but three phases can also be arranged on one wiring board 400. In this case, the present invention is also applicable.

[0039] like Figure 2As shown in (A), on the first layer of the wiring substrate 400, the four switching elements P1 to P4 of the upper arm are arranged in a straight line, and in the illustrated example, they are arranged in a vertical column from top to bottom. Furthermore, the four switching elements N1 to N4 of the lower arm are arranged in a vertical column from top to bottom, parallel to the arrangement of the switching elements P1 to P4 of the upper arm. On both sides of the arrangement of switching elements P1 to P4, the gate wiring GLP and high-potential wiring PL of switching elements P1, P2, P3, and P4 extend on the wiring substrate 400. On both sides of the arrangement of switching elements N1 to N4, the low-potential wiring NL and the gate wiring GLN of switching elements N1 to N4 extend on the wiring substrate 400.

[0040] Because the low-potential wiring NL extends along the arrangement of switching elements N1 to N4, wiring inductances L2, L3, and L4 are generated in the low-potential wiring NL between each switching element N1 to N4 when each switching element N1 to N4 is turned on. Additionally, Figure 2 In (A), the wiring inductances L2, L3, and L4 are illustrated as coils, but they are not actually coils. They are schematic representations for easy understanding of the wiring inductance generated by energization.

[0041] The gate sides of each switching element N1 to N4 are connected to the gate wiring GLN via gate resistors R1 to R4, respectively. In addition, the gate sides of each switching element P1 to P4 are connected to the gate wiring GLP.

[0042] like Figure 2 As shown in (A), the high-potential wiring PL is connected to the high-potential terminal P on the first layer of the wiring substrate 400. Figure 2 As shown in (B), the low-potential wiring NL is connected to the low-potential terminal N through a via in the second layer of the wiring substrate 400. Figure 3 As shown in (A), the source terminals of the switching elements P1, P2, P3, and P4 in the upper arm are connected to the AC wiring AL through vias. The drain terminals of the switching elements N1, N2, N3, and N4 in the lower arm are connected to the AC wiring AL through vias. Figure 3 The AC wiring AL connection is shown in (A). Figure 2 As shown in (A), the AC wiring AL is connected to the AC terminal AC through a through-hole in the first layer of the wiring substrate 400.

[0043] In the source terminals of switching elements P1, P2, P3, and P4, such as Figure 3 As shown in (B), the source terminal for applying the gate voltage between the gate and source is connected to the upper arm source wiring PSL through a via in the fourth layer of the wiring substrate 400. In the source terminals of switching elements N1, N2, N3, and N4, as shown... Figure 3As shown in (B), the source terminal for applying the gate voltage between the gate and the source is connected to the lower arm source wiring NSL in the fourth layer of the wiring substrate 400 through a via.

[0044] Figure 4 (A) Figure 4 (B) Figure 4 (C) Figure 4 (D) Figure 4 (E) is a diagram showing the switching element P1 of the power conversion device 100 in this embodiment.

[0045] Figure 4 (A) is a top view of the switching element P1. Figure 4 (B) is a top view of the low-potential electrode plate KL inside the switching element P1. Figure 4 (C) is a top view of the high-potential electrode plate KH inside the switching element P1. Figure 4 (D) is a cross-sectional view showing the low-potential electrode plate KL inside the switching element P1. Figure 4 (E) is a cross-sectional view of the high-potential electrode plate KH inside the switching element P1.

[0046] Taking switching element P1 as an example, the same applies to switching elements P2, P3, and P4. The same applies to switching elements N1, N2, N3, and N4, but they are configured in... Figure 2 The diagram in the middle becomes Figure 4 (A) Figure 4 (B) Figure 4 The diagram shown in (C) is rotated 180 degrees to become... Figure 4 (D) Figure 4 The diagram shown in (E) is a left-right reversed diagram.

[0047] like Figure 4 As shown in (A), the high-potential drain terminal D1 and the low-potential source terminal S1 protrude from one side of the switching element P1, which is sealed by molding resin, while the gate terminal G1 and the source terminal S2 for applying the gate voltage protrude from the other side of the switching element P1.

[0048] Figure 4 (B) is a top view of the switching element P1 with the upper layer of molding resin, etc., removed from the low-potential electrode plate KL, and the source terminal S1 is derived from the low-potential electrode plate KL. The cross-sectional view seen from section line A-A' in this figure is... Figure 4 (D). Additionally, the cross-sectional view seen from section line B-B' is... Figure 4 (E).

[0049] Figure 4(C) is a top view of the low-potential side of element Q, with the upper components, including the low-potential electrode plate KL, removed from the switching element P1. The source terminal S2 is connected to the source electrode of element Q on the substrate via a bonding wire. The gate terminal G1 is connected to the gate electrode of element Q on the substrate via a bonding wire. Additionally, the drain terminal D1 is derived from the high-potential electrode plate KH.

[0050] like Figure 4 As shown in (D), the low-potential electrode plate KL and the high-potential electrode plate KH are bonded to both sides of the component Q via solder. The low-potential electrode plate KL is connected to the source terminal S1. Additionally, the gate electrode of the component Q is connected to the gate terminal G1 via a bonding wire.

[0051] like Figure 4 As shown in (E), the high-potential electrode plate KH is connected to the drain terminal D1. Additionally, the source electrode of element Q is connected to the source terminal S2 via a bonding wire.

[0052] According to the first embodiment, it is possible to suppress the imbalance of current flowing through multiple switching elements caused by the difference in wiring inductance L2, L3, L4, eliminate the deviation of loss of each switching element, and improve the output density of the power conversion device 100.

[0053] Furthermore, the wiring inductances L2, L3, and L4 are not limited to the case where low-potential wiring NL is disposed on the wiring substrate 400. For example, they can also be generated in the case where wiring substrate 400 is not used, and leads are used instead of low-potential wiring NL. Even in such cases, the implementation method can still be applied.

[0054] [Second Implementation]

[0055] Figure 5 This is a circuit diagram of the power conversion device 100 according to the second embodiment of the present invention. Figure 1 Compared to the first embodiment shown, the connection of the gate resistors R1 to R4 is different. Other configurations are the same. Figure 1 The same symbols are used to mark the same parts and their descriptions are simplified.

[0056] In this embodiment, the gate resistors R1 to R4 are connected in series with the gate wiring GLN. Specifically, as shown... Figure 5 As shown, a gate resistor R1 is provided on the gate wiring GLN between switching elements N1 and N2. A gate resistor R2 is provided on the gate wiring GLN between switching elements N2 and N3. A gate resistor R3 is provided on the gate wiring GLN between switching elements N3 and N4. A gate resistor R4 is provided on the gate wiring GLN between switching element N4 and the drive circuit 300.

[0057] Furthermore, for switching elements with smaller wiring inductances L2, L3, and L4 up to the confluence point A where the currents from each of the multiple switching elements N1 to N4 converge to the low-potential wiring NL, the gate resistance of the gate wiring GL connected to that switching element is set to a larger resistance value. Specifically, the resistance values ​​of the gate resistances of each switching element N1 to N4 are set as R1+R2+R3+R4>R2+R3+R4>R3+R4>R4. Thus, by adjusting the difference in switching speed caused by the difference in wiring inductances L2, L3, and L4 using the gate resistance, the imbalance of current flowing through the switching elements can be suppressed.

[0058] Figure 6 This is a top view of the multilayer wiring board 400 on which the inverter circuit 200 of the power conversion device 100 of this embodiment is configured, showing its first layer. Furthermore, the second to fourth layers are the same as those shown in the first embodiment. Figure 2 (B) Figure 3 (A) Figure 3 (B) is the same, therefore the illustration is omitted. Furthermore, similar to the first embodiment, it is not limited to four layers; a multilayer wiring substrate 400 of any number of layers can be used, hereinafter referred to as wiring substrate 400. Alternatively, wiring substrate 400 may not be used, and leads may be used instead of low-potential wiring NL.

[0059] This implementation method and Figure 2 Compared to the first embodiment shown in (A), the configuration of the gate resistors R1 to R4 is different. Other configurations are the same. Figure 2 (A) are the same, and the same symbols are used to mark the same parts and their descriptions are simplified.

[0060] For reference Figure 5 As explained, in this embodiment, the gate resistors R1 to R4 are connected in series with the gate wiring GLN. Specifically, as... Figure 6 As shown, a gate resistor R1 is provided on the gate wiring GLN between switching elements N1 and N2. A gate resistor R2 is provided on the gate wiring GLN between switching elements N2 and N3. A gate resistor R3 is provided on the gate wiring GLN between switching elements N3 and N4. A gate resistor R4 is provided on the gate wiring GLN between switching element N4 and the drive circuit 300.

[0061] and Figure 2Compared to the first embodiment shown in (A), in this embodiment, gate resistors R1 to R4 are arranged on the gate wiring GLN. Therefore, the arrangement of switching elements N1 to N4 and the spacing of the gate wiring GLN can be reduced, and the proprietary area is reduced, thus enabling miniaturization of the power conversion device 100. In particular, when three phases are arranged on a single wiring substrate 400, the proprietary area can be further reduced.

[0062] According to the second embodiment, the imbalance of current flowing through multiple switching elements caused by the difference in wiring inductances L2, L3, and L4 can be suppressed, the deviation of losses of each switching element can be eliminated, and the output density of the power conversion device 100 can be improved. Furthermore, the power conversion device 100 can be miniaturized.

[0063] [Third Implementation Method]

[0064] Figure 7 This is a circuit diagram of the power conversion device 100 according to the third embodiment of the present invention. Figure 5 The difference between this embodiment and the second embodiment shown is that this embodiment includes a bypass wiring NdL, which has diodes d1, d2, and d3 that bypass the gate resistors R1, R2, and R3. Other configurations are the same as... Figure 5 The same symbols are used to mark the same parts and their descriptions are simplified.

[0065] like Figure 7 As shown, on the bypass wiring NdL that bypasses gate resistor R1, the anode of diode d1 is connected to the gate side of switching element N1. On the bypass wiring NdL that bypasses gate resistor R2, the anode of diode d2 is connected to the gate side of switching element N2. On the bypass wiring NdL that bypasses gate resistor R3, the anode of diode d3 is connected to the gate side of switching element N3. Furthermore, the bypass wiring NdL is not limited to a structure where all diodes d1, d2, and d3 bypass all gate resistors R1, R2, and R3; depending on the characteristics of the switching element or gate wiring GLN, it can also include a bypass wiring NdL that bypasses only a portion of the gate resistors R1, R2, and R3.

[0066] The bypass wiring NdL alters the current path, preventing switching speed adjustments when switching elements N1-N4 are off. Specifically, when switching elements N1-N4 are on, the gate wiring GLN serves as the current path; when switching elements N1-N4 are off, the bypass wiring NdL serves as the current path. Therefore, the influence of gate resistors R1-R4 can be eliminated when switching elements N1-N4 are off.

[0067] Figure 8This is a top view of the multilayer wiring board 400 on which the inverter circuit 200 of the power conversion device 100 of this embodiment is configured, showing its first layer. Furthermore, the second to fourth layers are the same as those shown in the second embodiment. Figure 6 The same applies, therefore the illustration is omitted. Furthermore, similar to the second embodiment, it is not limited to four layers; any number of layers of multilayer wiring substrate 400, hereinafter referred to as wiring substrate 400, can be used. Alternatively, wiring substrate 400 may not be used, and leads may be used instead of low-potential wiring NL.

[0068] In this embodiment, the difference lies in that... Figure 6 The second embodiment shown incorporates a bypass wiring NdL. Other configurations are similar. Figure 6 The same symbols are used to mark the same parts and their descriptions are simplified.

[0069] For reference Figure 7 As explained, this embodiment includes a bypass wiring NdL, which has diodes d1, d2, and d3 that bypass the gate resistors R1, R2, and R3. Specifically, as... Figure 8 As shown, the connection point of switching element N1 and gate resistor R1 is connected to the bypass wiring NdL via diode d1. The connection point of switching element N2 and gate resistor R2 is connected to the bypass wiring NdL via diode d2. The connection point of switching element N3 and gate resistor R3 is connected to the bypass wiring NdL via diode d3.

[0070] According to the third embodiment, the imbalance of current flowing through multiple switching elements caused by the difference in wiring inductances L2, L3, and L4 can be suppressed, the deviation of losses of each switching element can be eliminated, and the output density of the power conversion device 100 can be improved. Furthermore, when multiple switching elements are turned off, the influence of multiple gate resistors can be eliminated.

[0071] The following effects can be obtained by implementing the methods described above.

[0072] (1) The power conversion device 100 includes: a plurality of switching elements N1, N2, N3, N4 arranged along a low-potential wiring NL; and a drive circuit 300 that simultaneously supplies a gate voltage to each of the switching elements N1, N2, N3, N4 via a gate wiring GLN having predetermined gate resistances R1, R2, R3, R4. For switching elements N1, N2, N3, N4 connected to the plurality of switching elements N1, N2, N3, N4, and whose wiring inductances L2, L3, L4 are smaller up to the confluence point A where the currents output from the switching elements N1, N2, N3, N4 to the low-potential wiring NL converge, the gate resistances R1, R2, R3, R4 of the gate wiring GLN connected to the switching elements N1, N2, N3, N4 are set to larger resistance values. Therefore, it is possible to suppress the imbalance of current flowing through multiple switching elements caused by the difference in wiring inductance.

[0073] This invention is not limited to the embodiments described above. Other embodiments within the scope of the technical concept of this invention are also included within the scope of this invention, as long as they do not impair the characteristics of this invention. Additionally, it may be a combination of the embodiments described above.

[0074] Explanation of symbols

[0075] 100 … power conversion device, 200 … inverter circuit, 300 … drive circuit, 400 … wiring substrate, PL … high-potential wiring, P … high-potential terminal, NL … low-potential wiring, N … low-potential terminal, AL … AC wiring, AC … AC terminal, P1, P2, P3, P4 … switching element, N1, N2, N3, N4 … switching element, L2, L3, L4 … wiring inductance, R1, R2, R3, R4 … gate resistor, PSL … upper arm source wiring, NSL … lower arm source wiring, GLN, GLP … gate wiring, A … current confluence point, Q … element, S1, S2 … source terminal, G1 … gate terminal; D1 … drain terminal, KH … high-potential electrode plate, KL … low-potential electrode plate, NdL … bypass wiring, d1, d2, d3 … diode.

Claims

1. A power conversion device, characterized in that, It comprises: a plurality of switching elements arranged along a low-potential wiring; and a drive circuit that simultaneously supplies a gate voltage to each of the plurality of switching elements via a gate wiring having a predetermined gate resistance. For a switching element that has a smaller wiring inductance in the low-potential wiring connected to the plurality of switching elements, and whose wiring inductance is smaller up to the point where the currents from each of the plurality of switching elements are combined to the low-potential wiring, the gate resistance of the gate wiring connected to that switching element is set to a larger resistance value.

2. The power conversion device as described in claim 1, characterized in that, The gate resistor is connected in series with the gate wiring.

3. The power conversion device as described in claim 2, characterized in that, It has a bypass wiring that includes a diode that bypasses at least a portion of the plurality of gate resistors. The anode of the diode in the bypass wiring is connected to the gate side of the switching element, and at least a portion of the gate resistors are bypassed when the plurality of switching elements are turned off.

4. The power conversion device as described in claim 1, characterized in that, It has high-potential wiring connecting the plurality of switching elements. A wiring substrate comprising the plurality of switching elements, the gate wiring, the low-potential wiring, and the high-potential wiring. The gate wiring, the low-potential wiring, and the high-potential wiring extend and are arranged on the wiring substrate along the arrangement direction of the plurality of switching elements.

5. The power conversion device as described in claim 1, characterized in that, The driving circuit simultaneously supplies the gate voltage to each of the plurality of switching elements via the gate wiring having the gate resistor having the set resistance value, thereby turning on the plurality of switching elements.

6. The power conversion device according to any one of claims 1 to 4, characterized in that, The parallel connection of the multiple switching elements constitutes each phase, which is formed by the upper and lower arms of the inverter circuit, and forms the lower arm of each phase.

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