Domestic heterogeneous chip dynamic power consumption cooperative scheduling method for vehicle-mounted environment

Abstract

The invention discloses a domestic heterogeneous chip dynamic power consumption cooperative scheduling method oriented to a vehicle-mounted environment, and aims to solve the problem of system energy efficiency optimization caused by strict limitation of power supply and heat dissipation resources, dynamic mixing of calculation tasks and unique power consumption characteristics of domestic chips in the vehicle-mounted environment. The method is based on a vehicle-mounted heterogeneous computing platform comprising a domestic central processing unit, a field programmable gate array and a memory, and is realized through a closed-loop scheduling process executed by the central processing unit. According to the method, global, dynamic and collaborative power consumption management of domestic heterogeneous chip resources is realized, and the overall energy efficiency and the operation reliability of the system are remarkably improved on the premise of ensuring the real-time performance and the performance of a vehicle-mounted task.

Description

Technical Field

[0001] This invention relates to the field of vehicle computing technology, and in particular to a dynamic power consumption collaborative scheduling method for domestically produced heterogeneous chips for vehicle environments. Background Technology

[0002] As automotive electronic and electrical architectures evolve towards domain control and central computing, in-vehicle computing platforms need to process massive amounts of perception data, perform complex path planning and decision-making, and execute real-time control. This places unprecedented demands on the computing power and energy efficiency of these platforms. To meet this need, heterogeneous computing architectures, including central processing units, field-programmable gate arrays (FPGAs), and large-capacity memory, have become the mainstream solution. Meanwhile, considering supply chain security and self-reliance, using domestically produced chips to build in-vehicle heterogeneous computing platforms has become an important development direction.

[0003] However, efficient power management of domestically produced heterogeneous chips faces a series of unique challenges in the specific application environment of automotive. First, the automotive environment is subject to stringent resource constraints. The power output of its power sources (such as batteries and generators) is not unlimited and may fluctuate, while the vehicle's heat dissipation capacity is limited and the ambient temperature varies widely. Second, automotive computing tasks are highly dynamic and hybrid, including real-time-critical sensing and control tasks, high-throughput deep learning inference tasks, and sudden interactive tasks. These tasks place rapidly changing demands on the CPU, FPGA, and memory. Third, due to differences in manufacturing processes and microarchitecture design compared to imported products, the power consumption characteristics of domestically produced CPUs, FPGAs, and memory (such as the ratio of static to dynamic power consumption, energy efficiency curves at different operating voltage and frequency points, and power consumption models for memory access) and the power interference mechanisms among them have not yet been fully characterized and utilized.

[0004] In existing technologies, common dynamic power management techniques, such as dynamic voltage and frequency adjustment, clock gating, and power gating, are mostly designed for single chips or homogeneous multi-core systems, lacking collaborative optimization for automotive-grade heterogeneous chip scenarios. Some heterogeneous power management solutions for servers primarily base their decisions on task load and chip temperature, failing to fully consider the hard constraints of power supply in automotive scenarios, drastic changes in ambient temperature, and the unique power consumption behavior of domestically produced chips. Furthermore, existing solutions typically treat the CPU, FPGA, and memory as independent management objects, employing isolated strategies for adjustment, ignoring the cascading power consumption effects caused by task execution flow between chips. For example, allocating excessively high power budgets to FPGAs for accelerated tasks may lead to overheating and frequency throttling, forcing the CPU to take over some computations, thus increasing the total system power consumption; or excessively low memory power budgets may increase memory access latency, slowing down task execution for both the CPU and FPGA, and prolonging the duration of high-power states.

[0005] Therefore, there is an urgent need for a method specifically designed for the vehicle environment that can deeply integrate vehicle status, environmental information and the characteristics of domestically produced chips to perform global, dynamic and collaborative power consumption scheduling of the central processing unit, field-programmable gate array and memory, so as to maximize system-level energy efficiency while strictly adhering to the power supply and heat dissipation constraints of the vehicle platform, under the premise of meeting the real-time and performance requirements of complex vehicle tasks. Summary of the Invention

[0006] To achieve the above objectives, this invention provides a dynamic power consumption collaborative scheduling method for domestically produced heterogeneous chips in an automotive environment. This method is applied to an automotive heterogeneous computing platform that includes a domestically produced central processing unit (CPU), a domestically produced field-programmable gate array (FPGA), and domestically produced memory. The method is executed by the domestically produced CPU, forming a closed loop of perception, decision-making, and control. The method includes the following steps: Step S100, Multi-dimensional State Perception Step: Synchronously collect vehicle operating status data, domestic heterogeneous chip operating status data, and computing task execution status data; wherein, the vehicle operating status data includes at least the current maximum allocable power limit of the vehicle power bus and the ambient temperature; the domestic heterogeneous chip operating status data includes at least the current operating frequency, operating voltage, and temperature of the domestic central processing unit, the domestic field-programmable gate array, and the domestic memory; the computing task execution status data includes at least the type and performance constraints of the computing task to be executed; Step S200, Collaborative Optimization Decision Step: Based on the data collected in step S100, with the goal of optimizing the overall system energy efficiency, and under the constraints of the total system power consumption budget and temperature determined by the vehicle power supply and heat dissipation conditions, collaborative optimization is performed to generate a collaborative scheduling strategy for the next scheduling cycle; the collaborative scheduling strategy includes chip-level power consumption budgets allocated to the domestic central processing unit, the domestic field-programmable gate array, and the domestic memory, the execution unit specified for the computing task, and a set of initial operating voltage and frequency point combinations recommended for each chip; Step S300, Dynamic Closed-Loop Control Step: Execute the collaborative scheduling strategy generated in step S200, configure each chip to the corresponding working state and schedule computing tasks; during the scheduling cycle, monitor the actual power consumption and temperature of each chip in real time, and compare them with the chip-level power consumption budget and temperature constraints. If the actual power consumption and temperature of each chip deviate at the same time, trigger task migration or chip operating point adjustment.

[0007] Preferably, in step S100, collecting the vehicle operating status data specifically includes: Step S101: Continuously monitor the voltage of the vehicle power bus and obtain the current maximum allocable power limit from the vehicle power management module; Step S102: Monitor the vehicle's driving status, which includes stationary, low-speed cruising, high-speed driving, and rapid acceleration. Step S103: Monitor the current heat dissipation capacity level of the vehicle cooling system and read the ambient temperature sensor readings located near the vehicle heterogeneous computing platform.

[0008] Preferably, in step S100, collecting the operating status data of the domestically produced heterogeneous chip specifically includes: Step S111: Read the current utilization rate, operating frequency, operating voltage and junction temperature of all computing cores through the internal performance monitoring unit of the domestic central processing unit; Step S112: Through the system monitoring module embedded in the domestic field-programmable gate array, read the resource occupancy rate, current operating frequency, operating voltage and junction temperature of each programmable logic region inside it; Step S113: The access bandwidth utilization rate of the memory channel is read through the domestic memory controller, and the current operating frequency, operating voltage and temperature sensor data of the domestic memory chip are read through the serial presence detection interface.

[0009] Preferably, in step S100, collecting the execution status data of the computing task specifically includes: Step S121: Monitor the set of computational tasks currently being executed and those waiting to be executed in the queue, which are managed by the task scheduler; Step S122: Parse the metadata tags of each computing task or analyze its resource access patterns to determine the type of the computing task, which includes CPU-sensitive tasks, field-programmable gate array accelerated tasks, and memory bandwidth-intensive tasks. Step S123: Obtain the performance constraint metrics from the task descriptor of each computing task. The performance constraint metrics include the latest completion time of the task and the minimum throughput required by the task.

[0010] Preferably, step S200 specifically includes the following sub-steps: Step S201, System Constraint Quantification Sub-step: Based on the current maximum allocable power limit of the vehicle power bus collected in step S100, subtract the pre-calibrated basic power consumption estimates of other vehicle electronic systems to obtain the upper limit of the dynamic total power consumption budget that can be used for the vehicle heterogeneous computing platform; at the same time, based on the ambient temperature and the current heat dissipation capacity level, combined with the pre-established vehicle heat dissipation model, calculate the maximum allowable junction temperature constraints of the domestic central processing unit, the domestic field-programmable gate array, and the domestic memory. Step S202, Task-Chip Energy Efficiency Mapping Sub-step: For each computing task, based on the task type, query the pre-established domestic chip power consumption-performance lookup table to evaluate its expected unit computing energy consumption and expected execution time when executing on different cores of the domestic CPU, different programmable logic regions of the domestic field-programmable gate array, and accessing the domestic memory; the domestic chip power consumption-performance lookup table is obtained through joint power consumption characteristic testing and calibration of the domestic CPU, domestic field-programmable gate array, and domestic memory in the early stage; Step S203, Global Cooperative Decision Sub-step: Using the upper limit of the dynamic total power consumption budget and the maximum allowable junction temperature constraint as hard constraints, and taking maximizing the ratio of the overall performance satisfaction of all computing tasks to the actual total power consumption of the system as the optimization objective, a dynamic optimization model is constructed and solved; the decision variables of the dynamic optimization model include the power consumption budget of each chip, the mapping relationship between tasks and execution units, and the operating voltage frequency of each chip; solve the dynamic optimization model and output the cooperative scheduling strategy.

[0011] Preferably, in step S202, the process of establishing and updating the domestic chip power consumption-performance lookup table includes: Step S221, Offline calibration stage: On the vehicle-mounted heterogeneous computing platform, a benchmark test program covering different types and load intensities is run. At the same time, the power consumption and task execution time of the domestic central processing unit, the domestic field-programmable gate array and the domestic memory are accurately measured under different combinations of operating voltage and frequency points. The power consumption-performance lookup table of the domestic chip is recorded and generated. Step S222, Online Learning Phase: After each scheduling cycle ends, collect the actual types of computing tasks executed within that cycle, the actual allocated execution units, the actual chip operating point, and the final actual task execution time and chip power consumption; compare the collected actual data with the predicted values ​​in the domestic chip power consumption-performance lookup table, and use a moving average or regression algorithm to correct the expected unit computing energy consumption and expected execution time of the corresponding entries in the lookup table, so that the prediction model continuously approximates the actual energy efficiency characteristics of domestic chips in real vehicle environments.

[0012] Preferably, in step S203, the optimization objective of the dynamic optimization model, "maximizing the overall performance satisfaction of all computational tasks," is quantified in the following way: For each computation task, a soft real-time penalty function based on the actual completion time is defined according to its latest completion deadline; at the same time, a satisfaction function based on the actual throughput is defined according to its minimum throughput requirement. The overall performance satisfaction is expressed as the weighted sum of the satisfaction functions of all computing tasks minus the weighted sum of the soft real-time penalty functions; wherein the weight coefficients of different computing tasks are preset according to their task criticality level.

[0013] Preferably, the dynamic closed-loop control step in step S300 specifically includes: Step S301, Strategy Execution Sub-step: The domestic CPU, according to the cooperative scheduling strategy, adjusts itself to the corresponding state in the recommended initial operating voltage-frequency point combination in the cooperative scheduling strategy by writing to the configuration register; through the inter-chip communication interface, it sends configuration commands to the dynamic voltage-frequency adjustment controller of the domestic field-programmable gate array and the domestic memory controller, respectively adjusting them to the corresponding state in the recommended initial operating voltage-frequency point combination in the cooperative scheduling strategy; simultaneously, according to the strategy, it distributes computing tasks to the designated core of the domestic CPU or the programmable logic area of ​​the domestic field-programmable gate array; Step S302, Real-time monitoring and rapid adjustment sub-step: Within the scheduling cycle, with a monitoring cycle shorter than the scheduling cycle, repeat steps S111, S112, and S113 to obtain the actual instantaneous power consumption and real-time junction temperature of each chip; if the actual instantaneous power consumption of any chip continuously exceeds the preset ratio threshold of its chip-level power consumption budget, or the real-time junction temperature approaches the maximum allowable junction temperature constraint, then the rapid adjustment process is triggered. Step S303, the rapid adjustment process includes: firstly, attempting to migrate some pre-marked, currently executing computing task loads between the domestic field-programmable gate array and the domestic central processing unit to balance the power consumption and temperature between the chips; if the actual instantaneous power consumption or real-time junction temperature still exceeds the limit after migration, then according to the preset derating level, the operating frequency and voltage of the chips exceeding the limit are reduced sequentially until their power consumption and temperature return to the safe range.

[0014] Preferably, in step S302, the duration of the monitoring period is dynamically adjusted according to the vehicle's driving status: When the vehicle is accelerating rapidly or traveling at high speed, the monitoring cycle is shortened to increase the frequency of monitoring and adjustment in order to cope with rapidly changing load and heat dissipation conditions. When the vehicle is stationary or cruising at low speed, the monitoring cycle is extended to reduce the scheduling overhead of the domestically produced central processing unit.

[0015] Preferably, the scheduling period in step S200 is not a fixed value, but is adaptively adjusted according to the dynamics of the vehicle environment and the rate of change of the task queue: Calculate the rate of change of the queue of pending computing tasks at the current moment, and the fluctuation range of the ambient temperature in the previous period; When the task queue changes rapidly or the ambient temperature fluctuates significantly, the scheduling cycle for the next round is automatically shortened, enabling the collaborative scheduling strategy to respond to changes more quickly. When the task queue is stable and the ambient temperature is stable, the scheduling cycle of the next round is automatically extended to reduce the computational overhead of optimization decisions.

[0016] The beneficial effects of this invention are: 1. This invention utilizes multi-dimensional state perception to monitor the vehicle's power status, temperature, and the operating status of the onboard computing platform in real time. Based on this, it performs collaborative optimization decisions to generate a power consumption scheduling strategy that conforms to the limitations of the onboard environment. By dynamically adjusting the chip's operating state and the scheduling of computing tasks, this invention effectively reduces system power consumption, ensuring that the onboard platform can still operate efficiently under conditions of limited power supply and heat dissipation.

[0017] 2. This invention dynamically collects the execution status of computing tasks and, combined with the task type and performance constraints, accurately analyzes the computing resource requirements of each task. Based on the characteristics of different tasks, it optimizes the allocation and scheduling of tasks across different chips, ensuring that the real-time performance and throughput requirements of task execution are met, while maximizing system energy efficiency. In situations of drastic task changes, this invention can adapt quickly by adjusting the scheduling cycle and task scheduling strategy in real time to balance power consumption and performance requirements, thus solving the challenges posed by the dynamic nature of in-vehicle computing tasks.

[0018] 3. This invention establishes a power consumption-performance lookup table for domestically produced chips, and continuously updates and optimizes the power consumption model by combining offline calibration and online learning phases, adjusting the operating status of each chip in real time. In this way, the power consumption characteristics of domestically produced chips are accurately captured and utilized, avoiding power interference issues caused by insufficient consideration of inter-chip collaborative operation.

[0019] 4. This invention not only coordinates the power consumption of the central processing unit, field-programmable gate array, and memory according to changes in the in-vehicle environment, but also eliminates interference in power scheduling between chips through global optimization of task execution flow. By monitoring the power consumption and temperature of chips in real time, this invention can adjust the operating voltage and frequency of each chip in a timely manner, avoiding over-reliance on any single chip, thereby maximizing the overall energy efficiency of the system.

[0020] 5. This invention employs global collaborative optimization decision-making to accurately calculate the dynamic total power consumption budget and the maximum allowable junction temperature constraints of each chip, and then optimizes the allocation of tasks and execution units based on this. The dynamic optimization model ensures that the power consumption of each chip, the mapping relationship of task execution units, and the operating voltage and frequency of the chips strictly adhere to the energy efficiency and temperature constraints of the automotive platform while guaranteeing system performance. This method maximizes the ratio between the overall performance satisfaction of the computing tasks and the actual total power consumption of the system, thereby achieving optimal energy efficiency for the automotive computing platform. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of the steps of the method of the present invention; Figure 2 This is a flowchart illustrating the steps involved in establishing and updating the power consumption-performance lookup table for domestically produced chips using the method of this invention. Figure 3 This is a flowchart of the dynamic closed-loop control step in step S300 of the method of the present invention. Detailed Implementation

[0023] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should also be noted that, to make the embodiments more comprehensive, the following embodiments are the best and preferred embodiments, and those skilled in the art can use other alternative methods to implement some well-known technologies; moreover, the accompanying drawings are only for more specific description of the embodiments and are not intended to specifically limit the present invention.

[0024] Please see Figures 1-3 This invention provides a dynamic power consumption collaborative scheduling method for domestically produced heterogeneous chips in automotive environments. First, in step S100, the system synchronously collects various data, including vehicle operating status, chip operating status, and computing task execution status. Vehicle status data includes the current maximum allocable power limit of the onboard power bus and ambient temperature, which helps determine the availability of power and heat dissipation. Chip operating status data includes the current operating frequency, operating voltage, and temperature of the domestically produced central processing unit, field-programmable gate array, and memory. This information helps to understand the chip's load and heat dissipation requirements in real time. Computing task status data includes the task type (such as perception task, control task, or deep learning inference task) and the performance constraints of each task, such as real-time performance and throughput. This status data will serve as the basis for subsequent decisions.

[0025] In step S200, after acquiring complete operational status data, the system will constrain the total power consumption and temperature based on the power supply and heat dissipation conditions of the vehicle platform, and perform collaborative optimization. The optimization objective is to optimize the overall system energy efficiency, ensuring maximum system performance within a limited power budget. In this process, a specific power budget is first allocated to each chip (CPU, FPGA, memory), and appropriate computing resources and execution units are allocated according to the task execution requirements. The system will recommend a suitable initial operating voltage-frequency combination based on the chip's power consumption characteristics and workload to ensure the chip operates in optimal energy efficiency.

[0026] In step S300, during task execution, the system monitors the power consumption and temperature of each chip in real time. If both the actual power consumption and temperature deviate from the set budget range, the system will dynamically adjust them through task migration or chip operating point adjustment. Through the closed-loop feedback mechanism, the system can respond quickly during operation to prevent chip overheating or excessive power consumption, thereby maintaining the system in a highly efficient and stable state.

[0027] The embodiments of the present invention can achieve efficient power consumption control in complex automotive application scenarios, optimize the energy use of the system, and ensure the real-time performance of computing tasks and the stability of the platform.

[0028] In one possible implementation, the system continuously monitors the voltage of the vehicle's power bus to ensure real-time access to the vehicle's power system status. Simultaneously, the system obtains the current maximum allocable power limit from the vehicle's power management module, providing information on the maximum power the vehicle can currently supply to the heterogeneous computing platform. This information is crucial for subsequent power scheduling, ensuring the system optimizes scheduling within the overall power budget.

[0029] Vehicle driving conditions (including stationary, low-speed cruising, high-speed driving, and rapid acceleration) directly impact power consumption and heat dissipation. The system monitors vehicle status to assess the power consumption requirements of the onboard computing platform in real time. When stationary, the onboard platform's power consumption requirements are low, while during high-speed driving or rapid acceleration, the power consumption requirements increase. Different driving conditions necessitate adjustments to the computing platform's power consumption strategy to maximize energy efficiency.

[0030] The capability of the vehicle's cooling system is crucial for chip temperature control. In this step, the system monitors the current cooling capacity of the vehicle's cooling system to assess whether it meets the heat dissipation requirements of the current power consumption. Simultaneously, ambient temperature sensors read temperature values ​​to assess the impact of external temperature on the cooling system's performance. If the vehicle's interior temperature is too high, the cooling system's capacity may be insufficient, leading to chip overheating and affecting the efficiency of computing tasks. Therefore, real-time monitoring of the vehicle's ambient temperature provides important data for power consumption and temperature control strategies.

[0031] In one possible implementation, the performance monitoring unit (PMU) integrated within the domestically produced central processing unit (CPU) acquires real-time data on the current utilization, operating frequency, operating voltage, and junction temperature of all computing cores. Core utilization reflects the processor's current load, while operating frequency and voltage determine the core's power consumption and performance level. Junction temperature is a crucial indicator of chip temperature; excessively high temperatures can affect chip stability and lifespan. Therefore, by monitoring these parameters in real-time, the power consumption and heat dissipation requirements of the computing cores can be accurately assessed.

[0032] Furthermore, by using the system monitoring module embedded in the domestically produced Field-Programmable Gate Array (FPGA), information such as resource utilization, current operating frequency, operating voltage, and junction temperature of each programmable logic region can be read. As part of a heterogeneous chip, the FPGA can flexibly adjust computing resources. By monitoring the resource utilization of each logic region, scheduling strategies can be dynamically adjusted to ensure reasonable resource allocation and avoid excessive power consumption or low computing efficiency due to resource overload.

[0033] Furthermore, the system obtains the memory channel access bandwidth utilization rate through a domestically produced memory controller to determine whether the memory system is under high load. Simultaneously, it reads the current operating frequency, operating voltage, and temperature sensor data of the memory chip via the Serial Presence Detection (SVID) interface. Memory bandwidth utilization reflects the system's demand for memory resources, while memory frequency, operating voltage, and temperature directly affect memory power consumption and heat dissipation. Using this monitoring data, the system can make reasonable power scheduling decisions.

[0034] In one possible implementation, a Performance Monitoring Unit (PMU) embedded in a domestically produced central processing unit (CPU) can read the utilization, operating frequency, operating voltage, and junction temperature information of all computing cores in real time. Utilization reflects the load on each computing core at a specific moment, while operating frequency and operating voltage directly affect power consumption and performance. Junction temperature monitoring allows assessment of whether the chip's temperature is within a safe range. Excessively high temperatures can lead to performance degradation, poor stability, and shortened lifespan; therefore, real-time monitoring of junction temperature data is crucial for optimizing power consumption scheduling and preventing overheating. Through comprehensive analysis of this data, the operating frequency and voltage can be dynamically adjusted, thereby optimizing power consumption and heat dissipation while ensuring computing requirements are met.

[0035] By utilizing the system monitoring module embedded in a domestically produced Field-Programmable Gate Array (FPGA), the resource utilization, operating frequency, operating voltage, and junction temperature of each programmable logic region can be read. As part of a heterogeneous computing platform, the FPGA possesses high flexibility and can dynamically allocate resources according to computing needs. By monitoring the resource utilization of each logic region, scheduling can be performed based on the actual load, avoiding unnecessary power consumption increases or reduced computing efficiency due to overuse of resources. This measure ensures that the system rationally schedules computing tasks without overloading, thereby improving performance and power efficiency.

[0036] By using a domestically produced memory controller to obtain the access bandwidth utilization of the memory channels, it's possible to determine if the memory system is under high load. High memory channel bandwidth utilization indicates a high demand for memory resources. The Serial Presence Detection (SVID) interface is used to obtain the operating frequency, voltage, and temperature information of the memory chips. Memory frequency and voltage affect power consumption, while temperature information reflects the heat dissipation of the memory chips. Real-time monitoring of these parameters helps the system adjust the memory's operating frequency and voltage to ensure stable memory operation and optimize power consumption.

[0037] In one possible implementation, the maximum allocable power limit of the onboard power bus is first calculated by subtracting the basic power consumption of other vehicle electronic systems, thus determining the upper limit of the dynamic total power budget that can be provided for the onboard heterogeneous computing platform. Furthermore, considering the heat dissipation capacity and temperature variations in the onboard environment, and combining this with a pre-established onboard heat dissipation model, the maximum allowable junction temperatures of the domestically produced central processing unit (CPU), domestically produced field-programmable gate array (FPGA), and domestically produced memory are calculated. By quantifying power consumption and temperature constraints, hard constraints are provided for subsequent power scheduling decisions.

[0038] Based on the type of each computing task, a pre-established power consumption-performance lookup table for domestically produced chips is consulted. This lookup table was created after joint power consumption characteristic testing and calibration of domestically produced central processing units, FPGAs, and memory, and includes the expected unit energy consumption and expected execution time for different computing tasks on each computing unit. Using this data, the system can evaluate the execution efficiency of each computing task on different chip cores or logic regions and allocate the most suitable computing unit to the task. The core function of this sub-step is to ensure that computing tasks are completed with the lowest possible energy consumption through accurate energy efficiency assessment, thereby providing a basis for subsequent power scheduling.

[0039] By constructing a dynamic optimization model, considering the dynamic total power consumption budget ceiling, the maximum allowable junction temperature constraint, and the energy efficiency requirements of each computing task, the system's power consumption and performance are optimized. Specifically, the decision variables include the power consumption budget of each chip, the mapping relationship between tasks and execution units, and the operating voltage and frequency of each chip. When solving this dynamic optimization model, the goal is to maximize the overall performance satisfaction of all computing tasks, while ensuring that the total power consumption of the system does not exceed the preset upper limit, and that the temperature of each chip does not exceed the allowable junction temperature limit. The final output cooperative scheduling strategy enables efficient scheduling and power consumption control of computing tasks.

[0040] In one possible implementation, during the offline calibration phase, various types of benchmark programs need to be run on the in-vehicle heterogeneous computing platform. These programs cover different types of computing tasks and load intensities to simulate various possible working scenarios. Through these tests, the power consumption and task execution time of the domestically produced central processing unit (CPU), field-programmable gate array (FPGA), and memory can be accurately measured under different combinations of operating voltage and frequency. This test data will be recorded and generate an initial power consumption-performance lookup table for the domestically produced chips, providing basic data for subsequent scheduling and optimization. This lookup table contains the performance and power consumption characteristics of different tasks on different chip units.

[0041] At the end of each scheduling cycle, the system collects the actual types of computational tasks executed during that cycle, the actual allocated execution units, the chip's operating point, the actual execution time of the tasks, and the chip's actual power consumption. This collected actual execution data is compared with the predicted values ​​in a lookup table to evaluate the model's accuracy. If there is a deviation between the actual data and the predicted values, the expected unit computational energy consumption and expected execution time of the corresponding entries in the lookup table are corrected using a moving average or regression algorithm. Through this process, the prediction model is continuously optimized, consistently approaching the actual energy efficiency characteristics of domestically produced chips in real-world automotive environments.

[0042] In one possible implementation, for each computational task, a soft real-time penalty function based on the actual completion time is defined according to its latest completion deadline. If the completion time of a computational task exceeds the latest completion deadline, the system will penalize it. The purpose of this penalty function is to appropriately constrain delayed tasks to ensure that tasks are completed on time, thereby avoiding system performance degradation. In this way, the time constraints of tasks can be strengthened, ensuring that the system has strong real-time performance in the in-vehicle environment.

[0043] Simultaneously, considering the minimum throughput requirement for each task, the system defines a satisfaction function based on actual throughput for each task. If the actual throughput of a task is lower than the preset minimum requirement, the system will assess its satisfaction as low; otherwise, it will show a higher satisfaction. The purpose of this function is to measure the achievement of throughput targets during task execution, ensuring that the system can meet the performance requirements of high-throughput tasks.

[0044] The overall performance satisfaction is calculated by subtracting the weighted sum of the satisfaction functions of all computational tasks from the weighted sum of the soft real-time penalty functions. The satisfaction and penalty functions for each task are weighted according to its importance and priority, with the weight coefficients pre-set based on its criticality level. This ensures that high-priority tasks have a greater impact, guaranteeing that important tasks receive priority.

[0045] In one possible implementation, during the strategy execution phase, the domestically produced central processing unit (CPU) first adjusts itself to the corresponding state in the recommended initial operating voltage-frequency combination by writing to configuration registers according to a predetermined cooperative scheduling strategy. This adjustment ensures that the processor finds a suitable balance between energy efficiency and performance. Simultaneously, the inter-chip communication interface sends configuration commands to the field-programmable gate array (FPGA) and memory controller to ensure that the operating states of these chips also match the recommended initial voltage-frequency combination. Furthermore, the system will rationally allocate computing tasks to designated processor cores or programmable logic regions of the FPGA according to the scheduling strategy, ensuring load balancing and improving overall computing efficiency.

[0046] During the scheduling cycle, the system continuously monitors the real-time power consumption and junction temperature of each chip through a monitoring cycle that is shorter than the scheduling cycle. Specifically, the system continuously acquires the instantaneous power consumption and real-time junction temperature of each chip by executing steps S111, S112, and S113. If the power consumption of any chip continuously exceeds the set threshold of its power budget, or the real-time junction temperature approaches the maximum allowable junction temperature constraint, the system will trigger a fast adjustment process to begin dynamically adjusting the chip.

[0047] In the rapid adjustment process, the system first attempts to migrate a portion of pre-marked migrateable computing tasks between the Field Programmable Gate Array (FPGA) and the domestically produced CPU. This task migration effectively balances power consumption and temperature across chips, preventing any single chip from overloading and causing excessive power consumption or overheating. If, after migration, the instantaneous power consumption or junction temperature of a chip still exceeds the safe range, the system will gradually reduce the chip's operating frequency and voltage according to a preset derating level until the chip's power consumption and temperature return to the safe range, thus ensuring the system remains stable.

[0048] In one possible implementation, when the vehicle is accelerating rapidly or traveling at high speed, the load and heat dissipation conditions of the onboard system change quickly, requiring a higher system responsiveness. Therefore, the monitoring cycle is shortened, meaning the system checks the instantaneous power consumption and real-time junction temperature of each chip more frequently. This ensures the system can promptly detect any abnormal changes in power consumption or temperature, allowing for rapid adjustments to prevent overheating or excessive power consumption from affecting system performance and ensuring optimal performance even at high speeds.

[0049] On the other hand, when the vehicle is stationary or cruising at low speed, the system load changes relatively smoothly and the temperature fluctuations are small. In these situations, frequent power consumption and temperature monitoring is unnecessary. To reduce system scheduling overhead, the monitoring cycle is extended, allowing for more efficient use of system power consumption and computing resources. This not only reduces the scheduling burden on the central processing unit but also saves energy at low speeds, improving the overall system efficiency.

[0050] In one possible implementation, at each scheduling cycle, the system first calculates the rate of change of the current queue of pending computing tasks and the fluctuation range of the ambient temperature in the previous cycle. Changes in these two parameters reflect the degree of change in the current system load and the stability of the ambient temperature. When the task queue changes rapidly or the ambient temperature fluctuates significantly, it indicates that the system load is changing rapidly or the heat dissipation conditions are unstable. In this case, to better respond to these changes, the system automatically shortens the next scheduling cycle. This approach allows the collaborative scheduling strategy to adjust power consumption and temperature more quickly to cope with sharp fluctuations in system load or ambient temperature.

[0051] Conversely, when the task queue is stable and the ambient temperature is stable, it indicates that the system load changes little and the heat dissipation conditions are relatively stable. In this case, to reduce the computational overhead of optimization decisions, the system will automatically extend the scheduling cycle of the next round. This not only reduces the consumption of system resources during scheduling but also improves energy efficiency, making the system more energy-efficient under low load and stable environments.

[0052] Understandably, the vehicle environment refers to specific conditions during vehicle operation, including power limits, ambient temperature, driving conditions, and heat dissipation capacity. A task queue is a collection of computational tasks managed by a task scheduler, including tasks that are currently executing and those waiting to be executed. Its state changes dynamically and affects scheduling decisions.

[0053] It is understood that the domestically produced memory controller in this invention is integrated inside the domestically produced central processing unit. For ease of description, the domestically produced memory controller has been described independently, and there is no issue of ambiguity here.

[0054] Example: This is an electric vehicle equipped with a domestically produced advanced driver assistance system and intelligent cockpit. Its central computing platform employs a heterogeneous computing system composed of a domestically produced 8-core CPU, a domestically produced large-scale field-programmable gate array (FPGA), and domestically produced high-bandwidth memory. This platform must simultaneously handle real-time visual perception tasks from multiple high-definition cameras, LiDAR point cloud processing tasks, high-precision map positioning and path planning tasks, as well as in-cabin voice interaction and graphical interface rendering tasks. These tasks are highly dynamic, hybrid, and have varying real-time requirements. During vehicle operation, the power output from the power supply system (battery + generator) available for computation fluctuates drastically due to acceleration, deceleration, and air conditioning load. Simultaneously, the ambient temperature inside the chassis varies within a wide range of -20°C to 85°C, resulting in stringent heat dissipation conditions.

[0055] Detailed implementation process: Step S100: Multidimensional state perception step; This step forms the basis for collaborative scheduling data input, ensuring the comprehensiveness and real-time nature of decision-making.

[0056] Steps S101-S103: Vehicle operating status data is collected via the in-vehicle network. Specifically, in step S101, the power bus voltage is continuously read from the vehicle power management controller via the controller area network bus, and a "current maximum allocable power limit" is obtained, dynamically calculated by the power management controller based on the current battery charge, generator load, and overall vehicle power consumption. For example, this value may be limited to 150 watts during rapid acceleration, but can be relaxed to 300 watts during idle charging. In step S102, the vehicle driving status code is obtained from the vehicle controller via the in-vehicle Ethernet. The code clearly corresponds to four states: stationary, low-speed cruising (speed below 60 km / h), high-speed driving (speed above 80 km / h), and rapid acceleration (acceleration greater than 2.5 m / s²). In step S103, the fan control module is accessed via the local integrated circuit bus to read the "current heat dissipation capacity level" expressed as a percentage (0% indicates fan failure, 100% indicates full-speed operation), and the "ambient temperature sensor reading" is read from the digital temperature sensor attached to the heat sink fins of the computing platform.

[0057] Steps S111-S113: The acquisition of operational status data from domestically produced heterogeneous chips extends deep into the internal workings of each chip. In step S111, the domestically produced central processing unit (CPU) reads its internal performance monitoring counter register to obtain the average utilization percentage of all eight computing cores over the past 1-millisecond sampling period. It also reads the current real-time operating frequency, operating voltage, and junction temperature measured by an internal thermistor for each core through a model-specific register. In step S112, the domestically produced field-programmable gate array (FPGA) polls each major programmable logic partition through its embedded hard-core system monitoring module to obtain the occupancy percentage of its lookup table and registers, as well as the current clock frequency, power supply voltage, and partition temperature of that partition. In step S113, the domestically produced memory controller counts the read and write transaction volume of each channel within the sampling period and calculates the "access bandwidth utilization." Simultaneously, through the serial presence detection interface protocol, it sends instructions to the serial presence detection chip on the memory module to read the current operating frequency, voltage, and temperature sensor data of the memory chips.

[0058] Steps S121-S123: The acquisition of task execution status data is jointly completed by the task scheduler and task manager running on the central processing unit.

[0059] In step S121, the task scheduler maintains a priority queue containing all pending "computation task sets", each task having a unique task descriptor.

[0060] Step S122: Determine the task type by parsing the "metadata tag" in the task descriptor.

[0061] For example, a task labeled “ResNet50_INFERENCE” is resolved as a “Field Programmable Gate Array Accelerated Task”; a task labeled “MULTI_OBJECT_TRACKING” is resolved as a “CPU-Sensitive Task”; and a task labeled “POINTCLOUD_ALIGNMENT” is resolved as a “Memory Bandwidth Intensive Task”.

[0062] Step S123: Extract "performance constraint metrics" from the same task descriptor.

[0063] For example, for the visual perception task of forward collision warning, the "latest completion time" is 100 milliseconds; for the speech recognition task, the "minimum throughput requirement" is 16,000 sampling points per second.

[0064] Step S200: Collaborative optimization decision-making steps; This step is the core of the method, responsible for transforming the perceived data into an executable control strategy.

[0065] Step S201: System constraint quantification sub-step. First, from the "current maximum allocable power limit" (assumed to be 200 watts) obtained in step S101, subtract the "basic power consumption estimate of other vehicle electronic systems" (assumed to be 50 watts, including the instrument panel, network controller, etc.) calibrated through long-term monitoring, to obtain the "dynamic total power consumption budget upper limit" of 150 watts.

[0066] Next, input the "ambient temperature sensor reading value" (assumed to be 45°C) and "current heat dissipation capacity level" (assumed to be 80%) obtained in step S103 into a "pre-established vehicle heat dissipation model".

[0067] The model is an empirical formula based on thermal resistance networks: Maximum allowable junction temperature = ambient temperature + (chip thermal design power / heat dissipation coefficient) × thermal resistance.

[0068] The heat dissipation capacity coefficient is related to the fan grade, and the thermal resistance is determined through previous wind tunnel experiments.

[0069] After substituting the values, the model calculated that the "maximum allowable junction temperature constraints" for the central processing unit, field-programmable gate array, and memory under the current environment are 105°C, 100°C, and 95°C, respectively.

[0070] Step S202: Task - Chip Energy Efficiency Mapping Sub-step.

[0071] This step relies on a core component – ​​the “domestic chip power consumption-performance lookup table”.

[0072] This lookup table is essentially a multidimensional database, and its creation and updating are crucial to ensuring scheduling accuracy.

[0073] Step S221 (Offline calibration stage): In a laboratory environment, the domestic central processing unit, field programmable gate array and memory are jointly tested.

[0074] Different task types are simulated using a series of benchmark programs (such as matrix operations, image processing, data encryption, etc.).

[0075] During the test, the frequency and voltage of each core of the central processing unit, the frequency and voltage of each partition of the field programmable gate array, and the frequency and voltage of the memory were actively adjusted. At the same time, a high-precision power meter was used to measure the power consumption of each chip, and a timer was used to record the task execution time.

[0076] Finally, the four elements of "task type", "chip operating point", "measured power consumption" and "execution time" are associated to generate an initial lookup table.

[0077] For example, a record in the table might be: Task type [Image classification], Execution unit [Field-Programmable Gate Array Partition A], Operating point [Frequency 300MHz, Voltage 0.8V], Expected energy consumption per unit of computation [5 joules / thousand images], Expected execution time [10 milliseconds / image].

[0078] Step S222 (Online Learning Phase): After each scheduling cycle ends, collect actual execution data.

[0079] For example, in the last cycle, a speech recognition task was assigned to CPU core 3 to execute at a frequency of 2.0 GHz, which actually took 15 milliseconds and consumed 1.2 watts of power.

[0080] The actual data (speech recognition, CPU core 3, 2.0GHz, 15ms, 1.2W) is compared with the corresponding predicted entry in the lookup table (speech recognition, CPU core 3, 2.0GHz, prediction 12ms, prediction 1.0W).

[0081] Then, the entry is updated using an exponentially weighted moving average algorithm: new expected value = α × old expected value + (1-α) × actual value (where α is the forgetting factor, for example, 0.9), so that the lookup table can adapt to the characteristic drift of domestic chips under actual vehicle aging and temperature changes.

[0082] Step S203: Global collaborative decision-making sub-step.

[0083] This step solves a "dynamic optimization model".

[0084] Model objective function (maximizing overall performance satisfaction): This function is a weighted sum of multiple sub-functions. For each task, two functions are defined: The soft real-time penalty function is: P(t) = max(0, (actual completion time - latest completion deadline) × penalty coefficient). A linear penalty is applied if the task times out.

[0085] Satisfaction function: S(r) = min(1, actual throughput / minimum required throughput). Satisfaction is 1 if the requirement is met or exceeded; otherwise, it decreases proportionally.

[0086] "Overall performance satisfaction" = ∑(weight_i × S_i) - ∑(weight_j × P_j). Task weights are set according to the security level (e.g., AEB-related tasks have the highest weight).

[0087] Model constraints: The actual total power consumption of the central processing unit, field programmable gate array, and memory is ≤150 watts (maximum dynamic total power budget).

[0088] The predicted junction temperature of each chip is less than or equal to its respective maximum allowable junction temperature constraint.

[0089] A computational task can only be assigned to one execution unit.

[0090] Model Solving and Output: Since the model needs to be solved within a millisecond-level scheduling cycle, a fast solver combining heuristic and greedy algorithms is adopted.

[0091] The solver takes the current chip state and task queue as input, searches within the constraint space, and finally outputs a "cooperative scheduling strategy". For example, it allocates a budget of 60 watts to the central processing unit, a budget of 70 watts to the field-programmable gate array (FPGA), and a budget of 20 watts to the memory; it assigns the "image classification" task to FPGA partition B to run at [250 MHz, 0.75 V]; and it assigns the "path planning" task to central processing unit cores 1-2 to run at [1.5 GHz, 0.9 V].

[0092] Step S300: Dynamic closed-loop control steps; This step ensures the accurate execution of decisions and dynamic adaptation to the environment.

[0093] Step S301: Policy execution sub-step. The power management module of the central processing unit operating system kernel configures its own core operating point by writing to model-specific registers according to the policy.

[0094] Simultaneously, configuration command packets are sent to the dynamic voltage and frequency adjustment controller and memory controller of the field-programmable gate array (FPGA) via the peripheral component interconnection fast channel to complete their operating point settings. The task scheduler then delivers the task to the designated hardware unit.

[0095] Steps S302-S303: Real-time monitoring and rapid adjustment sub-steps. Set a "monitoring period" that is much shorter than the decision cycle (e.g., a decision cycle of 50 milliseconds and a monitoring period of 5 milliseconds).

[0096] Within each 5-millisecond monitoring cycle, repeat steps S111-S113 to obtain the "actual instantaneous power consumption" and "real-time junction temperature".

[0097] Triggering conditions: Two thresholds are set. First, power consumption threshold: The actual instantaneous power consumption of any chip exceeds 10% of its "chip-level power budget" for three consecutive monitoring cycles. Second, temperature threshold: The real-time junction temperature of any chip reaches 90% of its "maximum allowable junction temperature constraint".

[0098] Rapid adjustment process: Once triggered, for example, when the field programmable gate array temperature reaches 90°C (constrained to 100°C).

[0099] First, attempt "task migration": query the tasks running on the field-programmable gate array and migrate one of them marked as "migratable" (such as a part of the post-processing algorithm) to an idle core of the central processing unit.

[0100] If the temperature continues to rise after migration, "derating" will be initiated: the operating frequency of the field programmable gate array will be gradually reduced from 250MHz to 200MHz and then to 150MHz. After each frequency reduction, the frequency will be monitored for two cycles until the temperature stops rising and begins to fall back.

[0101] Dynamic adjustment of monitoring cycle: When step S102 detects that the vehicle is in a "rapid acceleration" state, the monitoring cycle is shortened from 5 milliseconds to 2 milliseconds to respond more quickly to possible power surges.

[0102] When a vehicle is "stationary", the monitoring period can be extended to 10 milliseconds to save on scheduling overhead.

[0103] Adaptive scheduling cycle: The scheduling cycle in this embodiment is not a fixed value. The decision-maker calculates the "task queue change rate" (the number of new tasks added per unit time) and the "ambient temperature fluctuation range" based on historical data.

[0104] If, on average, more than three high-priority tasks have been added per cycle over the past five cycles, and the temperature fluctuation exceeds 5°C, the next scheduling cycle will be shortened from 50 milliseconds to 30 milliseconds to increase the decision-making frequency. Conversely, if the system load is stable, the cycle can be extended to 70 milliseconds.

[0105] To demonstrate the effectiveness of this invention, a 10-minute comparative test was conducted on the following three scheduling methods in a simulated urban scenario (including dense traffic, pedestrians, traffic light recognition, and frequent voice interactions): Comparative Example 1 (Static Allocation Strategy): A fixed power budget (e.g., 60W, 80W, 10W) ​​and operating frequency are allocated to the central processing unit, field programmable gate array, and memory. Tasks are executed according to a preset fixed mapping without dynamic adjustment.

[0106] Comparative Example 2 (Isolated Dynamic Adjustment Strategy): The central processing unit, field programmable gate array, and memory each adjust their voltage and frequency independently based on their own load and temperature, but there is no power budget coordination or task migration mechanism between them.

[0107] The method of this invention, as described in this embodiment, involves global collaborative dynamic power budget allocation, task scheduling, and closed-loop control.

[0108] The test results are shown in Table 1: Table 1 Test Results Performance indicators Comparative Example 1: Static Allocation Strategy Comparative Example 2: Isolated Dynamic Adjustment Strategy Method of the present invention Total average power consumption of the system (watts) 155 142 130 Average task completion delay (milliseconds) 35 28 22 High-priority task completion rate (%) 85% 93% 99.5% Maximum junction temperature of the chip (°C) Central Processing Unit: 98 Central Processing Unit: 95 Central Processing Unit: 89 Field Programmable Gate Array: 102 Field Programmable Gate Array (FPGA): 99 Field Programmable Gate Array (FPGA): 92 Memory: 88 Memory: 85 Memory: 83 Number of mission failures when encountering a sudden drop in power 8 times 5 times 1 time Results analysis: Compared to Comparative Example 1, this invention significantly reduces total power consumption and greatly improves task completion rate and timeliness through dynamic budget allocation and collaborative scheduling, while effectively controlling chip temperature and avoiding performance degradation caused by overheating and frequency reduction.

[0109] Compared to Comparative Example 2, this invention, through globally optimized budget allocation and task-chip matching, avoids resource contention or idleness that may occur between chips due to isolated decisions, achieving a better energy efficiency ratio. Especially when dealing with the inherent power supply fluctuations in the automotive environment, the global perspective and rapid adjustment mechanism of this invention can more effectively allocate limited power to the most critical tasks, thereby greatly improving the robustness and reliability of the system.

[0110] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with a thorough understanding of this invention, specific details are described in detail in the following preferred embodiments; however, those skilled in the art will fully understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0111] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A dynamic power consumption collaborative scheduling method for domestically produced heterogeneous chips in an automotive environment, applied to an automotive heterogeneous computing platform including domestically produced central processing units, domestically produced field-programmable gate arrays, and domestically produced memory, characterized in that... The method, executed by the domestically produced central processing unit, forms a closed loop of perception, decision-making, and control, and includes the following steps: Step S100, Multi-dimensional State Perception Step: Synchronously collect vehicle operating status data, domestic heterogeneous chip operating status data, and computing task execution status data; wherein, the vehicle operating status data includes at least the current maximum allocable power limit of the vehicle power bus and the ambient temperature; the domestic heterogeneous chip operating status data includes at least the current operating frequency, operating voltage, and temperature of the domestic central processing unit, the domestic field-programmable gate array, and the domestic memory; the computing task execution status data includes at least the type and performance constraints of the computing task to be executed; Step S200, Collaborative Optimization Decision Step: Based on the data collected in step S100, with the goal of optimizing the overall system energy efficiency, and under the constraints of the total system power consumption budget and temperature determined by the vehicle power supply and heat dissipation conditions, collaborative optimization is performed to generate a collaborative scheduling strategy for the next scheduling cycle; the collaborative scheduling strategy includes chip-level power consumption budgets allocated to the domestic central processing unit, the domestic field-programmable gate array, and the domestic memory, the execution unit specified for the computing task, and a set of initial operating voltage and frequency point combinations recommended for each chip; Step S300, Dynamic Closed-Loop Control Step: Execute the collaborative scheduling strategy generated in step S200, configure each chip to the corresponding working state and schedule computing tasks; during the scheduling cycle, monitor the actual power consumption and temperature of each chip in real time, and compare them with the chip-level power consumption budget and temperature constraints. If the actual power consumption and temperature of each chip deviate at the same time, trigger task migration or chip operating point adjustment.

2. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 1, characterized in that, In step S100, collecting the vehicle operating status data specifically includes: Step S101: Continuously monitor the voltage of the vehicle power bus and obtain the current maximum allocable power limit from the vehicle power management module; Step S102: Monitor the vehicle's driving status, which includes stationary, low-speed cruising, high-speed driving, and rapid acceleration. Step S103: Monitor the current heat dissipation capacity level of the vehicle cooling system and read the ambient temperature sensor readings located near the vehicle heterogeneous computing platform.

3. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 1, characterized in that, In step S100, collecting the operating status data of the domestically produced heterogeneous chip specifically includes: Step S111: Read the current utilization rate, operating frequency, operating voltage and junction temperature of all computing cores through the internal performance monitoring unit of the domestic central processing unit; Step S112: Through the system monitoring module embedded in the domestic field-programmable gate array, read the resource occupancy rate, current operating frequency, operating voltage and junction temperature of each programmable logic region inside it; Step S113: The access bandwidth utilization rate of the memory channel is read through the domestic memory controller, and the current operating frequency, operating voltage and temperature sensor data of the domestic memory chip are read through the serial presence detection interface.

4. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 1, characterized in that, In step S100, collecting the execution status data of the computing task specifically includes: Step S121: Monitor the set of computational tasks currently being executed and those waiting to be executed in the queue, which are managed by the task scheduler; Step S122: Parse the metadata tags of each computing task or analyze its resource access patterns to determine the type of the computing task, which includes CPU-sensitive tasks, field-programmable gate array accelerated tasks, and memory bandwidth-intensive tasks. Step S123: Obtain the performance constraint metrics from the task descriptor of each computing task. The performance constraint metrics include the latest completion time of the task and the minimum throughput required by the task.

5. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 2, characterized in that, Step S200 specifically includes the following sub-steps: Step S201, System Constraint Quantification Sub-step: Based on the current maximum allocable power limit of the vehicle power bus collected in step S100, subtract the pre-calibrated basic power consumption estimates of other vehicle electronic systems to obtain the upper limit of the dynamic total power consumption budget that can be used for the vehicle heterogeneous computing platform; at the same time, based on the ambient temperature and the current heat dissipation capacity level, combined with the pre-established vehicle heat dissipation model, calculate the maximum allowable junction temperature constraints of the domestic central processing unit, the domestic field-programmable gate array, and the domestic memory. Step S202, Task-Chip Energy Efficiency Mapping Sub-step: For each computing task, based on the task type, query the pre-established domestic chip power consumption-performance lookup table to evaluate its expected unit computing energy consumption and expected execution time when executing on different cores of the domestic CPU, different programmable logic regions of the domestic field-programmable gate array, and accessing the domestic memory; the domestic chip power consumption-performance lookup table is obtained through joint power consumption characteristic testing and calibration of the domestic CPU, domestic field-programmable gate array, and domestic memory in the early stage; Step S203, Global Collaborative Decision Sub-step: Using the upper limit of the dynamic total power consumption budget and the maximum allowable junction temperature constraint as hard constraints, and maximizing the ratio of the overall performance satisfaction of all computing tasks to the actual total power consumption of the system as the optimization objective, a dynamic optimization model is constructed and solved; the decision variables of the dynamic optimization model include the power consumption budget of each chip, the mapping relationship between tasks and execution units, and the operating voltage frequency of each chip; the dynamic optimization model is solved, and the collaborative scheduling strategy is output; The optimal overall energy efficiency of the system is determined by quantifying the ratio of overall performance satisfaction to the actual total power consumption of the system, and then solving for the maximum value of the model under constraints, thereby achieving energy efficiency optimization.

6. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 5, characterized in that, In step S202, the process of establishing and updating the domestic chip power consumption-performance lookup table includes: Step S221, Offline calibration stage: On the vehicle-mounted heterogeneous computing platform, a benchmark test program covering different types and load intensities is run. At the same time, the power consumption and task execution time of the domestic central processing unit, the domestic field-programmable gate array and the domestic memory are accurately measured under different combinations of operating voltage and frequency points. The power consumption-performance lookup table of the domestic chip is recorded and generated. Step S222, Online Learning Phase: After each scheduling cycle ends, collect the actual types of computing tasks executed within that cycle, the actual allocated execution units, the actual chip operating point, and the final actual task execution time and chip power consumption; compare the collected actual data with the predicted values ​​in the domestic chip power consumption-performance lookup table, and use a moving average or regression algorithm to correct the expected unit computing energy consumption and expected execution time of the corresponding entries in the lookup table, so that the prediction model continuously approximates the actual energy efficiency characteristics of domestic chips in real vehicle environments.

7. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 5, characterized in that, In step S203, the optimization objective of the dynamic optimization model, "maximizing the overall performance satisfaction of all computational tasks," is quantified in the following way: For each computation task, a soft real-time penalty function based on the actual completion time is defined according to its latest completion deadline; at the same time, a satisfaction function based on the actual throughput is defined according to its minimum throughput requirement. The overall performance satisfaction is expressed as the weighted sum of the satisfaction functions of all computing tasks minus the weighted sum of the soft real-time penalty functions; wherein the weight coefficients of different computing tasks are preset according to their task criticality level.

8. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 3, characterized in that, The dynamic closed-loop control step in step S300 specifically includes: Step S301, Strategy Execution Sub-step: The domestic CPU, according to the cooperative scheduling strategy, adjusts itself to the corresponding state in the recommended initial operating voltage-frequency point combination in the cooperative scheduling strategy by writing to the configuration register; through the inter-chip communication interface, it sends configuration commands to the dynamic voltage-frequency adjustment controller of the domestic field-programmable gate array and the domestic memory controller, respectively adjusting them to the corresponding state in the recommended initial operating voltage-frequency point combination in the cooperative scheduling strategy; simultaneously, according to the strategy, it distributes computing tasks to the designated core of the domestic CPU or the programmable logic area of ​​the domestic field-programmable gate array; Step S302, Real-time monitoring and rapid adjustment sub-step: Within the scheduling cycle, with a monitoring cycle shorter than the scheduling cycle, repeat steps S111, S112, and S113 to obtain the actual instantaneous power consumption and real-time junction temperature of each chip; if the actual instantaneous power consumption of any chip continuously exceeds the preset ratio threshold of its chip-level power consumption budget, or the real-time junction temperature approaches the maximum allowable junction temperature constraint, then the rapid adjustment process is triggered. Step S303, the rapid adjustment process includes: firstly, attempting to migrate some pre-marked, currently executing computing task loads between the domestic field-programmable gate array and the domestic central processing unit to balance the power consumption and temperature between the chips; if the actual instantaneous power consumption or real-time junction temperature still exceeds the limit after migration, then according to the preset derating level, the operating frequency and voltage of the chips exceeding the limit are reduced sequentially until their power consumption and temperature return to the safe range.

9. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 8, characterized in that, In step S302, the duration of the monitoring period is dynamically adjusted according to the vehicle's driving status: When the vehicle is accelerating rapidly or traveling at high speed, the monitoring cycle is shortened to increase the frequency of monitoring and adjustment in order to cope with rapidly changing load and heat dissipation conditions. When the vehicle is stationary or cruising at low speed, the monitoring cycle is extended to reduce the scheduling overhead of the domestically produced central processing unit.

10. The method for dynamic power consumption collaborative scheduling of domestically produced heterogeneous chips for automotive environments according to claim 1, characterized in that, The scheduling period in step S200 is not a fixed value, but is adaptively adjusted according to the dynamics of the vehicle environment and the rate of change of the task queue: Calculate the rate of change of the queue of pending computing tasks at the current moment, and the fluctuation range of the ambient temperature in the previous period; When the task queue changes rapidly or the ambient temperature fluctuates significantly, the scheduling cycle for the next round is automatically shortened, enabling the collaborative scheduling strategy to respond to changes more quickly. When the task queue is stable and the ambient temperature is stable, the scheduling cycle of the next round is automatically extended to reduce the computational overhead of optimization decisions.

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