Precise time synchronization method based on Byzantine fault-tolerant model

Abstract

The invention relates to the technical field of precise time synchronization of a distributed network, in particular to a precise time synchronization method based on a Byzantine fault-tolerant model, which comprises the following steps of: monitoring a network after all clock devices are started, if no synchronous network exists, setting a master clock number of each clock device, and if no synchronous network exists, setting a master clock number of each clock device; the method comprises the following steps of: distributing a master clock or a slave clock by a device according to a matching relationship between a serial number of the device and a master clock number, broadcasting synchronous messages and cross-verifying timestamps, and entering a synchronization stage after collecting 2f synchronous messages with the same master clock number and the same timestamps by broadcasting the synchronous messages and cross-verifying the timestamps; on the basis of a Byzantine fault-tolerant model, redundant clock equipment is introduced, and a fault-tolerant time synchronization mechanism and a master clock replacement mechanism of a cold start stage and a synchronization stage of the clock equipment are added around a clock equipment set; therefore, it is ensured that the distributed network can still achieve accurate time synchronization between devices under the condition that Byzantine devices and burst interference exist.

Description

Technical Field

[0001] This invention relates to the field of precise time synchronization technology for distributed networks, specifically a precise time synchronization method based on the Byzantine fault-tolerant model. Background Technology

[0002] Currently, mainstream Ethernet time synchronization technologies are mainly based on three time synchronization protocols: NTP, IEEE 1588, and AS6802. NTP, as the earliest proposed time synchronization protocol, is widely used in traditional Ethernet, and its synchronization accuracy can reach the millisecond level. However, with the rise of real-time network research, the real-time requirements of aerospace, industrial control and other fields are no longer satisfied with millisecond-level synchronization accuracy.

[0003] The IEEE 1588 high-precision time synchronization protocol, adopted by the IEEE Standards Committee in 2002, achieves sub-microsecond accuracy compared to the NTP protocol, effectively solving the problem of insufficient time synchronization accuracy in real-time networks. Since its introduction, the IEEE 1588 time synchronization protocol has gained widespread acceptance, with many manufacturers developing their own products based on it. Currently, More Than IP and Arasan have launched MAC modules supporting the IEEE 1588 protocol, achieving clock synchronization accuracy of 50ns; Hirschmann uses FPGA chips to implement IEEE 1588 time synchronization, achieving an accuracy of 60ns. While the IEEE 1588 protocol provides high synchronization accuracy, it cannot filter out potential faulty nodes in the network. Furthermore, the master-slave time synchronization model defined in the IEEE 1588 protocol relies heavily on the stability of the master clock, thus having certain limitations.

[0004] Based on this, the present invention provides a precise time synchronization method based on the Byzantine fault-tolerant model to solve the aforementioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to provide a precise time synchronization method based on the Byzantine fault-tolerant model. Based on the Byzantine fault-tolerant model, this invention introduces redundant clock devices to solve the problem that the failure of a single clock device will prevent the distributed network from achieving time synchronization. Around the clock device set, a fault-tolerant time synchronization mechanism for the cold start phase and the synchronization phase of the clock devices, as well as a master clock replacement mechanism, are added, thereby ensuring that the distributed network can still achieve precise time synchronization between devices even in the presence of Byzantine devices and sudden interference.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] This invention provides a precise time synchronization method based on the Byzantine fault-tolerant model, comprising the following steps:

[0008] S1: After all clock devices start up, they listen to the network. If there is no synchronization network, they set their own master clock number. The device assigns itself to the role of master clock or slave clock according to the matching relationship between its own number and the master clock number. After collecting 2f synchronization messages with the same master clock number and the same timestamp, it enters the synchronization stage.

[0009] S2: The device in the synchronization phase receives and verifies synchronization messages from multiple clock devices. Based on the Byzantine fault tolerance mechanism, it completes time synchronization after receiving f+1 messages with the same synchronization period number and timestamp. During this phase, the device blocks the cold start phase messages, while the device in the cold start phase can enter the synchronization phase by directly receiving f+1 consistent synchronization messages.

[0010] S3: When the device fails to enter or maintain the synchronization phase within the preset timeout period, it enters the timeout state and triggers the master clock change process. This process includes incrementing the master clock number, periodically broadcasting view change messages, collecting 2f+1 view change messages to authorize the new master clock, and the new master clock broadcasting a synchronization message to restart the cold start process.

[0011] In step S1, the device assigns itself a role based on the matching relationship between its own serial number and the master clock number. The specific steps are as follows:

[0012] S1.1: If the device number of the clock device is the same as the master clock number m, the clock device enters the cold start phase as the master clock device; if the device number of the clock device is different from the master clock number m, the clock device enters the cold start phase as the slave clock device.

[0013] S1.2: After confirming its own role, the master clock device broadcasts a time synchronization message based on its own clock.

[0014] S1.3: After receiving a synchronization message from the master clock device, the clock device first synchronizes its time with the master clock device, and then broadcasts a synchronization message based on its own master clock number and clock time to the other clock devices.

[0015] In step S1, after collecting 2f synchronization messages with the same master clock number and timestamp as its own, the system enters the synchronization phase. Specifically, after collecting 2f synchronization messages from other clock devices with the same master clock number m and timestamp as its own, the master clock device or slave clock device calculates the sending time of the next synchronization message based on the originaltimestamp and syncInterval of the synchronization message sent by the master clock device. At the beginning of the next sending cycle, the system broadcasts the synchronization message and enters the synchronization phase.

[0016] The S1 also includes a timeout handling mechanism, specifically:

[0017] S1.4: If the slave clock device fails to collect 2f matching synchronization messages after waiting for one transmission interval and fails to enter the synchronization phase, the slave clock device enters a timeout state.

[0018] S1.5: If the clock device fails to enter the synchronization stage after the sum of two maximum delays and fault tolerance time after setting the master clock number, the clock device enters a timeout state.

[0019] S1.6: When there are enough clock devices in a timeout state, the clock device set elects a new master clock device to continue the cold start phase.

[0020] In step S2, the device in the synchronization phase receives and verifies synchronization messages from multiple clock devices. Based on the Byzantine fault tolerance mechanism, after receiving f+1 messages with the same synchronization period number and timestamp, time synchronization is completed, and fault-tolerant time synchronization calculation is performed. The specific steps are as follows:

[0021] S2.1: The clock device sends syncInterval messages at the set time synchronization interval, and periodically broadcasts Sync messages and corresponding Follow_Up messages;

[0022] S2.2: After receiving the Sync message and the corresponding Follow_Up message for the new time synchronization period, the device calculates the ratio of its own clock rate to that of the clock device, gmRateRatio, based on the Sync message and the corresponding Follow_Up message of the current time synchronization period and the previous time synchronization period.

[0023] S2.3: After the device has accumulated f+1 identical synchronization timestamps, according to the Byzantine fault tolerance mechanism, it can use any one of the f+1 identical master clock synchronization timestamps as the master clock synchronization timestamp "newTimefinal" of the node. Combined with the previously calculated ratio of its own clock rate to the clock rate of the corresponding clock device, gmRateRatio, the device can complete the time synchronization and rate adjustment with the distributed network.

[0024] In S2.2, the ratio gmRateRatio between the device's own clock rate and the clock device's clock rate is calculated as follows: after receiving the Sync message and the corresponding Follow_Up message, the device's slavePort calculates the ratio according to the transparent clock mechanism, obtains the accurate master clock synchronization timestamp and clock rate corresponding to the port, and then saves and updates the ratio according to the port number corresponding to the slavePort.

[0025] In S3, 2f+1 view change messages are collected to authorize a new master clock. Specifically, when the clock device numbered m+1 receives 2f+1 view change messages, the clock device numbered m+1 acts as the new master clock and broadcasts an m+1 synchronization message based on its own clock to all other clock devices.

[0026] The S3 also includes a timeout retry mechanism for view changes, with the following specific steps:

[0027] S3.1: A clock device that has entered a timeout state shall start timing after receiving 2f view v+1 view change messages from other clock devices;

[0028] S3.2: If a synchronization message with leader number v+1 is not received within the waiting time of 2 maximum delays, the operation of "changing its own master clock number m to m+1 and periodically broadcasting a view change synchronization message with master clock number m+1" is repeated.

[0029] The process also includes all devices performing link delay calculation operations, the specific steps of which are as follows:

[0030] a. All nodes periodically send link delay request messages to all their slavePorts according to the set link delay message sending interval pdelayInterval;

[0031] b. After receiving a link delay request message from a directly connected child node in the lower layer on its own masterPort, it responds in a timely manner according to the peer-to-peer link delay mechanism;

[0032] c. After each masterPort receives the Pdelay_Resp message and Pdelay_Resp_Follow_Up message corresponding to the previously sent Pdelay_Req message, it calculates the link delay corresponding to the slavePort according to the calculation mechanism of the peer-to-peer link delay mechanism.

[0033] d. The link latency corresponding to each slavePort is saved and updated according to the port number corresponding to the slavePort.

[0034] The process also includes the client device performing link latency calculation after startup, with the following specific steps:

[0035] ①After the client device starts up, it enters the synchronization state and begins listening for synchronization messages during the synchronization phase, without performing cold start phase operations.

[0036] ② The client device receives synchronization messages from the clock device during the synchronization phase. Using a fault-tolerant time synchronization mechanism, after receiving f+1 messages with the same synchronization period number and timestamp, it performs time synchronization based on one of the time messages and enters the synchronization phase.

[0037] Compared with the prior art, the beneficial effects of the present invention are:

[0038] This invention is based on the Byzantine fault-tolerant model and introduces redundant clock devices to solve the problem that the failure of a single clock device will cause the distributed network to fail to synchronize time. Around the clock device set, a fault-tolerant time synchronization mechanism for the cold start phase and the synchronization phase of the clock device, as well as a master clock replacement mechanism, are added, so as to ensure that the distributed network can still achieve accurate time synchronization between devices in the presence of Byzantine devices and sudden interference. Attached Figure Description

[0039] Figure 1 This is a flowchart of a precise time synchronization method based on the Byzantine fault-tolerant model according to the present invention.

[0040] Figure 2 This is a schematic diagram of the cold start phase in a precise time synchronization method based on the Byzantine fault-tolerant model of the present invention.

[0041] Figure 3 This is a schematic diagram of the synchronization stage in a precise time synchronization method based on the Byzantine fault-tolerant model of the present invention.

[0042] Figure 4 This is a flowchart of the master clock device state machine in a precise time synchronization method based on the Byzantine fault-tolerant model of the present invention.

[0043] Figure 5This is a flowchart of the state machine of the clock device in the precise time synchronization method based on the Byzantine fault-tolerant model of the present invention.

[0044] Figure 6 This is a flowchart of the client device state machine in the precise time synchronization method based on the Byzantine fault-tolerant model of the present invention. Detailed Implementation

[0045] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0046] Example:

[0047] like Figures 1-6 As shown, this embodiment provides a precise time synchronization method based on the Byzantine fault-tolerant model, including the following steps:

[0048] S1: After all clock devices start up, they listen to the network. If there is no synchronization network, they set their own master clock number. The device assigns itself to the role of master clock or slave clock according to the matching relationship between its own number and the master clock number. After collecting 2f synchronization messages with the same master clock number and the same timestamp, it enters the synchronization stage.

[0049] S2: The device in the synchronization phase receives and verifies synchronization messages from multiple clock devices. Based on the Byzantine fault tolerance mechanism, it completes time synchronization after receiving f+1 messages with the same synchronization period number and timestamp. During this phase, the device blocks the cold start phase messages, while the device in the cold start phase can enter the synchronization phase by directly receiving f+1 consistent synchronization messages.

[0050] S3: When the device fails to enter or maintain the synchronization phase within the preset timeout period, it enters the timeout state and triggers the master clock change process. This process includes incrementing the master clock number, periodically broadcasting view change messages, collecting 2f+1 view change messages to authorize the new master clock, and the new master clock broadcasting a synchronization message to restart the cold start process.

[0051] In S1, devices assign roles themselves based on the matching relationship between their own serial number and the master clock number. The specific steps are as follows:

[0052] S1.1: If the device number of the clock device is the same as the master clock number m, the clock device enters the cold start phase as the master clock device; if the device number of the clock device is different from the master clock number m, the clock device enters the cold start phase as the slave clock device.

[0053] S1.2: After confirming its own role, the master clock device broadcasts a time synchronization message based on its own clock.

[0054] S1.3: After receiving a synchronization message from the master clock device, the clock device first synchronizes its time with the master clock device, and then broadcasts a synchronization message based on its own master clock number and clock time to the other clock devices.

[0055] In S1, after collecting 2f synchronization messages with the same master clock number and timestamp as its own, it enters the synchronization phase. Specifically, after collecting 2f synchronization messages from other clock devices with the same master clock number m and timestamp as its own, the master clock device or slave clock device calculates the sending time of the next synchronization message based on the originaltimestamp and syncInterval of the synchronization message sent by the master clock device. At the beginning of the next sending cycle, it broadcasts the synchronization message and enters the synchronization phase.

[0056] S1 also includes a timeout handling mechanism, specifically:

[0057] S1.4: If the slave clock device fails to collect 2f matching synchronization messages after waiting for one transmission interval and fails to enter the synchronization phase, the slave clock device enters a timeout state.

[0058] S1.5: If the clock device fails to enter the synchronization stage after the sum of two maximum delays and fault tolerance time after setting the master clock number, the clock device enters a timeout state.

[0059] S1.6: When there are enough clock devices in a timeout state, the clock device set elects a new master clock device to continue the cold start phase.

[0060] In S2, the device in the synchronization phase receives and verifies synchronization messages from multiple clock devices. Based on the Byzantine fault tolerance mechanism, after receiving f+1 messages with the same synchronization period number and timestamp, time synchronization is completed, and fault-tolerant time synchronization calculation is performed. The specific steps are as follows:

[0061] S2.1: The clock device sends syncInterval messages at the set time synchronization interval, and periodically broadcasts Sync messages and corresponding Follow_Up messages;

[0062] S2.2: After receiving the Sync message and the corresponding Follow_Up message for the new time synchronization period, the device calculates the ratio of its own clock rate to that of the clock device, gmRateRatio, based on the Sync message and the corresponding Follow_Up message of the current time synchronization period and the previous time synchronization period.

[0063] S2.3: After the device has accumulated f+1 identical synchronization timestamps, according to the Byzantine fault tolerance mechanism, it can use any one of the f+1 identical master clock synchronization timestamps as the master clock synchronization timestamp "newTimefinal" of the node. Combined with the previously calculated ratio of its own clock rate to the clock rate of the corresponding clock device, gmRateRatio, the device can complete the time synchronization and rate adjustment with the distributed network.

[0064] In S2.2, the ratio of its own clock rate to the clock device's clock rate, gmRateRatio, is calculated as follows: after receiving the Sync message and the corresponding Follow_Up message, the slavePort of the device calculates the accurate master clock synchronization timestamp and clock rate corresponding to the port according to the transparent clock mechanism, and then saves and updates them according to the port number corresponding to the slavePort.

[0065] In S3, 2f+1 view change messages are collected to authorize a new master clock. Specifically, when the clock device numbered m+1 receives 2f+1 view change messages, the clock device numbered m+1 acts as the new master clock and broadcasts an m+1 synchronization message based on its own clock to all other clock devices.

[0066] S3 also includes a timeout retry mechanism for view changes, with the following steps:

[0067] S3.1: A clock device that has entered a timeout state shall start timing after receiving 2f view v+1 view change messages from other clock devices;

[0068] S3.2: If a synchronization message with leader number v+1 is not received within the waiting time of 2 maximum delays, the operation of "changing its own master clock number m to m+1 and periodically broadcasting a view change synchronization message with master clock number m+1" is repeated.

[0069] This also includes performing link delay calculation on all devices. The specific steps for link delay calculation are as follows:

[0070] a. All nodes periodically send link delay request messages to all their slavePorts according to the set link delay message sending interval pdelayInterval;

[0071] b. After receiving a link delay request message from a directly connected child node in the lower layer on its own masterPort, it responds in a timely manner according to the peer-to-peer link delay mechanism;

[0072] c. After each masterPort receives the Pdelay_Resp message and Pdelay_Resp_Follow_Up message corresponding to the previously sent Pdelay_Req message, it calculates the link delay corresponding to the slavePort according to the calculation mechanism of the peer-to-peer link delay mechanism.

[0073] d. The link latency corresponding to each slavePort is saved and updated according to the port number corresponding to the slavePort.

[0074] This also includes the link latency calculation operation performed by the client device after startup, with the specific steps as follows:

[0075] ①After the client device starts up, it enters the synchronization state and begins listening for synchronization messages during the synchronization phase, without performing cold start phase operations.

[0076] ② The client device receives synchronization messages from the clock device during the synchronization phase. Using a fault-tolerant time synchronization mechanism, after receiving f+1 messages with the same synchronization period number and timestamp, it performs time synchronization based on one of the time messages and enters the synchronization phase.

[0077] In this embodiment, a precise time synchronization method based on the Byzantine fault-tolerant model is described as follows: First, S1: After all clock devices start up, they listen to the network. If there is no synchronization network, they set their own master clock number. After starting up, all clock devices first wait for a synchronization cycle to check if there is a synchronization network in the current network. If not, they set their own master clock number m to 1. The device assigns itself to the role of master clock or slave clock according to the matching relationship between its own number and the master clock number. The specific steps are as follows: S1.1: If the device number of the clock device is the same as the master clock number m, the clock device enters the cold start stage as the master clock device. If the device number of the clock device is different from the master clock number m, the clock device enters the cold start stage as the slave clock device; S1.2: After confirming its role, the master clock device broadcasts a time synchronization message based on its own clock; S1.3: After receiving the synchronization message from the master clock device, the slave clock device first synchronizes its time with the master clock device, and then broadcasts a synchronization message based on its own master clock number and clock time to the other clock devices. After collecting 2f synchronization messages with the same master clock number and timestamp as its own, the master clock device or slave clock device enters the synchronization phase by broadcasting synchronization messages and cross-validating timestamps. Specifically, after collecting 2f synchronization messages with the same master clock number m and timestamp as its own from other clock devices, the master clock device or slave clock device calculates the sending time of the next synchronization message based on the originaltimestamp and sending interval syncInterval of the synchronization message sent by the master clock device. At the beginning of the next sending cycle, the master clock device broadcasts the synchronization message and enters the synchronization phase. S1 also includes a timeout handling mechanism, specifically: S1.4: If a slave clock device waits for one transmission interval and still fails to collect 2f matching synchronization messages and does not enter the synchronization phase, then the slave clock device enters a timeout state; S1.5: If a clock device, after setting the master clock number, still fails to enter the synchronization phase after the sum of two maximum delays and fault tolerance periods, then the clock device enters a timeout state; S1.6: When there are enough clock devices in the timeout state, the clock device set will elect a new master clock device to continue the cold start phase.S2: During the synchronization phase, the device receives and verifies synchronization messages from multiple clock devices. Based on the Byzantine fault tolerance mechanism, after receiving f+1 messages with the same synchronization period number and timestamp, time synchronization is completed, and fault-tolerant time synchronization calculation is performed. The specific steps are as follows: S2.1: The clock device sends time synchronization messages at the set interval syncInterval and periodically broadcasts Sync messages and corresponding Follow_Up messages; S2.2: After receiving the Sync message and corresponding Follow_Up message for a new time synchronization period, the device calculates the ratio gmRateRatio of its own clock rate to that of the clock device based on the Sync message and corresponding Follow_Up message of the current time synchronization period and the previous time synchronization period. Specifically, after receiving the Sync message and corresponding Follow_Up message, the device's slavePort calculates according to the transparent clock mechanism to obtain the accurate master clock synchronization timestamp and clock rate corresponding to the port, and then saves and updates it according to the port number corresponding to slavePort. S2.3: After accumulating f+1 identical synchronization timestamps, the device, according to the Byzantine fault tolerance mechanism, can use any one of the f+1 identical master clock synchronization timestamps as the master clock synchronization timestamp "newTimefinal" for that node. Combined with the previously calculated ratio of its own clock rate to the corresponding clock device's clock rate, gmRateRatio, it completes time synchronization and rate adjustment with the distributed network. During this stage, the device blocks cold start phase messages, and clock devices in the synchronization phase block cold start phase message messages. After entering the synchronization phase, if a clock device does not receive f+1 time synchronization messages with the same synchronization period number and timestamp for a long time, it will enter a timeout state and perform master clock change. When there are enough clock devices in the timeout state, the clock devices will hold a meeting to elect a master clock device and re-perform a cold start, so that the clock devices can re-synchronize time. Devices in the cold start phase can receive synchronization messages from the synchronization phase. When it receives f+1 messages with the same synchronization period number and timestamp, it performs fault-tolerant time synchronization calculation and enters the synchronization phase. Devices in the cold start phase can enter the synchronization phase by directly receiving f+1 consistent synchronization messages. S3: When a device fails to enter or maintain the synchronization phase within the preset timeout period, it enters the timeout state and triggers the master clock change process. After the clock device enters the timeout state, it blocks the message messages from the cold start phase. After the clock device enters the timeout state, it changes its own m to m+1 and periodically broadcasts view change synchronization messages with master clock number m+1.Simultaneously, VIEW-CHANGE messages from other clock devices are collected. This process includes incrementing the master clock number, periodically broadcasting view change messages, and collecting 2f+1 view change messages to authorize a new master clock. Specifically, when clock device number m+1 receives 2f+1 view change messages, this clock device, numbered m+1, becomes the new master clock and broadcasts an m+1 synchronization message based on its own clock to all other clock devices. The new master clock also broadcasts a synchronization message to restart the cold start process. S3 also includes a timeout retry mechanism for view changes, with the following steps: S3.1: After receiving 2f view change messages (v+1) from other clock devices, the clock device in the timeout state starts timing; S3.2: If a synchronization message with a leader number of v+1 is not received within the waiting time of two maximum delays, the operation of "changing its own master clock number m to m+1 and periodically broadcasting a view change synchronization message with master clock number m+1" is repeated. This also includes all devices performing link delay calculation operations. The specific steps of the link delay calculation operation are as follows: a) All nodes periodically send link delay request messages to all their slavePorts according to the set link delay message sending interval pdelayInterval; b) After receiving the link delay request message from the directly connected child node at the lower layer, the masterPort responds in a timely manner according to the peer-to-peer link delay mechanism; c) After receiving the Pdelay_Resp message and Pdelay_Resp_Follow_Up message corresponding to the previously sent Pdelay_Req message, each masterPort calculates the link delay corresponding to the slavePort according to the calculation mechanism of the peer-to-peer link delay mechanism; d) The link delay corresponding to each slavePort is saved and updated according to the port number corresponding to the slavePort. It also includes the client device performing link delay calculation after startup. The specific steps are as follows: ① After startup, the client device enters the synchronization state and starts listening for synchronization messages in the synchronization phase, without performing cold start phase operations; ② The client device receives synchronization messages from the clock device in the synchronization phase, uses a fault-tolerant time synchronization calculation mechanism, and after receiving f+1 messages with the same synchronization period number and timestamp, it performs time synchronization based on one of the time messages and enters the synchronization phase.

[0078] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A precise time synchronization method based on the Byzantine fault-tolerant model, characterized in that, Includes the following steps: S1: After all clock devices start up, they listen to the network. If there is no synchronization network, they set their own master clock number. The device assigns itself to the role of master clock or slave clock according to the matching relationship between its own number and the master clock number. After collecting 2f synchronization messages with the same master clock number and the same timestamp, it enters the synchronization stage. S2: The device in the synchronization phase receives and verifies synchronization messages from multiple clock devices. Based on the Byzantine fault tolerance mechanism, it completes time synchronization after receiving f+1 messages with the same synchronization period number and timestamp. During this phase, the device blocks the cold start phase messages, while the device in the cold start phase can enter the synchronization phase by directly receiving f+1 consistent synchronization messages. S3: When the device fails to enter or maintain the synchronization phase within the preset timeout period, it enters the timeout state and triggers the master clock change process. The process includes incrementing the master clock number, periodically broadcasting view change messages, collecting 2f+1 view change messages to authorize the new master clock, and the new master clock broadcasting a synchronization message to restart the cold start process.

2. The precise time synchronization method based on the Byzantine fault-tolerant model according to claim 1, characterized in that, In step S1, the device assigns itself a role based on the matching relationship between its own serial number and the master clock number. The specific steps are as follows: S1.1: If the device number of the clock device is the same as the master clock number m, the clock device enters the cold start phase as the master clock device; if the device number of the clock device is different from the master clock number m, the clock device enters the cold start phase as the slave clock device. S1.2: After confirming its own role, the master clock device broadcasts a time synchronization message based on its own clock. S1.3: After receiving a synchronization message from the master clock device, the clock device first synchronizes its time with the master clock device, and then broadcasts a synchronization message based on its own master clock number and clock time to the other clock devices.

3. The precise time synchronization method based on the Byzantine fault-tolerant model according to claim 2, characterized in that, In step S1, after collecting 2f synchronization messages with the same master clock number and timestamp as its own, the system enters the synchronization phase. Specifically, after collecting 2f synchronization messages from other clock devices with the same master clock number m and timestamp as its own, the master clock device or slave clock device calculates the sending time of the next synchronization message based on the originaltimestamp and syncInterval of the synchronization message sent by the master clock device. At the beginning of the next sending cycle, the system broadcasts the synchronization message and enters the synchronization phase.

4. The precise time synchronization method based on the Byzantine fault-tolerant model according to claim 3, characterized in that, The S1 also includes a timeout handling mechanism, specifically: S1.4: If the slave clock device fails to collect 2f matching synchronization messages after waiting for one transmission interval and fails to enter the synchronization phase, the slave clock device enters a timeout state. S1.5: If the clock device fails to enter the synchronization stage after the sum of two maximum delays and fault tolerance time after setting the master clock number, the clock device enters a timeout state. S1.6: When there are enough clock devices in a timeout state, the clock device set elects a new master clock device to continue the cold start phase.

5. The precise time synchronization method based on the Byzantine fault-tolerant model according to claim 1, characterized in that, In step S2, the device in the synchronization phase receives and verifies synchronization messages from multiple clock devices. Based on the Byzantine fault tolerance mechanism, after receiving f+1 messages with the same synchronization period number and timestamp, time synchronization is completed, and fault-tolerant time synchronization calculation is performed. The specific steps are as follows: S2.1: The clock device sends syncInterval messages at the set time synchronization interval, and periodically broadcasts Sync messages and corresponding Follow_Up messages; S2.2: After receiving the Sync message and the corresponding Follow_Up message for the new time synchronization period, the device calculates the ratio of its own clock rate to that of the clock device, gmRateRatio, based on the Sync message and the corresponding Follow_Up message of the current time synchronization period and the previous time synchronization period. S2.3: After the device has accumulated f+1 identical synchronization timestamps, according to the Byzantine fault tolerance mechanism, it can use any one of the f+1 identical master clock synchronization timestamps as the master clock synchronization timestamp "newTimefinal" of the node. Combined with the previously calculated ratio of its own clock rate to the clock rate of the corresponding clock device, gmRateRatio, the device can complete the time synchronization and rate adjustment with the distributed network.

6. The precise time synchronization method based on the Byzantine fault-tolerant model according to claim 5, characterized in that, In S2.2, the ratio gmRateRatio between the device's own clock rate and the clock device's clock rate is calculated as follows: after receiving the Sync message and the corresponding Follow_Up message, the device's slavePort calculates the ratio according to the transparent clock mechanism, obtains the accurate master clock synchronization timestamp and clock rate corresponding to the port, and then saves and updates the ratio according to the port number corresponding to the slavePort.

7. The precise time synchronization method based on the Byzantine fault-tolerant model according to claim 1, characterized in that, In S3, 2f+1 view change messages are collected to authorize a new master clock. Specifically, when the clock device numbered m+1 receives 2f+1 view change messages, the clock device numbered m+1 acts as the new master clock and broadcasts an m+1 synchronization message based on its own clock to all other clock devices.

8. The precise time synchronization method based on the Byzantine fault-tolerant model according to claim 7, characterized in that, The S3 also includes a timeout retry mechanism for view changes, with the following specific steps: S3.1: A clock device that has entered a timeout state shall start timing after receiving 2f view v+1 view change messages from other clock devices; S3.2: If a synchronization message with leader number v+1 is not received within the waiting time of 2 maximum delays, the operation of "changing its own master clock number m to m+1 and periodically broadcasting a view change synchronization message with master clock number m+1" is repeated.

9. The precise time synchronization method based on the Byzantine fault-tolerant model according to claim 1, characterized in that, The process also includes all devices performing link delay calculation operations, the specific steps of which are as follows: a. All nodes periodically send link delay request messages to all their slavePorts according to the set link delay message sending interval pdelayInterval; b. After receiving a link delay request message from a directly connected child node in the lower layer on its own masterPort, it responds in a timely manner according to the peer-to-peer link delay mechanism; c. After each masterPort receives the Pdelay_Resp message and Pdelay_Resp_Follow_Up message corresponding to the previously sent Pdelay_Req message, it calculates the link delay corresponding to the slavePort according to the calculation mechanism of the peer-to-peer link delay mechanism. d. The link latency corresponding to each slavePort is saved and updated according to the port number corresponding to the slavePort.

10. A precise time synchronization method based on a Byzantine fault-tolerant model according to claim 1, characterized in that, The process also includes the client device performing link latency calculation after startup, with the following specific steps: ①After the client device starts up, it enters the synchronization state and begins listening for synchronization messages during the synchronization phase, without performing cold start phase operations. ② The client device receives synchronization messages from the clock device during the synchronization phase. Using a fault-tolerant time synchronization mechanism, after receiving f+1 messages with the same synchronization period number and timestamp, it performs time synchronization based on one of the time messages and enters the synchronization phase.

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