A monitoring circuit and method for laser pulse intensity

Abstract

This invention relates to the field of laser technology and discloses a laser pulse intensity monitoring circuit and method. The circuit includes an optical signal monitoring circuit, a signal generation circuit, a sample-and-hold circuit, and a control module. The optical signal monitoring circuit generates a voltage signal to be monitored based on the pulse emitted by the pulsed laser. The signal generation circuit generates multiple hold signals whose trigger edges are sequentially delayed by the emitted light signal according to the control pulsed laser pulse generation signal. The sample-and-hold circuit is connected to both the optical signal monitoring circuit and the signal generation circuit, and is used to output multiple sampled voltage signals corresponding to the hold signals according to the voltage signal to be monitored and the multiple hold signals. The control module is connected to the sample-and-hold circuit and is used to sequentially sample the sampled voltage signals corresponding to each hold signal after detecting the trigger edge of a preset hold signal. This invention can solve the problem that short pulse signals cannot be sampled due to the slow response speed of the control module and the low sampling rate.

Description

Technical Field

[0001] This invention relates to the field of laser technology, and more specifically to a monitoring circuit and method for laser pulse intensity. Background Technology

[0002] The output signal of a pulsed laser is randomly generated by external processing equipment, making it random and unpredictable for the laser itself. The intensity of the first pulse directly affects the processing effect and equipment safety: too weak an intensity will result in insufficient processing depth, while too strong an intensity will easily cause excessive processing depth. Furthermore, when the intensity exceeds twice that of a conventional pulse, it can damage the internal optical fiber and cause the machine to burn out. Therefore, the intensity of the first pulse needs to be precisely monitored, with an accuracy requirement of within 5%.

[0003] Currently, the pulse width of short-pulse lasers is approximately 200 ns. However, the microcontroller unit (MCU) used for monitoring within these lasers has an ADC sampling rate on the microsecond level, which is insufficient to stably sample the peak intensity of nanosecond-level optical pulses, making it difficult to effectively detect the intensity of the first pulse. Furthermore, continuous-pulse lasers are prone to sudden, sub-microsecond-level light emission phenomena during operation. Due to the limitations of the MCU's ADC sampling rate, these short-term emission events also cannot be effectively monitored, potentially leading to processing defects or equipment malfunctions. Summary of the Invention

[0004] This invention provides a monitoring circuit and method for laser pulse intensity to solve the technical problem that the short pulses output by a pulsed laser cannot be effectively monitored due to sampling frequency limitations.

[0005] In a first aspect, the present invention provides a monitoring circuit for laser pulse intensity, comprising:

[0006] An optical signal monitoring circuit is used to generate a voltage signal to be monitored based on the pulse emitted by a pulsed laser.

[0007] The signal generation circuit is used to generate multiple hold signals whose trigger edges are sequentially delayed by the output light signal of the control pulse laser, based on the output light signal of the pulse laser. The interval between the trigger edges of two adjacent hold signals is less than the width of the pulse to be monitored.

[0008] The sample-and-hold circuit is connected to both the optical signal monitoring circuit and the signal generation circuit. It is used to output multiple sampled voltage signals corresponding to the holding signals based on the voltage signal to be monitored and the multiple holding signals. The sampled voltage signal is the voltage signal that holds the amplitude of the voltage signal to be monitored at the trigger edge of the corresponding holding signal.

[0009] The control module, connected to the sample-and-hold circuit, is used to sequentially sample the voltage signals to be sampled corresponding to each hold signal after detecting the trigger edge of the preset hold signal.

[0010] The laser pulse intensity monitoring circuit of the present invention generates multiple hold signals whose trigger edges lag behind the output light signals based on the output light signals generated by the control pulse laser. The sampling and holding circuit outputs multiple sampled voltage signals corresponding to the hold signals based on the monitored voltage signal generated by the optical signal monitoring circuit and the multiple hold signals. In this way, the control module can sequentially sample the sampled voltage signals corresponding to each hold signal after detecting the trigger edge of the preset hold signal. Since the sampled voltage signal is the voltage signal that holds the amplitude of the monitored voltage signal at the trigger edge of the corresponding hold signal, the control module only needs a low sampling frequency to obtain the amplitude of the monitored voltage signal at the trigger edge of each hold signal, thus obtaining the shape of the monitored pulse and realizing effective monitoring of the short pulses output by the pulse laser. This solves the problem that the control module cannot sample short pulse signals due to slow response speed and low sampling rate.

[0011] In one optional implementation, the signal generation circuit includes an inverting circuit, multiple RC filter circuits, and a non-inverting circuit. The non-inverting circuit includes multiple input / output units, each of which includes an input terminal and an output terminal. The output terminal of the emitted light signal is connected to the input terminal of the inverting circuit. The output terminal of the inverting circuit is connected to the input terminal of an input / output unit through an RC filter circuit. The output terminal of each input / output unit is connected to the input terminal of an adjacent input / output unit through a corresponding RC filter circuit. The output terminal of any input / output unit is connected to a sample-and-hold circuit.

[0012] In this method, two adjacent input and output units of the non-inverting circuit are connected to corresponding RC filter circuits. The signal delay is achieved through the RC filter circuit, which can change the time delay of each hold signal, thereby obtaining multiple hold signals with different delays.

[0013] In one optional implementation, the RC filter circuit includes an adjustable resistor and a target capacitor. The first end of the adjustable resistor is connected to the output terminal of the inverting circuit or the output terminal of the non-inverting circuit. The second end of the adjustable resistor is connected to both the first end of the target capacitor and the input terminal of the non-inverting circuit. The second end of the target capacitor is grounded.

[0014] In this method, the time delay of each hold signal can be flexibly changed by adjusting the resistor, thereby meeting the monitoring requirements of laser pulses of different widths.

[0015] In one optional implementation, the non-inverting circuit includes at least one non-inverting buffer, the input terminal of which is the input terminal of the non-inverting circuit, and the output terminal of which is the output terminal of the non-inverting circuit.

[0016] In this method, multiple hold signals can be easily obtained through a positive phase buffer.

[0017] In one optional implementation, the sample-and-hold circuit includes multiple sample-and-hold chips, with the input pin of any sample-and-hold chip connected to the output terminal of the optical signal monitoring circuit, the output pin of any sample-and-hold chip connected to the control module, and the control pin of each sample-and-hold chip connected to different output terminals of the signal generation circuit.

[0018] In this method, each hold signal corresponds to a sample-and-hold chip, which can synchronously sample and lock the amplitude of the voltage signal to be monitored at different trigger edges, ensuring that the multiple voltage signals to be sampled are a true reflection of the actual amplitude of the optical pulse, without sampling deviation.

[0019] In one optional implementation, the preset hold signal is the hold signal with the largest trigger edge delay. The control module includes input / output pins and multiple sampling pins. The input / output pins are connected to the output pins of the sample-and-hold chip that outputs the preset hold signal, and each sampling pin is connected to the corresponding output pin of the sample-and-hold chip.

[0020] In this method, after the trigger edge of the preset hold signal is detected, each voltage signal to be sampled is sampled sequentially to ensure that all sample-and-hold chips have completed amplitude locking, avoid invalid sampled values ​​due to premature sampling, and ensure the orderliness of sampling.

[0021] In one alternative implementation, the optical signal monitoring circuit includes:

[0022] A photoelectric conversion circuit is used to generate an initial voltage signal based on the pulse to be monitored emitted from a pulsed laser.

[0023] The voltage amplifier circuit, connected to the photoelectric conversion circuit, is used to amplify the initial voltage signal to obtain the voltage signal to be monitored.

[0024] In this method, the voltage signal to be monitored, converted from the pulse to be monitored, can be obtained through a photoelectric conversion circuit and a voltage amplification circuit, which facilitates subsequent sampling.

[0025] In one optional embodiment, the photoelectric conversion circuit includes a photoelectric sensor, a transimpedance amplifier circuit, and a digital potentiometer. The positive terminal of the photoelectric sensor is grounded, the negative terminal of the photoelectric sensor is connected to the negative input terminal of the transimpedance amplifier circuit, the positive input terminal of the transimpedance amplifier circuit is connected to the output terminal of the reference power supply circuit, the output terminal of the transimpedance amplifier circuit is connected to the high-side fixed terminal of the digital potentiometer, and the vernier terminal of the digital potentiometer is connected to the voltage amplifier circuit.

[0026] In this method, a photoelectric sensor is used in conjunction with a transimpedance amplifier circuit to directly convert the photocurrent signal of the photoelectric sensor into a voltage signal. This voltage signal is then introduced into a digital potentiometer and connected to the output terminal of the transimpedance amplifier circuit. The output gain of the photoelectric conversion circuit can be precisely adjusted by digitally adjusting the vernier position of the potentiometer.

[0027] In one optional embodiment, the voltage amplifier circuit includes a voltage amplifier circuit and a differential circuit. The negative input terminal of the voltage amplifier circuit is connected to the output terminal of the reference power supply circuit, the positive input terminal of the voltage amplifier circuit is connected to the vernier terminal of the digital potentiometer, the output terminal of the voltage amplifier circuit is connected to the positive input terminal of the differential circuit, the negative input terminal of the differential circuit is connected to the output terminal of the reference power supply circuit, and the output terminal of the differential circuit is connected to the sample and hold circuit.

[0028] In this method, the output voltage can be further amplified by voltage amplification circuit and differential circuit, and the reference voltage in the output voltage can be filtered out.

[0029] In a second aspect, the present invention provides a method for monitoring laser pulse intensity, applied to a laser pulse intensity control module as described in the first aspect and any one thereof, comprising:

[0030] Monitor whether the preset hold signal generates a trigger edge. If the preset hold signal generates a trigger edge, sample each voltage signal to be sampled in sequence according to the preset order.

[0031] The shape of the pulse to be monitored is obtained by sampling the voltage signals to be sampled and the pre-set interval between the trigger edges of the hold signals. Attached Figure Description

[0032] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a circuit diagram of the laser pulse intensity monitoring circuit according to an embodiment of the present invention;

[0034] Figure 2 This is a circuit diagram of the signal generation circuit according to an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the holding signal according to an embodiment of the present invention;

[0036] Figure 4 This is a circuit diagram of the sample-and-hold circuit according to an embodiment of the present invention;

[0037] Figure 5 This is a circuit diagram of the photoelectric conversion circuit according to an embodiment of the present invention;

[0038] Figure 6 This is a circuit diagram of a reference power supply circuit according to an embodiment of the present invention;

[0039] Figure 7 This is a circuit diagram of the voltage amplifier circuit according to an embodiment of the present invention;

[0040] Figure 8 This is a flowchart illustrating the laser pulse intensity monitoring method according to an embodiment of the present invention.

[0041] Explanation of reference numerals in the attached figures:

[0042] 101. Optical signal monitoring circuit; 102. Signal generation circuit; 103. Sample and hold circuit; 104. Control module; U1. Inverting buffer; U2A. First non-inverting buffer; U2B. Second non-inverting buffer; U14. Digital potentiometer; PD1. Photoelectric sensor; U13B. Fourth operational amplifier; U12. Third operational amplifier; R16. Sixteenth resistor; R17. Seventeenth resistor; R18. Eighteenth resistor; R19. Nineteenth resistor. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] It should be noted that the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection of two components. The terms "parallel," "perpendicular," and "equal" include the described situation and situations that are similar to the described situation, where the range of similarity is within an acceptable deviation range, which is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5°; "equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, the difference between the two equals being less than or equal to 5% of either one. For a person skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0045] Currently, for short-pulse lasers such as most green lasers, the pulse width of the first pulse is about 200 ns, while the sampling rate of the ADC used for monitoring inside the pulsed laser is at the microsecond level, making it difficult to effectively detect the intensity of the first pulse.

[0046] In view of this, embodiments of the present invention provide a monitoring circuit and method for laser pulse intensity, which can effectively detect short pulses output by a pulsed laser without increasing the sampling frequency.

[0047] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] According to an embodiment of the present invention, a monitoring circuit for laser pulse intensity is provided, such as... Figure 1 As shown, the laser pulse intensity monitoring circuit includes an optical signal monitoring circuit 101, a signal generation circuit 102, a sample and hold circuit 103, and a control module 104.

[0049] The optical signal monitoring circuit 101 is used to generate a voltage signal to be monitored based on the pulse emitted by the pulsed laser.

[0050] Specifically, pulsed lasers can be green lasers, ultraviolet lasers, etc. Taking green lasers as an example, their first pulse width is generally 200ns.

[0051] The pulses emitted by the pulsed laser to be monitored include, but are not limited to, the first pulse.

[0052] The voltage signal to be monitored is a voltage signal generated based on the optical signal of the pulse to be monitored. Its amplitude waveform is basically the same as the optical signal waveform of the pulse to be monitored, so the corresponding optical pulse waveform can be obtained based on the waveform of the voltage signal to be monitored.

[0053] The signal generation circuit 102 is used to generate multiple hold signals whose trigger edges are sequentially delayed by the output light signal of the control pulse laser, based on the output light signal of the pulse generated by the control pulse laser. The interval between the trigger edges of two adjacent hold signals is less than the width of the pulse to be monitored.

[0054] Specifically, the emitted light signal can be generated by external processing equipment and then input into the signal generation circuit 102, or it can be generated by the control module 104 and actively triggered for monitoring.

[0055] The trigger edges of the hold signal include, but are not limited to, falling edges and rising edges.

[0056] The number of hold signals can be set according to actual needs, such as 4, 8, or 10 channels. The trigger edge generation time of each hold signal increases sequentially, and the interval between the trigger edges of two adjacent hold signals is less than the width of the pulse to be monitored to ensure effective monitoring of the pulse. Furthermore, for monitoring the first pulse, the interval between the trigger edge of the first hold signal and the trigger edge of the emitted light signal must also be less than the width of the pulse to be monitored.

[0057] The sample-and-hold circuit 103 is connected to the optical signal monitoring circuit 101 and the signal generation circuit 102. It is used to output multiple sampled voltage signals corresponding to the holding signals based on the voltage signal to be monitored and the multiple holding signals. The sampled voltage signal is the voltage signal that holds the amplitude of the voltage signal to be monitored at the trigger edge of the corresponding holding signal.

[0058] Specifically, the sample-and-hold circuit 103 is a circuit module that receives the voltage signal to be monitored and multiple holding signals, locks the instantaneous amplitude of the voltage signal to be monitored at the trigger edge of the holding signal, and stably holds the amplitude as a DC voltage signal.

[0059] The sample-and-hold circuit 103 has multiple input terminals and multiple output terminals. Each input terminal receives a voltage signal to be monitored. When the trigger edge of any holding signal is detected, the voltage signal to be monitored is output and held through one of the output terminals, thereby obtaining multiple voltage signals that hold the amplitude of the voltage signals to be monitored at the corresponding trigger edge of the holding signal, i.e., the voltage signals to be sampled.

[0060] The control module 104 is connected to the sample-and-hold circuit 103 and is used to sample the voltage signals to be sampled corresponding to each holding signal in sequence after detecting the trigger edge of the preset holding signal.

[0061] Specifically, the control module 104 can be a microcontroller unit (MCU) or other type of processor, which has an internal ADC sampling module to sample the values ​​of each voltage signal to be sampled. The sampling frequency of the ADC sampling module can be on the order of microseconds.

[0062] The preset hold signal can be set according to the situation. Generally, the preset hold signal is the hold signal with the longest trigger edge delay. For example, if there are 1 to 8 hold signals sorted according to the trigger edge generation time, then the 8th hold signal is used as the preset hold signal.

[0063] Since the voltage signal to be sampled can maintain the signal of the voltage signal to be monitored at each trigger edge, even if the sampling frequency of the control module 104 is low and the sampling interval is greater than the pulse width, it can still acquire the value of the voltage signal to be sampled, thereby obtaining the shape of the optical pulse to be monitored.

[0064] The laser pulse intensity monitoring circuit of this embodiment generates multiple hold signals whose trigger edges lag behind the output light signals based on the output light signals of the control pulse laser. The sampling and holding circuit 103 outputs multiple sampled voltage signals corresponding to the hold signals based on the voltage signal to be monitored generated by the optical signal monitoring circuit 101 and the multiple hold signals. In this way, the control module 104 can sequentially sample the sampled voltage signals corresponding to each hold signal after detecting the trigger edge of the preset hold signal. Since the sampled voltage signal is the voltage signal that holds the amplitude of the voltage signal to be monitored at the trigger edge of the corresponding hold signal, the control module 104 only needs a low sampling frequency to obtain the amplitude of the voltage signal to be monitored at the trigger edge of each hold signal, thus obtaining the shape of the pulse to be monitored and realizing effective monitoring of the short pulses output by the pulse laser. This solves the problem that the control module 104 cannot sample short pulse signals due to the slow response speed and low sampling rate of the control module 104.

[0065] In some embodiments, such as Figure 2 and Figure 3 As shown, the signal generation circuit 102 includes an inverting circuit, multiple RC filter circuits, and a non-inverting circuit. The non-inverting circuit includes multiple input / output units, each of which includes an input terminal and an output terminal. The output terminal of the emitted light signal is connected to the input terminal of the inverting circuit. The output terminal of the inverting circuit is connected to the input terminal of an input / output unit through an RC filter circuit. The output terminal of the input / output unit is connected to the input terminal of the adjacent input / output unit through the corresponding RC filter circuit. The output terminal of any input / output unit is connected to a sample-and-hold circuit.

[0066] Specifically, the inverting circuit includes an inverting buffer U1, which can be an SN74LVC1G16-Q1. The propagation delay of this buffer is ≤4.6ns, which can minimize the delay.

[0067] Furthermore, the RC filter circuit includes an adjustable resistor and a target capacitor. The first end of the adjustable resistor is connected to the output terminal of the inverting circuit or the output terminal of the non-inverting circuit. The second end of the adjustable resistor is connected to both the first end of the target capacitor and the input terminal of the non-inverting circuit. The second end of the target capacitor is grounded.

[0068] A non-inverting circuit includes at least one non-inverting buffer. The input terminal of the non-inverting buffer is the input terminal of the non-inverting circuit, and the output terminal of the non-inverting buffer is the output terminal of the non-inverting circuit. Multiple hold signals can be easily obtained through a non-inverting buffer.

[0069] In one example, a precision adjustable resistor is used, and a simple time-adjustable RC filter circuit can be formed by combining the adjustable resistor and the target capacitor.

[0070] The non-inverting circuit includes a first non-inverting buffer U2A and a second non-inverting buffer U2B. Both non-inverting buffers are model SN74LVC244APW. Each non-inverting buffer has 4 inputs and 4 outputs, with each input and output corresponding to an input / output unit. The two non-inverting buffers work together to provide 8 outputs. Correspondingly, the RC filter circuit has 8 channels. The adjustable resistors include the first resistor R1 to the eighth resistor R8, and the target capacitors include the first capacitor C1 to the eighth capacitor C8. Specifically, the first RC filter circuit includes the first resistor R1 and the first capacitor C1, the second RC filter circuit includes the second resistor R2 and the second capacitor C2, and so on.

[0071] The emitted laser signal LaserSignal is converted into an inverted signal LaserSignal_R after passing through the inverting buffer U1. The inverted signal LaserSignal_R is then delayed by the first RC filter circuit before being input to the first input pin 1A1 of the first non-inverting buffer U2A. The output of the first output pin 1Y1 of the first non-inverting buffer U2A serves as the first hold signal HoldSignal1, which lags slightly behind the inverted signal LaserSignal_R. Next, the first hold signal HoldSignal1 passes through the second RC filter circuit and then the first non-inverting buffer U2A outputs the second hold signal HoldSignal2. This process generates a total of eight hold signals HoldSignal1-8, with each non-inverting buffer outputting four hold signals.

[0072] In the above scheme, the two adjacent input and output units of the non-inverting circuit are connected to corresponding RC filter circuits. The signal delay is achieved by the RC filter circuit, which can change the time delay of each holding signal, thereby obtaining multiple holding signals with different delays.

[0073] In some embodiments, the sample-and-hold circuit 103 includes a plurality of sample-and-hold chips. The input pin of any sample-and-hold chip is connected to the output terminal of the optical signal monitoring circuit 101, the output pin of any sample-and-hold chip is connected to the control module 104, and the control pin of each sample-and-hold chip is connected to different output terminals of the signal generation circuit 102.

[0074] Furthermore, the preset hold signal is the hold signal with the largest trigger edge delay. The control module 104 includes input / output pins and multiple sampling pins. The input / output pins are connected to the output pins of the sample-and-hold chip that outputs the preset hold signal, and each sampling pin is connected to the output pin of its corresponding sample-and-hold chip. After detecting the trigger edge of the preset hold signal, the module starts sampling each voltage signal to be sampled sequentially, ensuring that all sample-and-hold chips have completed amplitude locking, avoiding invalid sampled values ​​due to premature sampling, and ensuring the orderliness of sampling.

[0075] Specifically, the function of the sample-and-hold chip is to cut off the switch to hold the signal at the sampling terminal for the ADC sampling module to read when triggered by an external signal. For example, the sample-and-hold chip can be the AD783 chip.

[0076] The number of sample-and-hold chips is the same as the number of hold signals. In one example, the number of hold signals is 8. See also Figure 4 The voltage signal PD_POW generated by the optical signal monitoring circuit 101 is input to eight sample-and-hold chips U3-U10. When the hold signal HoldSignal is high, the output of the sample-and-hold chip follows the voltage of the voltage signal PD_POW in real time. When the hold signal HoldSignal is low, the output holds the voltage before the switching, which is then sampled by the ADC sampling module. Since the eight hold signals HoldSignal1-HoldSignal8 are sequentially delayed by the output optical signal LaserSignal, the output of the sample-and-hold chip can hold the voltage signal PD_POW for a period of time.

[0077] The 8th hold signal HoldSignal8 is connected to the input / output pin of the control module 104. The control module 104 uses a falling edge trigger. After triggering, it sequentially samples the output signals PD_POW_H1 to PD_POW_H8 of the sample-and-hold chips U3-U10 to obtain the sampled values ​​of each voltage signal to be sampled, thereby obtaining data that can form the size of an optical pulse.

[0078] In the above scheme, each hold signal corresponds to a sample-and-hold chip, which can synchronously sample and lock the amplitude of the voltage signal to be monitored at different trigger edges, ensuring that the multiple voltage signals to be sampled are true reflections of the actual amplitude of the optical pulse, without sampling deviation.

[0079] In some embodiments, the optical signal monitoring circuit 101 includes a photoelectric conversion circuit and a voltage amplification circuit.

[0080] The photoelectric conversion circuit is used to generate an initial voltage signal based on the pulse to be monitored emitted from the pulsed laser.

[0081] The voltage amplifier circuit and the photoelectric conversion circuit are connected to amplify the initial voltage signal to obtain the voltage signal to be monitored.

[0082] Specifically, the photoelectric conversion circuit includes a photoelectric sensor PD1, a transimpedance amplifier circuit, and a digital potentiometer U14. The positive terminal of the photoelectric sensor PD1 is grounded, the negative terminal of the photoelectric sensor PD1 is connected to the negative input terminal of the transimpedance amplifier circuit, the positive input terminal of the transimpedance amplifier circuit is connected to the output terminal of the reference power supply circuit, the output terminal of the transimpedance amplifier circuit is connected to the high-side fixed terminal of the digital potentiometer U14, and the vernier terminal of the digital potentiometer U14 is connected to the voltage amplifier circuit.

[0083] like Figure 5 As shown, the photoelectric sensor PD1 is a current-type photoelectric sensor that can convert light signals into current signals. The transimpedance amplifier circuit includes a first operational amplifier U11A, an eleventh resistor R11, a fifteenth resistor R15, and a tenth capacitor C10. The digital potentiometer U14 is an IPL0501-100DCNR. The control module 104 can control the voltage division by controlling the resistance value of the digital potentiometer U14, achieving a software-adjustable voltage amplification factor and making debugging and calibration more convenient.

[0084] Reference power supply circuit such as Figure 6 As shown, the circuit includes the second operational amplifier U13A, the thirteenth resistor, the fourteenth resistor, and the eleventh capacitor C11. Using a 3.3V power supply, a voltage divider is applied, and after passing through a voltage follower circuit to enhance the driving capability, a stable reference power supply is provided to the entire optical signal monitoring circuit 101. The formula for calculating the reference voltage VRef output by the reference power supply is:

[0085]

[0086] The formula for calculating the initial voltage signal PD_Volt output by the photoelectric conversion circuit is:

[0087]

[0088] Where I is the magnitude of the current sensed by the photoelectric sensor PD1 based on the pulse to be monitored, and K is the vernier position (1-256) set by the digital potentiometer U14.

[0089] According to the above scheme, the voltage signal to be monitored can be obtained by converting the pulse to be monitored through the photoelectric conversion circuit and the voltage amplification circuit, which is convenient for subsequent sampling. The photoelectric sensor PD1 is used in conjunction with the transimpedance amplification circuit to directly convert the photocurrent signal of the photoelectric sensor PD1 into a voltage signal. The digital potentiometer U14 is connected to the output terminal of the transimpedance amplification circuit, and the output gain of the photoelectric conversion circuit can be precisely adjusted by digitally adjusting the vernier position of the potentiometer.

[0090] In some embodiments, the voltage amplifier circuit includes a voltage amplifier circuit and a differential circuit. The negative input terminal of the voltage amplifier circuit is connected to the output terminal of the reference power supply circuit, the positive input terminal of the voltage amplifier circuit is connected to the vernier terminal of the digital potentiometer U14, the output terminal of the voltage amplifier circuit is connected to the positive input terminal of the differential circuit, the negative input terminal of the differential circuit is connected to the output terminal of the reference power supply circuit, and the output terminal of the differential circuit is connected to the sample and hold circuit 103.

[0091] Specifically, such as Figure 7 As shown, the voltage amplifier circuit includes a third operational amplifier U12, a ninth resistor R9, a tenth resistor R10, and a twelfth resistor R12. The output of the reference power supply circuit is connected to the negative input of the third operational amplifier U12 through the tenth resistor R10 to receive the reference voltage VRef. The vernier terminal of the digital potentiometer U14 is connected to the positive input of the third operational amplifier U12 through the ninth resistor R9 to receive the initial voltage signal PD_Volt. The negative input of the third operational amplifier U12 is connected to the output of the third operational amplifier U12 through the twelfth resistor R12. The output of the third operational amplifier U12 outputs an intermediate voltage Uout, the calculation formula of which is:

[0092]

[0093] From the above reasoning, it can be seen that the voltage amplifier circuit only... The reference voltage VRef is not amplified; since the reference voltage VRef is the base, only the effective signal is amplified, and the base is not amplified.

[0094] The differential circuit includes a fourth operational amplifier U13B, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, and a nineteenth resistor R19. The positive input terminal of the fourth operational amplifier U13B is connected to the output terminal of the third operational amplifier U12 through the sixteenth resistor R16, and grounded through the eighteenth resistor R18. The negative input terminal of the fourth operational amplifier U13B is connected to the output terminal of the reference power supply circuit through the seventeenth resistor R17, and connected to the output terminal of the fourth operational amplifier U13B through the nineteenth resistor R19. The output terminal of the fourth operational amplifier U13B outputs the voltage signal PD_POW to be monitored. According to the operational amplifier principle, we have:

[0095]

[0096] According to the design, R16=R17=R18, therefore:

[0097]

[0098] The reference voltage VRef can be removed using a differential circuit. Substituting this into the formula for PD_Volt, we get:

[0099]

[0100] Substituting the design values ​​R12=100K and R10=10K, we finally obtain:

[0101]

[0102] The photoelectric sensor PD1 senses the magnitude of the current based on the pulse to be monitored. At the μA level, by adjusting the vernier position set by the digital potentiometer U14, a voltage signal within 2V to be monitored can be obtained.

[0103] In the above scheme, the output voltage can be further amplified by the voltage amplifier circuit and the differential circuit, and the reference voltage in the output voltage can be filtered out.

[0104] This invention also provides a method for monitoring laser pulse intensity, applied to the laser pulse intensity control module 104 as described in any of the above embodiments of this invention, such as... Figure 8 As shown, the method includes:

[0105] Step S801: Monitor whether the preset hold signal generates a trigger edge. If the preset hold signal generates a trigger edge, sample each voltage signal to be sampled in sequence according to the preset order.

[0106] Step S802: Obtain the shape of the pulse to be monitored based on the sampled values ​​of each voltage signal to be sampled and the pre-set interval between the trigger edges of each hold signal.

[0107] The preset hold signal can be set according to the situation. Generally, the preset hold signal is the hold signal with the longest trigger edge delay. For example, if there are 1 to 8 hold signals sorted according to the trigger edge generation time, then the 8th hold signal is used as the preset hold signal.

[0108] The interval between the trigger edges of each hold signal is obtained by setting the adjustable resistor in the RC filter circuit.

[0109] Since the voltage signal to be sampled can maintain the signal of the voltage signal to be monitored at each trigger edge, even if the sampling frequency of the control module 104 is low and the sampling interval is greater than the pulse width, it can still acquire the value of the voltage signal to be sampled, thereby obtaining the shape of the optical pulse to be monitored.

[0110] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A monitoring circuit for laser pulse intensity, characterized in that, include: An optical signal monitoring circuit is used to generate a voltage signal to be monitored based on the pulse emitted by a pulsed laser. The signal generation circuit is used to generate multiple hold signals whose trigger edges are sequentially delayed by the output light signal of the control pulse laser, based on the output light signal of the pulse laser. The interval between the trigger edges of two adjacent hold signals is less than the width of the pulse to be monitored. The sample-and-hold circuit is connected to both the optical signal monitoring circuit and the signal generation circuit, and is used to output multiple sampled voltage signals corresponding to the holding signals according to the voltage signal to be monitored and multiple holding signals, wherein the sampled voltage signal is a voltage signal that holds the amplitude of the voltage signal to be monitored at the trigger edge of the corresponding holding signal; The control module, connected to the sample-and-hold circuit, is used to sequentially sample the voltage signals to be sampled corresponding to each of the preset holding signals after detecting the trigger edge of the holding signal; The signal generation circuit includes an inverting circuit, multiple RC filter circuits, and a non-inverting circuit. The non-inverting circuit includes multiple input / output units, each of which includes an input terminal and an output terminal. The output terminal of the emitted light signal is connected to the input terminal of the inverting circuit. The output terminal of the inverting circuit is connected to the input terminal of one of the input / output units through one of the RC filter circuits. The output terminal of each input / output unit is connected to the input terminal of the adjacent input / output unit through the corresponding RC filter circuit. The output terminal of any input / output unit is connected to the sample-and-hold circuit.

2. The laser pulse intensity monitoring circuit according to claim 1, characterized in that, The RC filter circuit includes an adjustable resistor and a target capacitor. The first end of the adjustable resistor is connected to the output terminal of the inverting circuit or the output terminal of the non-inverting circuit. The second end of the adjustable resistor is connected to both the first end of the target capacitor and the input terminal of the non-inverting circuit. The second end of the target capacitor is grounded.

3. The laser pulse intensity monitoring circuit according to claim 2, characterized in that, The non-inverting circuit includes at least one non-inverting buffer, the input terminal of which is the input terminal of the non-inverting circuit, and the output terminal of which is the output terminal of the non-inverting circuit.

4. The laser pulse intensity monitoring circuit according to claim 1, characterized in that, The sample-and-hold circuit includes multiple sample-and-hold chips. The input pin of any sample-and-hold chip is connected to the output terminal of the optical signal monitoring circuit, the output pin of any sample-and-hold chip is connected to the control module, and the control pin of each sample-and-hold chip is connected to different output terminals of the signal generation circuit.

5. The laser pulse intensity monitoring circuit according to claim 4, characterized in that, The preset hold signal is the hold signal with the largest trigger edge delay. The control module includes input / output pins and multiple sampling pins. The input / output pins are connected to the output pins of the sample-and-hold chip that outputs the preset hold signal. Each sampling pin is connected to the corresponding output pin of the sample-and-hold chip.

6. The laser pulse intensity monitoring circuit according to claim 1, characterized in that, The optical signal monitoring circuit includes: A photoelectric conversion circuit is used to generate an initial voltage signal based on the pulse to be monitored emitted from a pulsed laser. A voltage amplifier circuit, connected to the photoelectric conversion circuit, is used to amplify the initial voltage signal to obtain the voltage signal to be monitored.

7. The laser pulse intensity monitoring circuit according to claim 6, characterized in that, The photoelectric conversion circuit includes a photoelectric sensor, a transimpedance amplifier circuit, and a digital potentiometer. The positive terminal of the photoelectric sensor is grounded, the negative terminal of the photoelectric sensor is connected to the negative input terminal of the transimpedance amplifier circuit, the positive input terminal of the transimpedance amplifier circuit is connected to the output terminal of the reference power supply circuit, the output terminal of the transimpedance amplifier circuit is connected to the high-side fixed terminal of the digital potentiometer, and the vernier terminal of the digital potentiometer is connected to the voltage amplifier circuit.

8. The laser pulse intensity monitoring circuit according to claim 7, characterized in that, The voltage amplifier circuit includes a voltage amplifier circuit and a differential circuit. The negative input terminal of the voltage amplifier circuit is connected to the output terminal of the reference power supply circuit, the positive input terminal of the voltage amplifier circuit is connected to the vernier terminal of the digital potentiometer, the output terminal of the voltage amplifier circuit is connected to the positive input terminal of the differential circuit, the negative input terminal of the differential circuit is connected to the output terminal of the reference power supply circuit, and the output terminal of the differential circuit is connected to the sample-and-hold circuit.

9. A method for monitoring laser pulse intensity, characterized in that, The laser pulse intensity control module as described in any one of claims 1 to 8 comprises: Monitor whether the preset hold signal generates a trigger edge. If the preset hold signal generates a trigger edge, sample each voltage signal to be sampled in sequence according to the preset order. The shape of the pulse to be monitored is obtained based on the sampled values ​​of the voltage signals to be sampled in each channel and the pre-set interval between the trigger edges of the hold signals in each channel.

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