Physical simulation platform building method based on RISC-V high-throughput chip

Abstract

The invention relates to the technical field of physical platform building, and discloses a physical simulation platform building method based on an RISC-V high-throughput chip, which comprises the following steps: building a basic framework: carrying out standardization processing on simulation assets and a hardware calling interface, optimizing a display card, building a visual asset system library, and establishing a virtual asset system library; developing a task scheduler for executing intelligent task classification and dynamic resource allocation; wherein after the basic framework is constructed, a minimum test scene such as walking of a simulation robot is constructed, and the core function of the basic framework is verified. Through efficient computing power utilization, flexible and lightweight deployment, convenient development and expansion and real-time high-precision simulation, the performance and application scene of physical simulation are comprehensively improved, zero-loss packaging and hybrid task dynamic scheduling are adopted, optimization is combined with a special acceleration unit, and the performance of physical simulation is improved. The multi-core parallelism and vector expansion capability of the RISC-V high-throughput chip is fully exerted, the computing power utilization rate is improved, and the computing power waste is avoided.

Description

Technical Field

[0001] This invention relates to the field of physical platform construction technology, and more specifically, to a method for constructing a physical simulation platform based on a RISC-V high-throughput chip. Background Technology

[0002] A physics simulation platform is a software environment that integrates advanced computing technologies and physical models to simulate and predict real-world physical phenomena. It uses numerical calculations and algorithms to realistically reproduce the motion, collisions, and fluid dynamics of objects, and is widely used in engineering design, robotics development, game development, virtual reality, and other fields. This platform typically features efficient computing power utilization, flexible deployment options, user-friendly development interfaces, and real-time simulation capabilities, helping users quickly verify and optimize design solutions, and improve product performance and accuracy. Through physics simulation, users can conduct extensive experiments in a safe and low-cost environment, reducing the risks and expenses that may be encountered in actual development processes.

[0003] However, traditional physics simulation platforms mostly adopt x86 / GPU architecture solutions, which suffer from excessive power consumption and are difficult to adapt to the lightweight deployment requirements of edge computing. With the increasing demand for real-time edge simulation in fields such as autonomous driving and robotics, low-power, high-efficiency deployment solutions have become an urgent industry need. Secondly, the uneven distribution of computing power in a single hardware architecture cannot efficiently support the parallel processing of multiple mixed tasks such as physics calculation, AI inference, and rendering, resulting in serious waste of hardware resources and low simulation efficiency. In addition, the complex underlying interface calls of the chip require developers to have a deep understanding of the hardware details to implement resource calls, which not only raises the development threshold but also leads to low hardware resource utilization. Finally, the difficulty in sharing simulation assets between different business modules and the poor compatibility of multi-physics engine integration greatly limits the scalability and practicality of the simulation platform, making it difficult to quickly adapt to the needs of different business scenarios. Summary of the Invention

[0004] To overcome the above-mentioned deficiencies of the prior art, embodiments of the present invention provide a method for building a physical simulation platform based on a RISC-V high-throughput chip.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for building a physical simulation platform based on a RISC-V high-throughput chip, the method comprising:

[0007] S101. Basic framework construction: Standardize the simulation assets and hardware call interfaces and optimize the graphics cards; build a visual asset system library; and develop a task scheduler for performing intelligent task classification and dynamic resource allocation.

[0008] After the basic framework is built, a minimized test scenario simulating robot walking is constructed to verify the core functions of the basic framework.

[0009] S102, Physics Engine Integration: A unified abstract interface enables multi-engine compatibility, task splitting is based on the task scheduler to obtain multiple sub-tasks that are executed in parallel, and memory bandwidth is optimized through data compression and on-demand transmission strategies.

[0010] S103, Upper-layer application development: Develop a dynamic task scheduling center based on RISC-V high-throughput chip and build a high-speed data channel;

[0011] Scenario-based functional module development: Visualize the user interface, provide rich simulation parameter configuration functions, and export simulation results;

[0012] S104, Performance Optimization and Ecosystem Development: The dedicated acceleration unit based on the RISC-V high-throughput chip performs instruction-level optimization on the core computing modules of physical simulation, deepens the hardware call interface in the basic framework, and improves the compatibility of multi-dimensional software and asset formats.

[0013] Furthermore, the specific steps for building the visualized asset system library are as follows:

[0014] The visual asset system library integrates three core functions: asset version control, keyword search, and multi-user collaborative editing.

[0015] The asset version control function allows for the tracing and rollback of asset modification records, while the keyword search and user collaborative editing functions facilitate asset retrieval and team collaborative development.

[0016] Establish a unified asset indexing mechanism to allocate and label each type of asset, thereby obtaining a corresponding unique index identifier.

[0017] Furthermore, the specific steps for developing a task scheduler for performing intelligent task classification and dynamic resource allocation are as follows:

[0018] Obtain task samples, extract computational features from the task samples and perform feature standardization to obtain feature matrix and hard constraints. The computational features include floating-point operation density, memory access mode and parallelization degree.

[0019] Task identification and computing power requirement assessment training are performed based on feature matrices and hard constraints. A dynamic priority algorithm is adopted to adjust task priorities in combination with business requirements.

[0020] The priority calculation formula is as follows:

[0021]

[0022] In the formula: w1 and w2 are the weighting coefficients of business criticality and resource sensitivity, Criticism is the task criticality level, and T deadline For the remaining deadline, Resource demand Indicates the current task resource requirements, Resource available This represents the percentage of available system resources.

[0023] Furthermore, the task splitting based on the task scheduler yields multiple subtasks that can be executed in parallel, including:

[0024] First, calculate the utilization rate of a single module:

[0025]

[0026] In the formula: T active,j For the active time of the j-th task, T total C represents the total observation time, and C represents the number of cores.

[0027] Based on module utilization, task feature analysis and feasibility assessment of task splitting are performed. Splitting constraints are defined to obtain a list of splittable tasks. The splitting mode is selected by combining the RISC-V architecture parameters and task types, and the subtask granularity is optimized to obtain multiple subtasks that can be executed in parallel. These multiple subtasks are then distributed to the RISC-V multi-core architecture.

[0028] Furthermore, the step of combining RISC-V architecture parameters and task type to select the splitting mode and optimize the subtask granularity includes:

[0029] The task types include data-parallel tasks and task-parallel tasks, and the splitting modes include data sharding mode and functional decomposition mode.

[0030] The formula for calculating the granularity of optimized subtasks is as follows:

[0031]

[0032] In the formula: G is the number of subtasks, T comp Calculate the time for a single task, T sync This indicates the synchronization overhead.

[0033] Furthermore, the specific steps for allocating multiple parallel-executed subtasks to the RISC-V multi-core architecture are as follows:

[0034] For the data sharding tasks split by the data sharding mode, a round-robin allocation strategy is adopted to obtain the core number from the RISC-V high-throughput chip and allocate the tasks in a loop according to the core number order.

[0035] For the functional decomposition tasks split by the aforementioned functional decomposition mode, the Min-Min algorithm is adopted to calculate the expected completion time of each subtask on each core based on the subtask resource requirements and core performance parameters. The expected completion times are sorted from largest to smallest, and the tasks are allocated according to the sorted expected completion times.

[0036] Furthermore, the adoption of the Min-Min algorithm specifically includes:

[0037]

[0038] Where: Communication overhead i,j It is based on the inter-core bandwidth estimation.

[0039] Furthermore, the process of optimizing video memory bandwidth through data compression and on-demand transmission strategies is as follows:

[0040] Calculate bandwidth utilization:

[0041]

[0042] In the formula: S i B represents the size of the data transmitted in the i-th transmission. max This is the upper limit of video memory bandwidth;

[0043] Based on bandwidth utilization, a list of high bandwidth-occupied data blocks is obtained. The data types in the list of high bandwidth-occupied data blocks are then selected. A compression algorithm is selected based on the data type, and the optimal compression ratio is calculated for compression.

[0044] An electronic device includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the above-described method for building a physical simulation platform based on a RISC-V high-throughput chip.

[0045] A computer-readable storage medium storing a computer program, which, when executed, implements the aforementioned method for building a physical simulation platform based on a RISC-V high-throughput chip.

[0046] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0047] This application discloses a method for building a physics simulation platform based on a RISC-V high-throughput chip. This invention comprehensively improves the performance and application scenarios of physics simulation through efficient computing power utilization, flexible and lightweight deployment, convenient development and expansion, and real-time high-precision simulation. It employs zero-loss packaging and dynamic scheduling of hybrid tasks, combined with dedicated acceleration unit optimization, to fully leverage the multi-core parallelism and vector expansion capabilities of the RISC-V high-throughput chip, improving computing power utilization and avoiding waste. Based on the low-power characteristics of the RISC-V chip, the support for modular expansion of computing power allows users to configure hardware resources on demand according to the specific simulation scale, further reducing deployment costs. In addition, a unified physics engine API and hardware call interface, combined with comprehensive ecosystem compatibility, significantly reduces the development threshold and secondary expansion costs of the simulation platform, supporting rapid adaptation to multiple business scenarios. Finally, by optimizing end-to-end data transmission, memory loading strategies, and task splitting algorithms, low-latency simulation of large-scale scenarios is achieved while ensuring simulation accuracy. Attached Figure Description

[0048] Figure 1 A flowchart illustrating a method for building a physical simulation platform based on a RISC-V high-throughput chip, provided by this invention;

[0049] Figure 2 A schematic diagram of the structure of an electronic device provided by the present invention;

[0050] Figure 3 A schematic diagram of the structure of a computer-readable storage medium provided by the present invention;

[0051] Figure 4 The flowchart illustrates the task scheduling and splitting process in a method for building a physical simulation platform based on a RISC-V high-throughput chip, as provided in this invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Example 1

[0054] Please see Figure 1 and Figure 4 As shown in the figure, this embodiment discloses a method for building a physical simulation platform based on a RISC-V high-throughput chip, the method including:

[0055] S101. Basic framework construction: Standardize the simulation assets and hardware call interfaces and optimize the graphics cards; build a visual asset system library; and develop a task scheduler for performing intelligent task classification and dynamic resource allocation.

[0056] The standardization and optimization of simulation assets and hardware interfaces aim to achieve the import, parsing, and standardized storage of various simulation assets such as 3D models, materials, animations, and lighting, ensuring that simulation assets from different sources can be formatted uniformly. Leveraging the memory characteristics of RISC-V high-throughput chips (such as the DFU3500), a scene data loading strategy with block loading and pre-allocated memory cache is designed. Large-scale scene data is split into multiple data blocks for step-by-step loading, while memory cache space is pre-allocated for frequently accessed data, effectively reducing memory usage pressure and improving scene loading speed.

[0057] The specific process is as follows: Based on OpenUSD version 23.11, an asset import and parsing module was developed, supporting the import of 3D assets in USD, FBX, and OBJ formats, and defining a standardized storage structure through the USD Schema. Taking advantage of the 256GB of video memory in the DFU3500 chip, a scene data block loading strategy of 1GB per block was designed, with 20GB of video memory cache pre-allocated for storing frequently accessed scene materials and animation data. Testing showed that this strategy can reduce the loading time of a 10GB intelligent driving simulation scene from 120s to 45s, and reduce video memory usage by 35%.

[0058] Meanwhile, a software development kit based on the RISC-V high-throughput chip encapsulates the chip's general-purpose computing units, dedicated acceleration units, cache, and video memory access interfaces. A zero-loss calling architecture is designed, abstracting away the chip's underlying hardware details to form a standardized hardware calling interface. Upper-layer applications can efficiently call hardware resources through this interface without needing to deeply understand the chip's hardware architecture and working principles, reducing development difficulty while improving resource access efficiency.

[0059] Based on the DFU3500 chip SDK, this architecture uses C++17 to encapsulate the access interfaces for general-purpose computing units, Tensor Cores, cache, and video memory. It employs an architecture that separates the abstract interface layer from the concrete implementation layer. The abstract layer provides standardized calling functions, while the concrete implementation layer adapts to the DFU3500 hardware details. Upper-layer applications can access hardware resources by calling functions in the abstract layer, with interface call latency controlled within 1μs.

[0060] After the basic framework is built, a minimized test scenario simulating robot walking is constructed to verify the core functions of the basic framework.

[0061] Furthermore, the verification process includes setting up minimal test scenarios such as simulating robot walking to verify the core functions of the basic framework. The focus is on verifying the stability of OpenUSD scenario loading, the effectiveness of hardware interface calls, and the feasibility of basic physics solutions. Various data during scenario operation are collected through log analysis tools, including data link transmission latency, computing power allocation, and GPU memory usage. Problems such as excessive data transmission latency, uneven computing power allocation, and GPU memory overflow are investigated and resolved to continuously optimize the stability and reliability of the basic framework.

[0062] The specific steps are as follows: Build two minimal test scenarios for robot walking, import the robot models in USD format, and set the gravitational acceleration to 9.8 m / s². 2 The ground friction coefficient is 0.6. The system operates in a scenario and collects log data. Log analysis tools revealed a peak data link transmission latency of 8ms. By optimizing the data transmission channel, the peak latency was reduced to 2ms, ensuring the stable operation of the basic framework.

[0063] As a specific implementation method, the specific steps for building the visual asset system library are as follows:

[0064] The visual asset system library integrates three core functions: asset version control, keyword search, and multi-user collaborative editing.

[0065] The asset version control function allows for the tracing and rollback of asset modification records, while the keyword search and user collaborative editing functions facilitate asset retrieval and team collaborative development.

[0066] Establish a unified asset indexing mechanism to allocate and mark each type of asset, obtaining a corresponding unique index identifier, so as to realize the rapid sharing and access of assets between different business modules and solve the problems of low asset sharing efficiency and chaotic version management in traditional platforms.

[0067] In this embodiment, Vue.js is used to develop the front-end interface of the visual asset library, while the back-end is based on the Spring Boot framework to implement asset version control, keyword search, and multi-user collaborative editing functions. An asset index database based on MySQL is established, assigning a unique index identifier containing the asset type, version number, and creation time to each asset category. Tests show that the asset conflict rate is less than 5% during multi-user collaborative editing, and the keyword search response time is less than 0.5 seconds.

[0068] For example, the specific steps for developing a task scheduler for performing intelligent task classification and dynamic resource allocation are as follows:

[0069] A task scheduler was developed using C++, with a built-in LSTM computing power demand assessment model. The model was trained using historical task data to achieve accurate prediction of task computing power demand.

[0070] Obtain task samples, extract computational features from the task samples and perform feature standardization to obtain feature matrix and hard constraints. The computational features include floating-point operation density, memory access mode and parallelization degree.

[0071] Task identification and computing power requirement assessment training are performed based on feature matrices and hard constraints. A dynamic priority algorithm is adopted to adjust task priorities in combination with business requirements.

[0072] The priority calculation formula is as follows:

[0073]

[0074] In the formula: w1 and w2 are the weighting coefficients of business criticality and resource sensitivity, Criticism is the task criticality level, and T deadline For the remaining deadline, Resource demand Indicates the current task resource requirements, Resource available This represents the percentage of available system resources.

[0075] S102, Physics Engine Integration: A unified abstract interface enables multi-engine compatibility, task splitting is based on the task scheduler to obtain multiple sub-tasks that are executed in parallel, and memory bandwidth is optimized through data compression and on-demand transmission strategies.

[0076] The unified abstract interface ensures multi-engine compatibility by pooling mainstream open-source physics solvers such as MuJoCo and Newton, and deeply analyzing the differences in computational characteristics, calling interfaces, and applicable scenarios of each engine. Based on the analysis results, a unified physics computation API layer was designed, encapsulating core functions such as engine initialization, parameter configuration, solution calculation, and result output. This API layer provides standardized calling interfaces for upper-layer applications, using a unified calling method regardless of the physics engine being called, significantly reducing the cost of switching between multiple engines and improving development efficiency.

[0077] As a specific implementation method, the MuJoCo 2.3.7 and Newton 3.14 physics engines are integrated to develop a unified physics calculation API layer. The API layer encapsulates core functions such as the engine initialization function `InitEngine()`, the parameter configuration function `SetParams()`, and the solution calculation function `Solve()`, and uses a function pointer mechanism to achieve dynamic switching between different engines. Tests show that the engine switching time is less than 10ms, and upper-layer applications can implement engine switching without modifying their code.

[0078] For example, the task splitting based on the task scheduler to obtain multiple subtasks that can be executed in parallel includes:

[0079] First, calculate the utilization rate of a single module:

[0080]

[0081] In the formula: T active,j For the active time of the j-th task, T total C represents the total observation time, and C represents the number of cores.

[0082] Based on module utilization, task feature analysis and feasibility assessment of task splitting are performed. Splitting constraints are defined to obtain a list of splittable tasks. The splitting mode is selected by combining the RISC-V architecture parameters and task types, and the subtask granularity is optimized to obtain multiple subtasks that can be executed in parallel. These multiple subtasks are then distributed to the RISC-V multi-core architecture.

[0083] The method of selecting a splitting mode based on RISC-V architecture parameters and task type, and optimizing the granularity of subtasks, includes:

[0084] The task types include data-parallel tasks and task-parallel tasks, and the splitting modes include data sharding mode and functional decomposition mode.

[0085] The formula for calculating the granularity of optimized subtasks is as follows:

[0086]

[0087] In the formula: G is the number of subtasks, T comp Calculate the time for a single task, T sync This represents synchronization overhead. The specific steps for allocating multiple parallel-executed subtasks to the RISC-V multi-core architecture are as follows:

[0088] For the data sharding tasks split by the data sharding mode, a round-robin allocation strategy is adopted to obtain the core number from the RISC-V high-throughput chip and allocate the tasks in a loop according to the core number order.

[0089] For the functional decomposition tasks split by the aforementioned functional decomposition mode, the Min-Min algorithm is adopted to calculate the expected completion time of each subtask on each core based on the subtask resource requirements and core performance parameters. The expected completion times are sorted from largest to smallest, and the tasks are allocated according to the sorted expected completion times.

[0090] The adoption of the Min-Min algorithm specifically includes:

[0091]

[0092] Where: Communication overhead i,j It is based on the inter-core bandwidth estimation.

[0093] The process of optimizing video memory bandwidth through data compression and on-demand transmission strategies is as follows:

[0094] Calculate bandwidth utilization:

[0095]

[0096] In the formula: S i B represents the size of the data transmitted in the i-th transmission. max This is the upper limit of video memory bandwidth;

[0097] Based on bandwidth utilization, a list of high-bandwidth-occupying data blocks is obtained. The data types within this list are then identified, and a compression algorithm is selected based on the data type. The optimal compression ratio is calculated and applied. The formula for calculating the optimal compression ratio is:

[0098]

[0099] In the formula: S original R is the original data size, R is the compression ratio, and T is the compression ratio. trans T is the transmission time per unit bandwidth. compress To compress time.

[0100] In this embodiment, the LZ4 compression algorithm is used to compress the transmitted data, achieving a compression ratio of 4:1. An on-demand transmission strategy is adopted, transmitting only the object motion data required for the current solution step, reducing invalid data transmission. After optimization, the video memory bandwidth utilization rate is reduced from 92% to 65%, and the computational lag is completely eliminated.

[0101] S103, Upper-layer application development: Develop a dynamic task scheduling center based on RISC-V high-throughput chip and build a high-speed data channel;

[0102] Scenario-based functional module development: Visualize the user interface, provide rich simulation parameter configuration functions, and export simulation results;

[0103] Among these initiatives, the development of a dynamic task scheduling center based on RISC-V high-throughput chips involves using real-time computing power monitoring data from these chips to create the dynamic task scheduling center. This center can collect data such as chip computing power utilization and memory usage in real time, and accurately determine the current computing power load status through a computing power resource assessment model. Based on the load status, the priority of physics calculations, AI inference, and rendering tasks is dynamically adjusted to ensure that core simulation tasks (such as collision detection and robot motion control in intelligent driving scenarios) receive sufficient computing power support, guaranteeing the real-time performance and reliability of the simulation.

[0104] This involves using Prometheus to monitor the real-time computing power of the DFU3500 chip, collecting data such as computing power utilization and memory usage at a frequency of 100Hz. A Python-based computing resource assessment model was developed to determine the computing load status in real time. When the computing power utilization exceeds 90%, the priority of core simulation tasks is automatically increased. Tests show that the response latency of core tasks is controlled within 5ms.

[0105] For example, by optimizing the data transmission mechanism between the scene base, physics engine, and hardware acceleration layer, advanced technologies such as shared memory and direct memory access are adopted. Shared memory enables direct data access between multiple modules, reducing the number of data copies; DMA technology enables direct data transfer between memory and hardware devices without CPU intervention, further reducing data transmission latency and ensuring smooth data flow in large-scale simulation scenarios (such as multi-robot collaborative simulation and intelligent driving simulation in complex road conditions). This avoids data transmission bottlenecks affecting simulation efficiency, thus building a high-speed data channel.

[0106] In this embodiment, shared memory technology is used to achieve data sharing between the scene base, physics engine, and hardware acceleration layer, with the shared memory size set to 16GB. Direct data transmission is achieved through the DMA controller of the DFU3500 chip. After optimization, the cross-module data transmission latency is reduced from 15ms to 3ms, resulting in smooth data transmission in multi-robot collaborative simulation scenarios.

[0107] Meanwhile, the user interface is visualized, supporting visual editing of simulation scenes, including adding scene elements, adjusting layouts, and setting parameters. It also provides real-time status monitoring of the simulation process, intuitively displaying simulation progress, computing power usage, and data transmission status, allowing developers to monitor the simulation dynamics in real time. The visual interface is developed using Qt 6, supporting drag-and-drop addition of scene elements, terrain editing, and lighting adjustment. It displays simulation progress, computing power utilization, and data transmission rate in real time, with a refresh rate of 30fps.

[0108] It offers rich simulation parameter configuration functions, including physical property parameters (such as friction coefficient, gravity parameter, elastic coefficient), scene scale parameters (such as the number of objects in the scene, terrain complexity), simulation step size parameters, etc. It supports flexible adjustment and saving of parameters, making it convenient to conduct simulation experiments under different conditions.

[0109] Finally, the exported simulation results support real-time analysis of simulation data, including physical motion trajectory analysis, collision detection result analysis, and performance index evaluation. It provides data visualization capabilities, presenting analysis results intuitively through charts, curves, and other formats. It supports exporting simulation data in standardized formats such as CSV and JSON, facilitating subsequent data mining, model validation, and results archiving. It uses Matplotlib for simulation data visualization, supporting the display of motion trajectory curves, collision detection heatmaps, and more. It supports exporting data in CSV and JSON formats, with a 1GB simulation data export time of less than 10 seconds.

[0110] S104, Performance Optimization and Ecosystem Development: The dedicated acceleration unit based on the RISC-V high-throughput chip performs instruction-level optimization on the core computing modules of physical simulation, deepens the hardware call interface in the basic framework, and improves the compatibility of multi-dimensional software and asset formats.

[0111] As a specific implementation method, a dedicated acceleration unit based on a RISC-V high-throughput chip performs instruction-level optimization on the core computing module of physical simulation. The specific steps are as follows: adopting the RISC-V vector extension instruction set, designing customized instructions for parallel computing tasks, significantly improving the parallel processing capability of the core computing module, maximizing the chip's dedicated computing power advantage, and further improving simulation efficiency and real-time performance.

[0112] The hardware interface in the basic framework has been improved, including adapting to different specifications of RISC-V high-throughput chips, designing standardized hardware interface specifications, and supporting the expansion of computing power boards through PCIe cascading interfaces. Users can flexibly increase the number of computing power boards according to the needs of the simulation scale, realize on-demand expansion of the simulation platform's computing power, and improve the platform's hardware adaptability flexibility.

[0113] In this embodiment, two RISC-V high-throughput chips, DFU3500 and DFU4000, are adapted. Two DFU3500 computing power boards are cascaded through the PCIe 4.0 interface, increasing the computing power from 200 TOPS to 400 TOPS and expanding the simulation scale from 100 objects to 200 objects.

[0114] Meanwhile, it is deeply compatible with open-source algorithm libraries such as PCL (point cloud library), Open3D (3D data processing library), and OpenCV (computer vision library), enabling direct access to algorithm resources; it supports rapid integration with mainstream AI frameworks such as PyTorch and TensorFlow, facilitating AI-based simulation tasks (such as agent training and scene recognition); and it is compatible with industrial-grade simulation and development frameworks such as ROS2 (robot operating system) and Autoware (open-source framework for intelligent driving), ensuring seamless integration with existing industrial-grade toolchains and reducing the cost of algorithm porting and secondary development.

[0115] As a specific implementation method, this embodiment completes the adaptation and integration of PCL 1.13, Open3D 0.17, and OpenCV 4.8, enabling direct invocation of point cloud processing, 3D reconstruction, and image recognition algorithms; it supports rapid integration of PyTorch 2.0 and TensorFlow 2.10, completing the porting and training of reinforcement learning-based robot motion control models; and it is compatible with ROS2Humble and Autoware Universe frameworks, enabling simulation testing of intelligent driving perception and planning modules.

[0116] It supports the import and export of mainstream 3D asset formats such as USD, FBX, and OBJ, and achieves mutual compatibility between different asset formats through a format conversion tool. It ensures seamless integration with existing simulation toolchains (such as 3D modeling software and animation production tools), allowing users to reuse existing asset resources, improve simulation development efficiency, and enhance the compatibility of multi-dimensional software and asset formats.

[0117] Example 2

[0118] Please see Figure 2 As shown, this embodiment discloses an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the physical simulation platform construction method based on RISC-V high-throughput chip provided by the above methods.

[0119] Since the electronic device described in this embodiment is the electronic device used to implement the physical simulation platform construction method based on RISC-V high-throughput chip in the embodiments of this application, those skilled in the art can understand the specific implementation method and various variations of the electronic device in this embodiment based on the physical simulation platform construction method based on RISC-V high-throughput chip described in the embodiments of this application. Therefore, how the electronic device implements the method in the embodiments of this application will not be described in detail here. Any electronic device used by those skilled in the art to implement the physical simulation platform construction method based on RISC-V high-throughput chip in the embodiments of this application falls within the scope of protection of this application.

[0120] Example 3

[0121] Please see Figure 3 As shown, this embodiment discloses a computer-readable storage medium, including a memory, a processor, and a computer program stored on the memory and running on the processor. When the processor executes the computer program, it implements the physical simulation platform construction method based on RISC-V high-throughput chip provided by the above methods.

[0122] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters, weights, and thresholds in the formulas are set by those skilled in the art according to the actual situation.

[0123] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired or wireless network. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0124] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0125] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0126] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only one method, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0127] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0129] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0130] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for building a physical simulation platform based on a RISC-V high-throughput chip, characterized in that, The method includes: S101. Basic framework construction: Standardize the simulation assets and hardware call interfaces and optimize the graphics cards; build a visual asset system library; and develop a task scheduler for performing intelligent task classification and dynamic resource allocation. After the basic framework is built, a minimal test scenario simulating robot walking is built to verify the core functions of the basic framework. S102, Physics Engine Integration: A unified abstract interface enables multi-engine compatibility, task splitting is based on the task scheduler to obtain multiple sub-tasks that are executed in parallel, and memory bandwidth is optimized through data compression and on-demand transmission strategies. S103, Upper-layer application development: Develop a dynamic task scheduling center based on RISC-V high-throughput chip and build a high-speed data channel; Scenario-based functional module development: Visualize the user interface, provide rich simulation parameter configuration functions, and export simulation results; S104, Performance Optimization and Ecosystem Development: The dedicated acceleration unit based on the RISC-V high-throughput chip performs instruction-level optimization on the core computing modules of physical simulation, deepens the hardware call interface in the basic framework, and improves the compatibility of multi-dimensional software and asset formats.

2. The method for building a physical simulation platform based on a RISC-V high-throughput chip according to claim 1, characterized in that, The specific steps for building the visual asset system library are as follows: The visual asset system library integrates three core functions: asset version control, keyword search, and multi-user collaborative editing. The asset version control function allows for the tracing and rollback of asset modification records, while the keyword search and user collaborative editing functions facilitate asset retrieval and team collaborative development. Establish a unified asset indexing mechanism to allocate and label each type of asset, thereby obtaining a corresponding unique index identifier.

3. The method for building a physical simulation platform based on a RISC-V high-throughput chip according to claim 1, characterized in that, The specific steps for developing a task scheduler for performing intelligent task classification and dynamic resource allocation are as follows: Obtain task samples, extract computational features from the task samples and perform feature standardization to obtain feature matrix and hard constraints. The computational features include floating-point operation density, memory access mode and parallelization degree. Task identification and computing power requirement assessment training are performed based on feature matrices and hard constraints. A dynamic priority algorithm is adopted to adjust task priorities in combination with business requirements. The priority calculation formula is as follows: In the formula: w1 and w2 are the weighting coefficients of business criticality and resource sensitivity, Criticism is the task criticality level, and T deadline For the remaining deadline, Resource demand Indicates the current task resource requirements, Resource available This represents the percentage of available system resources.

4. The method for building a physical simulation platform based on a RISC-V high-throughput chip according to claim 1, characterized in that, The task splitting based on the task scheduler results in multiple subtasks that can be executed in parallel, including: First, calculate the utilization rate of a single module: In the formula: T active,j For the active time of the j-th task, T total C represents the total observation time, and C represents the number of cores. Based on module utilization, task feature analysis and feasibility assessment of task splitting are performed. Splitting constraints are defined to obtain a list of splittable tasks. The splitting mode is selected by combining the RISC-V architecture parameters and task types, and the subtask granularity is optimized to obtain multiple subtasks that can be executed in parallel. These multiple subtasks are then distributed to the RISC-V multi-core architecture.

5. The method for building a physical simulation platform based on a RISC-V high-throughput chip according to claim 4, characterized in that, The method of selecting a splitting mode based on RISC-V architecture parameters and task type, and optimizing the granularity of subtasks, includes: The task types include data-parallel tasks and task-parallel tasks, and the splitting modes include data sharding mode and functional decomposition mode. The formula for calculating the granularity of optimized subtasks is as follows: In the formula: G is the number of subtasks, T comp Calculate the time for a single task, T sync This indicates the synchronization overhead.

6. The method for building a physical simulation platform based on a RISC-V high-throughput chip according to claim 4, characterized in that, The specific steps for allocating multiple parallel-executed subtasks to the RISC-V multi-core architecture are as follows: For the data sharding tasks split by the data sharding mode, a round-robin allocation strategy is adopted to obtain the core number from the RISC-V high-throughput chip and allocate tasks in a cyclical manner according to the core number order. For the functional decomposition tasks split by the aforementioned functional decomposition mode, the Min-Min algorithm is adopted to calculate the expected completion time of each subtask on each core based on the subtask resource requirements and core performance parameters. The expected completion times are sorted from largest to smallest, and the tasks are allocated according to the sorted expected completion times.

7. The method for building a physical simulation platform based on a RISC-V high-throughput chip according to claim 6, characterized in that, The adoption of the Min-Min algorithm specifically includes: Where: Communication overhead i,j It is based on the inter-core bandwidth estimation.

8. The method for building a physical simulation platform based on a RISC-V high-throughput chip according to claim 1, characterized in that, The process of optimizing video memory bandwidth through data compression and on-demand transmission strategies is as follows: Calculate bandwidth utilization: In the formula: S i B represents the size of the data transmitted in the i-th transmission. max This is the upper limit of video memory bandwidth; Based on bandwidth utilization, a list of high bandwidth-occupied data blocks is obtained. The data types in the list of high bandwidth-occupied data blocks are then selected. A compression algorithm is selected based on the data type, and the optimal compression ratio is calculated for compression.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the physical simulation platform construction method based on the RISC-V high-throughput chip as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed, implements the physical simulation platform construction method based on the RISC-V high-throughput chip as described in any one of claims 1 to 8.

Images