Class-AB op-amp slew rate acceleration circuits and electronic equipment

Abstract

This application discloses a slew rate acceleration circuit and electronic device for a Class-AB operational amplifier. The circuit includes a first comparator and a second comparator. The input terminals of the first comparator include a first NMOS transistor, a second NMOS transistor, and a first resistor. The input terminals of the second comparator include a third NMOS transistor, a fourth NMOS transistor, and a second resistor. The output terminal of the first comparator is connected to the gate terminal of the Class-AB operational amplifier's output PMOS transistor. The output terminal of the second comparator is connected to the gate terminal of the Class-AB operational amplifier's output NMOS transistor via a fifth NMOS transistor. The positive input voltage of the Class-AB operational amplifier is simultaneously connected to the gates of the second and third NMOS transistors, and the negative input voltage is simultaneously connected to the gates of the first and fourth NMOS transistors. The source of the first NMOS transistor is connected to the first resistor, and the source of the third NMOS transistor is connected to the second resistor. This application can significantly improve the response capability of a Class-AB operational amplifier to rapid input signal changes.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more specifically, to a slew rate acceleration circuit and electronic device for a Class-AB operational amplifier. Background Technology

[0002] Class-AB op-amps are widely used due to their excellent balance between quiescent power consumption and dynamic performance. Specifically, Class-AB op-amps operate by biasing two sets of transistors (NPN and PNP) in the on-state. Under small-signal conditions, only one pair of transistors is turned on, thus maintaining low quiescent power consumption; while under large-signal conditions, the other pair of transistors turns on to provide sufficient output current. This design allows Class-AB op-amps to maintain their advantage in quiescent power consumption while providing a large output current when needed, making them widely used in VCOM (common electrode circuits).

[0003] To ensure high drive capability, Class-AB operational amplifiers typically use larger MOSFETs at their output terminals, which increases the charging and discharging time of the output signal to some extent. Slew rate is a parameter describing the rate of change of the operational amplifier's output voltage, usually expressed in V / µs. Due to the capacitive effect of larger MOSFETs, the operational amplifier's slew rate is reduced. In high-frequency or rapidly changing signal scenarios, if the operational amplifier cannot keep up with the signal changes, signal distortion will occur, affecting signal quality. In high-frequency applications, insufficient slew rate also directly affects the overall bandwidth of the system, limiting signal transmission capability. Summary of the Invention

[0004] The main objective of this application is to provide a slew rate acceleration circuit and electronic device for Class-AB op-amps, which can significantly improve the response capability of Class-AB op-amps to rapid input signal changes.

[0005] To achieve the above objectives, a first aspect of this application proposes a slew rate acceleration circuit for a Class-AB operational amplifier, comprising: a first comparator and a second comparator; the input terminals of the first comparator include a first NMOS transistor, a second NMOS transistor, and a first resistor; the input terminals of the second comparator include a third NMOS transistor, a fourth NMOS transistor, and a second resistor; the output terminal of the first comparator is connected to the gate terminal of the Class-AB operational amplifier's output PMOS transistor; the output terminal of the second comparator is connected to the gate terminal of the Class-AB operational amplifier's output NMOS transistor via a fifth NMOS transistor; the positive input voltage of the Class-AB operational amplifier is simultaneously connected to the gates of the second and third NMOS transistors, and the negative input voltage is simultaneously connected to the gates of the first and fourth NMOS transistors; the source of the first NMOS transistor is connected to the first resistor, and the source of the third NMOS transistor is connected to the second resistor.

[0006] In some embodiments of this disclosure, the first comparator further includes a first PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor, and the second comparator further includes a second PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a sixth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;

[0007] The sources of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth PMOS transistors, ninth NMOS transistor, and tenth NMOS transistor are connected to the input voltage, and the drains of the second, third, fifth, seventh, and tenth PMOS transistors are connected to the drains of the sixth, seventh, eighth, ninth, and tenth NMOS transistors, respectively.

[0008] The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, the gate of the ninth PMOS transistor is connected to the gate of the tenth PMOS transistor, the gate of the seventh NMOS transistor is connected to the gate of the eighth NMOS transistor, and the gate of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor. The drains of the fourth and fifth PMOS transistors are connected to the drains of the first and second NMOS transistors, respectively. The drains of the eighth and ninth PMOS transistors are connected to the drains of the third and fourth NMOS transistors, respectively. The gates and drains of the seventh, fourth, fifth, ninth, eighth, and ninth PMOS transistors are shorted.

[0009] In some embodiments of this disclosure, the first comparator and the second comparator are configured to monitor changes in the positive and negative input voltages of the Class-AB op-amp. The output of the first comparator controls the gate voltage of the PMOS transistor at the output of the Class-AB op-amp through the conduction state of the first PMOS transistor, and the output of the second comparator controls the gate voltage of the NMOS transistor at the output of the Class-AB op-amp through the conduction state of the second PMOS transistor. Under normal operating conditions of the Class-AB op-amp, the positive input voltage is equal to the negative input voltage, and the outputs of the first comparator and the second comparator remain stable.

[0010] In some embodiments of this disclosure, the gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fifth NMOS transistor is connected to the gate of the Class-AB operational amplifier output NMOS transistor, and the fifth NMOS transistor and the sixth NMOS transistor constitute a current mirror structure.

[0011] In some embodiments of this disclosure, when the Class-AB op-amp is operating normally, the gate-source voltage of the first NMOS transistor is less than the gate-source voltage of the second NMOS transistor, the drain current of the first NMOS transistor is less than the drain current of the second NMOS transistor, the first PMOS transistor, the second PMOS transistor, and the fifth NMOS transistor are turned off, and the gate voltages of the PMOS transistors and NMOS transistors at the output of the Class-AB op-amp remain unchanged.

[0012] In some embodiments of this disclosure, when the positive input voltage of the Class-AB op-amp increases, the output of the first comparator remains unchanged, the gate-source voltage of the third NMOS transistor increases, and the drain current increases. When the drain current of the third NMOS transistor is greater than the drain current of the fourth NMOS transistor, the second PMOS transistor and the fifth NMOS transistor are turned on, which pulls down the gate voltage of the NMOS transistor at the output terminal of the Class-AB op-amp, reduces the gate-source voltage of the NMOS transistor at the output terminal of the Class-AB op-amp, and increases the output voltage of the Class-AB op-amp.

[0013] In some embodiments of this disclosure, when the positive input voltage of the Class-AB op-amp decreases, the output of the second comparator remains unchanged, the gate-source voltage of the second NMOS transistor decreases, and the drain current decreases. When the drain current of the first NMOS transistor is greater than the drain current of the second NMOS transistor, the first PMOS transistor is turned on, which pulls up the gate voltage of the PMOS transistor at the output terminal of the Class-AB op-amp, reduces the gate-source voltage of the PMOS transistor at the output terminal of the Class-AB op-amp, and decreases the output voltage of the Class-AB op-amp.

[0014] In some embodiments of this disclosure, the Class-AB operational amplifier includes an input stage, a gain stage, and an output stage. The input stage consists of a differential amplifier for differential amplification of the input signal. The gain stage includes multiple amplifiers connected in series. The output stage consists of a pair of complementary NMOS transistors and PMOS transistors.

[0015] In some embodiments of this disclosure, the slew rate acceleration circuit controls the pull-up and pull-down currents of the PMOS and NMOS transistors at the output terminals of the Class-AB op-amp by controlling the gate-source voltages of the PMOS and NMOS transistors at the output terminals of the Class-AB op-amp.

[0016] In a second aspect, an electronic device is provided, including a slew rate acceleration circuit for a Class-AB operational amplifier as described in the first aspect.

[0017] As can be seen from the above scheme, the slew rate acceleration circuit of the Class-AB op-amp provided in this application can significantly improve the response capability of the Class-AB op-amp to rapid input signal changes. Specifically, by monitoring the input voltage change through a comparator and dynamically adjusting the conduction state of the MOSFET according to the input voltage change, the gate voltage of the MOSFET at the output terminal of the Class-AB op-amp is controlled, effectively managing the pull-up and pull-down currents of the MOSFET, thereby achieving faster output voltage changes. This design scheme effectively improves the slew rate of the op-amp, enabling it to maintain good tracking capability when facing rapid signal changes, reducing distortion, and providing the Class-AB op-amp with stronger dynamic response capability, meeting the needs of high-frequency and rapidly changing applications. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings:

[0019] Figure 1 This is a schematic diagram of a typical Class-AB operational amplifier structure;

[0020] Figure 2 This is a schematic diagram of the slew rate acceleration circuit structure of the Class-AB op-amp provided in this application. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0022] The Class-AB operational amplifier (op-amp) circuit structure mainly consists of an input stage, a gain stage, and an output stage. The input stage, composed of differential pair transistors, is responsible for the initial amplification of the input signal. It typically features high gain and a good common-mode rejection ratio (CMRR), effectively canceling noise interference in the input signal. The gain stage consists of multiple transistors arranged in a push-pull configuration to form one or more series amplifiers, providing further gain. The output stage is a pair of complementary transistors (one NPN and one PNP) responsible for providing a large current output to drive the load. When the input signal is positive, the NPN transistor conducts and provides the output current; when the signal is negative, the PNP transistor conducts and provides the output current. This switching method ensures that the two transistors alternately operate during the positive and negative half-cycles of the signal, thereby achieving high efficiency and reducing power consumption and heat generation.

[0023] In Class-AB op-amps, although their quiescent power consumption is relatively low, the output MOSFETs are typically designed to be quite large because they need to provide a large output current to drive the load. While this design improves drive capability, it also results in a lower slew rate (SR). Slew rate refers to the rate at which the op-amp's output voltage changes, usually expressed in V / μs. A high slew rate means the op-amp can respond quickly to changes in the input signal, which is crucial for processing high-speed signals. In many applications, such as audio amplification, video signal processing, and RF applications, a sufficient slew rate is an important factor in ensuring signal integrity.

[0024] Figure 1 This is a schematic diagram of a typical Class-AB operational amplifier structure. (Refer to...) Figure 1 As shown, VN and VP are the negative and positive input voltages of the operational amplifier, respectively, and these two voltages are compared through differential amplification. P0 and N0 are the PMOS and NMOS transistors at the output terminals, responsible for converting the gain signal into the output voltage vout. gop is the gate voltage of P0, and gon is the gate voltage of N0. Changes in the gate voltage directly affect the conduction state of the MOSFETs, thus affecting the rapid changes in the output voltage.

[0025] To meet the demands of a large load current, P0 and N0 are designed to be relatively large. Since the gate capacitance of a MOSFET is proportional to its area, a larger MOSFET results in a larger gate capacitance, which slows down the gate charging and discharging speed. This causes the output voltage to be unable to keep up with the input changes when they change rapidly, resulting in a slower slew rate of the op-amp. Without an acceleration circuit, when the VP voltage switches, the loop itself needs to adjust the pull-up and pull-down currents to adjust the output voltage. This adjustment time is long, naturally slowing down the output voltage change speed and resulting in a lower SR.

[0026] To address the shortcomings of Class-AB op-amps in terms of output slew rate, this disclosure presents a slew rate acceleration circuit for Class-AB op-amps. By using two comparators to detect changes in the positive and negative input voltages (VP, VN) of the op-amp, the gate voltage of the output stage MOSFET is dynamically adjusted to achieve rapid charging and discharging of the gate of the Class-AB op-amp output stage MOSFET. This allows the output voltage to respond quickly to changes in the input voltage, thereby improving the slew rate.

[0027] Figure 2 This is a schematic diagram of the slew rate acceleration circuit structure for the Class-AB operational amplifier provided in this application. (Refer to...) Figure 2 As shown, the slew rate acceleration circuit includes: a first comparator and a second comparator. The input terminals of the first comparator include a first NMOS transistor N1, a second NMOS transistor N2, and a first resistor R1. The input terminals of the second comparator include a third NMOS transistor N3, a fourth NMOS transistor N4, and a second resistor R2. The output terminal of the first comparator is connected to the output terminal of a Class-AB operational amplifier (PMOS transistor). Figure 1 The gate terminal of the P0); the output terminal of the second comparator is connected to the output terminal of the Class-AB operational amplifier via the fifth NMOS transistor N5. Figure 1 The gate terminal of the Class-AB op-amp is connected to the second NMOS transistor N2 and the third NMOS transistor N3. The negative input voltage VN is connected to the first NMOS transistor N1 and the fourth NMOS transistor N4. The source of the first NMOS transistor N1 is connected to the first resistor R1, and the source of the third NMOS transistor N3 is connected to the second resistor R2.

[0028] In a specific embodiment, the first comparator further includes a first PMOS transistor P1, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh NMOS transistor N7, and an eighth NMOS transistor N8; the second comparator further includes a second PMOS transistor P2, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a sixth NMOS transistor N6, a ninth NMOS transistor N9, and a tenth NMOS transistor N10.

[0029] The sources of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, the eighth PMOS transistor P8, the ninth PMOS transistor P9, the tenth PMOS transistor P10, the ninth NMOS transistor N9, and the tenth NMOS transistor N10 are connected to the input voltage VIN. The drains of the second PMOS transistor P2, the third PMOS transistor P3, the fifth PMOS transistor P5, the seventh PMOS transistor P7, and the tenth PMOS transistor P10 are connected to the drains of the sixth NMOS transistor N6, the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, and the tenth NMOS transistor N10, respectively.

[0030] The gate of the third PMOS transistor P3 is connected to the gate of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5 is connected to the gate of the sixth PMOS transistor P6, the gate of the seventh PMOS transistor P7 is connected to the gate of the eighth PMOS transistor P8, the gate of the ninth PMOS transistor P9 is connected to the gate of the tenth PMOS transistor P10, the gate of the seventh NMOS transistor N7 is connected to the gate of the eighth NMOS transistor N8, and the gate of the ninth NMOS transistor N9 is connected to the gate of the tenth NMOS transistor N10. The drains of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are connected to the drains of the first NMOS transistor N1 and the second NMOS transistor N2, respectively. The drains of the eighth PMOS transistor P8 and the ninth PMOS transistor P9 are connected to the drains of the third NMOS transistor N3 and the fourth NMOS transistor N4, respectively. The gates and drains of the seventh NMOS transistor N7, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the ninth NMOS transistor N9, the eighth PMOS transistor P8, and the ninth PMOS transistor P9 are short-circuited. When the gate and drain of a MOSFET are shorted, the gate voltage will change with the drain voltage.

[0031] The first and second comparators are configured to monitor changes in the positive and negative input voltages of the Class-AB op-amp. Based on the comparison result of VN relative to VP, the comparator outputs switch between high and low levels. The output of the first comparator controls the gate voltage of the PMOS transistor at the output of the Class-AB op-amp through the on-state of the first PMOS transistor, and the output of the second comparator controls the gate voltage of the NMOS transistor at the output of the Class-AB op-amp through the on-state of the second PMOS transistor. Under normal operating conditions of the Class-AB op-amp, the positive input voltage VP is equal to the negative input voltage VN, and the outputs of the first and second comparators remain stable.

[0032] In some embodiments of this disclosure, the gate of the sixth NMOS transistor N6 is connected to the gate of the fifth NMOS transistor N5, and the drain of the fifth NMOS transistor N5 is connected to the gate voltage gon of the Class-AB operational amplifier output NMOS transistor N0. The fifth NMOS transistor N5 and the sixth NMOS transistor N6 constitute a current mirror structure.

[0033] Under normal operating conditions, VP and VN voltages are equal, meaning the op-amp is in a static operating state. Because the source of the first NMOS transistor N1 is connected through resistor R1, the gate-source voltage of the first NMOS transistor is less than the gate-source voltage of the second NMOS transistor: V GS1 <V GS2 Therefore, the drain current of the first NMOS transistor is less than the drain current of the second NMOS transistor: I DS1 DS2 . Figure 2 When the voltage at point A is pulled high, P1 is in the off state, which does not affect the GOP voltage; the voltage at point C is lower, and the fifth NMOS transistor N5 is not conducting, so the GOP voltage remains unchanged. In this state, the gate voltages of the PMOS and NMOS transistors at the output of the Class-AB op-amp do not change, the op-amp consumes low power in the static state, and maintains good linearity.

[0034] This disclosure controls the pull-up and pull-down currents of the PMOS and NMOS transistors at the output terminals of the Class-AB op-amp by controlling the gate-source voltages of the PMOS and NMOS transistors at the output terminals of the Class-AB op-amp.

[0035] When the positive input voltage of the Class-AB op-amp increases, the output of the first comparator remains unchanged, and the gate-source voltage V of the third NMOS transistor N3... GS3 Increase, drain current I DS3 Increase, when the drain current I of the third NMOS transistor N3 increases DS3 The drain current I of the fourth NMOS transistor N4 is greater than DS4 When the voltage at point B flips to 0, the second PMOS transistor P2 turns on, the voltage at point C is pulled up, and the fifth NMOS transistor N5 turns on, causing the gate voltage gon of the NMOS transistor N0 at the output terminal of the Class-AB op-amp to drop. The gate-source voltage of the NMOS transistor at the output terminal of the Class-AB op-amp decreases, the pull-down current decreases, the pull-up current remains unchanged, and the output voltage of the Class-AB op-amp rises.

[0036] When the positive input voltage of the Class-AB op-amp decreases, the output of the second comparator remains unchanged, and the gate-source voltage V of the second NMOS transistor N2... GS2 Decrease, drain current I DS2 ​When the drain current of the first NMOS transistor N1 is greater than the drain current of the second NMOS transistor N2, the voltage at point A is pulled down, the first PMOS transistor P1 is turned on, which pulls up the gate voltage gop of the PMOS transistor P0 at the output terminal of the Class-AB op-amp. The gate-source voltage of the PMOS transistor at the output terminal of the Class-AB op-amp decreases, the pull-up current decreases, while the pull-down current remains unchanged, and the output voltage of the Class-AB op-amp decreases.

[0037] As can be seen from the above scheme, the slew rate acceleration circuit of the Class-AB op-amp provided in this application can significantly improve the response capability of the Class-AB op-amp to rapid input signal changes. Specifically, by monitoring the input voltage change through a comparator and dynamically adjusting the conduction state of the MOSFET according to the input voltage change, the gate voltage of the MOSFET at the output terminal of the Class-AB op-amp is controlled, effectively managing the pull-up and pull-down currents of the MOSFET, thereby achieving faster output voltage changes. This design scheme effectively improves the slew rate of the op-amp, enabling it to maintain good tracking capability when facing rapid signal changes, reducing distortion, and providing the Class-AB op-amp with stronger dynamic response capability, meeting the needs of high-frequency and rapidly changing applications.

[0038] Based on the above embodiments, this disclosure also provides an electronic device, including the slew rate acceleration circuit of the Class-AB operational amplifier described in the above embodiments, which has the beneficial effects described in any of the above embodiments. This disclosure will not provide specific examples of each of these effects.

[0039] The electronic device provided in this disclosure can be applied to flexible electronic devices to realize technologies such as Augmented Reality (AR), Virtual Reality (VR), Extended Reality (XR), and Mixed Reality (MR). For example, the display device can be the projection part of the electronic device, such as a projector or a head-up display (HUD); or, for example, the display device can be the display part of the electronic device, such as a smartphone, smartwatch, laptop, tablet, dashcam, navigator, head-mounted device, or any device with a display screen.

[0040] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0041] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. Moreover, the above embodiment numbers are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A slew rate acceleration circuit for a Class-AB operational amplifier, characterized in that, include: A first comparator and a second comparator, wherein the input terminals of the first comparator include a first NMOS transistor, a second NMOS transistor, and a first resistor, and the input terminals of the second comparator include a third NMOS transistor, a fourth NMOS transistor, and a second resistor; the first comparator further includes a first PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor; the second comparator further includes a second PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a sixth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The sources of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, ninth, and tenth NMOS transistors are connected to the input voltage, and the drains of the second, third, fifth, seventh, and tenth PMOS transistors are respectively connected to the drains of the sixth, seventh, eighth, ninth, and tenth NMOS transistors. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the sixth PMOS transistor, the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, the gate of the ninth PMOS transistor is connected to the gate of the tenth PMOS transistor, the gate of the seventh NMOS transistor is connected to the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, the drains of the fourth and fifth PMOS transistors are respectively connected to the drains of the first and second NMOS transistors, the drains of the eighth and ninth PMOS transistors are respectively connected to the drains of the third and fourth NMOS transistors, and the gates and drains of the seventh, fourth, fifth, ninth, eighth, and ninth PMOS transistors are short-circuited. The output of the first comparator is connected to the gate of the PMOS transistor at the output of the Class-AB op-amp; the output of the second comparator is connected to the gate of the NMOS transistor at the output of the Class-AB op-amp via a fifth NMOS transistor; the output of the first comparator controls the gate voltage of the PMOS transistor at the output of the Class-AB op-amp through the on-state of the first PMOS transistor, and the output of the second comparator controls the gate voltage of the NMOS transistor at the output of the Class-AB op-amp through the on-state of the second PMOS transistor. The positive input voltage of the Class-AB op-amp is connected to the gates of both the second and third NMOS transistors, and the negative input voltage is connected to the gates of both the first and fourth NMOS transistors; the source of the first NMOS transistor is connected to a first resistor, and the source of the third NMOS transistor is connected to a second resistor; when the positive input voltage of the Class-AB op-amp increases, the first comparator... The output remains unchanged. The gate-source voltage of the third NMOS transistor increases, and the drain current increases. When the drain current of the third NMOS transistor is greater than the drain current of the fourth NMOS transistor, the second PMOS transistor and the fifth NMOS transistor are turned on, pulling down the gate voltage of the NMOS transistor at the output terminal of the Class-AB op-amp. The gate-source voltage of the NMOS transistor at the output terminal of the Class-AB op-amp decreases, and the output voltage of the Class-AB op-amp increases. When the positive input voltage of the Class-AB op-amp decreases, the output of the second comparator remains unchanged. The gate-source voltage of the second NMOS transistor decreases, and the drain current decreases. When the drain current of the first NMOS transistor is greater than the drain current of the second NMOS transistor, the first PMOS transistor is turned on, pulling up the gate voltage of the PMOS transistor at the output terminal of the Class-AB op-amp. The gate-source voltage of the PMOS transistor at the output terminal of the Class-AB op-amp decreases, and the output voltage of the Class-AB op-amp decreases.

2. The slew rate acceleration circuit for a Class-AB operational amplifier according to claim 1, characterized in that, The first and second comparators are configured to monitor changes in the positive and negative input voltages of the Class-AB op-amp. Under normal operating conditions of the Class-AB op-amp, the positive input voltage is equal to the negative input voltage, and the outputs of the first and second comparators remain stable.

3. The slew rate acceleration circuit for a Class-AB operational amplifier according to claim 2, characterized in that, The gate of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, and the drain of the fifth NMOS transistor is connected to the gate of the Class-AB operational amplifier output NMOS transistor. The fifth and sixth NMOS transistors form a current mirror structure.

4. The slew rate acceleration circuit for a Class-AB operational amplifier according to claim 3, characterized in that, When the Class-AB op-amp is working normally, the gate-source voltage of the first NMOS transistor is less than the gate-source voltage of the second NMOS transistor, the drain current of the first NMOS transistor is less than the drain current of the second NMOS transistor, the first PMOS transistor, the second PMOS transistor, and the fifth NMOS transistor are turned off, and the gate voltages of the PMOS transistors and NMOS transistors at the output of the Class-AB op-amp remain unchanged.

5. The slew rate acceleration circuit for a Class-AB operational amplifier according to claim 1, characterized in that, The Class-AB operational amplifier includes an input stage, a gain stage, and an output stage. The input stage consists of a differential amplifier used to differentially amplify the input signal. The gain stage includes multiple amplifiers connected in series. The output stage consists of a pair of complementary NMOS and PMOS transistors.

6. The slew rate acceleration circuit for a Class-AB operational amplifier according to claim 5, characterized in that, The slew rate acceleration circuit controls the pull-up and pull-down currents of the PMOS and NMOS transistors at the output terminals of the Class-AB op-amp by controlling the gate-source voltages of these transistors.

7. An electronic device, characterized in that, The circuit includes the slew rate acceleration circuit of the Class-AB operational amplifier as described in any one of claims 1-6.

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