A high-voltage power amplifier with over-temperature and over-current protection circuit

Abstract

The application discloses a high-voltage power amplifier with over-temperature and over-current protection circuit and relates to the technical field of integrated circuits.The application comprises a high-voltage operational amplifier core unit and an adaptive protection circuit unit.The high-voltage operational amplifier core unit comprises a rail-to-rail input stage, a gain amplification stage and an AB class push-pull output stage which are cascaded in sequence.The AB class push-pull output stage comprises a PMOS upper power tube and an NMOS lower power tube.The adaptive protection circuit unit comprises a PMOS current-limiting protection circuit, an NMOS current-limiting protection circuit and an over-temperature protection circuit.The PMOS current-limiting protection circuit is used for generating a high-voltage domain over-current control signal when the PMOS upper power tube overflows.The NMOS current-limiting protection circuit is used for generating a low-voltage domain over-current control signal when the NMOS lower power tube overflows.The over-temperature protection circuit is used for generating high-voltage and low-voltage domain over-temperature shutdown signals when the amplifier over-temperature.Finally, the corresponding over-current control signals and over-temperature shutdown signals are logically synthesized to generate a gate clamping signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a high-voltage power amplifier with over-temperature and over-current protection circuitry. Background Technology

[0002] With the rapid development of new energy vehicles, industrial precision control, and medical electronics, the demand for high-voltage operational amplifiers is increasing. As a key analog front-end connecting sensors and actuators, high-voltage operational amplifiers are widely used in scenarios such as voltage sampling in battery management systems, piezoelectric actuator control, and motor servo drives. These applications typically require operational amplifiers to have high dynamic range and strong load driving capability, thus needing to operate over a wide power supply voltage range (e.g., 8V to 36V or higher). However, the operating voltage range of traditional general-purpose operational amplifiers is mostly concentrated between 1.8V and 5.5V, which is difficult to directly meet the requirements of the aforementioned high-voltage applications. Therefore, designing a high-voltage operational amplifier that still possesses superior input and output performance over a wide power supply voltage range has significant practical value.

[0003] In high-voltage analog circuit design, high-voltage MOS transistors are essential. However, due to the physical limitations of semiconductor manufacturing processes, these transistors typically only have high drain-source breakdown voltage, while their gate-source breakdown voltage is often similar to that of conventional low-voltage devices. In existing high-voltage circuit protection schemes, when an over-temperature or over-current fault is detected, the traditional method usually involves shutting down the preceding bias circuit. Since the high-voltage output stage operates at an extremely high potential, directly clamping the gate of the power transistor would place stringent demands on the breakdown voltage performance of the protection circuit's own components. Therefore, traditional circuits often employ a "disconnection of the drive path," leaving the gate potential of the high-voltage power transistor in a floating state. This method has a significant drawback: the gate charge in a floating state is susceptible to external interference and can accumulate, potentially causing the power transistor to enter an unexpected subconducting or misconducting state, leading to thermal runaway or even permanent breakdown. This unreliable protection state severely restricts the long-term operational stability of the circuit. Therefore, developing a protection circuit that can achieve efficient over-temperature and over-current protection, and can actively and reliably manage the gate potential of high-voltage power transistors and completely prevent them from being floating, has become a key technical problem that urgently needs to be solved in the field of high-voltage power amplifiers. Summary of the Invention

[0004] Based on the shortcomings of the prior art described above, the purpose of this invention is to provide a high-voltage power amplifier with over-temperature and over-current protection circuit to solve the above-mentioned technical problems.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a high-voltage power amplifier with over-temperature and over-current protection circuit, comprising:

[0006] The high-voltage operational amplifier core unit and the adaptive protection circuit unit include a rail-to-rail input stage, a gain amplification stage and an AB class push-pull output stage cascaded in sequence. The AB class push-pull output stage includes a PMOS upper power transistor and an NMOS lower power transistor.

[0007] The adaptive protection circuit unit includes a PMOS current limiting protection circuit, an NMOS current limiting protection circuit, and an over-temperature protection circuit.

[0008] The PMOS current limiting protection circuit is used to generate a low-voltage domain discrimination signal when the power transistor on the PMOS is overcurrent, and in conjunction with the high-voltage level conversion circuit, converts the low-voltage domain discrimination signal into a high-voltage domain overcurrent control signal.

[0009] The NMOS current limiting protection circuit is used to generate a low-voltage domain overcurrent control signal when the NMOS power transistor is overcurrent.

[0010] The over-temperature protection circuit is used to generate a low-voltage domain over-temperature shutdown signal when the amplifier over-temperatures, and in conjunction with the high-voltage level conversion circuit, converts the low-voltage domain over-temperature shutdown signal into a high-voltage domain over-temperature shutdown signal.

[0011] The present invention is further configured such that the adaptive protection circuit unit further includes a signal synthesis circuit, which is used to logically combine the high-voltage domain overcurrent control signal, the low-voltage domain overcurrent control signal, the high-voltage domain overtemperature turn-off signal and the low-voltage domain overtemperature turn-off signal to generate gate clamp signals that respectively control the turn-off of the PMOS upper power transistor and the NMOS lower power transistor.

[0012] The present invention is further configured such that the rail-to-rail input stage includes a first differential input pair and a second differential input pair connected in parallel;

[0013] The first differential input pair is a folded differential pair composed of PMOS transistors, and the second differential input pair is a folded differential pair composed of NMOS transistors.

[0014] The first differential input pair is configured to be in an active state when the input common-mode voltage is close to ground potential;

[0015] The second differential input pair is configured to be in an active state when the input common-mode voltage is close to the high-voltage power supply potential;

[0016] The first differential input pair and the second differential input pair are also configured to be in an effective working state simultaneously when the input common-mode voltage is higher than the turn-on threshold of the first differential input pair and lower than the turn-off threshold of the second differential input pair.

[0017] The first differential input pair and the second differential input pair are configured together to enable the input common-mode voltage range of the high-voltage power amplifier to cover the full voltage range input from ground potential to high-voltage power supply potential.

[0018] The present invention is further configured such that the gain amplification stage is connected between the on-rail to on-rail input stage and the Class AB push-pull output stage;

[0019] The gain amplifier stage is configured to receive and sum the output currents of the first differential input pair and the second differential input pair;

[0020] The gain amplification stage includes a folded cascode structure, which includes a first group of cascode transistors and a second group of cascode transistors.

[0021] The gain amplification stage also includes a first auxiliary amplifier and a second auxiliary amplifier;

[0022] The output terminal of the first auxiliary amplifier is connected to the gate of the first group of common-source cascode transistors to increase the output impedance of the first group of common-source cascode transistors;

[0023] The output of the second auxiliary amplifier is connected to the gate of the second set of cascode transistors to increase the output impedance of the second set of cascode transistors.

[0024] The present invention is further configured such that the AB class push-pull output stage includes a PMOS upper power transistor, an NMOS lower power transistor, and a bias circuit;

[0025] The source of the PMOS upper power transistor is connected to a high-voltage power supply, and its drain is connected to the output terminal together with the drain of the NMOS lower power transistor. The source of the NMOS lower power transistor is grounded.

[0026] The bias circuit includes a transconducting linear loop structure connected between the gates of the PMOS upper power transistor and the NMOS lower power transistor, used to dynamically clamp the voltage difference between the two gates and provide a static bias current for the PMOS upper power transistor and the NMOS lower power transistor.

[0027] The present invention is further configured such that the high-voltage level conversion circuit is a clamping high-voltage level conversion circuit, including a differential common-source common-gate voltage switch composed of conventional MOS transistors and a clamping structure composed of high-voltage resistant MOS transistors;

[0028] The differential common-source cascode voltage switch is used to receive input signals in the low-voltage domain;

[0029] The gates of the high-voltage MOS transistors in the clamping structure are respectively connected to a low-voltage power supply or a floating reference potential to limit the voltage swing of the internal nodes of the high-voltage level conversion circuit.

[0030] The high-voltage level conversion circuit is configured to use the clamping structure to convert the input signal of the low-voltage domain into a high-voltage domain control signal based on the floating reference potential.

[0031] The floating reference potential is configured to follow the potential changes of the high-voltage power supply, and the voltage difference between the floating reference potential and the high-voltage power supply potential is limited to a preset safe voltage range.

[0032] The present invention is further configured such that the PMOS current limiting protection circuit includes a turn-off potential generation circuit, a high voltage sampling circuit, a current comparator, a rectifier circuit, and a high voltage level conversion circuit;

[0033] The shutdown potential generation circuit is connected between the high-voltage power supply and ground to generate a floating reference potential that follows the changes in the high-voltage power supply potential.

[0034] The high-voltage sampling circuit is powered by a high-voltage power supply and includes a sampling PMOS transistor. The gate of the sampling PMOS transistor is connected to the gate of the PMOS power transistor, and its source and drain are connected in parallel with the source and drain of the PMOS power transistor, respectively, to form a current mirror and replicate the load current of the PMOS power transistor according to a preset ratio to generate a sampling current.

[0035] The current comparator is powered by a low-voltage power supply. Its input terminal receives the sampled current and is used to compare the voltage converted from the sampled current with a preset first reference voltage threshold. When the voltage of the sampled current is greater than the preset first reference voltage threshold, it outputs a level flip signal.

[0036] The input terminal of the rectifier circuit is connected to the output terminal of the current comparator, and is used to shape the level-flipping signal to output a low-voltage domain discrimination signal.

[0037] The input terminal of the high-voltage level conversion circuit is connected to the output terminal of the rectifier circuit, and is used to convert the low-voltage domain discrimination signal into a high-voltage domain overcurrent control signal based on the floating reference potential.

[0038] The present invention is further configured such that the NMOS current limiting protection circuit includes a sampling circuit, a current comparator, and a shaping circuit;

[0039] The sampling circuit includes a sampling NMOS transistor, the gate of which is connected to the gate of the NMOS lower power transistor, and its source and drain are connected in parallel with the source and drain of the NMOS lower power transistor, respectively, to replicate the current flowing through the NMOS lower power transistor according to a preset ratio to generate a sampling current.

[0040] The current comparator is powered by a low-voltage power supply. Its input terminal receives the sampled current and is used to compare the voltage converted from the sampled current with a preset second reference voltage threshold. When the voltage of the sampled current is greater than the preset second reference voltage threshold, it outputs a level flip signal.

[0041] The input terminal of the shaping circuit is connected to the output terminal of the current comparator, and is used to shape the level flip signal and output a low-voltage domain overcurrent control signal for controlling the gate potential of the NMOS power transistor.

[0042] The present invention is further configured such that the over-temperature protection circuit includes a bandgap reference circuit, a programmable resistor voltage divider network, a transmission gate, a high-gain comparator, a hysteresis shaping circuit, and a high-voltage level conversion circuit;

[0043] The bandgap reference circuit is used to generate a reference voltage and a negative temperature coefficient voltage.

[0044] The programmable resistor divider network is connected to a negative temperature coefficient voltage and is configured to generate an independently adjustable first programmable voltage divider and a second programmable voltage divider based on digital configuration codes.

[0045] The input terminal of the transmission gate is connected to the output terminal of the programmable resistor divider network, and its control terminal is connected to the feedback output terminal of the over-temperature protection circuit, for selecting to output the first programmable voltage divider or the second programmable voltage divider according to the feedback signal.

[0046] The first input terminal of the high-gain comparator is connected to the output terminal of the transmission gate, and its second input terminal is connected to the reference voltage. It is used to compare the selected programmable voltage divider with the reference voltage and output a comparison signal.

[0047] The input terminal of the hysteresis shaping circuit is connected to the output terminal of the high-gain comparator, and is used to perform hysteresis processing and waveform shaping on the comparison signal to generate a low-voltage domain over-temperature shutdown signal.

[0048] The input terminal of the high-voltage level conversion circuit is connected to the output terminal of the hysteresis shaping circuit, and is used to convert the low-voltage domain over-temperature shutdown signal into a high-voltage domain over-temperature shutdown signal.

[0049] The present invention is further configured such that the signal synthesis circuit includes a first AND gate and a second AND gate;

[0050] The first logic AND gate uses a high-voltage power supply as its power source and the floating reference potential in the PMOS current limiting protection circuit as its reference ground. Its first input receives the high-voltage domain overcurrent control signal output by the PMOS current limiting protection circuit, its second input receives the high-voltage domain overtemperature shutdown signal output by the overtemperature protection circuit, and its output outputs the first gate clamp signal used to shut down the PMOS power transistor.

[0051] The second logic AND gate uses a low-voltage power supply as its power source and ground potential as its reference ground. Its first input receives the low-voltage domain overcurrent control signal output by the NMOS current limiting protection circuit, its second input receives the low-voltage domain overtemperature shutdown signal output by the overtemperature protection circuit, and its output outputs the second gate clamp signal used to shut down the NMOS lower power transistor.

[0052] This invention provides a high-voltage power amplifier with over-temperature and over-current protection circuits. It comprises a high-voltage operational amplifier core unit and an adaptive protection circuit unit. The high-voltage operational amplifier core unit includes a rail-to-rail input stage, a gain amplification stage, and an AB-class push-pull output stage cascaded sequentially. The AB-class push-pull output stage includes a PMOS upper power transistor and an NMOS lower power transistor. The adaptive protection circuit unit includes a PMOS current-limiting protection circuit, an NMOS current-limiting protection circuit, and an over-temperature protection circuit. The PMOS current-limiting protection circuit generates a low-voltage domain discrimination signal when the PMOS upper power transistor experiences overcurrent, and converts this signal into a high-voltage domain overcurrent control signal using a high-voltage level conversion circuit. The NMOS current-limiting protection circuit generates a low-voltage domain overcurrent control signal when the NMOS lower power transistor experiences overcurrent. The over-temperature protection circuit generates a low-voltage domain over-temperature shutdown signal when the amplifier over-temperatures, and converts this signal into a high-voltage domain over-temperature shutdown signal using a high-voltage level conversion circuit. The beneficial effects include:

[0053] 1. By separating the high-voltage operational amplifier core unit from the low-voltage adaptive protection circuit unit that integrates multiple protection functions, effective coordination between the high-voltage signal path and the low-voltage intelligent control path is achieved. This architecture enables the core amplifier to operate efficiently under high voltage, while complex protection logic, comparison, and judgment functions are implemented in the low-voltage domain in a low-power, high-precision manner. In particular, through an innovative high-voltage level conversion circuit and floating reference potential generation mechanism, the low-voltage control domain and the high-voltage power domain are safely bridged, ensuring that the protection signal generated by the low voltage can be transmitted to the high-voltage side without loss, quickly, and safely. This constructs a complete and reliable cross-voltage domain intelligent protection system at the system level, solving the problems of complex design, slow response speed, or insufficient electrical safety of traditional high-voltage amplifier protection circuits.

[0054] 2. The clamping high-voltage level conversion circuit integrates a low static power consumption voltage clamping mechanism into a differential common-source common-gate switch structure. The gate of the clamping transistor is fixedly connected to a safe potential instead of using the traditional diode connection method. This effectively limits the voltage swing of the internal low-voltage node to prevent high-voltage breakdown and reduces the static power consumption of the circuit to an extremely low level. This design is the core of realizing the safe, fast, and efficient conversion of low-voltage protection signals into high-voltage control signals, laying a solid foundation for directly and reliably turning off the high-voltage side PMOS power transistor.

[0055] 3. The PMOS current limiting protection circuit constructs a complete protection link from high-voltage sampling, low-voltage judgment to high-voltage execution; the floating reference potential generated by its turn-off potential generation circuit creates a safe high-voltage floating operating domain, thereby solving the voltage withstand problem of the high-voltage side control circuit; the circuit performs accurate current sampling through a current mirror structure, sets the protection threshold using a low-voltage domain intelligent comparator, and finally achieves fast and accurate detection and forced turn-off protection of the overcurrent state of the PMOS power transistor through signal conversion and direct gate clamping, and the isolation between the high and low voltage domains is clear throughout the process, ensuring the safety and reliability of the system operation.

[0056] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0058] Figure 1 A structural diagram of a high-voltage power amplifier with over-temperature and over-current protection circuit is shown as an exemplary embodiment of the present invention;

[0059] Figure 2 This is a circuit diagram for a high-voltage power amplifier.

[0060] Figure 3 This is the circuit diagram for the amplifier input stage.

[0061] Figure 4 This is the circuit diagram for the amplifier gain stage;

[0062] Figure 5 This is a circuit diagram of the push-pull output stage of an amplifier.

[0063] Figure 6 This is a circuit diagram for high-voltage level conversion;

[0064] Figure 7 Diagram of PMOS current limiting protection circuit;

[0065] Figure 8 Diagram of NMOS current limiting protection circuit;

[0066] Figure 9 This is a circuit diagram for over-temperature protection. Detailed Implementation

[0067] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0068] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0070] A high-voltage power amplifier with over-temperature and over-current protection circuitry, such as Figure 1 As shown, it includes:

[0071] The high-voltage operational amplifier core unit and the adaptive protection circuit unit include a rail-to-rail input stage, a gain amplification stage and an AB class push-pull output stage cascaded in sequence. The AB class push-pull output stage includes a PMOS upper power transistor and an NMOS lower power transistor.

[0072] The adaptive protection circuit unit includes a PMOS current limiting protection circuit, an NMOS current limiting protection circuit, and an over-temperature protection circuit.

[0073] The PMOS current limiting protection circuit is used to generate a low-voltage domain discrimination signal when the power transistor on the PMOS is overcurrent, and in conjunction with the high-voltage level conversion circuit, converts the low-voltage domain discrimination signal into a high-voltage domain overcurrent control signal.

[0074] The NMOS current limiting protection circuit is used to generate a low-voltage domain overcurrent control signal when the NMOS power transistor is overcurrent.

[0075] The over-temperature protection circuit is used to generate a low-voltage domain over-temperature shutdown signal when the amplifier over-temperatures, and in conjunction with the high-voltage level conversion circuit, converts the low-voltage domain over-temperature shutdown signal into a high-voltage domain over-temperature shutdown signal.

[0076] Specifically, this embodiment provides a high-voltage power amplifier with over-temperature and over-current protection functions. Its architecture is divided into a high-voltage operational amplifier core unit and an adaptive protection circuit unit. The high-voltage operational amplifier core unit operates in the high-voltage domain and consists of a cascaded rail-to-rail input stage, a gain amplification stage, and a Class AB push-pull output stage. The Class AB push-pull output stage includes a PMOS upper power transistor and an NMOS lower power transistor, used to realize rail-to-rail input, amplification, and high-current drive of the high-voltage signal. The adaptive protection circuit unit mainly operates in the low-voltage domain and integrates a PMOS current-limiting protection circuit, an NMOS current-limiting protection circuit, an over-temperature protection circuit, and a high-voltage level conversion circuit. The PMOS current-limiting protection circuit samples the current of the PMOS upper power transistor through a current mirror structure. When an overcurrent occurs, it generates a low-voltage domain discrimination signal. This low-voltage domain discrimination signal is converted to a high-voltage domain signal by the high-voltage level conversion circuit using a floating reference potential as a reference. The overcurrent control signal; the NMOS current limiting protection circuit directly generates a low-voltage domain overcurrent control signal when the NMOS power transistor experiences overcurrent; the overtemperature protection circuit simultaneously generates a high-voltage domain overtemperature shutdown signal and a low-voltage domain overtemperature shutdown signal when it detects amplifier overtemperature; the high-voltage domain overcurrent control signal and the high-voltage domain overtemperature shutdown signal are combined into a first gate clamp signal through a high-voltage domain logic AND operation, which is used to control an enable transistor to pull up the gate potential of the PMOS power transistor to near the high-voltage power supply to turn off the transistor; the low-voltage domain overcurrent control signal and the low-voltage domain overtemperature shutdown signal are combined into a second gate clamp signal through a low-voltage domain logic AND operation, which is used to control another enable transistor to pull down the gate potential of the NMOS power transistor to near ground potential to turn off the transistor, thereby achieving direct and reliable clamping shutdown protection of the output stage power transistor under a single fault condition of overcurrent or overtemperature through the floating reference potential generation and cross-voltage domain signal conversion mechanism.

[0077] The present invention is further configured such that the rail-to-rail input stage includes a first differential input pair and a second differential input pair connected in parallel;

[0078] The first differential input pair is a folded differential pair composed of PMOS transistors, and the second differential input pair is a folded differential pair composed of NMOS transistors.

[0079] The first differential input pair is configured to be in an active state when the input common-mode voltage is close to ground potential;

[0080] The second differential input pair is configured to be in an active state when the input common-mode voltage is close to the high-voltage power supply potential;

[0081] The first differential input pair and the second differential input pair are also configured to be in an effective working state simultaneously when the input common-mode voltage is higher than the turn-on threshold of the first differential input pair and lower than the turn-off threshold of the second differential input pair.

[0082] The first differential input pair and the second differential input pair are jointly configured to enable the high-voltage power amplifier to cover the entire voltage range from ground potential to the high-voltage power supply potential; specifically, this embodiment combines... Figure 3The circuit architecture and working principle of the rail-to-rail input stage are described in detail. The core of this stage lies in the use of an input stage circuit structure consisting of two parallel differential input pairs. The rail-to-rail input stage includes a first differential input pair and a second differential input pair connected in parallel. The first differential input pair is composed of PMOS transistors connected in a folded differential configuration, and the second differential input pair is composed of NMOS transistors connected in a folded differential configuration. To ensure reliable operation under high voltage power, the key transistor components in these two differential input pair circuits that directly withstand high voltage stress are all implemented as high-voltage metal-oxide-semiconductor field-effect transistors with high drain-source breakdown voltage. Specifically, in the first differential input pair, the transistors whose source or drain potential may fluctuate to high voltage with the signal use high-voltage PMOS devices. In the second differential input pair, the transistors facing similar voltage stress use high-voltage NMOS devices, thus ensuring the safety of the entire input stage under high-voltage conditions from a physical perspective. The principle of this parallel structure to achieve rail-to-rail input function is based on the different conduction characteristics of PMOS and NMOS transistors. When the input common-mode voltage is close to ground potential, the PMOS differential pair enters an effective amplification state and dominates signal transmission due to the large absolute value of the gate-source voltage, while the NMOS differential pair is in the cutoff state due to insufficient gate-source voltage. When the common-mode voltage approaches the high-voltage power supply potential, the situation reverses. The NMOS differential pair is fully turned on and becomes the dominant path, while the PMOS differential pair tends to turn off. When the input common-mode voltage is at an intermediate level, i.e., higher than the minimum threshold for the PMOS differential pair to be effectively turned on but lower than the maximum threshold for the NMOS differential pair to be completely turned off, both pairs of differential input transistors are turned on simultaneously and participate in amplification together, making the total transconductance of the input stage the sum of the two, thereby ensuring the continuity of signal transmission without dead zones throughout the entire voltage range. The input voltage range achieved by the input stage circuit structure is determined by the minimum overdrive voltage or saturation voltage margin required for the normal operation of its internal transistors. For the PMOS... For the stacked differential pair, the linear operating region requires the input common-mode voltage to be no lower than the smaller of the sum of the ground potential and the minimum voltage required to prevent all transistors connected in series in the branch from entering the linear region. With proper circuit parameter design, the lower limit of this condition can reach the ground potential. For the NMOS folded differential pair, the linear operating region requires the input common-mode voltage to be no higher than the larger of the positive power supply voltage and the sum of the positive power supply voltage and the minimum voltage required to prevent all transistors connected in series in the branch from entering the linear region. With proper circuit parameter design, the upper limit of this condition can reach the positive power supply voltage. Thus, the circuit strictly achieves complete coverage of the input differential signal terminal voltage range from the ground potential to the positive power supply voltage.By precisely designing the dimensions, bias current, and level shift parameters of each transistor in the two differential input pairs, their respective effective operating voltage windows can be finely controlled. This ultimately allows for a smooth transition and complete coverage of the operating characteristics of the PMOS differential pair under low common-mode voltage and the NMOS differential pair under high common-mode voltage. Consequently, the common-mode voltage acceptance range of the input stage continuously extends from ground potential to the high-voltage power supply potential, achieving complete rail-to-rail input capability and fundamentally solving the problem of limited input range in high-voltage amplifiers.

[0083] The present invention is further configured such that the gain amplification stage is connected between the on-rail to on-rail input stage and the Class AB push-pull output stage;

[0084] The gain amplifier stage is configured to receive and sum the output currents of the first differential input pair and the second differential input pair;

[0085] The gain amplification stage includes a folded cascode structure, which includes a first group of cascode transistors and a second group of cascode transistors.

[0086] The gain amplification stage also includes a first auxiliary amplifier and a second auxiliary amplifier;

[0087] The output terminal of the first auxiliary amplifier is connected to the gate of the first group of common-source cascode transistors to increase the output impedance of the first group of common-source cascode transistors;

[0088] The output of the second auxiliary amplifier is connected to the gate of the second group of cascode transistors to increase the output impedance of the second group of cascode transistors; specifically, this embodiment combines... Figure 4The circuit architecture and working principle of the gain amplifier stage are described in detail. This gain amplifier stage is connected between the rail-to-rail input stage and the Class AB push-pull output stage. The gain amplifier stage circuit adopts a folded cascode structure, which includes two independent pairs of cascode transistors. One pair of cascode transistors is mainly used to receive and transmit the signal current from the PMOS differential input pair in the input stage, while the other pair is mainly used to receive and transmit the signal current from the NMOS differential input pair in the input stage. These two signal currents are combined at a specific summing node inside the gain amplifier stage, thereby ensuring the signal current across the entire input common-mode voltage range. Within this range, regardless of whether the input stage uses PMOS differential pairs, NMOS differential pairs, or both, the signal current can be continuously and completely transmitted to subsequent circuits. To achieve a voltage gain higher than that of the basic folded cascode structure, this amplification gain stage configures a dedicated auxiliary operational amplifier for each cascode transistor pair, namely a first auxiliary amplifier and a second auxiliary amplifier. The output of the first auxiliary amplifier is connected to the control gate of the core transistor in the cascode transistor pair serving the PMOS differential pair, which performs the cascode amplification function. The output of the second auxiliary amplifier is connected to the corresponding core transistor in the cascode transistor pair serving the NMOS differential pair. The control gate of the transistor; these auxiliary amplifiers are configured as voltage operational amplifiers with high DC gain, their inputs connected to the source of the cascode transistor they control or a critical relay node in the branch to continuously monitor the node potential; their gain boosting mechanism is that when a change in signal current causes a small AC signal voltage fluctuation at the source node of the cascode transistor, the auxiliary amplifier connected thereto immediately senses this change and then generates a correction voltage at its output, i.e., the gate of the cascode transistor, that is inversely phase and amplified. This local negative feedback effect theoretically keeps the AC potential of the cascode transistor source constant, thereby suppressing The change in AC signal current flowing through the transistor, analyzed from the small-signal equivalent model of the circuit, shows that the feedback effect is equivalent to increasing the small-signal output resistance of the cascode transistor by approximately a multiple of the DC gain of the auxiliary amplifier itself. Since the total voltage gain of the gain amplifier stage is proportional to the product of the effective transconductance of the input stage and the total equivalent output impedance looking inward from the output node of the stage, and this total equivalent output impedance is mainly composed of the parallel connection of the output resistances of the two cascode branches enhanced by the auxiliary amplifier, the total voltage gain of the entire gain amplifier stage is increased by the same order of magnitude after the output impedance of each branch is increased by an order of magnitude through the auxiliary amplifier.In high-voltage circuit design, transistors located in the main signal path and potentially subjected to high voltages, including specific cascode transistors, active load transistors, and bias current source transistors, are implemented using high-voltage-resistant metal-oxide-semiconductor field-effect transistors (MOSFETs). Other transistors processing small signals or operating in low-voltage regions utilize conventional low-voltage devices. This hybrid design ensures high voltage tolerance while achieving high voltage gain, providing the amplifier with the required high open-loop gain.

[0089] The present invention is further configured such that the AB class push-pull output stage includes a PMOS upper power transistor, an NMOS lower power transistor, and a bias circuit;

[0090] The source of the PMOS upper power transistor is connected to a high-voltage power supply, and its drain is connected to the output terminal together with the drain of the NMOS lower power transistor. The source of the NMOS lower power transistor is grounded.

[0091] The bias circuit includes a transcontinental linear loop structure connected between the gates of the PMOS upper power transistor and the NMOS lower power transistor, used to dynamically clamp the voltage difference between the two gates and provide a static bias current for the PMOS upper power transistor and the NMOS lower power transistor; specifically, this embodiment combines Figure 5The circuit architecture and working principle of the AB-class push-pull output stage are described in detail. This AB-class push-pull output stage serves as the final driver stage of the amplifier, employing AB-class operation to balance high output current drive capability and low quiescent power consumption. The AB-class push-pull output stage includes a PMOS upper power transistor, an NMOS lower power transistor, and a bias circuit providing bias. The source of the PMOS upper power transistor is connected to a high-voltage power supply, and its drain is connected to the drain of the NMOS lower power transistor, together forming the amplifier's output terminal. The source of the NMOS lower power transistor is connected to ground. The bias circuit includes a circuit connected to... The transcontinuous linear loop structure between the gate of the PMOS upper power transistor and the gate of the NMOS lower power transistor consists of multiple transistors connected in a diode configuration and one or more transistors controlled by the preceding stage signal connected in series. Its function is to dynamically establish and maintain the voltage difference between the two gates, thereby providing a small and stable static bias current for the PMOS upper power transistor and the NMOS lower power transistor. Its static bias principle is based on Kirchhoff's voltage law followed by the transcontinuous linear loop, that is, the sum of the gate-source voltages of all transistors in the loop satisfies a closed loop relationship. When all transistors in the loop are operating in the saturation region, according to the crystal... The square-law characteristic of the transistor means its gate-source voltage is a function of its drain current and the width-to-length ratio of the device channel. By setting the width-to-length ratio of each transistor in the loop and its reference bias current, the static current values ​​flowing through the PMOS upper power transistor and the NMOS lower power transistor can be uniquely determined and set according to the equation containing the ratio of the square root of the drain current to the square root of its width-to-length ratio. This ensures that when there is no input signal, both the PMOS upper power transistor and the NMOS lower power transistor are in a slightly conducting state, thereby eliminating crossover distortion in the zero-crossing region of the output waveform caused by the alternating conduction of transistors. During dynamic operation, when the current stage drive signal is generated... The transconducting linear loop can quickly respond to and adjust the gate voltages of the two power transistors. The mechanism is that the differential current injected in the previous stage changes the current of the transistors in the loop, and then forces the gate voltage difference of the two power transistors to change accordingly through the loop constraint conditions. For example, when the output terminal needs to provide pull-down current, the loop mechanism will reduce the gate voltage of the lower NMOS power transistor and enhance its conduction, while increasing the gate voltage of the upper PMOS power transistor and weakening its conduction until it is turned off, thereby achieving efficient unidirectional supply of large current. The reverse is also true. This mechanism ensures that the output stage can quickly provide large drive current and maintain extremely low power consumption in the static state.Given that this output stage operates directly between the high-voltage power supply and ground, most of the transistors in its circuit, especially the power transistors themselves and the transistors in the bias loop that directly withstand high voltage, are implemented using high-voltage resistant metal-oxide-semiconductor field-effect transistors. Only a few transistors processing small-swing control signals or operating at local low-voltage nodes can use conventional low-voltage devices. This hybrid design optimizes the overall circuit performance while ensuring high-voltage tolerance.

[0092] The present invention is further configured such that the high-voltage level conversion circuit is a clamping high-voltage level conversion circuit, including a differential common-source common-gate voltage switch composed of conventional MOS transistors and a clamping structure composed of high-voltage resistant MOS transistors;

[0093] The differential common-source cascode voltage switch is used to receive input signals in the low-voltage domain;

[0094] The gates of the high-voltage MOS transistors in the clamping structure are respectively connected to a low-voltage power supply or a floating reference potential to limit the voltage swing of the internal nodes of the high-voltage level conversion circuit.

[0095] The high-voltage level conversion circuit is configured to use the clamping structure to convert the input signal of the low-voltage domain into a high-voltage domain control signal based on the floating reference potential.

[0096] The floating reference potential is configured to follow the potential changes of the high-voltage power supply, and the voltage difference between the floating reference potential and the high-voltage power supply potential is limited to a preset safe voltage range; specifically, this embodiment combines... Figure 6The high-voltage level conversion circuit is described in detail. This circuit aims to achieve level conversion between a low-voltage logic signal referenced to system ground potential and a high-voltage power control signal referenced to the floating reference potential. Its circuit structure consists of a low-voltage differential common-source common-gate voltage switch and a high-voltage-resistant transistor clamping structure integrated on its high-voltage side. The low-voltage differential common-source common-gate voltage switch receives low-voltage complementary discrimination signals from a PMOS current-limiting protection circuit or an over-temperature protection circuit and performs current path switching. The clamping structure consists of multiple high-voltage-resistant transistors, whose gates are respectively fixedly connected to the low-voltage power supply or the aforementioned voltage level. A floating reference potential is used in this connection method to allow the high-voltage transistor to operate in a specific state, dynamically limiting the voltage swing of critical internal nodes. This ensures that the voltage does not exceed the withstand voltage limit of the low-voltage transistor. Simultaneously, because the gate-source voltage is fixed, its static on-current is maintained at an extremely low level, thereby reducing the static power consumption inherent in traditional clamping methods. The floating reference potential is generated by the turn-off potential generation circuit of the PMOS current-limiting protection circuit. Its potential value follows the changes in the high-voltage power supply and maintains a fixed voltage difference between it and the high-voltage power supply within a preset safe voltage range. This voltage difference is designed not to exceed the reliable gate oxide withstand voltage of conventional low-voltage transistors, thus constructing an internal voltage difference safety system. The controllable high-voltage floating operating region protects the control circuit devices operating within this region from overvoltage stress. The signal conversion principle is illustrated using the input signal transition from low to high level as an example. In the initial steady state, the input signal turns on the corresponding low-voltage NMOS transistor and its series-connected high-voltage NMOS clamp transistor, forming a pull-down path and pulling down the internal node voltage at the drain of the high-voltage NMOS clamp transistor. This voltage drop causes the high-voltage PMOS clamp transistor connected between this node and the high-voltage power supply to enter saturation. This high-voltage PMOS clamp transistor then rapidly pulls down the voltage at another internal node connected to its source. This voltage change leads to… When the low-voltage PMOS transistor on the other side of the differential cascode voltage switch is turned on, current is drawn from the high-voltage power supply path through the high-voltage PMOS clamping transistor on the corresponding side, and the final output node potential is pulled up. At the same time, the previously turned-on low-voltage NMOS transistor tends to turn off due to the high gate input signal, which weakens the pull-down effect on the output node. This chain reaction constitutes a positive feedback process, which causes the circuit state to flip rapidly until the output node voltage is close to the high-voltage power supply potential and the corresponding internal node voltage is close to the floating reference potential, thereby completing the conversion to the high-voltage domain logic high level. When the input signal jumps from high level to low level, the working principle is symmetrical and opposite.This high-voltage level conversion circuit integrates a low-static-power active clamping mechanism into a differential cascode switch architecture and combines it with a floating reference potential that dynamically follows the high-voltage power supply to construct a safe high-voltage floating operating domain. This design not only ensures the operational safety of the low-voltage control logic in a high-voltage environment, preventing device breakdown, but also achieves lossless and rapid transmission of protection signals from the low-voltage control domain to the high-voltage power execution domain. This provides a key technological foundation for directly and safely controlling the turn-off operation of the high-voltage side PMOS power transistor, thereby solving the problem of floating gate potential of the PMOS power transistor caused by the inability of traditional protection circuits to safely generate an effective turn-off level in the high-voltage domain.

[0097] The present invention is further configured such that the PMOS current limiting protection circuit includes a turn-off potential generation circuit, a high voltage sampling circuit, a current comparator, a rectifier circuit, and a high voltage level conversion circuit;

[0098] The shutdown potential generation circuit is connected between the high-voltage power supply and ground to generate a floating reference potential that follows the changes in the high-voltage power supply potential.

[0099] The high-voltage sampling circuit is powered by a high-voltage power supply and includes a sampling PMOS transistor. The gate of the sampling PMOS transistor is connected to the gate of the PMOS power transistor, and its source and drain are connected in parallel with the source and drain of the PMOS power transistor, respectively, to form a current mirror and replicate the load current of the PMOS power transistor according to a preset ratio to generate a sampling current.

[0100] The current comparator is powered by a low-voltage power supply. Its input terminal receives the sampled current and is used to compare the voltage converted from the sampled current with a preset first reference voltage threshold. When the voltage of the sampled current is greater than the preset first reference voltage threshold, it outputs a level flip signal.

[0101] The input terminal of the rectifier circuit is connected to the output terminal of the current comparator, and is used to shape the level-flipping signal to output a low-voltage domain discrimination signal.

[0102] The input terminal of the high-voltage level conversion circuit is connected to the output terminal of the rectifier circuit, and is used to convert the low-voltage domain discrimination signal into a high-voltage domain overcurrent control signal based on the floating reference potential; specifically, this embodiment combines Figure 7The PMOS current limiting protection circuit is described in detail. This circuit is the core component of the adaptive protection circuit unit, providing overcurrent protection for the high-voltage side power transistors. It is used to detect and protect the PMOS power transistors in the Class AB push-pull output stage from overcurrent. The circuit mainly consists of a turn-off potential generation circuit, a high-voltage sampling circuit, a current comparator, a rectifier circuit, and a high-voltage level conversion circuit connected sequentially. Each functional module is powered by either a high-voltage or low-voltage power supply according to the signal level and withstand voltage requirements it processes, optimizing power consumption and reliability. The turn-off potential generation circuit is connected between the high-voltage power supply and ground. Its circuit consists of multiple PMOS transistors, NMOS transistors, and preset resistors connected in series according to a preset topology. The design allows for the series connection to be optimized. The connected PMOS transistors have a consistent channel width-to-length ratio, ensuring that they have the same source-gate voltage when turned on. Based on Kirchhoff's voltage law for this series circuit, its output floating reference potential is always numerically lower than a constant voltage value of the high-voltage power supply, determined by the number of series transistors and their on-state voltage drop. This voltage difference is designed within the safe withstand voltage range of the gate oxide layer of conventional low-voltage transistors, thus forming a floating ground potential that dynamically follows the changes in the high-voltage power supply while maintaining a safe and fixed voltage difference. Using this floating reference potential as a reference ground, together with the high-voltage power supply, a high-voltage floating operating domain with a safe low internal potential difference is defined. This allows subsequent circuits that need to operate under this high-voltage environment to control the gate of the PMOS transistors to operate safely within this high-voltage environment. The circuit operates reliably within the voltage domain. The high-voltage sampling circuit operates in the high-voltage power supply domain, and its core is a small-sized sampling PMOS transistor. The gate of this transistor is connected to the gate of the PMOS power transistor, and its source and drain are connected in parallel with the source and drain of the PMOS power transistor, respectively, thus forming a current mirror structure. By designing the channel width-to-length ratio between the sampling PMOS transistor and the PMOS power transistor, the current flowing through the sampling PMOS transistor mirrors the load current of the PMOS power transistor according to a preset ratio; this current is the sampling current. The current comparator operates in the low-voltage power supply domain and internally contains two symmetrical branches with paired transistors, but the resistance values ​​of the resistors connected in series between the two branches are designed to be different. Under static operating conditions without sampling current injection, the bias current mirror network inside the current comparator provides a definite initial bias current for the two branches. Since the transistor parameters are perfectly matched but the series resistance values ​​are different, according to the current-voltage characteristics of the metal-oxide-semiconductor field-effect transistor in the saturation region, the two branches will automatically stabilize at two different static currents. The branch with the larger series resistance value will stabilize at the larger static current. This state constitutes the initial balance and output of the current comparator under no overcurrent conditions. The overcurrent protection threshold is set by the internal parameter relationship of the circuit structure. Its essence corresponds to a preset first reference voltage threshold determined by the resistance ratio of the two branches inside the current comparator, the transconductance parameter of the transistor, and the width-to-length ratio.When the sampling current increases and is injected into a specific branch of the current comparator, it disrupts the internal current balance and generates an additional voltage drop across its resistor, causing the voltage at a critical node in that branch to rise. When this node voltage rises above the preset first reference voltage threshold and causes a connected detection NMOS transistor to switch from the off state to the on state, it triggers subsequent cascaded amplification and logic switching processes, ultimately causing a deterministic switch in the logic state of the current comparator output. The sampling current corresponding to this switch is the overcurrent protection point of the circuit. The rectifier circuit is connected to the output of the current comparator and is typically composed of a multi-stage inverter chain. It is used to shape the waveform and enhance the driving capability of the logic switching signal output by the current comparator, which may not be steep enough on the transition edge or may be superimposed with circuit noise. This circuit can suppress noise spikes in the signal and generate a low-voltage domain discrimination signal with a steep edge, clear logic level, and sufficient driving capability. The input of the high-voltage level conversion circuit is connected to... The low-voltage domain discrimination signal is received, and using the floating reference potential provided by the shutdown potential generation circuit, the low-voltage domain discrimination signal is safely and quickly switched to the aforementioned high-voltage floating operating domain, thereby outputting a high-voltage domain overcurrent control signal with the floating reference potential as the reference potential. This high-voltage domain overcurrent control signal is ultimately transmitted to the gate control path of the PMOS power transistor to control an enable transistor connected in series between the gate of the PMOS power transistor and the high-voltage power supply. When the circuit is operating normally and no overcurrent occurs, the high-voltage domain overcurrent control signal is at an inactive level, the enable transistor is off, and it does not affect the normal operation of the PMOS power transistor. When the overcurrent condition is met, the high-voltage domain overcurrent control signal becomes active, driving the enable transistor to fully conduct, thereby rapidly pulling the gate potential of the PMOS power transistor up to a potential close to the high-voltage power supply through the low-resistance path, forcing the PMOS power transistor to immediately turn off, achieving fast and direct overcurrent protection and gate potential clamping.

[0103] The present invention is further configured such that the NMOS current limiting protection circuit includes a sampling circuit, a current comparator, and a shaping circuit;

[0104] The sampling circuit includes a sampling NMOS transistor, the gate of which is connected to the gate of the NMOS lower power transistor, and its source and drain are connected in parallel with the source and drain of the NMOS lower power transistor, respectively, to replicate the current flowing through the NMOS lower power transistor according to a preset ratio to generate a sampling current.

[0105] The current comparator is powered by a low-voltage power supply. Its input terminal receives the sampled current and is used to compare the voltage converted from the sampled current with a preset second reference voltage threshold. When the voltage of the sampled current is greater than the preset second reference voltage threshold, it outputs a level flip signal.

[0106] The input terminal of the shaping circuit is connected to the output terminal of the current comparator, used to shape the level-flipping signal and output a low-voltage overcurrent control signal for controlling the gate potential of the NMOS power transistor; specifically, this embodiment combines Figure 8 The NMOS current limiting protection circuit is described in detail. This circuit is used to perform overcurrent detection and protection on the NMOS lower power transistor in the Class AB push-pull output stage. The entire circuit operates in the low-voltage power supply domain and includes three main parts: a sampling circuit, a current comparator, and a shaping circuit. The sampling circuit uses a sampling NMOS transistor, whose gate is connected to the gate of the NMOS lower power transistor, and whose source and drain are connected in parallel with the source and drain of the NMOS lower power transistor, respectively, thus forming a current mirror structure with the NMOS lower power transistor. By setting the sampling NMOS transistor and the NMOS lower power transistor... The channel width-to-length ratio between the lower power transistors ensures that the current flowing through the sampling NMOS transistor replicates the load current of the lower power transistor according to a preset ratio; this current is the sampling current. The current comparator is powered by a low-voltage supply, and its function is to convert the sampling current into a voltage and compare it with a preset second reference voltage threshold inside the current comparator. Specifically, the sampling current is guided to an integrated resistor in the input branch of the current comparator to generate a voltage drop proportional to the sampling current. This voltage drop is applied to a matched differential input structure inside the current comparator. The preset second reference voltage threshold inside the current comparator... The second reference voltage threshold is set by the ratio of the series resistors in its two branches and the size ratio of the relevant transistors. Under normal conditions, when the sampling current is zero, the two branches reach a static balance due to the difference in resistance values ​​and the matching of transistor sizes. When the sampling current is injected and increases, the additional voltage generated across the resistors disrupts this balance. Once this voltage effect exceeds the preset second reference voltage threshold determined by the ratio of the branch resistances, the transconductance parameters of the transistors, and their aspect ratio, the output state of the current comparator flips and generates a level-to-level switching signal. The shaping circuit is connected to the output of the current comparator. It typically consists of multiple inverters or Schmitt triggers, used to shape the waveform, filter noise, and enhance the driving capability of the level-flipping signal, ultimately outputting a low-voltage overcurrent control signal with steep edges and a clear logic level. This low-voltage overcurrent control signal is directly sent to the gate control path of the NMOS lower power transistor, which can pull down the gate potential of the NMOS lower power transistor when an overcurrent occurs, thereby forcibly limiting its output current and achieving fast clamping protection. Since the source of the NMOS lower power transistor is directly grounded and its gate control uses ground as the potential reference, the entire protection circuit does not require high-voltage level conversion.

[0107] The present invention is further configured such that the over-temperature protection circuit includes a bandgap reference circuit, a programmable resistor voltage divider network, a transmission gate, a high-gain comparator, a hysteresis shaping circuit, and a high-voltage level conversion circuit;

[0108] The bandgap reference circuit is used to generate a reference voltage and a negative temperature coefficient voltage.

[0109] The programmable resistor divider network is connected to a negative temperature coefficient voltage and is configured to generate an independently adjustable first programmable voltage divider and a second programmable voltage divider based on digital configuration codes.

[0110] The input terminal of the transmission gate is connected to the output terminal of the programmable resistor divider network, and its control terminal is connected to the feedback output terminal of the over-temperature protection circuit, for selecting to output the first programmable voltage divider or the second programmable voltage divider according to the feedback signal.

[0111] The first input terminal of the high-gain comparator is connected to the output terminal of the transmission gate, and its second input terminal is connected to the reference voltage. It is used to compare the selected programmable voltage divider with the reference voltage and output a comparison signal.

[0112] The input terminal of the hysteresis shaping circuit is connected to the output terminal of the high-gain comparator, and is used to perform hysteresis processing and waveform shaping on the comparison signal to generate a low-voltage domain over-temperature shutdown signal.

[0113] The input terminal of the high-voltage level conversion circuit is connected to the output terminal of the hysteresis shaping circuit, and is used to convert the low-voltage domain over-temperature shutdown signal into a high-voltage domain over-temperature shutdown signal; specifically, this embodiment combines... Figure 9 A detailed description of the over-temperature protection circuit is required, and it must be clearly stated that... Figure 9 As a schematic diagram of the core architecture of the over-temperature protection circuit, its voltage divider circuit section abstractly represents the voltage divider function using a general fixed resistor symbol. In the specific implementation of this embodiment, the specific circuit implementation of this voltage divider function is a programmable resistor voltage divider network. The connection position of this programmable resistor voltage divider network in the over-temperature protection circuit is... Figure 9The corresponding input and output nodes of the voltage divider circuit shown correspond to each other. This over-temperature protection circuit operates in the low-voltage power domain. It continuously compares a temperature-insensitive reference voltage generated by an internal bandgap reference circuit with a negative temperature coefficient voltage derived from the same circuit, whose voltage value decreases approximately linearly with increasing amplifier junction temperature. This enables monitoring of the amplifier junction temperature and provides programmable over-temperature protection. The circuit includes a bandgap reference circuit, a programmable resistor divider network, a transmission gate, a high-gain comparator, a hysteresis shaping circuit, and a high-voltage level conversion circuit. The bandgap reference circuit generates the reference voltage and the negative temperature coefficient voltage. The input of the programmable resistor divider network is connected to the negative temperature coefficient voltage. It consists of a precision resistor string and multiple sets of analog switches controlled by digital signals. The precision resistor string is composed of multiple unit resistors with high precision and consistent temperature characteristics connected in series between the negative temperature coefficient voltage and ground potential to form a series of voltage divider nodes with a defined proportional relationship. Each set of analog switches contains multiple switch units arranged in parallel. The control terminals of each switch unit are connected to a corresponding output terminal of a digital configuration decoder. Its current path selectively connects a specific voltage divider node of the resistor string to a voltage output terminal of the programmable resistor voltage divider network. The input terminal of the digital configuration decoder receives a multi-bit digital configuration code, which can be stored in a non-volatile configuration register inside the amplifier. The digital configuration code can be written during system operation via an external communication interface. The decoder decodes the digital configuration code, controlling the corresponding analog switch group to conduct, thereby selecting and outputting the voltages of the two voltage divider nodes specified by the code on the resistor string as a first programmable voltage divider and a second programmable voltage divider. By changing the value of the digital configuration code, the specific voltage divider nodes conducted by the analog switch group can be adjusted independently and precisely, thereby continuously or incrementally adjusting the voltage division ratio of the first and second programmable voltage dividers relative to the negative temperature coefficient voltage. The value of the first programmable voltage divider corresponds to a programmable shutdown temperature threshold uniquely set by the current digital configuration code. The value of the second programmable voltage divider corresponds to a programmable recovery temperature threshold, which is independently set by the current digital configuration code and is different from the shutdown threshold. The two voltage input terminals of the transmission gate are respectively connected to the two output terminals of the programmable resistor divider network to receive the first programmable voltage divider and the second programmable voltage divider. The control terminal of the transmission gate is electrically connected to the feedback output terminal of the over-temperature protection circuit itself, that is, the complementary logic signal pair output by the hysteresis shaping circuit. One differential input terminal of the high-gain comparator is connected to the output terminal of the transmission gate to receive the programmable voltage divider currently selected and output by the transmission gate, and its other differential input terminal is connected to the reference voltage.The input of the hysteresis shaping circuit is connected to the output of the high-gain comparator. It includes a Schmitt trigger and a multi-stage inverter chain, used to perform hysteresis processing and waveform edge shaping on the comparison signal output by the high-gain comparator to generate a logic-level stable low-voltage domain over-temperature shutdown signal and its complementary logic signal. The input of the high-voltage level conversion circuit is connected to the output of the hysteresis shaping circuit, used to convert the low-voltage domain over-temperature shutdown signal to a high-voltage level with the high-voltage power supply and floating reference potential as the operating voltage domain, thereby generating a high-voltage domain over-temperature shutdown signal. This high-voltage domain over-temperature shutdown signal is used to control the turn-off of the PMOS power transistor in the AB push-pull output stage. The over-temperature protection circuit... The principle of programmable threshold protection is based on the linear inverse relationship between the negative temperature coefficient voltage and the amplifier's absolute junction temperature, and that the programmable voltage divider is the negative temperature coefficient voltage scaled by a variable scaling factor controlled by digital configuration code. Therefore, when the amplifier temperature changes and causes the first programmable voltage divider to drop to equal the reference voltage, the corresponding precise junction temperature is the programmable shutdown temperature threshold set by the current digital configuration code. Similarly, when the second programmable voltage divider rises to equal the reference voltage, the corresponding junction temperature is the programmable recovery temperature threshold set by the current digital configuration code. By adjusting the digital configuration code, the programmable threshold protection can be changed. The voltage division ratio of the programmable resistor divider network allows for independent, continuous, or step-by-step precise setting and adjustment of the turn-off temperature threshold, the recovery temperature threshold, and the size of the temperature hysteresis window between them. In the specific operation of the over-temperature protection circuit, its initial state is set at the moment of power-on or reset from the over-temperature protection state. At this time, under the control signal of the transmission gate (i.e., the complementary logic signal from the hysteresis shaping circuit), the first programmable voltage divider is selected and output to the corresponding input terminal of the high-gain comparator. As the high-voltage power amplifier's junction temperature rises due to power consumption during operation, the negative temperature coefficient voltage decreases linearly, thereby enabling the first programmable voltage divider to... The programmable voltage divider decreases synchronously; when the amplifier temperature reaches the shutdown temperature threshold set by the current digital configuration code, the first programmable voltage divider decreases to be equal to the reference voltage, causing the output state of the high-gain comparator to flip; after this flip signal is processed by the hysteresis shaping circuit, the output low-voltage domain over-temperature shutdown signal jumps to an effective logic level; one of this effective logic levels is used to directly shut down the lower NMOS power transistor, and the other is converted by the high-voltage level conversion circuit to shut down the upper PMOS power transistor; at the same time, the complementary logic signal generated by the hysteresis shaping circuit is fed back to the control terminal of the transmission gate to control its switching selection state so as to output the second programmable voltage divider to the high-gain comparator;Subsequently, only when the amplifier temperature drops, causing the negative temperature coefficient voltage to rise again, thus raising the second programmable voltage divider to equal the reference voltage once more, does the high-gain comparator flip again, causing the over-temperature protection circuit to reset entirely. The low-voltage domain over-temperature shutdown signal returns to an invalid logic level, and the transmission gate switches back to its initial gated state. This closed-loop control process implements an overheat protection function with a programmable temperature hysteresis window, effectively preventing thermal oscillations caused by temperature fluctuations near the protection point. This embodiment replaces the traditional fixed-value voltage divider network with a programmable resistor voltage divider network controlled by digital configuration code, transforming the shutdown temperature threshold, recovery temperature threshold, and hysteresis window width of the over-temperature protection circuit from fixed parameters into system variables that can be flexibly configured through the digital configuration code.

[0114] The present invention further comprises, wherein the adaptive protection circuit unit includes a signal synthesis circuit, used to logically combine the high-voltage domain overcurrent control signal, the low-voltage domain overcurrent control signal, the high-voltage domain overtemperature shutdown signal, and the low-voltage domain overtemperature shutdown signal to generate gate clamp signals that respectively control the shutdown of the PMOS upper power transistor and the NMOS lower power transistor; the present invention further comprises, wherein the signal synthesis circuit includes a first AND gate and a second AND gate; the first AND gate uses the high-voltage power supply as its power supply terminal and the floating reference potential in the PMOS current limiting protection circuit as its reference ground, its first input terminal receives the high-voltage domain overcurrent control signal output by the PMOS current limiting protection circuit, and its second input terminal receives the overtemperature shutdown signal. The high-voltage over-temperature shutdown signal output by the protection circuit outputs a first gate clamp signal for shutting down the PMOS upper power transistor. The second AND gate uses a low-voltage power supply as its power source and ground potential as its reference. Its first input receives the low-voltage overcurrent control signal output by the NMOS current limiting protection circuit, its second input receives the low-voltage over-temperature shutdown signal output by the over-temperature protection circuit, and its output outputs a second gate clamp signal for shutting down the NMOS lower power transistor. Specifically, the signal synthesis circuit consists of a first AND gate and a second AND gate, used to generate the final shutdown signals controlling the PMOS upper power transistor and the NMOS lower power transistor, respectively. The AND gate operates in the high-voltage floating power domain defined by the high-voltage power supply and the floating reference potential generated by the PMOS current-limiting protection circuit. Its first input receives a high-voltage domain overcurrent control signal from the PMOS current-limiting protection circuit (after level conversion), and its second input receives a high-voltage domain over-temperature shutdown signal from the over-temperature protection circuit. Its output outputs a first gate clamp signal. When either input receives a valid logic level indicating a fault, the first AND gate outputs a valid first gate clamp signal. This signal drives an enable transistor connected in series between the gate of the PMOS power transistor and the high-voltage power supply to turn on, thereby pulling the gate potential of the PMOS power transistor up to near the high-voltage power supply voltage. The second AND gate operates in the low-voltage power domain defined by the low-voltage power supply and system ground potential. Its first input receives the low-voltage domain overcurrent control signal from the NMOS current limiting protection circuit, its second input receives the low-voltage domain overtemperature shutdown signal from the overtemperature protection circuit, and its output outputs the second gate clamp signal. When either input receives a valid logic level indicating a fault, the second AND gate outputs a valid second gate clamp signal. This signal drives an enable transistor connected in series between the gate of the NMOS power transistor and ground to turn on, thereby pulling down the gate potential of the NMOS power transistor to near ground potential to achieve forced shutdown of the transistor.This signal synthesis circuit performs logical AND operations on overcurrent and overtemperature fault signals in different voltage domains, ensuring that the corresponding output stage power transistor can be directly and forcibly shut down when either overcurrent or overtemperature fault condition occurs, thereby achieving fast and reliable system protection.

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high-voltage power amplifier with over-temperature and over-current protection circuit, comprising a high-voltage operational amplifier core unit and an adaptive protection circuit unit, characterized in that, The core unit of the high-voltage operational amplifier includes a rail-to-rail input stage, a gain amplification stage and a Class AB push-pull output stage cascaded in sequence. The Class AB push-pull output stage includes a PMOS upper power transistor and an NMOS lower power transistor. The adaptive protection circuit unit includes a PMOS current limiting protection circuit, an NMOS current limiting protection circuit, and an over-temperature protection circuit. The PMOS current limiting protection circuit is used to generate a low-voltage domain discrimination signal when the power transistor on the PMOS is overcurrent, and in conjunction with the high-voltage level conversion circuit, converts the low-voltage domain discrimination signal into a high-voltage domain overcurrent control signal. The NMOS current limiting protection circuit is used to generate a low-voltage domain overcurrent control signal when the NMOS power transistor is overcurrent. The over-temperature protection circuit is used to generate a low-voltage domain over-temperature shutdown signal when the amplifier over-temperatures, and in conjunction with the high-voltage level conversion circuit, converts the low-voltage domain over-temperature shutdown signal into a high-voltage domain over-temperature shutdown signal. The adaptive protection circuit unit further includes a signal synthesis circuit for logically combining the high-voltage domain overcurrent control signal, the low-voltage domain overcurrent control signal, the high-voltage domain over-temperature shutdown signal, and the low-voltage domain over-temperature shutdown signal to generate gate clamping signals that respectively control the shutdown of the PMOS upper power transistor and the NMOS lower power transistor. The signal synthesis circuit includes a first AND gate and a second AND gate. The first AND gate uses the high-voltage power supply as its power source and the floating reference potential in the PMOS current limiting protection circuit as its reference ground. Its first input terminal receives the PMOS current limiting protection signal. The high-voltage domain overcurrent control signal output by the circuit has its second input terminal receiving the high-voltage domain over-temperature shutdown signal output by the over-temperature protection circuit, and its output terminal outputting the first gate clamp signal for shutting down the PMOS upper power transistor; the second logic AND gate uses the low-voltage power supply as its power supply terminal and ground potential as its reference ground, its first input terminal receiving the low-voltage domain overcurrent control signal output by the NMOS current limiting protection circuit, its second input terminal receiving the low-voltage domain over-temperature shutdown signal output by the over-temperature protection circuit, and its output terminal outputting the second gate clamp signal for shutting down the NMOS lower power transistor.

2. A high-voltage power amplifier with over-temperature and over-current protection circuit according to claim 1, characterized in that, The rail-to-rail input stage includes a first differential input pair and a second differential input pair connected in parallel; The first differential input pair is a folded differential pair composed of PMOS transistors, and the second differential input pair is a folded differential pair composed of NMOS transistors. The first differential input pair is configured to be in an active state when the input common-mode voltage is close to ground potential; The second differential input pair is configured to be in an active state when the input common-mode voltage is close to the high-voltage power supply potential; The first differential input pair and the second differential input pair are also configured to be in an effective working state simultaneously when the input common-mode voltage is higher than the turn-on threshold of the first differential input pair and lower than the turn-off threshold of the second differential input pair. The first differential input pair and the second differential input pair are configured together to enable the input common-mode voltage range of the high-voltage power amplifier to cover the full voltage range input from ground potential to high-voltage power supply potential.

3. A high-voltage power amplifier with over-temperature and over-current protection circuit according to claim 2, characterized in that, The gain amplification stage is connected between the on-rail to rail input stage and the Class AB push-pull output stage; The gain amplifier stage is configured to receive and sum the output currents of the first differential input pair and the second differential input pair; The gain amplification stage includes a folded cascode structure, which includes a first group of cascode transistors and a second group of cascode transistors. The gain amplification stage also includes a first auxiliary amplifier and a second auxiliary amplifier; The output terminal of the first auxiliary amplifier is connected to the gate of the first group of common-source cascode transistors to increase the output impedance of the first group of common-source cascode transistors; The output of the second auxiliary amplifier is connected to the gate of the second set of cascode transistors to increase the output impedance of the second set of cascode transistors.

4. A high-voltage power amplifier with over-temperature and over-current protection circuit according to claim 1, characterized in that, The AB class push-pull output stage includes a PMOS upper power transistor, an NMOS lower power transistor, and a bias circuit. The source of the PMOS upper power transistor is connected to a high-voltage power supply, and its drain is connected to the output terminal together with the drain of the NMOS lower power transistor. The source of the NMOS lower power transistor is grounded. The bias circuit includes a transconducting linear loop structure connected between the gates of the PMOS upper power transistor and the NMOS lower power transistor, used to dynamically clamp the voltage difference between the two gates and provide a static bias current for the PMOS upper power transistor and the NMOS lower power transistor.

5. A high-voltage power amplifier with over-temperature and over-current protection circuit according to claim 1, characterized in that, The high-voltage level conversion circuit is a clamping high-voltage level conversion circuit, which includes a differential common-source common-gate voltage switch composed of conventional MOS transistors and a clamping structure composed of high-voltage resistant MOS transistors. The differential common-source cascode voltage switch is used to receive input signals in the low-voltage domain; The gates of the high-voltage MOS transistors in the clamping structure are respectively connected to a low-voltage power supply or a floating reference potential to limit the voltage swing of the internal nodes of the high-voltage level conversion circuit. The high-voltage level conversion circuit is configured to use the clamping structure to convert the input signal of the low-voltage domain into a high-voltage domain control signal based on the floating reference potential. The floating reference potential is configured to follow the potential changes of the high-voltage power supply, and the voltage difference between the floating reference potential and the high-voltage power supply potential is limited to a preset safe voltage range.

6. A high-voltage power amplifier with over-temperature and over-current protection circuit according to claim 1, characterized in that, The PMOS current limiting protection circuit includes a turn-off potential generation circuit, a high-voltage sampling circuit, a current comparator, a rectifier circuit, and a high-voltage level conversion circuit. The shutdown potential generation circuit is connected between the high-voltage power supply and ground to generate a floating reference potential that follows the changes in the high-voltage power supply potential. The high-voltage sampling circuit is powered by a high-voltage power supply and includes a sampling PMOS transistor. The gate of the sampling PMOS transistor is connected to the gate of the PMOS power transistor, and its source and drain are connected in parallel with the source and drain of the PMOS power transistor, respectively, to form a current mirror and replicate the load current of the PMOS power transistor according to a preset ratio to generate a sampling current. The current comparator is powered by a low-voltage power supply. Its input terminal receives the sampled current and is used to compare the voltage converted from the sampled current with a preset first reference voltage threshold. When the voltage of the sampled current is greater than the preset first reference voltage threshold, it outputs a level flip signal. The input terminal of the rectifier circuit is connected to the output terminal of the current comparator, and is used to shape the level-flipping signal to output a low-voltage domain discrimination signal. The input terminal of the high-voltage level conversion circuit is connected to the output terminal of the rectifier circuit, and is used to convert the low-voltage domain discrimination signal into a high-voltage domain overcurrent control signal based on the floating reference potential.

7. A high-voltage power amplifier with over-temperature and over-current protection circuit according to claim 1, characterized in that, The NMOS current limiting protection circuit includes a sampling circuit, a current comparator, and a shaping circuit. The sampling circuit includes a sampling NMOS transistor, the gate of which is connected to the gate of the NMOS lower power transistor, and its source and drain are connected in parallel with the source and drain of the NMOS lower power transistor, respectively, to replicate the current flowing through the NMOS lower power transistor according to a preset ratio to generate a sampling current. The current comparator is powered by a low-voltage power supply. Its input terminal receives the sampled current and is used to compare the voltage converted from the sampled current with a preset second reference voltage threshold. When the voltage of the sampled current is greater than the preset second reference voltage threshold, it outputs a level flip signal. The input terminal of the shaping circuit is connected to the output terminal of the current comparator, and is used to shape the level flip signal and output a low-voltage domain overcurrent control signal for controlling the gate potential of the NMOS power transistor.

8. A high-voltage power amplifier with over-temperature and over-current protection circuit according to claim 1, characterized in that, The over-temperature protection circuit includes a bandgap reference circuit, a programmable resistor divider network, a transmission gate, a high-gain comparator, a hysteresis shaping circuit, and a high-voltage level conversion circuit. The bandgap reference circuit is used to generate a reference voltage and a negative temperature coefficient voltage. The programmable resistor divider network is connected to a negative temperature coefficient voltage and is configured to generate an independently adjustable first programmable voltage divider and a second programmable voltage divider based on digital configuration codes. The input terminal of the transmission gate is connected to the output terminal of the programmable resistor divider network, and its control terminal is connected to the feedback output terminal of the over-temperature protection circuit, for selecting to output the first programmable voltage divider or the second programmable voltage divider according to the feedback signal. The first input terminal of the high-gain comparator is connected to the output terminal of the transmission gate, and its second input terminal is connected to the reference voltage. It is used to compare the selected programmable voltage divider with the reference voltage and output a comparison signal. The input terminal of the hysteresis shaping circuit is connected to the output terminal of the high-gain comparator, and is used to perform hysteresis processing and waveform shaping on the comparison signal to generate a low-voltage domain over-temperature shutdown signal. The input terminal of the high-voltage level conversion circuit is connected to the output terminal of the hysteresis shaping circuit, and is used to convert the low-voltage domain over-temperature shutdown signal into a high-voltage domain over-temperature shutdown signal.

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