A method, system and terminal for anti-aperture jitter based on heterogeneous fully integrated optical sampling clock

Abstract

The application relates to the technical field of data processing, and discloses an aperture jitter resisting method, system and terminal based on a heterogeneous full-integrated optical sampling clock, which comprises the following steps: constructing a heterogeneous full-integrated optical sampling clock; generating a high-frequency optical signal through the heterogeneous full-integrated optical sampling clock, and performing signal conversion processing on the high-frequency optical signal to obtain a plurality of parallel sampling optical pulses; performing aperture jitter compensation processing on the sampling optical pulses to obtain a plurality of time-delayed optical pulses; performing loss-coherent superposition processing on the plurality of time-delayed optical pulses to obtain a continuous optical signal; and performing signal amplification processing, filtering processing and photoelectric conversion processing on the continuous optical signal to obtain a high-frequency clock signal. Through the construction of the heterogeneous full-integrated optical sampling clock, the timing mismatch problem of the traditional high-frequency electrical sampling clock can be effectively solved, and the stability and accuracy of the high-frequency clock signal output are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to an anti-aperture jitter method, system, and terminal based on a heterogeneous fully integrated optical sampling clock. Background Technology

[0002] The analog-to-digital (ADC) conversion process transforms an analog signal whose amplitude varies continuously over time into a digital signal that is discrete in both the time domain and amplitude domain. This is typically accomplished using an electrical ADC converter. The sampling clock in an electrical ADC converter is provided by a radio frequency (RF) oscillator. Due to the laws of thermodynamics, the performance of the active components in these RF oscillators is limited by thermal noise, resulting in timing uncertainties in the sampling clock, also known as clock jitter. Clock jitter significantly limits the effective accuracy of the ADC conversion.

[0003] To overcome the performance bottleneck of electrical clocks, optical sampling clock technology has emerged, which often employs a multi-channel interleaved structure to improve the sampling rate. However, existing optical sampling clocks suffer from clock skew sensitivity and low integration, failing to meet the requirements of ultra-high-speed ADC (Analog-to-digital converter) sampling scenarios.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] The main objective of this invention is to provide an anti-aperture jitter method, system, and terminal based on a heterogeneous fully integrated optical sampling clock, aiming to solve the problem that the optical sampling clock is sensitive to offset and has low integration in the prior art, thus failing to meet the requirements of ultra-high-speed ADC sampling scenarios.

[0006] To achieve the above objectives, the present invention provides an anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock, the method comprising the following steps:

[0007] Constructing a heterogeneous, fully integrated optical sampling clock;

[0008] A high-frequency optical signal is generated by the heterogeneous fully integrated optical sampling clock, and the high-frequency optical signal is processed by signal conversion to obtain multiple parallel sampling optical pulses;

[0009] The sampled optical pulses are subjected to aperture jitter compensation processing to obtain multi-path delayed optical pulses;

[0010] The multi-path delayed optical pulses are subjected to lossy coherent superposition processing to obtain a continuous optical signal;

[0011] The continuous optical signal is amplified, filtered, and converted into a high-frequency clock signal.

[0012] Optionally, in the method for resisting aperture jitter based on a heterogeneous fully integrated optical sampling clock, the construction of the heterogeneous fully integrated optical sampling clock specifically involves:

[0013] The optical frequency comb generation module, the optical signal processing module, and the TEC temperature control module are identified. The optical frequency comb generation module, the optical signal processing module, and the TEC temperature control module are connected through silicon vias and integrated on the same silicon-based packaging substrate to obtain a heterogeneous fully integrated optical sampling clock.

[0014] Optionally, the method for resisting aperture jitter based on a heterogeneous fully integrated optical sampling clock, wherein generating a high-frequency optical signal using the heterogeneous fully integrated optical sampling clock and performing signal conversion processing on the high-frequency optical signal to obtain multiple parallel sampling optical pulses specifically includes:

[0015] The optical frequency comb generation module in the heterogeneous fully integrated optical sampling clock is driven by a laser chip, and a high-frequency optical signal with uniform wavelength and uniform spacing is generated by the optical frequency comb generation module.

[0016] The high-frequency optical signal is transmitted through the optical frequency comb generation module to the electro-optic modulation unit arranged in parallel in the optical signal processing module;

[0017] The high-frequency optical signal is photoelectrically converted and periodically sampled by the electro-optic modulation unit to obtain multiple parallel sampling optical pulses.

[0018] Optionally, the method for resisting aperture jitter based on a heterogeneous fully integrated optical sampling clock, wherein the step of performing photoelectric conversion processing and periodic sampling processing on the high-frequency optical signal through the electro-optic modulation unit to obtain multiple parallel sampling optical pulses specifically includes:

[0019] A high-frequency analog electrical signal is acquired and used as a modulation signal to be connected to the electrode of a lithium niobate modulator to obtain the target lithium niobate crystal.

[0020] The high-frequency optical signal is subjected to intensity control and phase modulation by the target lithium niobate crystal to obtain a converted optical signal;

[0021] A lithium niobate modulator is determined, and the converted optical signal is periodically sampled through the lithium niobate modulator to obtain multiple parallel sampling optical pulses.

[0022] Optionally, the method for resisting aperture jitter based on heterogeneous fully integrated optical sampling clocks, wherein the aperture jitter compensation processing of the sampled optical pulses to obtain multi-path delayed optical pulses specifically includes:

[0023] The sampling optical pulse is sent to the optical delay array in the optical signal processing module through the electro-optic modulation unit, wherein the optical delay array includes multiple micro-ring resonant cavity delay units connected in series;

[0024] The sampling light pulse is phase-modulated and amplitude-modulated by the micro-ring resonant cavity delay unit based on the interference and resonance effect of light to obtain multi-path delayed light pulses.

[0025] Optionally, the method for resisting aperture jitter based on heterogeneous fully integrated optical sampling clocks, wherein the lossy coherent superposition processing of the multi-path delayed optical pulses to obtain a continuous optical signal specifically includes:

[0026] The multi-path delayed optical pulses are transmitted to the coherent coupling unit in the optical signal processing module via the optical delay array.

[0027] The coherent coupling unit performs optical signal uniform convergence processing, phase matching processing, and coherent superposition processing on the multi-path delayed optical pulses to obtain a continuous optical signal.

[0028] Optionally, the method for resisting aperture jitter based on heterogeneous fully integrated optical sampling clocks, wherein the step of performing optical signal uniform convergence processing, phase matching processing, and coherent superposition processing on the multi-path delayed optical pulses through the coherent coupling unit to obtain a continuous optical signal specifically includes:

[0029] The silicon-based multimode interference coupler array in the coherent coupling unit is obtained, and the power of the optical signal of each branch in the multi-path delayed optical pulse is uniformly distributed through the silicon-based multimode interference coupler array to obtain a uniform optical signal;

[0030] The uniform optical signal is phase-matched by the coherent coupling unit and the optical delay array to obtain a continuous and smooth optical signal waveform.

[0031] Discrete sampling points in the optical signal waveform are obtained, and the discrete sampling points are superimposed to obtain a continuous optical signal.

[0032] Optionally, the method for resisting aperture jitter based on heterogeneous fully integrated optical sampling clocks, wherein the step of performing signal amplification, filtering, and photoelectric conversion on the continuous optical signal to obtain a high-frequency clock signal specifically includes:

[0033] The continuous optical signal is amplified using an on-chip SOA amplification unit on an InP substrate to obtain an amplified signal.

[0034] A silicon-based AWG bandpass filter is used to filter out spontaneous emission noise, stray light, and interference signals generated by circuit crosstalk in the amplified signal to obtain a filtered signal.

[0035] A germanium-silicon APD photodetector is used to absorb, excite, convert current, and convert voltage of the filtered signal through a strong electric field to obtain a high-frequency clock signal.

[0036] Furthermore, to achieve the above objectives, the present invention also provides an anti-aperture jitter system based on a heterogeneous fully integrated optical sampling clock, wherein the anti-aperture jitter system based on a heterogeneous fully integrated optical sampling clock comprises:

[0037] The optical sampling clock construction module is used to construct a heterogeneous, fully integrated optical sampling clock.

[0038] The signal conversion and processing module is used to generate a high-frequency optical signal through the heterogeneous fully integrated optical sampling clock, and to perform signal conversion processing on the high-frequency optical signal to obtain multiple parallel sampling optical pulses;

[0039] An aperture jitter compensation module is used to perform aperture jitter compensation processing on the sampled optical pulses to obtain multi-path delayed optical pulses;

[0040] The loss coherent superposition module is used to perform loss coherent superposition processing on the multi-path delayed optical pulses to obtain a continuous optical signal;

[0041] The high-frequency clock signal generation module is used to amplify, filter, and perform photoelectric conversion on the continuous optical signal to obtain a high-frequency clock signal.

[0042] In this invention, a heterogeneous fully integrated optical sampling clock is constructed. A high-frequency optical signal is generated using this clock, and signal conversion processing is performed on the high-frequency optical signal to obtain multiple parallel sampling optical pulses. Aperture jitter compensation processing is applied to the sampling optical pulses to obtain multiple delayed optical pulses. Loss coherence superposition processing is performed on the multiple delayed optical pulses to obtain a continuous optical signal. Signal amplification, filtering, and photoelectric conversion processing are then performed on the continuous optical signal to obtain a high-frequency clock signal. This invention, by constructing a heterogeneous fully integrated optical sampling clock, can convert the discrete sampling points of multiple sampling optical pulses into a continuous signal range, effectively suppressing aperture jitter within the sampling period range, and simultaneously improving the stability and accuracy of the high-frequency clock signal output. Attached Figure Description

[0043] Figure 1 This is a schematic diagram illustrating the noise introduced by sampling clock jitter in existing technologies;

[0044] Figure 2 This is a schematic diagram illustrating the distribution of ADC performance metrics as statistically analyzed by a university team in the existing technology. Figure 2 The data shows a significant decrease in the dark count rate: from 1 ps in 1999 (10 12 Hz), to 100 fs (10 Hz) in 2007 14 From Hz), to 67 fs (1.5×10⁻⁶) in 2023. 13 (Hz); In the figure, 2012 MIT refers to the Massachusetts Institute of Technology in 2012, 2014 UniPi refers to the University of Pardubice (UniPi) in 2014, 2016 SJTU refers to Shanghai Jiao Tong University in 2016, 2018 Berkeley refers to the University of California, Berkeley in 2018, 2018 IBM 14nm refers to IBM's 14nm process in 2018; ISSCC2023 refers to devices presented at the International Solid State Circuits Conference in 2023, VLSI2023 refers to devices presented at the Very Large Scale Integration Workshop in 2023, ISSCC2022 refers to devices presented at ISSCC in 2022 and earlier, VLSI2022 refers to devices presented at VLSI in 2022 and earlier, PADC refers to photonic avalanche diode related devices, and jitter refers to device timing).

[0045] Figure 3 This is a schematic diagram illustrating the basic principle of optical sampling analog-to-digital conversion technology in existing technologies;

[0046] Figure 4 This is a flowchart of a preferred embodiment of the anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock according to the present invention;

[0047] Figure 5 This is a schematic diagram of three mainstream technical paths for a preferred embodiment of the anti-aperture jitter method for heterogeneous fully integrated optical sampling clocks of the present invention (used to integrate devices or chips of different materials (such as silicon CMOS, III-V compound semiconductors) on the same substrate to achieve high-performance, multifunctional system-on-a-chip (SoC) or packaging; the three mainstream technical paths include: heteroepitaxial growth ( Figure 5 a) Heterogeneous epitaxial transfer ( Figure 5 (b) and heterogeneous wafer bonding ( Figure 5 c and d in the middle)

[0048] Figure 6 This is a schematic diagram of the heterogeneous integrated optoelectronic system architecture of a preferred embodiment of the anti-aperture jitter method based on heterogeneous fully integrated optical sampling clock of the present invention. Figure 6(a) in the diagram represents the core optoelectronic device. Figure 6 (b) in the text refers to an integrated system.

[0049] Figure 7 This is a structural diagram of a preferred embodiment of the anti-aperture jitter system based on a heterogeneous fully integrated optical sampling clock of the present invention;

[0050] Figure 8 This is a structural diagram of a preferred embodiment of the terminal of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0052] The analog-to-digital (ADC) conversion process transforms an analog signal whose amplitude varies continuously over time into a digital signal that is discretized in both the time domain and amplitude. The basic physical process of ADC includes three steps: sampling, quantization, and encoding. After sampling, the analog signal is periodically discretized in the time domain. Then, in the quantization step, multiple comparators with different thresholds compare and quantize the amplitude of the analog signal; amplitudes above the comparator threshold are recorded as 1, and amplitudes below the threshold are recorded as 0. Finally, in the encoding step, logic circuits are used to obtain a digital signal that can be further processed. The most important technical specifications of an ADC are: sampling rate (fS), input bandwidth (BW), quantization bits, and effective number of bits (ENOB). The effective number of bits is defined as the number of bits that can be accurately quantized. According to the 2000 internationally recognized calculation standard, the formula for calculating the effective number of bits (ENOB) is as follows:

[0053] ENOB = (SNDR - 1.76) / 6.02;

[0054] SNDR stands for Signal-to-Noise-and-Distortion Ratio.

[0055] In electrical analog-to-digital converters (ADCs), the sampling clock is provided by an RF oscillator. Due to the laws of thermodynamics, the performance of the active components in these RF oscillators is limited by thermal noise, resulting in timing uncertainties in the sampling clock, also known as clock jitter. For example... Figure 1 As shown, when sampling an analog signal with continuously varying amplitude, if the sampling time deviates from the ideal time, the obtained amplitude value will also deviate accordingly. This is the noise caused by sampling clock jitter, and its impact on the signal-to-noise ratio (SNR) is shown below:

[0056] SNR=20×log10[1 / (2pi×f in ×t j )];

[0057] Among them, t j For clock jitter, f in The input signal frequency.

[0058] Currently, the sampling clock jitter level in electrical analog-to-digital converters (ADCs) is in the picosecond to sub-picosecond range. However, clock jitter significantly limits the effective accuracy of ADCs. As shown in Table 1, with a 45GHz input signal, a clock jitter of approximately 10 fs is required to achieve 8-bit effective accuracy. Figure 2 The image shows the performance distribution of ADC (Analog-to-Digital Converter) metrics compiled by a university team, highlighting the obvious performance bottleneck of electrical analog-to-digital converters. In optical sampling ADC systems, the sampling clock is mostly generated by mode-locked lasers or optical frequency combs, and the repetition frequency of the generated optical pulses is the sampling rate. Currently, commercially available mode-locked lasers can generate optical pulses with repetition frequencies up to 40 GHz. According to existing technology, the total sampling rate of an optical sampling ADC system can be doubled to 83.9 GSa / s and 10 TSa / s respectively through wavelength-time interleaving and time stretching. The corresponding mode-locked laser clock jitter can reach approximately 10 fs. Optical sampling analog-to-digital conversion technology utilizes periodic photon pulses to complete the crucial sampling step, such as... Figure 3 As shown, the basic principle of optical sampling analog-to-digital conversion technology is illustrated. A mode-locked laser generates ultrashort optical pulses with a repetition period TR. This series of optical pulses is input to an electro-optic modulator, where the amplitude information of the analog signal is modulated onto the optical pulses through the electro-optic effect. In other words, the optical pulses discretize the analog signal in the time domain with an interval TR. Next, the optical pulses containing the sampling information are converted into electrical signals by a photodetector, and then quantization and encoding are completed by an electronic analog-to-digital converter.

[0059] Table 1: Estimation of effective accuracy and sampling clock jitter

[0060]

[0061] in, The input signal frequency.

[0062] In high-frequency signal processing systems such as ultra-high-speed ADC sampling, the stability and synchronization accuracy of the clock signal directly determine the system performance. Traditional clocking solutions based on electrical chips require multiple signal processing steps to achieve low-frequency to high-frequency conversion, resulting in drawbacks such as high power consumption, high heat generation, high noise, high cost, and large size. As communication and computing technologies evolve towards the terahertz frequency band, traditional electrical clocks can no longer meet the requirements of ultra-high-speed applications and cannot adapt to the stringent clock signal requirements of ultra-high-speed ADC sampling.

[0063] To overcome the performance bottleneck of electrical clocks, optical sampling clock technology has emerged. Existing optical sampling clocks mostly employ multi-channel interleaved structures to improve sampling rates; however, this type of structure faces severe inter-channel clock skew problems, leading to timing mismatches and significantly reducing the system's spurious dynamic range, making it difficult to meet the clock synchronization accuracy and integration requirements of ultra-high-speed ADC sampling. Although some research has proposed using calibration algorithms to suppress skew, this increases system complexity and power consumption, and calibration accuracy is limited by algorithm performance. Furthermore, existing optical sampling clocks are mostly assembled from discrete components, resulting in low integration, high coupling costs, and poor stability, hindering large-scale applications. In summary, existing optical sampling clocks suffer from core problems such as clock skew sensitivity, low integration, high power consumption, and poor stability, failing to meet the stringent requirements of ultra-high-speed ADC sampling scenarios. Developing a highly integrated optical sampling clock with strong clock skew resistance has become an urgent need in the current technological field.

[0064] To address the problems of existing optical sampling clocks, such as aperture jitter due to multi-channel interleaved structures, low integration density, high power consumption, and poor stability caused by discrete component assembly or single-material integration, which are unsuitable for high-frequency signal processing requirements, this invention provides a fully integrated optical sampling clock with aperture jitter resistance, based on a fully integrated on-chip architecture. Through a vector superposition all-optical sample-and-hold mechanism and a heterogeneous on-chip integration design, all functional modules are integrated onto a single silicon photonics chip, achieving stable generation and precise synchronization of a 20GHz high-frequency clock signal. This simultaneously reduces system complexity and power consumption, solving the timing mismatch and large-scale application challenges of traditional solutions.

[0065] This invention relates to the fields of optoelectronic technology and clock synchronization technology, and specifically discloses a fully integrated optical sampling clock that is resistant to aperture jitter, which can be widely used in high-frequency signal processing scenarios such as 6G communication, aerospace remote sensing, quantum computing and AI high-speed computing.

[0066] The preferred embodiment of the present invention describes an anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock, such as... Figure 4 As shown, the anti-aperture jitter method based on heterogeneous fully integrated optical sampling clock includes the following steps:

[0067] Step S10: Construct a heterogeneous fully integrated optical sampling clock.

[0068] This invention presents a fully integrated on-chip architecture (i.e., the heterogeneous fully integrated optical sampling clock of this invention), specifically comprising three main modules: an optical frequency comb module, an optical signal processing module, and a TEC temperature control module. All modules achieve vertical interconnection and signal transmission via through-silicon vias (TSVs), integrated onto the same silicon-based packaging substrate, without any external discrete functional devices. TSVs serve as vertical interconnect channels between modules, enabling low-loss, high-density interconnection of electrical or optical signals. The TEC temperature control module directly connects to temperature-controlled devices (such as lasers and microring resonators) within other modules via metal wires interconnected by TSVs, ensuring full integration at the architectural level and significantly improving integration density, connection stability, and temperature control accuracy.

[0069] The working principle of the fully integrated on-chip architecture is as follows: The optical frequency comb module generates a high-frequency optical local oscillator signal and transmits it to the optical signal processing module; the optical signal processing module receives external electrical signals, completes electro-optical conversion and generates multiple parallel sampling optical pulses, and after vector superposition to compensate for aperture jitter, amplifies, filters and optimizes the optical signal; further, the PD unit (Photodetector) and TEC temperature control module receive the optimized optical signal, complete the photoelectric conversion through the PD unit, and then output a stable electrical clock signal. At the same time, the TEC temperature control unit accurately controls the temperature of the core components of the entire system to ensure the stable operation of each module, and finally outputs a high-precision, aperture jitter-resistant high-frequency clock signal.

[0070] It is understood that this invention provides a fully integrated optical sampling clock system resistant to aperture jitter. The core of this system is a fully integrated on-chip architecture (i.e., the heterogeneous fully integrated optical sampling clock in this invention), comprising three main modules integrated on the same silicon-based packaging substrate: an optical frequency comb module, an optical signal processing module, and a TEC temperature control module. These modules are vertically interconnected via TSV (Through Silicon Via) technology, forming a closed-loop operating system. There are no external discrete functional devices, enabling fully on-chip integrated high-frequency clock signal generation and aperture jitter suppression.

[0071] Specifically, an optical frequency comb generation module, an optical signal processing module, and a TEC temperature control module are identified. The optical frequency comb generation module, the optical signal processing module, and the TEC temperature control module are connected through silicon vias and integrated on the same silicon-based packaging substrate to obtain a heterogeneous fully integrated optical sampling clock.

[0072] For the fully integrated on-chip architecture (i.e., the heterogeneous fully integrated optical sampling clock in this invention), its specific structure and connection relationship are as follows: This process utilizes MEMS (Micro-Electro-Mechanical Systems) silicon bulk processing technology to perform three-dimensional overlay on the silicon substrate, which can obtain cavities and interconnect vias of different depths, and can precisely embed heterogeneous fused chips of different materials and thicknesses. Low-dielectric-constant and low-loss BCB (Benzocyclobutene) is used as the insulating medium for multi-layer three-dimensional wiring or integration of passive components. It is compatible with heterogeneous fusion processes such as wafer integration and wafer stacking integration, and can significantly shorten the wiring length between chips and between chips and passive devices. The minimum spacing can achieve 5µm chip-to-chip interconnection, overcoming the incompatibility problem between the interconnect structure of compound semiconductors and the back-end processes of CMOS (Complementary Metal-Oxide-Semiconductor) semiconductor devices, and can better integrate compound semiconductors and silicon-based semiconductors.

[0073] like Figure 5 and Figure 6 As shown, this invention discloses a three-dimensional heterogeneous integration method for stacking semiconductor lasers, silicon photonic chips, and silicon-based CMOS chips. The specific implementation steps of the process path are as follows: 1. As shown Figure 6 As shown in (a), a DFB laser chip (such as...) is fabricated based on an InP substrate (Indium Phosphide substrate). Figure 6 In this context, A (referred to as chip A) refers to a microcavity optical frequency comb (such as one made of SiN (Silicon Nitride) material) fabricated from this material. Figure 6 In this context, B (referred to as chip B) refers to silicon photonic wafers fabricated using SOI technology (such as...). Figure 6 The C in the text refers to the chip C), and the wafers for electrical domain processing chips fabricated using silicon-based CMOS technology (such as...). Figure 6 1. The process involves: 1) bonding the diced D chip (referred to as chip D); 2) temporarily bonding the diced D chip to the Carrier wafer; 3) wafer bonding the Carrier wafer to the C wafer; 4) removing the substrate layer at the bottom of the C wafer and connecting the signals between the C and D stacked chips via TSV; 5) fabricating RDL and flip-chip bumps on the surface of the C wafer; 6) debonding the Carrier wafer; 7) slicing to obtain chip E; 8) bonding chips A and B, and B and E in pairs to form an assembly (referred to as F), achieving end-face coupling of the optical path; 9) fabrication of the Si Interposer; 10) flip-chip F onto the Si Interposer; 11) flip-chip F onto the substrate.

[0074] It is understood that the technical approach of this invention first integrates various modules onto the same silicon photonic chip through heterogeneous wafer bonding technology to achieve a fully integrated design. The technical approach of this invention first fabricates the three main modules (i.e., the optical frequency comb module, the optical signal processing module, and the PD and TEC temperature control modules) as integrated modules, and then interconnects and integrates all modules onto the same silicon-based packaging substrate through TSV technology to achieve a fully integrated design. The optical frequency comb module generates a high-frequency optical local oscillator signal (i.e., the high-frequency optical signal in this invention). Subsequently, the signal is transmitted to the optical signal processing module through a TSV vertical interconnect channel, driving it to complete electro-optical conversion, parallel sampling, and signal optimization. Then, the optimized optical signal is transmitted to the PD (photodetector) and TEC temperature control modules through the TSV interconnect channel. The PD unit completes photoelectric conversion and outputs an electrical clock signal, while the TEC temperature control unit precisely controls the temperature of the core components of the entire system. This forms a complete signal processing link of "optical local oscillator generation - optical signal processing - photoelectric conversion and temperature control assurance." TSV technology ensures low-loss transmission and high stability between modules, thereby ensuring high precision of the clock signal.

[0075] This invention takes the application scenario of generating a 20GHz clock signal as an example to explain in detail the specific implementation process of this invention, including device selection, process parameters, and performance verification:

[0076] The process for selecting components and setting core parameters is as follows:

[0077] 1. The optical frequency comb generation module includes: a distributed feedback laser (output power of 400mW, center wavelength of 1550nm), a silicon nitride microring resonator (radius of 50μm, cross-section of 450nm×300nm), and a TEC temperature control module (temperature control accuracy of 0.1℃).

[0078] 2. The optical signal processing module includes: 4 parallel lithium niobate modulators (operating bandwidth 0-10GHz, driving voltage 0-5V, half-wave voltage 3-5V, insertion loss ≤2dB, extinction ratio ≥25dB) and on-chip matching resistors (50Ω); 4 series silicon nitride micro-ring delay units (radius 50μm), TiN microheaters (resistance 100Ω), 4-input 1-output 3dB silicon-based multimode interference coupler array (insertion loss <0.3dB); InP-based SOA (small signal gain ≥20dB), silicon-based AWG filter (center wavelength 1555nm, bandwidth 20GHz), and germanium-silicon avalanche photodiode (conversion gain 50V / W, dark current <1nA).

[0079] 3. The connection and temperature control links include: gold nanowires (bonding point diameter 5μm, transmission loss <0.3dB), Ti / Au wires (Ti 50nm + Au 200nm), thermally conductive adhesive (thermal conductivity 10W / (m·K)), and Al output wires (thickness 500nm, width 2μm).

[0080] Regarding the integration process and connection details: All three major modules (optical frequency comb module, optical signal processing module, and TEC temperature control module) are integrated on a silicon-based packaging substrate. The core technology uses TSV (Through Silicon Via) to achieve vertical interconnection of each module. This technology can construct high-density vertical interconnection channels, solving the interconnection compatibility problem of modules with different material systems. Specific process details are as follows:

[0081] 1. Pre-treatment of silicon-based packaging substrate: TSV vias are fabricated on the silicon-based packaging substrate using deep reactive ion etching (DRIE) process. The via diameter is 5μm-10μm and the depth is 50μm-100μm. Ti or W barrier layer and Cu seed layer are deposited on the inner wall of the via using sputtering process, and then Cu is filled by electroplating process to form conductive interconnect channels. At the same time, positioning grooves are processed on the substrate surface. The groove size is precisely matched with each functional chip to achieve precise positioning and mounting of each independent chip.

[0082] 2. Module Mounting and TSV Interconnection: The optical frequency comb module, optical signal processing module, and TEC temperature control module are mounted in positioning grooves on the silicon substrate. A flip-chip bonding process is used to precisely align the pads of each module with the TSV interconnection channels on the substrate, achieving vertical electrical or optical signal interconnection between the modules. The signal transmission between the optical frequency comb module and the optical signal processing module is achieved through the TSV vertical channel. The output of the sampling trigger unit inside the optical signal processing module is split into four beams through a Y-shaped branch waveguide (branch angle of 10°) inside the substrate, and then transmitted to the vector superposition unit through the module link, ensuring low-loss optical signal transmission (coupling loss ≤0.2dB). At the same time, on-chip passive components can be integrated through the TSV channel to further shorten the interconnection link length.

[0083] 3. Insulation Encapsulation and Performance Assurance: Low dielectric constant and low loss BCB material is used to insulate and encapsulate the interconnected modules and TSV channels to avoid signal crosstalk. The TEC temperature control module is connected to the laser of the optical frequency comb module, the micro-ring resonator, and the optical delay array micro heater of the optical signal processing module through TSV interconnected Ti or Au wires (Ti 50nm + Au 200nm), respectively. The wires form ohmic contacts with the electrodes of the devices in the module (contact resistance <5Ω). Relying on the high-density vertical interconnection characteristics of TSV technology, the wiring length between modules can be effectively shortened, signal delay and loss can be reduced, and the electromagnetic compatibility performance between wirings can be improved. Efficient shielding between modules can be achieved, further ensuring the stability of high-frequency clock signals and helping to realize system miniaturization and low profile.

[0084] Step S20: Generate a high-frequency optical signal using the heterogeneous fully integrated optical sampling clock, and perform signal conversion processing on the high-frequency optical signal to obtain multiple parallel sampling optical pulses.

[0085] The optical frequency comb module is used to generate a multi-wavelength uniformly spaced optical frequency comb signal with a comb tooth spacing of 10GHz-200GHz, which is used as the optical local oscillator signal for sampling clock. Its output end is coupled to the input end of the optical signal processing module through a TSV vertical interconnect channel, with a coupling loss ≤0.5dB.

[0086] The optical signal processing module of this invention integrates electro-optic conversion, parallel sampling pulse generation, vector superposition, optical signal amplification and filtering, and photoelectric conversion functions. It includes a parallel electro-optic modulation unit, an optical delay array, a coherent coupling unit, an optical amplification unit, a filtering unit, and a PD (photodetector) unit. This module converts an input electrical signal with a bandwidth of 0-10 GHz into an optical signal. Based on the optical frequency comb signal trigger, it generates multiple parallel sampling optical pulses (single-channel sampling rate 5 GHz-50 GHz, total sampling rate ≥ 20 GHz after superposition), which are then processed by the optical delay array (…). After compensating for aperture jitter with a precise delay of 0-10 picoseconds (adjustment step size ≤ 0.1 picoseconds), the optical signal is coherently superimposed at low loss through a coherent coupling unit (signal-to-noise ratio of superimposed optical signal ≥ 50dB). Then, the optical signal is optimized by optical amplification (small signal gain ≥ 15dB) and filtering (bandwidth matching 10GHz-200GHz). Finally, the optimized optical signal is converted into an electrical clock signal through a PD unit (output electrical clock signal phase noise ≤ -110dBc / Hz, spurious dynamic range ≥ 55dB), and its output terminal serves as the clock signal output terminal.

[0087] Specifically, the optical frequency comb generation module in the heterogeneous fully integrated optical sampling clock is driven by the laser chip, and a high-frequency optical signal with uniform wavelength and uniform spacing is generated by the optical frequency comb generation module.

[0088] For the optical frequency comb generation module: This invention employs an integrated optical frequency comb structure based on a microring resonant cavity, driven by a laser chip with an output power not exceeding 500 milliwatts, and equipped with a TEC temperature control module for precise temperature control of the laser chip and the microring resonant cavity. The microring resonant cavity utilizes the interference and resonance effects of light to modulate the phase and amplitude of the optical signal. By adjusting the voltage or current on the tuning electrodes, the refractive index or geometry of the microring resonant cavity can be changed, thereby achieving precise control of the optical signal. Due to the excellent electro-optic and thermo-optic effects of silicon nitride material, this adjustment process can achieve rapid and stable adjustment. This invention integrates a TiN material microheater and NTC next to the microring, and changes the temperature of the silicon nitride by controlling the microheater with voltage. Utilizing the self-injection locking method, since there is no optical isolator between the laser and the microcavity, the light field incident on the microcavity will undergo Rayleigh scattering on the sidewalls of the microcavity to form a back-propagating light field that returns along the original path, feeding back the light field inside the laser cavity. When the initial detuning of the laser is within a certain range and meets the corresponding feedback phase conditions, the system automatically reaches the soliton state, realizing the "key-on" start-up of the microcavity optical comb. This generates a multi-wavelength, uniformly spaced optical frequency comb signal with a length of 1550nm, centered on the pump light and a comb tooth spacing of 20GHz (serving as the optical local oscillator signal for sampling clock). Its output is connected to the input of the sampling trigger module via optical waveguide end-face coupling. In short, the core function of this module is to provide a high-frequency, stable optical frequency comb signal, laying the foundation for subsequent sampling triggering.

[0089] It is understood that the optical frequency comb generating chip includes a distributed feedback laser chip and a silicon nitride microring resonator, which are integrated through wafer bonding. The silicon nitride microring resonator is fabricated using PECVD technology, has a rectangular cross-section with a width of 300nm-600nm, a height of 200nm-400nm, a radius of 30μm-100μm, and a temperature coefficient of 2×10⁻⁶. -5 / ℃-4×10 -5The distributed feedback laser chip has an output power of 5mW-500mW and a center wavelength of 1550nm-1553nm. The bonding interface between the laser and the micro-ring resonator uses a SiO2 dielectric layer for transition, with a dielectric layer thickness of 50nm-200nm. The bonding process parameters are: temperature set at 180℃-220℃, pressure at 3MPa-8MPa, and holding time at 20min-40min. The optical frequency comb generation chip uses a self-injection locking method to generate the optical frequency comb. The specific implementation steps are: no optical isolator is set between the laser and the microcavity. The light field incident on the microcavity is back-propagated by Rayleigh scattering on the sidewall of the microcavity and returns along the original path to the light field inside the laser cavity. When the initial detuning of the laser is within the set range and the feedback phase condition is met, the system automatically reaches the soliton state, realizing the "key-on" start of the microcavity optical comb. Subsequently, the optical frequency comb signal is stably generated by four-wave mixing (third-order nonlinear effect) generated by the Kerr effect.

[0090] The high-frequency optical signal is sent to the electro-optic modulation unit arranged in parallel in the optical signal processing module through the optical frequency comb generation module; a high-frequency analog electrical signal is acquired and used as a modulation signal to be connected to the electrode of the lithium niobate modulator to obtain the target lithium niobate crystal; the high-frequency optical signal is subjected to intensity control and phase modulation through the target lithium niobate crystal to obtain the converted optical signal; the lithium niobate modulator is determined and the converted optical signal is periodically sampled through the lithium niobate modulator to obtain multiple parallel sampling optical pulses.

[0091] For optical signal processing chips: the core function is to complete the full-link processing of high-frequency signals and optimize anti-aperture jitter. Internally, it integrates multiple parallel electro-optic modulation units (using lithium niobate modulator structures), optical delay arrays, coherent coupling units, on-chip SOA amplification units, silicon-based AWG bandpass filtering units, and germanium-silicon avalanche photodiode (APD) photodetector units. These units are integrated through heterogeneous processes and interconnected via on-chip links, ultimately outputting a stable electrical clock signal. The functions and signal processing procedures of each core unit are as follows:

[0092] For the electro-optic modulation unit: the core functions are to realize "electro-optic signal conversion" and "multi-channel parallel sampling optical pulse generation". The specific process is as follows: For electro-optic signal conversion, based on the Pockels electro-optic effect of lithium niobate material, the externally input 0-10GHz high-frequency analog electrical signal is used as the modulation signal and connected to the lithium niobate modulator electrode. At the same time, the optical frequency comb signal output by the optical frequency comb module (i.e., the high-frequency optical signal in this invention, with a center wavelength of 1550nm and a comb tooth spacing of 20GHz) is introduced as the carrier light. The key parameters of the selected lithium niobate modulator are adapted to the requirements of high-frequency scenarios, with a half-wave voltage of 3-5V, insertion loss ≤2dB, and extinction ratio ≥25dB. After the electrical signal is applied, the refractive index of the lithium niobate crystal can be changed, thereby controlling the light intensity and phase of the carrier light. The physical characteristics of the carrier light respond synchronously with the change law of the input electrical signal. Finally, the amplitude / phase information of the electrical signal is accurately loaded onto the optical signal to complete the electro-optic conversion. During the conversion process, the modulation bandwidth completely covers the 0-10GHz input signal range, and the modulation distortion is ≤1%. For multi-channel parallel sampling optical pulse generation, the principle of multi-channel interleaved sampling is used, combined with the multi-wavelength characteristics of the optical frequency comb signal. The optical frequency comb signal is split into equal-amplitude and in-phase paths by an on-chip power divider and then input to four parallel lithium niobate modulators. Each modulator periodically samples the converted optical signal under the trigger of the optical frequency comb signal, with the sampling time precisely locked by the timing of the optical frequency comb teeth. To achieve interleaved sampling times, a control scheme of "on-chip precise phase control link + optical frequency comb timing reference" is adopted. The specific steps are: 1. Timing reference anchoring: Using the optical frequency comb signal as a unified reference (20GHz comb tooth spacing corresponds to a 50ps period), ensuring that the optical carrier phase of each modulator is consistent in the initial state (phase difference ≤ ±5°); 2. Phase fine-tuning unit configuration: An independent lithium niobate electrode voltage-adjustable phase fine-tuning unit is integrated into the optical input link of each modulator, utilizing the "refractive index sensitive to voltage" characteristic of lithium niobate material to control the optical signal transmission. 3. Phase offset setting for each channel: The four modulators are adjusted in the order of "0°→90°→180°→270°". The first channel maintains a 0° phase as the reference. The second to fourth channels achieve 90°, 180° and 270° phase lag respectively by adjusting the voltage of the additional electrodes. The corresponding sampling times are delayed by 50ps, 100ps and 150ps respectively. Finally, the phase offset of adjacent channels is stabilized within the range of 90°±5°. The sampling times of the four channels are staggered at 50ps intervals to form a multi-channel parallel sampling optical pulse with a total sampling rate of 20GHz.

[0093] Step S30: Perform aperture jitter compensation processing on the sampled optical pulse to obtain multi-path delayed optical pulses.

[0094] In this invention, a picosecond-level precise delay processing of multi-channel sampled optical pulses is achieved by setting up an optical delay array, thereby compensating for aperture jitter.

[0095] Specifically, the sampled optical pulse is sent to the optical delay array in the optical signal processing module through the electro-optic modulation unit. The optical delay array includes multiple micro-ring resonant cavity delay units connected in series. The sampled optical pulse is phase-modulated and amplitude-modulated by the micro-ring resonant cavity delay units based on the interference and resonance effect of light to obtain multi-path delayed optical pulses.

[0096] For optical delay arrays, the core objective is to achieve picosecond-level precise delay of multi-channel sampled optical pulses to compensate for aperture jitter. The optical delay array consists of multiple series-connected microring resonant cavity delay units, utilizing the optical circulation characteristics within the microrings to achieve delay. The microring resonant cavity modulates the phase and amplitude of the optical signal based on the interference and resonance effects of light. By adjusting the voltage or current of the tuning electrodes, the refractive index or geometry of the microring resonant cavity can be changed, thereby achieving precise control of the delay time. Furthermore, the excellent electro-optic and thermo-optic effects of silicon-based materials ensure the speed and stability of adjustment. This array is linked to a TEC temperature control module, which precisely adjusts the refractive index of the microrings (ensuring temperature control accuracy consistent with the optical frequency comb module), achieving picosecond-level delay precision and enabling precise compensation for aperture jitter within the sampling period.

[0097] It is understood that the optical delay array consists of 4-16 silicon nitride microring resonant cavity delay units connected in series. The fabrication process of each delay unit is consistent with that of the microring resonant cavity of the optical frequency comb generation module. The micro heater integrated next to each delay unit is made of TiN material with a resistance of 100Ω±5Ω. The microring temperature is adjusted by applying a 0-3V voltage through the TEC temperature control module, thereby changing the refractive index of the microring and achieving precise delay adjustment of 0.1 picosecond to 10 picoseconds, ensuring that the aperture jitter compensation error is ≤0.05 picoseconds.

[0098] Step S40: Perform lossy coherent superposition processing on the multi-path delayed optical pulses to obtain a continuous optical signal.

[0099] This invention employs a silicon-based multimode interference coupler array in conjunction with an optical delay array to achieve low-loss convergence, phase matching, and efficient coherent superposition of multi-path delayed optical pulses, thereby obtaining a continuous optical signal.

[0100] Specifically, the multi-path delayed optical pulses are transmitted to the coherent coupling unit in the optical signal processing module through the optical delay array; the silicon-based multimode interference coupler array in the coherent coupling unit is obtained, and the optical signal of each branch in the multi-path delayed optical pulses is uniformly distributed through the silicon-based multimode interference coupler array to obtain a uniform optical signal; the uniform optical signal is phase-matched through the coherent coupling unit and the optical delay array to obtain a continuous and smooth optical signal waveform; discrete sampling points in the optical signal waveform are obtained, and the discrete sampling points are superimposed to obtain a continuous optical signal.

[0101] For the coherent coupling unit: a silicon-based multimode interference coupler array is used. Its core function is to work in conjunction with the optical delay array to achieve low-loss convergence, phase matching, and efficient coherent superposition of multiple delayed optical pulses, ultimately obtaining a continuous optical signal. Specifically, this is manifested in two ways: First, the optical signal is uniformly converged. The array adopts a 1×N (N is the number of sampled optical pulses) port configuration, which can accurately receive multiple delayed signals output by the optical delay array. The internal multimode interference structure achieves uniform power distribution of the optical signals in each branch, ensuring consistent weights for each path during superposition and avoiding signal distortion. Second, it ensures low-loss transmission. The array is integrated with the silicon substrate through photolithography and etching. The interference region has a length of 200μm-500μm and a width of 5μm-10μm, with a transmission loss of ≤0.2dB, which significantly reduces signal energy attenuation. Third, it features phase locking and constructive interference. Through coordinated control with the optical delay array, each optical pulse meets the phase matching condition (phase difference ≤±π / 10), achieving constructive interference and integrating discrete sampled optical pulses into a continuous and smooth optical signal waveform. Fourth, it synergistically suppresses aperture jitter. By superimposing the precisely delayed discrete sampling points into a continuous signal interval, it can effectively cover the time jitter deviation of a single sampling pulse, physically offsetting the impact of aperture jitter on signal timing. The signal-to-noise ratio of the superimposed optical signal is no less than 55dB.

[0102] It is understood that the coherent coupling unit adopts a silicon-based multimode interference coupler array with an interference region length of 200μm-500μm and a width of 5μm-10μm. It is fabricated integrally with the silicon substrate through photolithography etching process, with a transmission loss ≤0.2dB, and supports low-loss coherent superposition of 2-8 optical signals.

[0103] Step S50: Perform signal amplification, filtering, and photoelectric conversion processing on the continuous optical signal to obtain a high-frequency clock signal.

[0104] This invention optimizes the optical signal and achieves precise photoelectric conversion by performing signal amplification, filtering, and photoelectric conversion on the continuous optical signal, thereby obtaining a high-frequency clock signal.

[0105] Specifically, the continuous optical signal is amplified using an SOA amplification unit on an InP substrate to obtain an amplified signal.

[0106] For the signal conditioning and photoelectric conversion unit: the core is to achieve the optimization of optical signals and precise photoelectric conversion, which is divided into three progressive steps: First, optical amplification is performed, using an on-board optical array (SOA) on an InP substrate as the amplification unit, based on the principle of stimulated emission of semiconductor materials to improve the optical signal gain; when the superimposed optical signal (power -20dBm to -10dBm) is input into the SOA, its active region generates population inversion under the excitation of a 100mA injection current, and the incident optical signal triggers stimulated emission to multiply the photon number, achieving an amplification effect of ≥20dB for small signals; at the same time, through gain flattening design, it is ensured that the optical signal power fluctuation within the 20GHz operating bandwidth is ≤1dB, avoiding signal distortion.

[0107] A silicon-based AWG bandpass filter is used to filter out spontaneous emission noise, stray light, and interference signals generated by circuit crosstalk in the amplified signal to obtain a filtered signal.

[0108] After optical amplification, filtering and purification are performed using a silicon-based AWG bandpass filter, which is integrated with the chip through photolithography and etching. The center wavelength is precisely matched to the optical frequency comb signal of 1550nm, with a bandwidth of 20GHz. It can selectively transmit target light wavelength components and efficiently filter out spontaneous emission noise, stray light, and interference signals generated by circuit crosstalk introduced during amplification. This improves the signal-to-noise ratio of the filtered optical signal to over 55dB, ensuring signal purity.

[0109] A germanium-silicon APD photodetector is used to absorb, excite, convert current, and convert voltage of the filtered signal through a strong electric field to obtain a high-frequency clock signal.

[0110] After filtering and purification, photoelectric conversion is performed using a germanium-silicon APD to convert the light into an electrical signal. Under a 15V reverse bias, a strong electric field is formed in the depletion region of the APD. The filtered light signal is absorbed and excited to generate electron-hole pairs. These electron-hole pairs accelerate in the strong electric field and collide with the crystal lattice to generate more electron-hole pairs, achieving an avalanche multiplication effect (conversion gain 50V / W). Finally, the light intensity change of the light signal is converted into a corresponding current change. The weak current signal is then converted into a stable voltage signal (i.e., an electrical clock signal) by the preamplifier circuit inside the chip. The phase noise of the output electrical clock signal is ≤-110dBc / Hz, which can meet the stringent requirements of ultra-high-speed ADC sampling for clock signal stability.

[0111] For the TEC temperature control module: its core function is to stabilize the temperature of all core components in the system. Through TSV interconnected Ti and Au wires (i.e., Ti 50nm + Au 200nm), it connects to the laser of the optical frequency comb module, the micro-ring resonator, and the optical delay array micro-heater of the optical signal processing module, respectively. The temperature control accuracy is ≤0.1℃, and the temperature adjustment range is 15℃-40℃. During operation, it monitors the temperature changes of each core component in real time. By precisely adjusting the heating or cooling power, it compensates for temperature drift caused by ambient temperature fluctuations and device heat generation, ensuring stable signal generation from the optical frequency comb, accurate delay of the optical delay array, and stable performance of all electro-optical devices, avoiding signal distortion caused by temperature drift. The core function of this module is to provide high-precision, full-range temperature assurance for the entire system, making it a key support module for stable system operation.

[0112] It is understood that the TEC temperature control module is connected to the laser of the optical frequency comb module, the micro-ring resonator, and the optical delay array micro heater of the optical signal processing module via on-chip metal wires interconnected by TSV. The temperature control accuracy is ≤0.1℃, and the temperature control adjustment range is 15℃-40℃. The micro heater is made of a high resistance temperature coefficient material with a resistance value of 50Ω-200Ω. The refractive index of the micro-ring is dynamically controlled by adjusting the voltage from 0-3V.

[0113] Working process and performance verification:

[0114] 1. Working process: The process follows the flow of "optical local oscillator generation → parallel sampling → jitter compensation → coherent superposition → signal conditioning → clock output". The specific control parameters are as follows: laser temperature is 25℃ (current is 0.6A), micro-ring temperature is 25.3℃ (current is 0.4A), modulator drive voltage is 3V, SOA injection current is 100mA, and detector reverse bias voltage is 15V.

[0115] 2. Performance Verification: The output clock signal of this embodiment has a main frequency of 20GHz, a spurious dynamic range of 62dB, a phase noise of -120dBc / Hz, can effectively compensate for ±5 picosecond aperture jitter, optical signal transmission loss ≤0.5dB, and total system power consumption ≤500mW, which fully meets the stringent requirements of ultra-high speed ADC sampling for high frequency clock signals.

[0116] The core innovation of this invention lies in the use of TSV technology to achieve vertical interconnection of the three major modules, which solves the compatibility and interconnection problems of modules with different material systems. The integrated design of the optical signal processing module realizes full-link signal processing and aperture jitter compensation. The TEC temperature control module provides precise temperature control for the entire system. The on-chip integrated design ensures system stability and miniaturization.

[0117] Compared with the prior art, the technical effects of the present invention are significant, specifically reflected in the following aspects:

[0118] 1. Excellent anti-aperture jitter capability: By using a vector superposition mechanism to convert the discrete sampling points of multi-channel sampling optical pulses into a continuous signal range, aperture jitter within a range of ±0.1 sampling period can be effectively suppressed, and the spurious dynamic range is not less than 60dB. This solves the timing mismatch problem of traditional high-frequency electrical sampling clocks and ensures the accuracy of high-frequency signal processing.

[0119] 2. Significant Advantages of Fully Integrated On-Chip Architecture: The core innovation of this invention is a fully integrated on-chip architecture that integrates core modules from different material systems, such as silicon nitride microring resonators, lithium niobate modulators, and germanium-silicon photodetectors, onto a single silicon photonic chip through heterogeneous integration technology. This completely eliminates the limitations of traditional discrete device assembly and single silicon photonic integration. This architecture not only significantly reduces device assembly and coupling costs, with the potential for substantial cost reduction after mass production, but also fundamentally improves system stability and miniaturization. It solves the pain point of traditional discrete architectures being difficult to scale up, providing core support for the miniaturization and portability of equipment in high-frequency signal processing scenarios.

[0120] 3. Excellent high-frequency performance: The optical frequency comb generation module can directly generate high-frequency optical signals of 10GHz-200GHz, breaking through the 100GHz main frequency limit of traditional electric clocks. The output clock signal has low phase noise (-120dBc / Hz) and high stability, which can be adapted to the needs of high-frequency scenarios such as 6G communication and quantum computing.

[0121] Furthermore, such as Figure 7 As shown, based on the above-mentioned anti-aperture jitter method based on heterogeneous fully integrated optical sampling clock, the present invention also provides an anti-aperture jitter system based on heterogeneous fully integrated optical sampling clock, wherein the anti-aperture jitter system based on heterogeneous fully integrated optical sampling clock includes:

[0122] The optical sampling clock construction module 51 is used to construct a heterogeneous fully integrated optical sampling clock.

[0123] The signal conversion and processing module 52 is used to generate a high-frequency optical signal through the heterogeneous fully integrated optical sampling clock, and to perform signal conversion processing on the high-frequency optical signal to obtain multiple parallel sampling optical pulses;

[0124] Aperture jitter compensation module 53 is used to perform aperture jitter compensation processing on the sampled optical pulse to obtain multi-path delayed optical pulses;

[0125] The loss coherent superposition module 54 is used to perform loss coherent superposition processing on the multi-path delayed optical pulses to obtain a continuous optical signal;

[0126] The high-frequency clock signal generation module 55 is used to amplify, filter, and convert the continuous optical signal to obtain a high-frequency clock signal.

[0127] Furthermore, such as Figure 8 As shown, based on the above-mentioned anti-aperture jitter method and system based on heterogeneous fully integrated optical sampling clock, the present invention also provides a terminal, which includes a processor 10, a memory 20 and a display 30. Figure 8 Only some of the terminal components are shown; however, it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0128] In some embodiments, the memory 20 may be an internal storage unit of the terminal, such as a hard disk or memory. In other embodiments, the memory 20 may be an external storage device of the terminal, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc. Further, the memory 20 may include both internal and external storage devices. The memory 20 is used to store application software and various types of data installed on the terminal, such as the program code installed on the terminal. The memory 20 can also be used to temporarily store data that has been output or will be output. In one embodiment, the memory 20 stores an anti-aperture jitter program 40 based on a heterogeneous fully integrated optical sampling clock. This anti-aperture jitter program 40 can be executed by the processor 10, thereby implementing the anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock in this application.

[0129] In some embodiments, the processor 10 may be a central processing unit (CPU), a microprocessor, or other data processing chip, used to run program code stored in the memory 20 or process data, such as executing the anti-aperture jitter method based on heterogeneous fully integrated optical sampling clock.

[0130] In some embodiments, the display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. The display 30 is used to display information on the terminal and to display a visual user interface.

[0131] In one embodiment, the steps of the anti-aperture jitter method based on the heterogeneous fully integrated optical sampling clock are implemented when the processor 10 executes the anti-aperture jitter program 40 based on the heterogeneous fully integrated optical sampling clock in the memory 20.

[0132] In summary, this invention provides a method, system, and terminal for resisting aperture jitter based on a heterogeneous fully integrated optical sampling clock. The method includes: constructing a heterogeneous fully integrated optical sampling clock; generating a high-frequency optical signal using the heterogeneous fully integrated optical sampling clock, and performing signal conversion processing on the high-frequency optical signal to obtain multiple parallel sampling optical pulses; performing aperture jitter compensation processing on the sampling optical pulses to obtain multiple delayed optical pulses; performing lossy coherent superposition processing on the multiple delayed optical pulses to obtain a continuous optical signal; and performing signal amplification, filtering, and photoelectric conversion processing on the continuous optical signal to obtain a high-frequency clock signal. This invention, by constructing a heterogeneous fully integrated optical sampling clock, can convert the discrete sampling points of multiple sampling optical pulses into a continuous signal range, effectively suppressing aperture jitter within the sampling period range, and simultaneously improving the stability and accuracy of the high-frequency clock signal output.

[0133] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal that includes that element.

[0134] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for resisting aperture jitter based on a heterogeneous fully integrated optical sampling clock, characterized in that, The anti-aperture jitter method based on heterogeneous fully integrated optical sampling clock includes: Constructing a heterogeneous, fully integrated optical sampling clock; The construction of the heterogeneous fully integrated optical sampling clock specifically involves: The optical frequency comb generation module, the optical signal processing module, and the TEC temperature control module are identified. The optical frequency comb generation module, the optical signal processing module, and the TEC temperature control module are connected through silicon vias and integrated on the same silicon-based packaging substrate to obtain a heterogeneous fully integrated optical sampling clock. A high-frequency optical signal is generated by the heterogeneous fully integrated optical sampling clock, and the high-frequency optical signal is processed by signal conversion to obtain multiple parallel sampling optical pulses; The sampled optical pulses are subjected to aperture jitter compensation processing to obtain multi-path delayed optical pulses; The multi-path delayed optical pulses are subjected to lossy coherent superposition processing to obtain a continuous optical signal; The continuous optical signal is amplified, filtered, and converted into a high-frequency clock signal.

2. The anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock according to claim 1, characterized in that, The process of generating a high-frequency optical signal using the heterogeneous fully integrated optical sampling clock and performing signal conversion processing on the high-frequency optical signal to obtain multiple parallel sampling optical pulses specifically includes: The optical frequency comb generation module in the heterogeneous fully integrated optical sampling clock is driven by a laser chip, and a high-frequency optical signal with uniform wavelength and uniform spacing is generated by the optical frequency comb generation module. The high-frequency optical signal is transmitted through the optical frequency comb generation module to the electro-optic modulation unit arranged in parallel in the optical signal processing module; The high-frequency optical signal is photoelectrically converted and periodically sampled by the electro-optic modulation unit to obtain multiple parallel sampling optical pulses.

3. The anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock according to claim 2, characterized in that, The process of performing photoelectric conversion and periodic sampling on the high-frequency optical signal through the electro-optic modulation unit to obtain multiple parallel sampling optical pulses specifically includes: A high-frequency analog electrical signal is acquired and used as a modulation signal to be connected to the electrode of a lithium niobate modulator to obtain the target lithium niobate crystal. The high-frequency optical signal is subjected to intensity control and phase modulation by the target lithium niobate crystal to obtain a converted optical signal; A lithium niobate modulator is determined, and the converted optical signal is periodically sampled through the lithium niobate modulator to obtain multiple parallel sampling optical pulses.

4. The anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock according to claim 2, characterized in that, The process of performing aperture jitter compensation on the sampled optical pulse to obtain multi-path delayed optical pulses specifically includes: The sampling optical pulse is sent to the optical delay array in the optical signal processing module through the electro-optic modulation unit, wherein the optical delay array includes multiple micro-ring resonant cavity delay units connected in series; The sampling light pulse is phase-modulated and amplitude-modulated by the micro-ring resonant cavity delay unit based on the interference and resonance effect of light to obtain multi-path delayed light pulses.

5. The anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock according to claim 4, characterized in that, The step of performing lossy coherent superposition processing on the multi-path delayed optical pulses to obtain a continuous optical signal specifically includes: The multi-path delayed optical pulses are transmitted to the coherent coupling unit in the optical signal processing module via the optical delay array. The coherent coupling unit performs optical signal uniform convergence processing, phase matching processing, and coherent superposition processing on the multi-path delayed optical pulses to obtain a continuous optical signal.

6. The anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock according to claim 5, characterized in that, The process of performing uniform focusing, phase matching, and coherent superposition processing on the multi-path delayed optical pulses through the coherent coupling unit to obtain a continuous optical signal specifically includes: The silicon-based multimode interference coupler array in the coherent coupling unit is obtained, and the power of the optical signal of each branch in the multi-path delayed optical pulse is uniformly distributed through the silicon-based multimode interference coupler array to obtain a uniform optical signal; The uniform optical signal is phase-matched by the coherent coupling unit and the optical delay array to obtain a continuous and smooth optical signal waveform. Discrete sampling points in the optical signal waveform are obtained, and the discrete sampling points are superimposed to obtain a continuous optical signal.

7. The anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock according to claim 1, characterized in that, The process of amplifying, filtering, and converting the continuous optical signal to obtain a high-frequency clock signal specifically includes: The continuous optical signal is amplified using an on-chip SOA amplification unit on an InP substrate to obtain an amplified signal. A silicon-based AWG bandpass filter is used to filter out spontaneous emission noise, stray light, and interference signals generated by circuit crosstalk in the amplified signal to obtain a filtered signal. A high-frequency clock signal is obtained by using a germanium-silicon APD photodetector and performing absorption, excitation, current conversion, and voltage conversion on the filtered signal through a strong electric field.

8. An anti-aperture jitter system based on a heterogeneous fully integrated optical sampling clock, characterized in that, The anti-aperture jitter system based on a heterogeneous fully integrated optical sampling clock is used to implement the anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock as described in any one of claims 1-7. The anti-aperture jitter system based on a heterogeneous fully integrated optical sampling clock includes: The optical sampling clock construction module is used to construct a heterogeneous, fully integrated optical sampling clock. The signal conversion and processing module is used to generate a high-frequency optical signal through the heterogeneous fully integrated optical sampling clock, and to perform signal conversion processing on the high-frequency optical signal to obtain multiple parallel sampling optical pulses; An aperture jitter compensation module is used to perform aperture jitter compensation processing on the sampled optical pulses to obtain multi-path delayed optical pulses; The loss coherent superposition module is used to perform loss coherent superposition processing on the multi-path delayed optical pulses to obtain a continuous optical signal; The high-frequency clock signal generation module is used to amplify, filter, and perform photoelectric conversion on the continuous optical signal to obtain a high-frequency clock signal.

9. A terminal, characterized in that, The terminal includes: a memory, a processor, and an anti-aperture jitter program based on a heterogeneous fully integrated optical sampling clock stored in the memory and executable on the processor. When the anti-aperture jitter program based on a heterogeneous fully integrated optical sampling clock is executed by the processor, it implements the steps of the anti-aperture jitter method based on a heterogeneous fully integrated optical sampling clock as described in any one of claims 1-7.

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