An event counting method, apparatus, electronic device, and storage medium
By obtaining the values of the mutex lock and the power-on count register, and combining them with the current count value to calculate the target count value, the problem of inaccurate event counting after IP restart is solved, and efficient and accurate event statistics are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CIX TECH (SHANGHAI) CO LTD
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-30
Smart Images
Figure CN121832735B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to an event counting method, apparatus, electronic device, and storage medium. Background Technology
[0002] In a System-on-Chip (SoC), the most common method for estimating IP power consumption is by using the power management system (PM) to count various behavioral events of the Intellectual Property Core (IP) over a period of time. This counting is typically done through the Power Management Unit (PMU). The PMU usually reads the counts of specific events at a fixed frequency and calculates the difference between two consecutive counts. This difference represents the number of events that occurred during that period, and is used to calculate the IP's power consumption. However, in actual operation, the IP will continuously shut down and restart as needed. After a restart, all IP counts will reset from 0, meaning that two consecutive counts will no longer reflect the true number of events.
[0003] When the power management system (PMS) is responsible for powering on and off the IP, there are no problems because the PMS knows when the counter will reach zero. However, when the power-on / off operation of the IP is handled by other systems (such as ARM Trust Firmware, ATF), the PMS cannot know when the counter will reach zero. Furthermore, when the IP is powered off, the PM reading the counter can cause the entire system to crash or restart. To solve this problem, the IP needs to send a signal to the PMS before and after each restart. The PMS then calculates the event count for each of these two scenarios (whether a restart has occurred) using different methods. This increases the complexity of the PMS software, especially when there are many IPs. If the IP uses interrupts to notify the PMS of restart events, it consumes a significant amount of the PMS's interrupt resources. Therefore, how to efficiently and accurately count IP events has become a pressing issue. Summary of the Invention
[0004] This invention provides an event counting method, apparatus, electronic device, and storage medium to solve the problem that existing technologies cannot accurately and efficiently count IP events.
[0005] According to one aspect of the present invention, an event counting method is provided, wherein the method includes:
[0006] Obtain the mutex lock corresponding to the chip intellectual property core according to the target cycle;
[0007] When the mutex is successfully acquired, the read value of the power-on count register is determined, and the initial count value of the chip intellectual property core event is determined based on the read value.
[0008] Obtain the current count value, and determine the target count value of the chip intellectual property core event based on the current count value and the initial count value.
[0009] According to another aspect of the present invention, an event counting device is provided, wherein the device comprises:
[0010] The mutex lock acquisition module is used to acquire the mutex lock corresponding to the chip intellectual property core according to the target cycle;
[0011] The numerical reading module is used to determine the read value of the power-on count register when the mutex is successfully acquired, and to determine the initial count value of the chip intellectual property core event based on the read value;
[0012] The count value determination module is used to obtain the current count value and determine the target count value of the chip intellectual property core event based on the current count value and the initial count value.
[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:
[0014] At least one processor; and
[0015] A memory communicatively connected to the at least one processor; wherein,
[0016] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the event counting method according to any embodiment of the present invention.
[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the event counting method according to any embodiment of the present invention.
[0018] According to another aspect of the present invention, embodiments of the present invention also provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the event counting method of any embodiment of the present invention.
[0019] The technical solution of this invention obtains the mutex lock corresponding to the chip intellectual property core according to the target cycle. When the mutex lock is successfully obtained, the read value of the power-on count register is determined. The initial count value of the chip intellectual property core event is determined based on the read value. The current count value is obtained. The target count value of the chip intellectual property core event is determined based on the current count value and the initial count value. This enables the detection of whether the chip intellectual property core has undergone power-on and power-off before determining the target count value, avoiding the problem of inaccurate target count value when the chip intellectual property core is powered on and off, and improving the accuracy of determining the target count value.
[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a flowchart of an event counting method provided in Embodiment 1 of the present invention;
[0023] Figure 2 This is a flowchart of an event counting method provided in Embodiment 2 of the present invention;
[0024] Figure 3 This is a schematic diagram of the structure of an event counting system provided in Embodiment 3 of the present invention;
[0025] Figure 4 This is a flowchart of an event counting method provided in Embodiment 3 of the present invention;
[0026] Figure 5 This is a flowchart of another event counting method provided in Embodiment 3 of the present invention;
[0027] Figure 6 This is a schematic diagram of the structure of an event counting device according to Embodiment 4 of the present invention;
[0028] Figure 7 This is a schematic diagram of the structure of an electronic device that implements the event counting method of this invention. Detailed Implementation
[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0031] Example 1
[0032] Figure 1 This is a flowchart of an event counting method according to Embodiment 1 of the present invention. This embodiment is applicable to situations where the count of chip intellectual property core events is accurately determined. The method can be executed by an event counting device, which can be implemented in hardware and / or software. This event counting device can be configured in an electronic device, such as a power management system (PM). Figure 1 As shown, the method includes:
[0033] S110. Obtain the mutex lock corresponding to the chip intellectual property core according to the target cycle.
[0034] The target period can be understood as a fixed time interval for acquiring the mutex. Generally, the target period can be customized according to business needs, such as 4ms, 5ms, 10ms, etc. The chip intellectual property core (IP core) can be understood as a pre-set hardware functional module in the context of system-on-chip (SOC) power management and performance statistics. It can be an independent functional circuit or a fully functional subsystem integrated into the SOC chip, forming the basic unit of the SOC chip. The mutex is a hardware-level exclusive access control mechanism that ensures that only one entity (the chip IP core or PM) can access the performance monitoring unit register and power-on count register of the chip IP core at any given time, avoiding data read errors or counting chaos caused by concurrent access. In one embodiment, the mutex is released to an idle state by the chip IP core after the driver completes initialization and the power-on count register is read normally. That is, when the chip IP core completes initialization such as requesting IP power, enabling related clocks, and releasing reset signals, and the power-on count register can be read normally, the chip IP core releases the mutex to an idle state.
[0035] In this embodiment, the mutex locks corresponding to the chip's intellectual property core can be acquired according to a target period. In actual operation, the target period can be set via a timer, and the mutex locks corresponding to the chip's intellectual property core can be acquired automatically after the timer expires.
[0036] S120. When the mutex is successfully acquired, determine the read value of the power-on count register, and determine the initial count value of the chip intellectual property core event based on the read value.
[0037] In one embodiment, the mutex is successfully acquired when it is in an idle state released by the chip intellectual property core (IPC). That is, acquisition fails when the mutex is in a held state. The power-on count register can be understood as a non-volatile hardware register that records the cumulative number of power-on resets of the IPC. Generally, the power-on count register can be accessed by the IPC and the power management system. In one embodiment, the IPC increments the read value of the power-on count register after the driver completes initialization. IPC events refer to hardware-level operations or state changes that occur during the operation of the IPC and are strongly related to its own functions, such as specific hardware events triggered during operation, interaction, or state switching. In practical applications, the read value can include the read value of the power-on count register at a historical time and the read value of the power-on count register at the current time.
[0038] In this embodiment, when it is determined that the chip intellectual property core has completed driver initialization and the power-on count register can be read normally, the mutex lock is successfully acquired. At this time, the read value of the power-on count register can be read, and the initial count value of the chip intellectual property core events can be determined according to the read value. In actual application, the read value of the power-on count register at the current moment and the read value of the power-on count register at a historical moment can be read separately. If the read value of the power-on count register at the current moment and the read value of the power-on count register at a historical moment are the same, it can be considered that the chip intellectual property core has not been re-powered within the target period. At this time, the count value of the chip intellectual property core events recorded at a historical moment can be extracted as the initial count value. If the read value of the power-on count register at the current moment and the read value of the power-on count register at a historical moment are different, it can be considered that the chip intellectual property core has been re-powered within the target period. At this time, the chip intellectual property core events can be re-counted within the target period, and the count value of the recorded chip intellectual property core events can be initialized to determine the initial count value as zero.
[0039] S130. Obtain the current count value, and determine the target count value of the chip intellectual property core event based on the current count value and the initial count value.
[0040] The current count value can be understood as the count value of chip intellectual property core events at the current moment. In actual operation, the count value of chip intellectual property core events can be recorded through the performance monitoring unit register. The target count value can be understood as the number of intellectual property core events within the target period.
[0041] In this embodiment, the count value of the chip intellectual property core event can be read as the current count value, the difference between the current count value and the initial count value can be determined, and the difference can be used as the target count value for the chip intellectual property core event. In practical applications, the count value of the monitoring unit register can be read as the current count value.
[0042] In this embodiment of the invention, the mutex lock corresponding to the chip intellectual property core is obtained according to the target cycle. When the mutex lock is successfully acquired, the read value of the power-on count register is determined. The initial count value of the chip intellectual property core event is determined based on the read value. The current count value is obtained. The target count value of the chip intellectual property core event is determined based on the current count value and the initial count value. This enables the chip intellectual property core to be detected as having undergone a power-on / off cycle before the target count value is determined, avoiding the problem of inaccurate target count value when the chip intellectual property core is powered on / off, and improving the accuracy of determining the target count value.
[0043] In one embodiment, after acquiring the mutex lock corresponding to the chip intellectual property core according to the target period, the method further includes:
[0044] If the mutex lock cannot be acquired, the target count value is determined to be zero.
[0045] In this embodiment, if the acquisition of the mutex is unsuccessful when the mutex is in a held state, it can be assumed that the chip intellectual property core has not generated a chip intellectual property core event, and the target count value is recorded as zero.
[0046] In one embodiment, after obtaining the current count value and determining the target count value of the chip intellectual property core event based on the current count value and the initial count value, the method further includes:
[0047] Release the mutex lock and store the current power-on count register value as the historical power-on count register value;
[0048] Store the current count value as a historical count value.
[0049] The historical count value can be understood as the count value of chip intellectual property core events in the previous target cycle, that is, the count value at a historical moment. Generally speaking, the historical count value can be read from the monitoring unit register.
[0050] In this embodiment, after obtaining the current count value and determining the target count value of the chip intellectual property core event based on the current count value and the initial count value, the mutex can be released to allow the chip intellectual property core event to acquire the mutex. Simultaneously, the current power-on count register read value can be recorded as the historical power-on count register read value, and the current count value can be recorded as the historical count value, facilitating the determination of the target count value in the next target cycle.
[0051] Example 2
[0052] Figure 2 This is a flowchart of an event counting method according to Embodiment 2 of the present invention. This embodiment is a further optimization and extension based on the above embodiments, and can be combined with various optional technical solutions in the above embodiments. Figure 2 As shown, the method includes:
[0053] S210. Obtain the mutex lock corresponding to the chip intellectual property core according to the target cycle.
[0054] S220. Collect the current power-on count register reading value and extract the historical power-on count register reading value.
[0055] In this embodiment, the current power-on count register value and the historical power-on count register value can be read separately.
[0056] S230. Determine whether the read value of the power-on count register at the historical time is the same as the read value of the power-on count register at the current time.
[0057] In this embodiment, after determining the reading value of the power-on count register at a historical time and the reading value of the power-on count register at the current time, it can be determined whether the reading value of the power-on count register at a historical time and the reading value of the power-on count register at the current time are the same.
[0058] S240. If they are the same, extract the historical count value as the initial count value for the chip intellectual property core event.
[0059] If the reading value of the power-on count register at a historical moment is the same as the reading value of the power-on count register at the current moment, the historical count value can be extracted and used as the initial count value of the chip intellectual property core event.
[0060] S250. If they are not the same, determine that the initial count value of the intellectual property nuclear event is zero.
[0061] If the reading value of the power-on count register at a historical time is the same as the reading value of the power-on count register at the current time, the initial count value of the intellectual property kernel event is determined to be zero.
[0062] S260, the count value of the acquisition performance monitoring unit register is used as the current count value.
[0063] Among them, the performance monitoring unit register is a set of dedicated hardware registers used to configure monitoring rules and record hardware chip intellectual property events.
[0064] In this embodiment, the count value of the performance monitoring unit register can be read and used as the current count value.
[0065] S270. Determine the difference between the current count value and the initial count value as the target count value for the chip intellectual property core event.
[0066] In this embodiment, the difference between the current count value and the initial count value can be determined, and the difference between the current count value and the initial count value can be used as the target count value for the chip intellectual property core event.
[0067] In this embodiment of the invention, the mutex corresponding to the chip intellectual property core is obtained according to the target cycle. The read value of the power-on count register at the current moment is collected, and the read value of the power-on count register at the historical moment is extracted. It is determined whether the read value of the power-on count register at the historical moment is the same as the read value of the power-on count register at the current moment. If they are the same, the historical count value is extracted as the initial count value of the chip intellectual property core event. If they are different, the initial count value of the intellectual property core event is determined to be zero, thus achieving accurate determination of the initial count value. The count value of the performance monitoring unit register is collected as the current count value, and the difference between the current count value and the initial count value is determined as the target count value of the chip intellectual property core event, thereby improving the accuracy of determining the target count value.
[0068] Example 3
[0069] Figure 3 This is a schematic diagram of an event counting system according to Embodiment 3 of the present invention. This embodiment takes the execution of an event counting method by the event counting system as an example, and uses IP as the core of chip intellectual property rights as an example to further explain an event counting method, such as... Figure 3 As shown, the system includes: a global resource area, a central processing unit (CPU), a power management system (PM), and IP. The global resource area is typically reserved in a System-on-a-Chip (SoC) for data sharing, accessible to all modules. Relevant to this application are a power-on count register and a hardware mutex. The IP driver increments the power-on count register by 1 after each IP power-on. Access to the IP's power management unit (PMU) register is only permitted when the PM acquires the mutex. The mutex is held by the IP driver during SoC power-on. The power management system (PM) reads the IP's PMU register at regular intervals. The IP's PMU register increments to count the occurrence of a specific event for performance evaluation, power consumption calculation, etc., and starts counting from 0 after each reboot. The IP driver, running on the CPU, releases the mutex when the IP driver is initialized and the PMU can be read normally. When the IP driver is about to shut down, it acquires the mutex to prevent the PM from accessing the PMU after acquiring the mutex, thus preventing errors.
[0070] In one embodiment, Figure 4 This is a flowchart of an event counting method provided in Embodiment 3 of the present invention, as shown below. Figure 4 The diagram shows the software execution flow on the PM side, which includes:
[0071] Step 1: Initialize variables p(new)=p(last)=0 (representing the current register reading and the previous PMU register reading, respectively), n(new)=n(last)=0 (representing the current power-on count register reading and the previous power-on count register reading, respectively), initialize a timer, and trigger it in a loop according to the target period (e.g., 5ms).
[0072] Step 2: Wait for the timer to expire. After the timer expires, the following steps will be executed to obtain the count value of the PMU register for this cycle.
[0073] Step 3: Try to acquire the mutex lock corresponding to the IP address.
[0074] Step 4: If the mutex acquisition fails, it means that the mutex is occupied by the IP, which means that the IP is in a suspended or idle state. Assign p(new) = p(last), and then go to step 9. Finally, the count of the PMU in this cycle is 0.
[0075] Step 5: If the mutex lock acquisition in step 3 is successful, it means that the IP is in working state and the PMU register is readable. Then, first read the power-on count register.
[0076] Step 6: Determine whether the power-on count register read this time is consistent with the value read last time. If they are inconsistent, it means that the IP has undergone power-off and power-on operations between these two reads. That is, the PMU count will be reset to zero and start counting again. At this time, set p(last) to 0 and go to step 7.
[0077] Step 7: Read the PMU register and assign the value to p(new).
[0078] Step 8: Release the mutex.
[0079] Step 9: Calculate the effective count of PMU in this period as p(new) - p(last).
[0080] Step 10: Reinitialize the variables, i.e., p(last) = p(new) and n(last) = n(new) to prepare for the next cycle.
[0081] In one embodiment, Figure 5 This is a flowchart of another event counting method provided in Embodiment 3 of the present invention, as shown below. Figure 5 The diagram shows the CPU-side software execution flow, which includes:
[0082] Step 1: When the system is powered on, the mutex lock is initialized to the IP driver's occupied state. The system scheduler determines when the IP will start. When the IP is determined to start, the IP driver will be called to initialize it, which leads to Step 2.
[0083] Step 2: Request IP power, enable relevant clocks, and remove reset signals to provide the prerequisites for IP to start working.
[0084] Step 3: Complete the IP initialization process. At this point, the PMU will officially start working and begin incrementing the count of specific events.
[0085] Step 4: Increment the power-on count counter to notify PM that the PMU has been reset to zero and will start counting again.
[0086] Step 5: Release the mutex lock. After that, the PM can read the PMU registers in a loop.
[0087] Step 6: The IP performs a normal workflow, which may take an indefinite period of time.
[0088] Step 7: Determine whether to suspend the IP based on factors such as system scheduling and IP working status. If it is determined not to suspend, proceed to step 6; if it is determined to suspend the IP, proceed to step 8.
[0089] Step 8: Continuously try to acquire the mutex lock until successful. After acquiring the lock, the PM side will no longer access the PMU register.
[0090] Step 9: Clear the resources occupied by the IP, prepare to suspend the IP, and then jump back to Step 1 to return to the system scheduling state.
[0091] In this embodiment, a global mutex lock and a power-on count register enable the PM to perceive the IP's state before accessing the IP. This allows the PM to confirm whether the PMU is currently readable and to know whether the IP has undergone a power-on / power-off cycle between two reads. Combined with the process method of this invention, no other communication mechanism needs to be established between the PM and the IP, resulting in minimal software and hardware overhead.
[0092] Example 4
[0093] Figure 6 This is a schematic diagram of the structure of an event counting device according to Embodiment 4 of the present invention. Figure 6 As shown, the device includes: a mutex lock acquisition module 61, a value reading module 62, and a count value determination module 63.
[0094] Among them, the mutex lock acquisition module 61 is used to acquire the mutex lock corresponding to the chip intellectual property core according to the target period.
[0095] The numerical reading module 62 is used to determine the read value of the power-on count register when the mutex lock is successfully acquired, and to determine the initial count value of the chip intellectual property core event based on the read value.
[0096] The count value determination module 63 is used to obtain the current count value and determine the target count value of the chip intellectual property core event based on the current count value and the initial count value.
[0097] The technical solution of this invention involves a mutex lock acquisition module acquiring the mutex lock corresponding to the chip intellectual property core according to the target cycle. When the mutex lock is successfully acquired, the value reading module determines the read value of the power-on count register and determines the initial count value of the chip intellectual property core event based on the read value. The count value determination module acquires the current count value and determines the target count value of the chip intellectual property core event based on the current count value and the initial count value. This allows the system to detect whether the chip intellectual property core has undergone a power-on / off cycle before determining the target count value, avoiding inaccurate target count values when the chip intellectual property core is powered on / off, and improving the accuracy of determining the target count value.
[0098] In one embodiment, the event counting device further includes:
[0099] The counter value assignment module is used to determine the target counter value to be zero when the mutex lock acquisition fails.
[0100] In one embodiment, the mutex is released to an idle state by the chip intellectual property core after the chip intellectual property core has completed initialization and the power-on count register has a normal reading.
[0101] The mutex was successfully acquired while in an idle state that was released by the chip's intellectual property core.
[0102] In one embodiment, the numerical reading module 62 includes:
[0103] The read value determination unit is used to collect the read value of the power-on count register at the current moment and extract the read value of the power-on count register at historical moments;
[0104] The read value judgment unit is used to determine whether the read value of the power-on count register at a historical time is the same as the read value of the power-on count register at the current time;
[0105] The first determining unit is used to extract historical count values as the initial count values for chip intellectual property core events if they are the same.
[0106] The second determining unit is used to determine the initial count value of the intellectual property nuclear event as zero if they are not the same.
[0107] In one embodiment, the count value determination module 63 includes:
[0108] The counting acquisition unit is used to acquire the count value from the performance monitoring unit register as the current count value;
[0109] The count value determination unit is used to determine the difference between the current count value and the initial count value as the target count value for chip intellectual property core events.
[0110] In one embodiment, the event counting device further includes:
[0111] The mutex release module is used to release the mutex and store the current power-on count register as the historical power-on count register.
[0112] The numerical storage module is used to store the current count value as a historical count value.
[0113] In one embodiment, after the driver completes initialization, the chip intellectual property core increments the read value of the power-on count register.
[0114] The event counting device provided in the embodiments of the present invention can execute the event counting method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.
[0115] Example 5
[0116] Figure 7 This is a schematic diagram of the structure of an electronic device implementing the event counting method of embodiments of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.
[0117] like Figure 7 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0118] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0119] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the event counting method.
[0120] In some embodiments, the event counting method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the event counting method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the event counting method by any other suitable means (e.g., by means of firmware).
[0121] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0122] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0123] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0124] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0125] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.
[0126] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.
[0127] In one embodiment, the present invention further includes a computer program product, which includes a computer program that, when executed by a processor, implements the event counting method of any embodiment of the present invention.
[0128] In implementing the computer program product, computer program code for performing the operations of this invention can be written in one or more programming languages or a combination thereof. Programming languages include object-oriented programming languages such as Java, Smalltalk, and C++, as well as conventional procedural programming languages such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0129] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0130] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. An event counting method, characterized in that, include: The mutex lock corresponding to the chip intellectual property core is obtained according to the target cycle; wherein, the mutex lock is used to control that only one subject can access the performance monitoring unit register and power-on count register of the chip intellectual property core at the same time; the subject includes the power management system and the chip intellectual property core; If the mutex is successfully acquired, the read value of the power-on count register is determined, and the initial count value of the chip intellectual property core event is determined based on the read value; wherein, if the mutex is in a held state, the acquisition of the mutex is unsuccessful. The mutex is released to an idle state by the chip intellectual property core when the chip intellectual property core has completed initialization and the power-on count register is reading normally. The mutex was successfully acquired while in an idle state that was released by the chip's intellectual property core. Obtain the current count value, and determine the target count value of the chip intellectual property core event based on the current count value and the initial count value; The determination of the read value of the power-on count register, and the determination of the initial count value of the chip intellectual property core event based on the read value, includes: Collect the current power-on count register value and extract the historical power-on count register value; Determine whether the reading value of the power-on count register at a historical time is the same as the reading value of the power-on count register at the current time; If they are the same, extract the historical count value as the initial count value for the chip intellectual property core event; If they are not the same, the initial count value of the intellectual property core event is determined to be zero.
2. The method according to claim 1, characterized in that, After obtaining the mutex lock corresponding to the chip intellectual property core according to the target period, the method further includes: If the acquisition of the mutex lock fails, the target count value is determined to be zero.
3. The method according to claim 1, characterized in that, The step of obtaining the current count value and determining the target count value of the chip intellectual property core event based on the current count value and the initial count value includes: The count value in the performance monitoring unit register is used as the current count value; The difference between the current count value and the initial count value is determined as the target count value for the chip intellectual property core event.
4. The method according to claim 1, characterized in that, After obtaining the current count value and determining the target count value of the chip intellectual property core event based on the current count value and the initial count value, the method further includes: Release the mutex lock and store the current power-on count register value as the historical power-on count register value; The current count value is stored as a historical count value.
5. The method according to claim 1, characterized in that, After the driver completes initialization, the chip's intellectual property core increments the power-on count register value.
6. An event counting device, characterized in that, include: A mutex lock acquisition module is used to acquire the mutex lock corresponding to the chip intellectual property core according to the target cycle; wherein, the mutex lock is used to control that only one subject can access the performance monitoring unit register and power-on count register of the chip intellectual property core at the same time; the subject includes the power management system and the chip intellectual property core; The value reading module is used to determine the read value of the power-on count register when the mutex is successfully acquired, and to determine the initial count value of the chip intellectual property core event based on the read value; wherein, when the mutex is in a holding state, the acquisition of the mutex is unsuccessful; the count value determination module is used to obtain the current count value, and to determine the target count value of the chip intellectual property core event based on the current count value and the initial count value; The mutex is released to an idle state by the chip intellectual property core when the chip intellectual property core has completed initialization and the power-on count register is reading normally. The mutex was successfully acquired while in an idle state that was released by the chip's intellectual property core. The numerical reading module includes: The read value determination unit is used to collect the read value of the power-on count register at the current moment and extract the read value of the power-on count register at historical moments; The read value judgment unit is used to determine whether the read value of the power-on count register at a historical time is the same as the read value of the power-on count register at the current time; The first determining unit is used to extract historical count values as the initial count values for chip intellectual property core events if they are the same. The second determining unit is used to determine that the initial count value of the intellectual property core event is zero if they are not the same.
7. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the event counting method according to any one of claims 1-5.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the event counting method according to any one of claims 1-5.