Neural network processor core scheduling method and system for simd architecture

By optimizing the in-core scheduling method of the neural network processor on the SIMD architecture, and utilizing DAG topology sorting and cache management, the problem of low resource utilization is solved, achieving more efficient resource utilization and lower operator runtime.

CN121833052BActive Publication Date: 2026-06-12HUAZHONG UNIV OF SCI & TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
HUAZHONG UNIV OF SCI & TECH
Filing Date
2026-03-11
Publication Date
2026-06-12

AI Technical Summary

Technical Problem

Existing neural network processors have low resource utilization on SIMD architecture, failing to effectively utilize idle computing power within the chip, resulting in low resource utilization.

Method used

We adopt an in-core scheduling method for neural network processors with SIMD architecture. By using topological sorting and cache management of the directed acyclic graph (DAG), combined with the list of free intervals based on node priority and cache type, we optimize cache allocation and swap-in/swap-out operations, generate a scheduling sequence that satisfies the topological order, and improve resource utilization.

Benefits of technology

It effectively utilizes the idle computing power within the chip, reduces cache fragmentation, lowers the total operator runtime, and improves resource utilization and scheduling efficiency.

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Abstract

The application discloses a neural network processor kernel scheduling method and system for a SIMD architecture, and belongs to the technical field of processor scheduling.The three-level screening mechanism of node type priority, time window priority and memory influence degree priority is used in combination with dependency constraint processing and L0 cache mutual exclusion constraint management to generate a scheduling sequence meeting topological order and having minimum peak cache residence, idle computing power in the chip is effectively utilized, and resource utilization is improved.On this basis, the application also optimizes cache allocation and swap-in and swap-out operations based on a cost-aware strategy to generate an optimized scheduling sequence containing swap-in and swap-out operation nodes, realizes minimum swap-in and swap-out memory, and further improves scheduling efficiency and resource utilization.In addition, the application further optimizes the swap-in and swap-out positions, further reduces the total operator running time on the premise of ensuring that the total additional data carrying amount does not significantly increase.
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