A method, system, medium and product for processing a translation lookaside buffer entry
By storing non-critical entries from the translation lookup buffer into the L1 cache during process switching in the RISC-V architecture and writing them back to the translation lookup buffer before switching back to the previous process, the problem of low TLB hit rate is solved, and processor performance is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2026-03-13
- Publication Date
- 2026-05-29
Smart Images
Figure CN121833555B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of processor technology, and in particular to a method, system, medium, and product for processing translation backup buffer entries. Background Technology
[0002] In the RISC-V (Reduced Instruction Set Computing – Five) architecture, the TLB (Translation Lookaside Buffer) needs to cache TLB entries for multiple processes. However, the CPU (Central Processing Unit) core only runs one process at a time. A large amount of TLB space is cached with TLB entries for processes that are not currently running. This results in a low hit rate for currently running processes when performing TLB lookups, often leading to a page table lookup. Since page tables reside in memory, multiple memory accesses may be required, resulting in performance degradation.
[0003] Therefore, how to improve the hit rate of translation back buffer entries, thereby improving processor performance, is a problem that needs to be solved by those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a method, system, medium, and product for processing translated backup buffer entries, which can improve the hit rate of translated backup buffer entries and thus improve processor performance.
[0005] In a first aspect, the present invention provides a method for processing translation back buffer entries, comprising: during process switching, determining non-critical entries in the translation back buffer corresponding to the previous process to obtain a target non-critical entry; storing the target non-critical entry in the L1 cache corresponding to the processor core, and deleting the target non-critical entry from the translation back buffer; obtaining a recovery deadline issued by the operating system corresponding to the previous process; and, based on the recovery deadline, writing the target non-critical entry back to the translation back buffer from the L1 cache before switching back to the previous process.
[0006] Optionally, after storing the target non-critical entry in the L1 cache corresponding to the processor core and deleting the target non-critical entry from the translation back buffer, the method further includes: if the estimated running time of the process after the switch is greater than a first preset time threshold, then storing the target non-critical entry in memory and deleting the target non-critical entry from the L1 cache.
[0007] Optionally, before writing the target non-critical entry back to the translation backup buffer from the first-level cache, the method further includes: if the recovery deadline is less than a second preset time threshold, writing the target non-critical entry back to the first-level cache from the memory.
[0008] Optionally, it also includes: if the estimated running time of the process before the switch is less than or equal to the first preset time threshold, then the target non-critical entry is retained in the first-level cache.
[0009] Optionally, it also includes: during process switching, if the first-level cache has not allocated space corresponding to the translation back buffer table entries, then based on the space allocation information, a target space for storing translation back buffer table entries is allocated in the first-level cache.
[0010] Optionally, determining the non-critical entries corresponding to the previous process in the translation backup buffer includes: determining the non-critical entries corresponding to the previous process in the translation backup buffer based on the monitoring information of the critical entries corresponding to the previous process.
[0011] Optionally, it also includes: monitoring the first N entries in the translation backup buffer accessed by the process before the switchover during its first run, to obtain the key entry monitoring information corresponding to the process before the switchover.
[0012] Optionally, it also includes: monitoring entries in the translation backup buffer that are continuously accessed by the process before the switchover to obtain key entry monitoring information corresponding to the process before the switchover.
[0013] Optionally, it also includes: monitoring high-frequency access entries of the process before the switchover in the translation backup buffer to obtain key entry monitoring information corresponding to the process before the switchover, wherein the access frequency of the high-frequency access entries is greater than the access frequency of the low-frequency access entries.
[0014] Optionally, it further includes: determining entries with the same physical address from the translation backup buffer to obtain common entries; deleting duplicate physical addresses in the common entries from the translation backup buffer, and retaining one of the physical addresses with the same physical address.
[0015] Secondly, the present invention provides a translation backup buffer entry processing system, comprising:
[0016] The entry determination module is used to determine the non-critical entries corresponding to the previous process in the translation backup buffer during process switching, and obtain the target non-critical entries.
[0017] The table entry caching module is used to store the target non-critical table entry into the L1 cache corresponding to the processor core, and to delete the target non-critical table entry from the translation back buffer.
[0018] The time acquisition module is used to acquire the recovery deadline corresponding to the process before the switch, issued by the operating system.
[0019] The table entry write-back module is used to write the target non-critical table entry from the first-level cache to the translation backup buffer based on the recovery deadline and before switching back to the process before the switchover.
[0020] Optionally, it also includes: a process key entry analysis module, used to monitor key entries of the process before the switch and obtain key entry monitoring information corresponding to the process before the switch.
[0021] Optionally, it also includes: a common entry analysis module, used to determine entries with the same physical address from the translation backup buffer to obtain common entries; delete duplicate physical addresses in the common entries in the translation backup buffer, and retain one of the physical addresses with the same physical address.
[0022] Thirdly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the aforementioned translation back buffer table entry processing method.
[0023] Fourthly, the present invention provides a computer program product, including a computer program / instruction that, when executed by a processor, implements the aforementioned translation back buffer table entry processing method.
[0024] As can be seen, the beneficial effects of this invention are as follows: During process switching, non-critical entries corresponding to the previous process in the translation back buffer are first determined and stored in the L1 cache corresponding to the processor core, and then deleted from the translation back buffer. Furthermore, the recovery deadline for the previous process issued by the operating system is obtained. Based on the recovery deadline, it is ensured that non-critical entries are written back to the translation back buffer from the L1 cache before switching back to the previous process. This increases the available translation back buffer space for the switched process and reduces the number of entries for other processes in the translation back buffer. While ensuring rapid recovery of the previous process, it can improve the hit rate of translation back buffer entries, thereby improving processor performance. Attached Figure Description
[0025] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a diagram of a multi-core RISC-V CPU architecture;
[0027] Figure 2 This is a schematic diagram of a physical address lookup and data lookup process.
[0028] Figure 3 A flowchart of a translation backup buffer entry processing method provided in an embodiment of the present invention;
[0029] Figure 4 An application architecture diagram of a translation backup buffer entry processing scheme provided in an embodiment of the present invention;
[0030] Figure 5 This is a schematic diagram of a spatial repartitioning module provided in an embodiment of the present invention;
[0031] Figure 6 A schematic diagram of a process key entry analysis module provided in an embodiment of the present invention;
[0032] Figure 7 This is a schematic diagram of a common item analysis module provided in an embodiment of the present invention;
[0033] Figure 8 This is a schematic diagram of a translation backup buffer entry processing system provided in an embodiment of the present invention. Detailed Implementation
[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.
[0035] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.
[0036] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0037] Multi-core RISC-V CPUs: A multiprocessor design based on the open-source RISC-V instruction set architecture (ISA), widely used in embedded systems, high-performance computing (HPC), and artificial intelligence acceleration. In the RISC-V architecture, the TLB (TLB) is a core component of the Memory Management Unit (MMU), responsible for accelerating the translation from virtual to physical addresses. It caches the mapping between virtual and physical addresses, avoiding page table lookups. Virtual addresses are issued by the kernel, and each process has its own independent virtual address space. Physical addresses are unique and represent the addresses of data in memory.
[0038] See Figure 1 As shown, Figure 1 This is a diagram of a multi-core RISC-V CPU architecture. In traditional multi-core RISC-V CPU implementations, as shown in the diagram, the multi-core CPU is a multi-core RISC-V CPU. A multi-core RISC-V CPU contains multiple RISC-V Cores (i.e., RISC-V processor cores). Each core has corresponding instruction fetch units, decode units, execution units, memory access units, and write-back units. Each core corresponds to an L1 cache (Level 1 cache), which is unique to the RIC-V core. Each core also corresponds to a TLB, which caches the mapping between virtual and physical addresses of multiple processes running on the corresponding RISC-V core. Multi-core RISC-V CPUs range from 2 cores, 4 cores, 8 cores, 16 cores, 32 cores… to 128 cores. The L1 cache (Level 1 cache) space is typically 32KB-64KB, while the L2 cache (Level 2 cache) is shared by multiple RISC-V cores, typically ranging from 256KB to 2MB, and can be accessed via the memory bus. Figure 2 As shown, Figure 2This diagram illustrates a physical address lookup and data lookup process. The RISC-V Core issues a virtual address for accessing cached data. First, it checks the corresponding TLB to see if the physical address corresponding to the virtual address is cached in the TLB. If the physical address is found in the TLB, the physical address currently being accessed by the process is directly obtained. If the physical address is not found in the TLB, it needs to access a multi-level page table (page tables reside in memory (which can be DDR (Double Data Rate) memory). In SV48 (Supervisor-level Virtual Memory with 48-bit addresses) structures, there are 4 levels of page tables, requiring 4 memory accesses; in SV39 (39-bit supervisor-level virtual memory) structures, there are 3 levels of page tables, requiring 3 memory accesses. 48 / 39 refers to the width of the virtual address) via the memory bus to obtain the physical address. Simultaneously, the TLB entry corresponding to the current process is updated, i.e., the TLB entry for the current process is replaced, thus updating the TLB. TLB entries for other processes are not replaced. After obtaining the physical address currently accessed by the current process, the data is retrieved from the data cache (L1 / L2 cache), that is, cached data is retrieved.
[0039] In the RISC-V architecture, each cached entry in the TLB has a unique ASID (Address Space Identifier). This ID indicates the process to which the TLB entry belongs. TLB entries are uniquely identified by [virtual address + ASID]. When switching processes in a RISC-V multi-core CPU, the TLB entries of the old process are not automatically cleared. If the process is rescheduled, it can be quickly restored to prevent the phenomenon of cold start caused by the empty TLB after the old TLB is completely cleared during the process switching (memory access requires refilling, which adds about 50-100 clock cycles / missing). However, the traditional implementation of TLB functionality in multi-core RISC-V CPUs has significant drawbacks: TLB space cannot be used efficiently because it caches TLB entries for multiple processes. These TLB entries are independent and cannot be reused. In multi-process scenarios with RISC-V CPUs, TLB utilization is very low. This results in a low TLB hit rate when running multi-process programs (because multiple processes' TLBs are cached, while the CPU only runs one process at a time). A large amount of TLB space is cached for TLB entries of other processes not currently running. This causes the currently running process to frequently miss TLB queries, leading to page table lookups. Page tables reside in DDR memory; for example, SV48 uses a 4-level page table structure. A single page table lookup to obtain the physical address requires four DDR memory accesses, resulting in a low TLB hit rate and a decrease in multi-core RISC-V CPU performance. Even during TLB updates, only the TLB entries for the current process are updated, leaving other TLB entries untouched. To this end, the present invention provides a translation back buffer table entry processing scheme, which can improve the TLB space utilization of multi-core RISC-V CPU, improve the TLB hit rate, improve the overall performance of multi-core RISC-V CPU, and promote the product application of multi-core RISC-V CPU in high-performance processor scenarios without affecting the efficiency of multi-process switching.
[0040] Next, a method for processing translation backup buffer entries provided by an embodiment of the present invention will be described in detail. Figure 3 A flowchart of a translation backup buffer entry processing method provided in this embodiment of the invention is shown. The method includes:
[0041] Step S11: During process switching, determine the non-critical entries in the translation backup buffer corresponding to the previous process, and obtain the target non-critical entries.
[0042] In this embodiment, during process switching, the old process is the process before the switch and the new process is the process after the switch. The number of processes that will be run by the core in a core is 1.
[0043] This embodiment can determine non-critical entry information based on critical entry monitoring information, and determine the non-critical entries corresponding to the previous process in the translation backup buffer based on the non-critical entry information corresponding to the previous process. The critical entry monitoring information carries the critical entries of the process, which can be obtained through monitoring.
[0044] This embodiment can monitor the first N entries in the translation backup buffer accessed when the process before the switchover runs for the first time, and obtain the key entry monitoring information corresponding to the process before the switchover.
[0045] Where N is a positive integer, which can be a preset default value and can be adjusted. The first N entries are the starting entries of the process and are critical entries. If the process cannot access the starting entry in the translation backing buffer, it needs to access the cached entries in memory multiple times to start the current process, which will greatly reduce the running speed of the current process and reduce the performance of the RISC-V CPU. This embodiment can overcome this problem.
[0046] This embodiment can monitor entries in the translation back buffer that are continuously accessed by the process before the switchover, and obtain the key entry monitoring information corresponding to the process before the switchover. Here, "continuous" refers to continuous virtual address access. Continuous access indicates that the current process needs to continuously load / write data. Identifying such entries as key entries ensures fast, continuous TLB hits, avoids pipeline interruptions, and thus improves RISC-V CPU performance.
[0047] This embodiment can also monitor the high-frequency access entries of the pre-switch process in the translation backup buffer to obtain the key entry monitoring information corresponding to the pre-switch process, wherein the access frequency of the high-frequency access entries is greater than the access frequency of the low-frequency access entries.
[0048] Specifically, entries with access frequencies exceeding a preset access frequency threshold can be identified as high-frequency access entries, or entries with the highest access frequencies from the previous process can be selected as high-frequency access entries according to a preset ratio, such as the top 10%. In an optional implementation, this application can count the number of accesses for each entry within a statistical period. Each entry is configured with a counter. After the statistical period ends, the access frequency of the entry is determined based on the counter, and the counter is reset to zero. An interval time can be set. After any statistical period ends, the interval time is reached, and the statistics are started again to update the access frequency. The statistical period is a preset time, but it can also be adjusted. That is, in this application, the number of accesses to TLB entries (i.e., entries) is counted within the statistical period. Each TLB entry is configured with a counter, but the count is not performed every cycle, such as once every 10ms. After the statistics within the statistical period are completed, the counter is reset to zero, and the counter starts counting again in the next statistical period. The above method is only an example, and this application does not limit the method of determining the access frequency.
[0049] In an optional implementation, the key entry monitoring information may include one or more of the following: monitoring information of the aforementioned first N entries, monitoring information of continuously accessed entries in the translation backup buffer, and monitoring information of frequently accessed entries.
[0050] Step S12: Store the target non-critical entry into the L1 cache corresponding to the processor core, and delete the target non-critical entry from the translation back buffer.
[0051] In this embodiment, each processor core corresponds to a level 1 cache. Target non-critical entries can be stored in the level 1 cache corresponding to the processor core, and target non-critical entries can be deleted from the translation back buffer.
[0052] Additionally, during process switching, if the L1 cache has not allocated space for the translated back buffer entries, then a target space for storing translated back buffer entries is allocated in the L1 cache based on space allocation information. The target non-critical entries are then stored in the target space within the L1 cache corresponding to the processor core.
[0053] The space allocation information can be a space ratio, such as 5%, 10%, etc. This ratio of space is used as the target non-critical entries for caching. It's worth noting that the Level 1 cache controller controls the remaining space. The function of allocating target space in the Level 1 cache for storing translated backing buffer entries can be enabled via corresponding registers. If the Level 1 cache has already allocated space corresponding to translated backing buffer entries, no further allocation is needed, and the space ratio can be adjusted.
[0054] Furthermore, in an optional implementation, a corresponding subspace can be allocated to each process within the target space, meaning one subspace per process. This space partitioning can be implemented by configuring registers in the operating system.
[0055] Furthermore, in this embodiment of the invention, after storing the target non-critical entry in the L1 cache corresponding to the processor core and deleting the target non-critical entry from the translation back buffer, it may further include: if the estimated running time of the process after the switch is greater than a first preset time threshold, then storing the target non-critical entry in memory and deleting the target non-critical entry from the L1 cache.
[0056] In other words, if the process running after the switch takes a long time, the target non-critical entries in the L1 cache are migrated to memory to free up cache space. The estimated running time can be issued by the operating system and is estimated from the start time of the process after the switch. If the estimated running time of the process before the switch is less than or equal to the first preset time threshold, the target non-critical entries can be retained in the L1 cache. The estimated running time is issued by the operating system.
[0057] Step S13: Obtain the recovery deadline corresponding to the process before the switch issued by the operating system.
[0058] In this embodiment, the recovery deadline corresponding to the previous process can be issued by the operating system. The recovery deadline is the remaining time after the previous process has run, before the operating system switches back to that previous process. The operating system also runs on a RISC-V Core.
[0059] Step S14: Based on the recovery deadline, before switching back to the process before the switchover, write the target non-critical entry from the first-level cache back to the translation backup buffer.
[0060] That is, the target non-critical entries are pre-loaded from the first-level cache into the translation backup buffer. The write-back time can be determined based on the recovery deadline, and the write-back time can be before the recovery deadline, with a preset difference between the two.
[0061] Before writing the target non-critical entry back to the translation backup buffer from the first-level cache, this embodiment may further include: if the recovery deadline is less than a second preset time threshold, writing the target non-critical entry back to the first-level cache from the memory.
[0062] That is, if the target non-critical entry is in memory and the recovery deadline is less than the second preset time threshold, the target non-critical entry is written back to the first-level cache from memory. If the target non-critical entry is not in memory but in the first-level cache, this action is not required, that is, there is no need to write the target non-critical entry back to the first-level cache from memory. Based on the recovery deadline, before switching back to the previous process, the target non-critical entry is written back to the translation backup buffer from the first-level cache.
[0063] Alternatively, in an optional implementation, if the target non-critical entry is in the L1 cache and the recovery deadline is greater than a specific time threshold, the target non-critical entry can be migrated from the L1 cache to memory.
[0064] Furthermore, in this embodiment of the invention, entries with the same physical address can be determined from the translation backup buffer to obtain common entries; duplicate physical addresses in the common entries are deleted from the translation backup buffer, and one of the physical addresses with the same physical address is retained.
[0065] In other words, multiple entries with the same duplicate physical address share the same physical address, and duplicate physical addresses are deleted to save space.
[0066] As can be seen, during process switching, this invention first determines the non-critical entries corresponding to the previous process in the translation back buffer and stores them in the L1 cache corresponding to the processor core, and then deletes them from the translation back buffer. Furthermore, it obtains the recovery deadline for the previous process issued by the operating system. Based on the recovery deadline, it ensures that non-critical entries are written back to the translation back buffer from the L1 cache before switching back to the previous process. This increases the available translation back buffer space for the switched process and reduces the number of entries for other processes in the translation back buffer. While ensuring rapid recovery of the previous process, it can improve the hit rate of translation back buffer entries, thereby improving processor performance.
[0067] Further, see Figure 4 As shown, Figure 4This invention provides an application architecture diagram for a translation back buffer (TLB) entry processing scheme. It proposes an optimized TLB performance scheme for multi-core RISC-V CPUs, which can be implemented by adding corresponding hardware modules. New modules include a space repartitioning module, a process key entry analysis module, and a common entry analysis module. These modules enable cached storage of old process TLB entries during RISC-V Core process switching and fast loading during process recovery. Simultaneously, it identifies key TLB entries in each process for temporary storage in the TLB after process switching, while migrating non-key TLB entries to the cache. Efficient storage of common entries across multiple processes is also designed to save TLB storage space. All three functions improve the TLB performance of multi-core RISC-V CPUs in multi-process scenarios, increase the available TLB space for the current process, improve the TLB hit rate of the current process, and ensure efficient recovery of old processes. This, in turn, improves the overall performance of RISC-V CPUs and promotes the commercial application of multi-core RISC-V CPUs in high-performance processor scenarios.
[0068] See Figure 5 As shown, Figure 5 This diagram illustrates a space repartitioning module provided in an embodiment of the present invention. This module enables the reuse of the L1 Cache space during RISC-V Core process switching. The L1 Cache is used to temporarily cache the TLB entries (TLB entries refer to the mapping relationship between the virtual address and physical address of the corresponding process) of the old process that have been flushed from the TLB. When the old process is restored, the corresponding TLB entries are quickly written back to the TLB space. The space repartitioning module may include a cache space partitioning module, an entry reading module, and an entry writing-back module.
[0069] Cache space partitioning module: The main function of this sub-module is to partition the L1 cache space corresponding to the RISC-V Core and modify the corresponding control logic. This submodule can receive operating system configuration (in this embodiment, the operating system can be optimized, and corresponding registers in this submodule can be configured during process switching). For example, configuring registers like PROCESS_EN=1 enables space partitioning. Then, it partitions a predetermined space in the L1 Cache, such as setting an initial ratio of 10% (this ratio can be modified by user-defined registers). This space is used to cache TLB entries migrated from the TLB. It's worth noting that this submodule simultaneously modifies the L1 Cache controller, changing its control scope to the remaining space (e.g., if 10% of the L1 Cache space is allocated for TLB entry caching, the modified L1 controller can only control the remaining 90% of the space). In an optional implementation, configuration registers are used to partition space for corresponding processes. For example, the configuration value can be a multi-bit value, with each bit corresponding to a process. Setting this bit to 1 indicates that space partitioning is performed for the corresponding process. Different processes can correspond to the same size space, or a specific process can be configured with a specific size.
[0070] Simultaneously, this submodule receives the estimated running time T of the new process from the operating system (this time is estimated from the start time of the new process). If T > T_MAX (i.e., the aforementioned first preset time threshold), where T_MAX is the default maximum value for the temporary TLB entry time, meaning the new process runs for a long time and the old process cannot be restored in a short time, this submodule needs to delete the TLB entries cached in part of the L1 Cache space and write the corresponding TLB entries to the specified DDR address space. This part of the L1 Cache space can then be allocated back to the L1 controller for data caching of the new process. If T is less than or equal to T_MAX, the TLB entries of the old process are retained in the L1 Cache for rapid restoration of the old process. Obtaining T can be simultaneous with receiving the operating system configuration register PROCESS_EN; that is, in addition to receiving the register configuration, this estimated time T must also be received, with one T corresponding to one process.
[0071] Moreover, this embodiment can receive the recovery deadline T1 of the corresponding old process to be restored sent by the operating system (this time can be the remaining time for the operating system to switch to the corresponding old process after the new process runs). If T1 < T_MAX1 (i.e., the aforementioned second preset time threshold), where T_MAX1 is the default maximum time for restoring the old process, then read back the TLB entries previously written to the DDR from the corresponding DDR space specified for writing before and cache them. This helps to more quickly restore the TLB entries of the old process. That is, when the old process is about to be restored, the corresponding TLB entries of the old process are loaded into the L1 Cache in advance. In this application, if the entry is in the L1 Cache, there is no need to load it from the memory again. If the entry is not in the L1 Cache and T1 < T_MAX1, it is loaded from the memory into the L1 Cache. According to the ASID, there can be multiple old processes, and the L1 Cache caching and restoration of the corresponding TLB entries are performed according to the corresponding ASID. For example, if the current running process is Process 2, and both Process 1 and Process 2 are old processes, and the old process to be switched back is Process 2, then the TLB entries of Process 2 are loaded into the L1 Cache.
[0072] Entry reading module: The function of this sub-module is to receive the corresponding enable signal during process switching and, according to the indication signal (this indication signal comes from the process key entry analysis module), read the corresponding replaced TLB entries of the old process from the TLB. These entries are the non-critical TLB of the old process, and write these entries to a partial space of the L1 Cache divided by the cache space division module.
[0073] Entry write-back module: The function of this sub-module is to write back the entries of the corresponding old process (according to the ASID) cached in a partial space of the L1 Cache to the TLB space when about to switch back to the old process (at this time, the TLB entries of the process about to complete the switch have been written to a partial space of the L1 Cache, and at this time, the TLB has space to store the written-back TLB entries of the old process).
[0074] Furthermore, as shown in Figure 6 shown Figure 6This diagram illustrates a process critical entry analysis module provided in an embodiment of the present invention. The module's function is to monitor critical entries (three types of critical TLB entries are defined in this invention) of the currently running process. Critical entries are TLB entries that can facilitate efficient process recovery after the current process is switched. Simultaneously, during process switching, only the critical entries of the switched process are retained in the TLB space, while non-critical entries are temporarily stored in a portion of the L1 Cache. This increases the TLB space available to the new process, improving its TLB hit rate. The old process can also recover quickly. The module may include a start entry monitoring module, a continuous entry monitoring module, a high-frequency entry monitoring module, and a non-critical entry address output module.
[0075] The initial entry monitoring module monitors the first N TLBs accessed by the current process during its initial execution. These first N TLBs contain the initial entry, which is defined as a critical TLB entry in this embodiment. If the process cannot access the initial TLB entry, it will need to access cached entries in memory multiple times to start the current process, significantly reducing its execution speed and thus the performance of the RISC-V CPU.
[0076] Continuous entry monitoring module: This submodule monitors continuous accesses to the TLB space issued by the current process. Such behavior corresponds to the current process needing to continuously load / write data operations (because the RISC-V CPU does not need to continuously access the TLB when running non-load / write instructions). In this invention, such entries are defined as critical TLB entries because if the process cannot quickly and continuously hit the TLB, the RISC-V CPU will not be able to quickly execute data load / write operations, causing the instruction pipeline to break down and reducing the performance of the RISC-V CPU.
[0077] High-Frequency Entry Monitoring Module: This submodule monitors the frequency of TLB entries accessed by the current process. TLB entries with higher access frequencies are designated as high-frequency entries, such as the top 10% of TLB entries accessed most frequently in the current process. In this invention, such entries are also defined as critical TLB entries because missing access to high-frequency TLB entries significantly reduces the execution efficiency of RISC-V CPU instructions. Initially, there may not be enough monitoring data; this can be configured, for example, to determine high-frequency entries after 20 TLB accesses.
[0078] Non-critical entry address output module: The function of this sub-module is to use the critical TLB entries of the current process defined in the above three sub-modules to define the remaining TLB entries of the current process as non-critical entries, and at the same time output the address of the TLB space of the non-critical entries to the entry reading module in the cache space allocation module, that is, the indication signal in the description of the entry reading module.
[0079] Further, see Figure 7 As shown, Figure 7 This diagram illustrates a common entry analysis module provided in an embodiment of the present invention. The module analyzes multiple processes running on a RISC-V Core, identifies common entries among these processes, reduces the TLB space occupied by these common entries, thereby increasing the TLB space available for new processes and improving their TLB hit rate. Common entries refer to TLB entries from different processes that share the same physical address but different virtual addresses; that is, critical data used by multiple processes uses a fixed address range (the same address range). The module may include a multi-process TLB entry analysis module, a common entry output module, and a TLB space common entry deletion module.
[0080] Multi-process TLB entry analysis module: This submodule analyzes TLB entries in the TLB space of different processes (belonging to multiple processes according to different ASIDs) to identify TLB entries in the same physical address space. Such entries are defined as common multi-process entries, and the common entry statistics table 1 is shown below.
[0081] Table 1
[0082]
[0083] Common Entry Output Module: This submodule compresses the common entries based on the common entry statistics table obtained from the previous module, retaining only the ASID and its corresponding virtual address, while keeping only one complete physical address. The aim is to save storage space. The resulting common entry statistics table, as shown in Table 2, is the actual table to be stored.
[0084] Table 2
[0085]
[0086] The TLB space common entry deletion module: This submodule deletes corresponding common entries from the stored common entry statistics table in the TLB space, freeing up more TLB space for the currently running process. Specifically, the TLB space can store multiple ASIDs and virtual addresses sequentially, followed by a unique physical address, according to the memory storage entries of the common entry statistics table. Simultaneously, new TLB query information from the current process is entered into the stored common entry statistics table for searching. If a match is found, the physical address information is directly obtained. This achieves unified storage of the common TLB space for multiple processes, further saving TLB space, increasing the available TLB space for the current process, and improving the TLB hit rate.
[0087] In this way, the newly added space repartitioning module, process key entry analysis module, and common entry analysis module enable the cached temporary storage of old process TLB entries during RISC-V Core process switching and the fast loading during process recovery. Simultaneously, it implements the identification of key TLB entries in each process for temporary storage in the TLB after process switching, while flushing non-key TLB entries to the cache. Efficient storage of common entries across multiple processes is also designed to save TLB storage space. All three functions improve the TLB performance of multi-core RISC-V CPUs in multi-process scenarios, increase the available TLB space for the current process, improve the TLB hit rate of the current process, and ensure efficient recovery of old processes, thereby improving the overall performance of RISC-V CPUs and promoting the product application of multi-core RISC-V CPUs in high-performance processor scenarios.
[0088] This invention achieves efficient reuse of the L1 Cache space during RISC-V Core process switching. A portion of the L1 Cache is used to temporarily cache TLB entries of the old process flushed from the TLB. Simultaneously, considering the recovery time of the old process, the impact on L1 Cache efficiency is further reduced, significantly accelerating the recovery efficiency of the old process and improving the TLB performance of multi-core RISC-V CPUs. Critical entry analysis is implemented, retaining only critical entries of the switched process in the TLB space, while temporarily storing non-critical process entries in a portion of the L1 Cache. This increases the TLB space available to the new process, improving its TLB hit rate. Simultaneously, the old process can also recover quickly. Furthermore, common entry analysis is implemented, efficiently storing and querying common entries from multiple processes, further increasing the available TLB space for the current process, improving its TLB hit rate and TLB performance, and significantly enhancing the overall performance of multi-core RISC-V CPUs. It enables hardware design that optimizes the performance of multi-core RISC-V TLB, improves the performance of TLB systems during process switching, and enhances the overall performance of multi-core RISC-V CPUs.
[0089] In this embodiment of the invention, during process switching, the entry determination module determines the non-critical entry corresponding to the previous process in the translation backup buffer to obtain the target non-critical entry; the entry caching module stores the target non-critical entry into the L1 cache corresponding to the processor core and deletes the target non-critical entry from the translation backup buffer; the time acquisition module obtains the recovery deadline corresponding to the previous process issued by the operating system; and the entry write-back module, based on the recovery deadline, writes the target non-critical entry back from the L1 cache to the translation backup buffer before switching back to the previous process.
[0090] After the target non-critical entry is stored in the L1 cache corresponding to the processor core and deleted from the translation back buffer via the memory write module, if the estimated runtime of the process after the switch is greater than a first preset time threshold, the target non-critical entry is stored in memory and deleted from the L1 cache. If the estimated runtime of the process before the switch is less than or equal to the first preset time threshold, the target non-critical entry is retained in the L1 cache.
[0091] Before writing the target non-critical entry back to the translation backup buffer from the first-level cache using the cache write-back module, if the recovery deadline is less than a second preset time threshold, the target non-critical entry is written back to the first-level cache from memory.
[0092] During process switching, if the L1 cache has not allocated space for the translation back buffer entries, the space allocation module allocates target space in the L1 cache based on the space allocation information to store the translation back buffer entries.
[0093] The entry determination module determines the non-critical entries corresponding to the previous process in the translation backup buffer based on the critical entry monitoring information corresponding to the previous process.
[0094] The process key entry analysis module monitors key entries of the process before the switchover to obtain key entry monitoring information corresponding to the process before the switchover. The start entry monitoring module monitors the first N entries accessed by the process before the switchover during its first run to obtain key entry monitoring information corresponding to the process before the switchover. The continuous entry monitoring module monitors entries continuously accessed by the process before the switchover in the translation backup buffer to obtain key entry monitoring information corresponding to the process before the switchover. The high-frequency entry monitoring module monitors frequently accessed entries of the process before the switchover in the translation backup buffer to obtain key entry monitoring information corresponding to the process before the switchover, wherein the access frequency of the high-frequency access entries is greater than the access frequency of the low-frequency access entries.
[0095] The common entry analysis module identifies entries with the same physical address from the translation backup buffer to obtain common entries; duplicate physical addresses in the common entries are deleted from the translation backup buffer, and one of the physical addresses with the same physical address is retained.
[0096] In other words, the aforementioned space repartitioning module includes a cache space partitioning module, a table entry reading module, and a table entry write-back module. The cache space partitioning module includes a space partitioning module, a memory writing module, and a cache write-back module. The cache write-back module includes a time acquisition module, and the aforementioned table entry reading module includes a table entry determination module and a table entry caching module.
[0097] Furthermore, Figure 8 This is a schematic diagram of a translation backup buffer entry processing system provided in an embodiment of the present invention. The translation backup buffer entry processing system may include:
[0098] The entry determination module 11 is used to determine the non-critical entries corresponding to the previous process in the translation backup buffer during process switching, and obtain the target non-critical entries.
[0099] The table entry caching module 12 is used to store the target non-critical table entry into the L1 cache corresponding to the processor core, and to delete the target non-critical table entry from the translation back buffer.
[0100] Time acquisition module 13 is used to acquire the recovery deadline corresponding to the process before the switch issued by the operating system;
[0101] The table entry write-back module 14 is used to write the target non-critical table entry from the first-level cache to the translation backup buffer based on the recovery deadline and before switching back to the process before the switchover.
[0102] The system further includes a memory write module, used to, after storing the target non-critical entry in the L1 cache corresponding to the processor core and deleting the target non-critical entry from the translation back buffer, if the estimated runtime of the process after the switch is greater than a first preset time threshold, then store the target non-critical entry in memory and delete the target non-critical entry from the L1 cache. If the estimated runtime of the process before the switch is less than or equal to the first preset time threshold, then retain the target non-critical entry in the L1 cache.
[0103] The system further includes a cache write-back module, which is used to write the target non-critical entry back to the first-level cache from the memory before writing the target non-critical entry back to the translation backup buffer from the first-level cache, provided that the recovery deadline is less than a second preset time threshold.
[0104] The space allocation module is used to allocate target space in the first-level cache for storing translation back buffer entries based on space allocation information when switching processes, if the space corresponding to the translation back buffer entries has not been allocated in the first-level cache.
[0105] Furthermore, the entry determination module 11 is specifically used to determine the non-critical entries corresponding to the previous process in the translation backup buffer based on the critical entry monitoring information corresponding to the previous process.
[0106] In this embodiment, a process key entry analysis module is also included, which is used to monitor the key entries of the process before the switch and obtain the key entry monitoring information corresponding to the process before the switch.
[0107] The process key entry analysis module includes a start entry monitoring module, which is used to monitor the first N entries in the translation backup buffer accessed by the process before the switchover when it first runs, and obtain the key entry monitoring information corresponding to the process before the switchover.
[0108] The process key entry analysis module also includes a continuous entry monitoring module, which is used to monitor the entries in the translation backup buffer that are continuously accessed by the process before the switchover, and obtain the key entry monitoring information corresponding to the process before the switchover.
[0109] The process key entry analysis module also includes a high-frequency entry monitoring module, which is used to monitor the high-frequency access entries of the process before the switch in the translation backup buffer, and obtain the key entry monitoring information corresponding to the process before the switch, wherein the access frequency of the high-frequency access entries is greater than the access frequency of the non-high-frequency access entries.
[0110] The common entry analysis module is used to identify entries with the same physical address from the translation backup buffer to obtain common entries; and to delete duplicate physical addresses in the common entries from the translation backup buffer, retaining one of the physical addresses with the same physical address.
[0111] As can be seen, during process switching, this invention first determines the non-critical entries corresponding to the previous process in the translation back buffer and stores them in the L1 cache corresponding to the processor core, and then deletes them from the translation back buffer. Furthermore, it obtains the recovery deadline for the previous process issued by the operating system. Based on the recovery deadline, it ensures that non-critical entries are written back to the translation back buffer from the L1 cache before switching back to the previous process. This increases the available translation back buffer space for the switched process and reduces the number of entries for other processes in the translation back buffer. While ensuring rapid recovery of the previous process, it can improve the hit rate of translation back buffer entries, thereby improving processor performance.
[0112] Furthermore, if the translation backup buffer entry processing method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.
[0113] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the translation back buffer table entry processing method described above. The computer program can be a program corresponding to a hardware description language.
[0114] Furthermore, embodiments of the present invention also provide a computer program product, including a computer program / instructions, which, when executed by a processor, implements the aforementioned method for processing translated back buffer entries. The computer program can be a program corresponding to a hardware description language.
[0115] The foregoing has provided a detailed description of a translation backup buffer entry processing method, system, medium, and product provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0116] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0117] The foregoing has provided a detailed description of the translation backup buffer entry processing method, system, medium, and product provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.
Claims
1. A method for processing translation backup buffer entries, characterized in that, include: During process switching, determine the non-critical entries in the translation buffer corresponding to the previous process and obtain the target non-critical entry. The target non-critical entry is stored in the L1 cache corresponding to the processor core, and the target non-critical entry is deleted from the translation back buffer. Obtain the recovery deadline corresponding to the process before the switch issued by the operating system; Based on the recovery deadline, before switching back to the process before the switchover, the target non-critical entry is written back from the first-level cache to the translation backup buffer; After storing the target non-critical entry in the L1 cache corresponding to the processor core and deleting the target non-critical entry from the translation back buffer, the method further includes: if the estimated running time of the process after the switch is greater than a first preset time threshold, then storing the target non-critical entry in memory and deleting the target non-critical entry from the L1 cache. Before writing the target non-critical entry back to the translation backup buffer from the first-level cache, the method further includes: if the recovery deadline is less than a second preset time threshold, writing the target non-critical entry back to the first-level cache from the memory; The method further includes: if the estimated running time of the switched process is less than or equal to the first preset time threshold, then the target non-critical entry is retained in the first-level cache.
2. The translation backup buffer entry processing method according to claim 1, characterized in that, Also includes: During process switching, if the L1 cache has not allocated space for the translation back buffer entries, then the target space for storing translation back buffer entries is allocated in the L1 cache based on the space allocation information.
3. The translation backup buffer entry processing method according to claim 1, characterized in that, Identify the non-critical entries in the translation backup buffer corresponding to the process before the switch, including: Based on the monitoring information of the key entries corresponding to the process before the switchover, the non-key entries corresponding to the process before the switchover are determined in the translation backup buffer.
4. The translation backup buffer entry processing method according to claim 3, characterized in that, Also includes: By monitoring the first N entries in the translation backup buffer accessed during the first run of the process before the switchover, the key entry monitoring information corresponding to the process before the switchover is obtained.
5. The translation backup buffer entry processing method according to claim 3, characterized in that, Also includes: By monitoring the entries in the translation backup buffer that are continuously accessed by the process before the switchover, the monitoring information of the key entries corresponding to the process before the switchover is obtained.
6. The translation backup buffer entry processing method according to claim 3, characterized in that, Also includes: By monitoring the high-frequency access entries of the process before the switchover in the translation backup buffer, the key entry monitoring information corresponding to the process before the switchover is obtained, wherein the access frequency of the high-frequency access entries is greater than the access frequency of the low-frequency access entries.
7. The method for processing translation backup buffer entries according to any one of claims 1 to 6, characterized in that, Also includes: From the translation backup buffer, entries with the same physical address are identified to obtain common entries; The duplicate physical addresses in the commonality table entries are deleted from the translation backup buffer, and only one physical address with the same physical address is retained.
8. A translation backup buffer entry processing system, characterized in that, include: The entry determination module is used to determine the non-critical entries corresponding to the previous process in the translation backup buffer during process switching, and obtain the target non-critical entries. The table entry caching module is used to store the target non-critical table entry into the L1 cache corresponding to the processor core, and to delete the target non-critical table entry from the translation back buffer. The time acquisition module is used to acquire the recovery deadline corresponding to the process before the switch, issued by the operating system. The table entry write-back module is used to write the target non-critical table entry from the first-level cache to the translation backup buffer based on the recovery deadline and before switching back to the process before the switchover. The system further includes a memory write module, used to, after storing the target non-critical entry into the L1 cache corresponding to the processor core and deleting the target non-critical entry from the translation back buffer, if the estimated running time of the switched process is greater than a first preset time threshold, store the target non-critical entry into memory and delete the target non-critical entry from the L1 cache; if the estimated running time of the switched process is less than or equal to the first preset time threshold, retain the target non-critical entry in the L1 cache. The system further includes a cache write-back module, which is used to write the target non-critical entry back to the first-level cache from the memory before writing the target non-critical entry back to the translation backup buffer from the first-level cache, provided that the recovery deadline is less than a second preset time threshold.
9. The translation backup buffer entry processing system according to claim 8, characterized in that, Also includes: The process key entry analysis module is used to monitor the key entries of the process before the switch and obtain the key entry monitoring information corresponding to the process before the switch.
10. The translation backup buffer entry processing system according to claim 8, characterized in that, Also includes: The common entry analysis module is used to determine entries with the same physical address from the translation backup buffer to obtain common entries; The duplicate physical addresses in the commonality table entries are deleted from the translation backup buffer, and only one physical address with the same physical address is retained.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the translation back buffer entry processing method as described in any one of claims 1 to 7.
12. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the translation back buffer table entry processing method as described in any one of claims 1 to 7.