A large-scale qubit simulation method and system based on quantum circuit decomposition

Abstract

The application provides a large-scale quantum bit simulation method and system based on quantum circuit decomposition, and relates to the field of quantum computing, which comprises: preprocessing and normalizing the input quantum circuit; converting the multi-qubit gate in the circuit into a combination composed of single-qubit gate and two-qubit CZ gate, and fusing adjacent single-qubit gates; performing multi-region dynamic partitioning and optimization on the simplified circuit; performing implicit decomposition on the CZ gate across the partition, and performing secondary fusion on the single-qubit gate generated by the decomposition; finally, task scheduling and parallel simulation calculation are performed, and the output result is verified. The application expands the application range of implicit decomposition through gate conversion, greatly saves memory through dynamic partitioning and implicit decomposition, improves calculation efficiency through gate fusion, and enhances parallel scalability through communication optimization, thereby realizing efficient classical simulation of general and large-scale quantum circuits.

Description

Technical Field

[0001] This invention relates to the field of quantum computing, and more specifically to a method and system for simulating large-scale qubits based on quantum circuit decomposition. Background Technology

[0002] Classical simulation of quantum circuits is a core method for verifying the fidelity of quantum hardware and optimizing quantum algorithms. However, for large-scale quantum circuits, traditional simulation methods are limited by the exponential storage requirements of quantum states, facing memory bottlenecks and low computational efficiency. Therefore, large-scale quantum circuits must be partitioned. However, the partitioning of quantum circuits inevitably generates a large amount of additional memory and computational requirements.

[0003] Existing implicit decomposition techniques can achieve some memory savings by absorbing the branch index of cross-partition CZ gates, but they have the following significant drawbacks: 1. Limited applicable gate types: only supporting CZ gates, unable to handle common off-diagonal 2-qubit gates such as CNOT gates and common 3-qubit gates such as Toffili gates. 2. Limited partition structure and number, making it difficult to apply to large-scale quantum circuits. 3. Increased number and depth of circuit gates lead to decreased simulation efficiency, making it difficult to adapt to general-purpose quantum algorithm circuits. These drawbacks make it difficult to balance the applicability, efficiency, and versatility of quantum circuit simulation.

[0004] Implicit decomposition is a technique that decomposes more CZ gates without significantly increasing memory overhead. Its key lies in the discovery that some decomposed CZ gates no longer have any gate operations on the control qubits in subsequent paths. In this case, the branch path index can be "absorbed" into the state index of that qubit, thus avoiding doubling the memory usage. The specific principle is as follows:

[0005] In the process of quantum circuit decomposition, the CZ gate can be decomposed into: Note: Among them, quantum gates The superscript indicates the number of qubits involved in the U action, and the subscript indicates the branch index of these qubits, i.e., their state, such as... This means that a CZ gate acts on qubit 0 and qubit 1, where qubit 0 is the control qubit and qubit 1 is the target qubit, and qubit 0 is in the... Quantum bit 1 is in .

[0006] When the CZ gate is decomposed, a branch index is introduced. This represents the state of the control qubit at the moment of decomposition. After ordinary decomposition, the region A containing the control qubit needs to store two branch states. Its total memory requirements are , where q is the number of qubits contained in region A.

[0007] For implicit decomposition, since the control qubit c has no subsequent gate operations, its state remains unchanged after the decomposition time. Therefore, its branch index l can be "absorbed" into the state index of that qubit. Its total memory requirement is... In other words, compared to traditional decomposition methods, implicit decomposition saves half the internal requirements for each decomposed CZ gate that satisfies the condition that no more gate operations are required on the control qubit. However, implicit decomposition methods are limited to specific gate types, supporting only CZ gates and unable to handle common multi-qubit gates such as CNOT and Toffili gates. Summary of the Invention

[0008] In view of this, in order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a large-scale quantum bit simulation method and system based on quantum circuit decomposition. By expanding the scope of application through gate synthesis, it breaks through the limitation that implicit decomposition is only applicable to CZ gates and extends it to other commonly used multi-bit gates, which can significantly save storage space. The dynamic partitioning method is adopted to perform flexible dynamic partitioning, which is suitable for ultra-large-scale quantum circuits. By improving computational efficiency through gate fusion, the number and depth of quantum circuits are reduced, further reducing the computational complexity of the simulation.

[0009] This invention is achieved using the following technical solution:

[0010] In a first aspect, the present invention provides a method for simulating large-scale qubits based on quantum circuit decomposition, comprising the following steps:

[0011] The input quantum circuit is preprocessed to obtain a regularized quantum circuit;

[0012] The normalized quantum circuit is subjected to quantum gate conversion, which transforms the multi-qubit gates in the circuit, except for the two-qubit CZ gate, into a combined structure composed of single-qubit gates and two-qubit CZ gates, thus obtaining a standardized quantum circuit.

[0013] In the standardized quantum circuit, adjacent single-qubit gates acting on the same qubit are gate-fused to obtain a simplified quantum circuit;

[0014] Based on a preset partitioning principle, the simplified quantum circuit is dynamically partitioned into multiple regions, dividing the circuit into multiple input regions and at least one output region.

[0015] An implicit decomposition operation is performed on the cross-partition CZ gates generated after partitioning, and the single-qubit gates generated by the decomposition operation are fused again.

[0016] Based on the partitioned and merged circuits, task scheduling and parallel simulation computation are performed on classical computing devices to obtain the simulation results of quantum circuits.

[0017] As a further aspect of the present invention, the input quantum circuit is preprocessed, including the following steps:

[0018] Circuit analysis and gate type identification: Analyze the number of qubits, gate type, operation sequence and qubit mapping relationship of the quantum circuit to generate a structured circuit description file;

[0019] Redundant gate removal: Identify and remove invalid or redundant quantum gates from the quantum circuit;

[0020] Gate timing sorting: Sort the gate sequence according to the operation timing of the qubits, mark the parallel gate operations of different qubits, and output the preprocessed quantum circuit.

[0021] As a further aspect of the present invention, quantum gate transformation is performed on the regularized quantum circuit, including the following steps:

[0022] The two-qubit CNOT gate is converted into a combination of "preorder H gate on the target bit + CZ gate + postorder H gate on the target bit";

[0023] The two-qubit SWAP gate is converted into a combination of three CNOT gates, and then the conversion rule of CNOT gate is applied to each CNOT gate to convert it into a CZ gate;

[0024] Convert the three-qubit Toffoli gate into four on the target bit. The combination of the door and three CZ doors;

[0025] The three-qubit CCZ gate is converted into a combination of a single-qubit H gate and a Tooffoli gate. Then, the Tooffoli gate conversion rule is applied to the Tooffoli gate part to decompose the CCZ gate into a combination of a single-qubit gate and a CZ gate, thus completing the dimensionality reduction adaptation of the CCZ gate.

[0026] The three-qubit Fredkin gate is converted into a combination of a two-qubit CNOT gate, a three-qubit Tofoli gate, and a two-qubit CNOT gate. Then, the CNOT gate and Tofoli gate parts are decomposed into combinations of single-qubit gates and CZ gates by applying the corresponding conversion rules, thus completing the dimensionality reduction adaptation of the Fredkin gate.

[0027] As a further aspect of the present invention, the gate fusion specifically involves: for multiple adjacent single-qubit gates on the same qubit, merging them into an equivalent single-qubit SU(2) gate through matrix multiplication; after fusion, deleting the original gate sequence and retaining only the equivalent fused gate.

[0028] As a further aspect of the present invention, the preset partitioning principles include:

[0029] The error in the number of qubits in the regions divided according to spatial dimensions is less than a preset threshold;

[0030] CZ gates between regions defined solely by spatial dimensions are treated as cross-regional gates for cutting;

[0031] There is no cut-off CZ gate between the input and output regions;

[0032] The input region ends with one or more cut CZ gates.

[0033] As a further aspect of the present invention, an implicit decomposition operation is performed on the cross-partition CZ gates generated after partitioning, and a secondary fusion is performed on the single-qubit gates generated by the decomposition operation, including the following steps:

[0034] For each cross-partition CZ gate, determine whether its control qubit has no subsequent gate operations in the remaining lines of its partition;

[0035] If so, then perform implicit decomposition on the CZ gate and absorb the branch index generated by the decomposition into the state index of the control qubit;

[0036] If not, perform normal decomposition on the CZ gate to generate a projection gate P that acts on the control bits and a Z gate that acts on the target bits;

[0037] The projection gate P used to mark branches in the implicit decomposition, or the Z gate generated by the ordinary decomposition, is fused by matrix multiplication with the preceding or following single-qubit gates adjacent to the active qubit.

[0038] As a further aspect of the present invention, task scheduling and parallel simulation computation are performed on a classical computing device, including the following steps:

[0039] Data partitioning and distribution: The output state vectors of each partition are partitioned according to the locality of the qubit index and distributed to multiple computing nodes of the parallel computing cluster;

[0040] Communication optimization: Reconstruct the centralized data collection communication mode into a packet-parallel global data exchange communication mode;

[0041] Parallel computing: Each computing node performs parallel computation of the quantum state evolution of the segment it is responsible for, and exchanges necessary data through optimized communication methods to merge the results of each partition and complete the simulation of the entire circuit;

[0042] Post-processing: Verify the unitarity and probability distribution of the quantum states obtained from the simulation calculation, and output a simulation result file with verification information.

[0043] As a further aspect of the present invention, the grouped parallel global data exchange communication mode is based on the MPI_Alltoall operation of the MPI library.

[0044] Secondly, the present invention also provides a large-scale qubit simulation system based on quantum circuit decomposition, deployed on a classical computing cluster, comprising:

[0045] The input module is used to receive the input quantum circuit description;

[0046] The circuit preprocessing module, connected to the input module, is used to analyze the input quantum circuit, remove redundant gates, and sort the time sequence to obtain a regularized quantum circuit.

[0047] The gate conversion and fusion module, connected to the circuit preprocessing module, is used to convert the multi-qubit gates in the regularized quantum circuit into a combination of single-qubit gates and two-qubit CZ gates, and to fuse adjacent single-qubit gates on the same qubit to obtain a simplified quantum circuit.

[0048] A multi-region dynamic planning module, connected to the gate conversion and fusion module, is used to dynamically partition and optimize the simplified quantum circuit, dividing the circuit into multiple regions and identifying the CZ gates that cross regions.

[0049] The implicit decomposition and quadratic gate fusion module is connected to the multi-region dynamic programming module. It is used to perform implicit decomposition or ordinary decomposition operations on cross-region CZ gates and perform secondary fusion on the single-qubit gates generated by the decomposition to generate an optimized scheme that includes partitioned computing tasks and implicit decomposition configuration.

[0050] The task scheduling and communication optimization module, connected to the implicit decomposition and quadratic gate fusion module, is used to map the computing tasks of each partition to computing nodes according to the optimization scheme, and plan the data exchange and communication strategies between nodes.

[0051] The parallel cluster, consisting of multiple computing nodes, is connected to the task scheduling and communication optimization module and is used to perform the evolution calculation of quantum states in each partition in parallel.

[0052] The post-processing and verification module, connected to the parallel cluster, is used to collect and merge the calculation results of each node, perform unitarity and probability verification, and generate a simulation report.

[0053] The output module, connected to the post-processing and verification module, is used to output the final simulation result file and simulation report.

[0054] As a further aspect of the present invention, the line preprocessing module is specifically used for:

[0055] The number of qubits, gate type, and operation sequence of the quantum circuit are analyzed to generate a structured circuit description file;

[0056] Identify and remove redundant quantum gates from the circuit;

[0057] The gate sequences are sorted according to the operation timing of the qubits, and gate operations that can be executed in parallel are marked.

[0058] As a further aspect of the present invention, the gate conversion and fusion module includes:

[0059] The gate conversion unit is used to traverse the normalized quantum circuit, identify all non-CZ gate multi-qubit gates, and apply a preset conversion rule to convert them into a combined structure consisting of a single-qubit gate and a two-qubit CZ gate. The multi-qubit gate includes at least a two-qubit CNOT gate, a SWAP gate, and a three-qubit Toffoli gate, a CCZ gate, and a Fredkin gate.

[0060] The gate fusion unit is used to perform matrix multiplication on adjacent single-qubit gates that act on the same qubit in the converted circuit and the original circuit, and merge them into an equivalent single-qubit SU(2) gate.

[0061] As a further aspect of the present invention, the multi-region dynamic planning module is specifically used for:

[0062] Based on the structure, depth and simulation target of the simplified quantum circuit, an initial partitioning scheme is generated to divide the circuit into multiple input regions and at least one output region, and to ensure that the cross-region gates are only CZ gates.

[0063] Dynamic optimization search is performed under the condition of satisfying partition constraints, which include: balancing the number of qubits in each region, minimizing the number of CZ gates to be cut, and maximizing the number of control qubits generated after the cut without subsequent gate operations.

[0064] Output the final partitioning scheme and the list of CZ gates to be partitioned.

[0065] As a further aspect of the present invention, the implicit decomposition and quadratic gate fusion module includes:

[0066] The condition judgment unit is used to determine, for each identified cross-region CZ gate, whether its control qubit has no subsequent gate operation in the remaining lines of its respective partition;

[0067] The decomposition execution unit is used to perform implicit decomposition on CZ gates that meet the conditions, and absorb the branch index generated by the decomposition into the state index of the control qubit; and to perform ordinary decomposition on CZ gates that do not meet the conditions, generating projection gates P and Z.

[0068] The secondary fusion unit is used to perform matrix multiplication fusion of the projection gate P generated in the implicit decomposition or the Z gate generated in the ordinary decomposition with the single-qubit gate adjacent to the active qubit.

[0069] As a further aspect of the present invention, the task scheduling and communication optimization module is specifically used for:

[0070] The output state vectors of each partition are divided into data slices according to the locality of their qubit indices, and the sliced ​​data is mapped to each computing node of the parallel cluster.

[0071] The traditional centralized data collection and communication mode is reconstructed into a packet parallel global data exchange and communication mode based on the message passing interface MPI.

[0072] Before initiating communication, the data in the local fragments of the node is preprocessed by memory alignment and sorting to meet the data transmission requirements of the efficient communication library.

[0073] As a further aspect of the present invention, the grouped parallel global data exchange communication mode is a communication mode based on the MPI_Alltoall operation.

[0074] As a further aspect of the present invention, the post-processing and verification module is specifically used for:

[0075] Calculate the total probability of the final output state vector and verify whether it is normalized;

[0076] Based on user needs, the partial state vectors of the distributed storage can be assembled into a complete state vector file, or the specified target amplitude can be calculated and output.

[0077] Record key performance indicators and verification results during the simulation process, and generate structured simulation reports.

[0078] Compared with existing technologies, the present invention provides a large-scale qubit simulation method and system based on quantum circuit decomposition, which overcomes the limitation that implicit decomposition is only applicable to CZ gates and extends to commonly used 2-qubit and 3-qubit gates; it features flexible dynamic partitioning, making it suitable for ultra-large-scale quantum circuits; and it reduces the number of gates and depth of quantum circuits, further reducing the computational complexity of the simulation, and has the following beneficial effects:

[0079] 1. It significantly expands the versatility and applicability of simulation technology, breaking through the application limitations of implicit decomposition.

[0080] This invention transforms various commonly used, off-diagonal two-qubit gates and complex three-qubit gates into standard combinations of single-qubit gates and two-qubit CZ gates through quantum gate conversion. By performing dimensionality reduction through conversion rules, many quantum gates that were originally unsuitable for implicit factorization can now adapt their CZ gate portions to the index absorption mechanism of implicit factorization after conversion. This expands the applicability of implicit factorization, a memory-saving technique, from a single CZ gate to almost all universal quantum gate sets, greatly enhancing the ability of simulation systems to process universal quantum algorithm circuits.

[0081] 2. Significantly reduced memory consumption for large-scale quantum circuit simulations.

[0082] This invention achieves significant memory savings compared to traditional decomposition methods by synergistically optimizing circuit segmentation strategies through multi-region dynamic partitioning and implicit decomposition, and maximizing the use of the implicit decomposition's index absorption mechanism. Using implicit decomposition, when the control bits of a segmented CZ gate have no subsequent operations, the branch index can be absorbed, thus preventing the state storage size of that region from doubling. Through dynamic partitioning optimization, this invention actively optimizes the partitioning process to increase the number of control qubits without subsequent gate operations after segmentation, directly increasing the opportunities for applying implicit decomposition. This allows for the decomposition of more gates without increasing additional memory overhead when simulating ultra-large-scale circuits, effectively alleviating the memory bottleneck caused by the exponential storage of quantum states.

[0083] 3. Effectively improves the computational efficiency of the simulation process.

[0084] This invention significantly reduces the number of quantum gates that need to be actually computed, thereby lowering computational complexity, through gate fusion and quadratic gate fusion techniques. By performing matrix multiplication fusion on adjacent single-qubit gates on the same qubit, the number of single-qubit gates can be greatly reduced, eliminating additional computational overhead and directly reducing the number of matrix multiplication operations required during simulation. The cumulative efficiency improvement is particularly significant in deep circuits.

[0085] 4. Enhanced the system's scalability and parallel efficiency for ultra-large-scale lines.

[0086] The multi-region dynamic partitioning method and task scheduling and communication optimization strategy of this invention enable simulation tasks to be flexibly and evenly distributed across large-scale parallel computing clusters, optimize inter-node communication, and improve overall resource utilization and parallel speedup. By using partitioning principles and optimization objectives to decompose large-scale problems into multiple load-balanced subtasks, this is a prerequisite for efficient parallel computing. The inefficient centralized communication is reconstructed into efficient peer-to-peer full-switching communication, and combined with data localization and preprocessing, effectively solving the key problem that communication overhead often becomes a performance bottleneck in distributed computing, enabling the system to scale better to hundreds or thousands of computing nodes.

[0087] In summary, this invention effectively promotes the development of classical simulation technology for quantum computing through technological breakthroughs and synergies, such as gate conversion to extend applicability, dynamic partitioning and implicit decomposition to save memory, gate fusion to improve computational efficiency, communication optimization to enhance scalability, and system integration to ensure reliability. It systematically solves the key bottlenecks faced by existing classical simulation technology for quantum circuits.

[0088] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0089] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the accompanying drawings used in the description of the exemplary embodiments or related technologies will be briefly introduced below. The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation thereof. In the drawings:

[0090] Figure 1 This is a logical architecture diagram of a large-scale qubit simulation method based on quantum circuit decomposition according to an embodiment of the present invention.

[0091] Figure 2 This is a 4-qubit circuit diagram in the large-scale qubit simulation method based on quantum circuit decomposition in an embodiment of the present invention.

[0092] Figure 3 This is a quantum bit circuit diagram after quantum gate transformation in the large-scale quantum bit simulation method based on quantum circuit decomposition in an embodiment of the present invention.

[0093] Figure 4 This is an adjusted qubit circuit diagram in the large-scale qubit simulation method based on quantum circuit decomposition in an embodiment of the present invention.

[0094] Figure 5 This is a schematic diagram of the partitioning of a quantum circuit in the large-scale quantum bit simulation method based on quantum circuit decomposition according to an embodiment of the present invention.

[0095] Figure 6 This is a system architecture block diagram of a large-scale quantum bit simulation method and system based on quantum circuit decomposition, according to an embodiment of the present invention. Detailed Implementation

[0096] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0097] In some of the processes described in the specification, claims, and accompanying drawings of this invention, multiple operations appearing in a specific order are included. However, it should be clearly understood that these operations may not be executed in the order they appear herein, or may be executed in parallel. The operation numbers, such as 101, 102, etc., are merely used to distinguish different operations and do not themselves represent any execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first," "second," etc., in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to different types.

[0098] The technical solutions in the exemplary embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described exemplary embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0099] See Figure 1 As shown in the figure, a large-scale qubit simulation method based on quantum circuit decomposition provided in this embodiment of the invention includes the following steps:

[0100] Step S10: Preprocess the input quantum circuit to obtain a regularized quantum circuit.

[0101] This step involves preprocessing the input quantum circuit, including the following steps:

[0102] Step S101, Circuit Analysis and Gate Type Identification: Analyze the number of qubits, gate type, operation sequence and qubit mapping relationship of the quantum circuit to generate a structured circuit description file.

[0103] During circuit analysis and gate type identification, input any structured quantum circuit, and analyze the number of qubits and gate type (single qubit gates: H, X, Y, T, R) of the circuit. Y Examples of gate types include: two-qubit gates (CZ, CNOT, SWAP, etc.) and three-qubit gates (Toffoli, Fredkin, etc.). The gate operation sequence is mapped to the qubits, generating a structured circuit description file (including gate type, active bit index, and operation timing).

[0104] Step S102, Redundant Gate Removal: Identify and remove invalid or redundant quantum gates from the quantum circuit. For example, two consecutive identical H gates ( ), identity gate Repeated projection gates P, etc., reduce the amount of computation required for processing.

[0105] Step S103, Gate Timing Sort: Sort the gate sequence according to the operation timing of the qubits, mark the parallel gate operations of different qubits, and output the preprocessed quantum circuit. This ensures that the gate operations of the same qubit are arranged in chronological order, and marks the parallel gate operations of different qubits, providing support for subsequent gate fusion and parallel simulation.

[0106] Step S20: Perform quantum gate conversion on the normalized quantum circuit, converting the multi-qubit gates in the circuit (excluding the two-qubit CZ gate) into a combined structure consisting of a single-qubit gate and a two-qubit CZ gate, to obtain the normalized quantum circuit.

[0107] To address the limitation that implicit decomposition only supports 2-qubit CZ gates, other 2-qubit and 3-qubit gates are transformed into composite gate structures of "single-qubit gate + 2-qubit CZ gate," adapting the index absorption condition of implicit decomposition through dimensionality reduction decomposition. The specific steps are as follows:

[0108] Step S201: Non-CZ gate screening and classification.

[0109] Non-CZ gate multi-qubit gates were selected from the preprocessed circuits and classified into two categories according to the number of qubits:

[0110] 2. Quantum bit gates: CNOT gate, SWAP gate, etc.;

[0111] 3. Quantum bit gates: Tofoli gate (CCNOT gate), CCZ gate, Fredkin gate (CSWAP gate), etc. Different types of gates adopt targeted conversion rules. The core is to decompose multi-qubit gates into a low-dimensional combination of "single-qubit gate + 2-qubit CZ gate".

[0112] Step S202: Gate conversion execution.

[0113] The various multi-qubit gates classified in the circuit are subjected to gate conversion operations to transform them into a combination of single-qubit gates and CZ gates. This step of performing quantum gate conversion on the normalized quantum circuit includes the following steps:

[0114] Step S2021: Convert the two-qubit CNOT gate into a combination of "preorder H gate on the target bit + CZ gate + postorder H gate on the target bit".

[0115] In this step, the two-qubit CNOT gate is transformed into Where c is the control bit and t is the target bit, the transformation generates a composite structure of "preorder H gate + CZ gate + postorder H gate". The CZ gate retains the correlation between the original control bit and the target bit, maintaining the dimensionality of the 2-qubit gate.

[0116] Step S2022: Convert the two-qubit SWAP gate into a combination of three CNOT gates, and then apply the CNOT gate conversion rule to each CNOT gate to convert it into a CZ gate.

[0117] In this step, the SWAP gate can first be converted into a CNOT gate: After conversion, three CNOT gates are generated. Then, according to the rules in step S2021, the CNOT gates are converted into CZ gates.

[0118] Step S2023: Convert the three-qubit Tooffoli gate into four gates on the target qubit. A combination of a door and three CZ doors.

[0119] During this step, the Toffoli gate transformation occurs. After transformation, a composite structure of "4 rotating single-qubit gates + 3 CZ gates" is generated. and Here, t represents the target bit, and t represents the dual control bit. The 3-qubit Tofoli gate is decomposed into a structure of "single-qubit gate + CZ gate," with the CZ gates respectively associated... and It adapts to the processing requirements of implicit decomposition.

[0120] Step S2024: Convert the three-qubit CCZ gate into a combination of a single-qubit H gate and a Tooffoli gate. Then apply the Tooffoli gate conversion rule to the Tooffoli gate part to decompose the CCZ gate into a combination of a single-qubit gate and a CZ gate, thus completing the dimensionality reduction adaptation of the CCZ gate.

[0121] In this step, during the CCZ gate conversion, it first passes through... The CCZ gate is transformed into a structure of "single-qubit H gate + Tofoli gate", and then further decomposed into a composite structure of "single-qubit gate + CZ gate" according to the rules in step S2023, thus completing the dimensionality reduction adaptation of the CCZ gate. , t represents the dual control bits, and t represents the target bit.

[0122] Step S2025: Convert the three-qubit Fredkin gate into a combination of a two-qubit CNOT gate, a three-qubit Tofoli gate, and a two-qubit CNOT gate. Then, apply the corresponding conversion rules to the CNOT gate and Tofoli gate parts respectively to decompose them into combinations of single-qubit gates and CZ gates, thus completing the dimensionality reduction adaptation of the Fredkin gate.

[0123] In this step, during the Fredkin gate conversion, it first passes through... The Fredkin gate is transformed into a structure of "2-qubit CNOT gate + 3-qubit Tofoli gate + 2-qubit CNOT gate". Then, according to the rules of steps S2022 and S2023, the CNOT gate and Tofoli gate are further decomposed into a composite structure of "single-qubit gate + CZ gate". Finally, the dimensionality reduction adaptation of the Fredkin gate is completed, and the standardized circuit is output: it contains only 2-qubit CZ gate and single-qubit gate, without native 3-qubit gate and other 2-qubit gate.

[0124] Step S30: In the standardized quantum circuit, adjacent single-qubit gates acting on the same qubit are gate-fused to obtain a simplified quantum circuit.

[0125] In this step, the gate fusion specifically involves: for multiple adjacent single-qubit gates on the same qubit, merging them into an equivalent single-qubit SU(2) gate through matrix multiplication; after fusion, deleting the original gate sequence and retaining only the equivalent fused gate.

[0126] In this embodiment, redundant single-qubit gates introduced by gate conversion are combined using gate fusion technology to improve computational efficiency. During quantum gate fusion, adjacent single-qubit gates (such as H, R, T, X gates, etc.) on the same qubit are merged into an equivalent gate. Gate: Let the sequence of adjacent single-qubit gates be . (All are 2×2 unitary matrices), the equivalent fusion gate is: After fusion, the original gate sequence is deleted, and only the equivalent fused gate is retained, which can significantly reduce the number of single-bit gates.

[0127] Step S40: Based on the preset partitioning principle, the simplified quantum circuit is dynamically partitioned into multiple regions, dividing the circuit into multiple input regions and at least one output region.

[0128] In this step, the simplified circuit is adaptively divided into multiple partitions based on the number of qubits, circuit complexity, and circuit depth, ensuring that cross-partition gates are CZ gates to maximize the memory savings of implicit decomposition. The partitioned regions include two types: an input region (starting from the initial state of the quantum circuit) and an output region (not starting from the initial state of the quantum circuit) divided according to the time dimension, and a region containing specific qubits divided according to the spatial dimension. The preset partitioning principles include:

[0129] The error in the number of qubits in the regions divided according to spatial dimensions is less than a preset threshold;

[0130] CZ gates between regions defined solely by spatial dimensions are treated as cross-regional gates for cutting;

[0131] There is no cut-off CZ gate between the input and output regions;

[0132] The input region ends with one or more cut CZ gates.

[0133] like Figure 5 As shown, Figure 5 This is a schematic diagram of the partitioning of a quantum circuit. Parts A, B, and C all belong to the input region and are divided according to the spatial dimension. Each region contains a certain number of qubits. Part D belongs to the output region and is divided from Parts A and B according to the temporal dimension.

[0134] Step S50: Perform implicit decomposition operation on the cross-partition CZ gates generated after partitioning, and perform secondary fusion on the single-qubit gates generated by the decomposition operation.

[0135] For the circuits partitioned and optimized in step S40, implicit decomposition operations are performed at the defined partition boundaries, and the single-qubit operations generated by the decomposition are further fused to maximize memory savings and minimize computational overhead. In this step, implicit decomposition operations are performed on the cross-partition CZ gates generated after partitioning, and the single-qubit gates generated by the decomposition operations are fused a second time, including the following steps:

[0136] Step S501: For each cross-partition CZ gate, determine whether its control qubit has no subsequent gate operations in the remaining lines of its partition;

[0137] If so, then perform implicit decomposition on the CZ gate and absorb the branch index generated by the decomposition into the state index of the control qubit;

[0138] If not, perform a normal decomposition on the CZ gate to generate a projection gate P that acts on the control bits and a Z gate that acts on the target bits.

[0139] The implicit decomposition condition for cross-partition CZ gates is as follows: check whether the control qubit of the CZ gate has no subsequent gate operations in the remaining lines of its partition. During index absorption, if the condition is met, implicit decomposition is performed. Mathematically, the branch index l generated by the decomposition of the CZ gate corresponds to the control bit state 0 or 1, and the final state index of the control qubit is absorbed. In the phase gate processing, for CZ gates that do not meet the implicit decomposition conditions, ordinary decomposition is performed to generate standard branch paths: the projection gate (P gate) acting on the control bits and the Z gate acting on the target bits.

[0140] Step S502: Perform matrix multiplication fusion on the projection gate P used to mark branches in the implicit decomposition, or the Z gate generated by the ordinary decomposition, and the adjacent pre-order or post-order single-qubit gates on the active qubit.

[0141] In this step, the secondary fusion of the P-gate and Z-gate fuses the single-qubit operations generated in the decomposition step to eliminate additional computational overhead: the projection gate (P-gate) used to mark branches in the implicit decomposition is fused with its adjacent pre- or post-order single-qubit gates on the active qubit through matrix multiplication. Similarly, the Z-gate generated in the ordinary decomposition is fused with its adjacent single-qubit gates.

[0142] The final output consists of the optimized path after implicit decomposition and secondary fusion, as well as the quantum state computation task corresponding to each partition with absorbed branch indices.

[0143] Step S60: Based on the partitioned and merged circuit, perform task scheduling and parallel simulation calculation on a classical computing device to obtain the simulation results of the quantum circuit.

[0144] In this step, task scheduling and communication optimization can reduce cross-node interactions and improve parallel efficiency. For the cross-node data exchange required during the merging calculation of the partition output states generated in step S50 in large-scale distributed simulations, communication modes and data layout optimizations are performed to reduce communication latency and improve the overall parallel efficiency of the system.

[0145] In this embodiment, task scheduling and parallel simulation computation are performed on a classical computing device, including the following steps:

[0146] Step S601, Data Sharding and Distribution: The output state vectors of each partition are sharded according to the locality of the qubit index and distributed to multiple computing nodes of the parallel computing cluster.

[0147] In this step, the output state vector of each partition to be merged is fragmented according to the locality of its qubit index. Each fragment contains a set of consecutive amplitude indices and is assigned to a core group (computing nodes) of the supercomputer. The allocation principle is to maximize data locality: ensuring that in subsequent computations, most of the data required by a node can be provided by its local fragments or a few neighboring nodes, thereby minimizing remote data access.

[0148] Step S602, Communication Optimization: Reconstruct the centralized data collection communication mode into a grouped parallel global data exchange communication mode.

[0149] In this step, the communication mode reconstruction and parallelization transforms the traditional, centralized MPI_Gather communication mode into a more efficient, peer-to-peer MPI_Alltoall communication mode. During parallel group execution, all nodes participating in the merging computation are divided into several communication groups, for example, 128 nodes per group. Within each group, the MPI_Alltoall operation is executed in parallel, enabling full data exchange between all nodes within the group.

[0150] Step S603, Parallel Computing: Each computing node performs parallel computation on the quantum state evolution of the segment it is responsible for, and exchanges necessary data through an optimized communication method to merge the results of each partition and complete the simulation of the entire circuit.

[0151] In this step, before initiating communication, the data in each node's local shards undergoes memory alignment and sorting preprocessing to conform to the memory layout requirements of efficient communication libraries (such as MPI) for data transmission. This data preprocessing and alignment avoids the overhead of packing / unpacking caused by inconsistent data formats during communication, thereby maximizing the effective bandwidth of the inter-node interconnect network. Finally, the optimized communication configuration and data distribution scheme are output.

[0152] During simulation execution, quantum states are computed in parallel, and simulation results are output. Based on the optimized circuitry and data distribution, quantum state computations are performed in parallel on a classical supercomputer.

[0153] Step S6031: Merge output region status:

[0154] Based on the output state of the input region, the input state of the output region is calculated. Tensor product and summation operations are performed in parallel using communication-optimized fragmented data.

[0155] Step S6032, Output area gate operation execution:

[0156] Parallel computation is performed on gate operations (including single-qubit gates and CZ gates) in the output region. Each core group is responsible for the state update of a slice. Single-node optimizations, such as vectorization and register communication, are used during the computation process to improve floating-point operation efficiency.

[0157] Step S6033, Output of complete state vector / target amplitude:

[0158] If the complete output state vector needs to be calculated: merge the calculation results of all slices to generate a complex vector of length 2n;

[0159] If only a small number of amplitudes need to be calculated: calculate the target amplitude using the inner product. No need to generate a complete state vector;

[0160] Output: Simulation results, complete state vector or target amplitude.

[0161] Step S604, Post-processing: Verify the unitarity and probability distribution of the quantum state obtained from the simulation calculation, and output the simulation result file with verification information.

[0162] In this step, the parallel computation of quantum states and the output simulation results are verified and their reliability analyzed to ensure compliance with quantum mechanics principles and to evaluate the simulation accuracy. The grouped parallel global data exchange communication mode is based on the MPI_Alltoall operation of the MPI library.

[0163] In this embodiment, post-processing involves result verification and error analysis, including unitarity verification, probability distribution verification, and result storage and output. Unitarity verification checks whether the combination of all gate operations maintains unitarity throughout the simulation process. This can be verified by calculating the norm of the final output state vector: for pure-state simulations, it should satisfy... (Within the allowable range of floating-point errors). For block computation, verify the unitarity of each partition evolution operation.

[0164] The probability distribution verification involves calculating the probability of all amplitudes in the output state. The simulation results are then processed and verified to ensure that the sum is normalized (totaling to 1). During result storage and output, the final simulation results (amplitude vector or sampled values), key simulation parameters (circuit structure, partitioning scheme, number of nodes used, time consumption, etc.), and verification metrics (norm, degree of agreement with theoretical distribution) are stored in standard formats (such as HDF5, JSON). Result parsing tools or interfaces are provided to support the use of simulation results for subsequent quantum hardware benchmarking, algorithm performance evaluation, and other applications. The final output is a reliable, standard-format simulation result file with verification information and metadata.

[0165] For example, input a such Figure 2 The quantum circuit shown. When processing it using the large-scale qubit simulation method based on quantum circuit decomposition in this embodiment, the following steps are included:

[0166] Step 1: Line Pre-processing

[0167] The system identified this as a 4-qubit circuit. Since there are no consecutive identical single-qubit gates (such as H·H) in the circuit, no redundant gates can be eliminated. It contains the following gate sequence (in chronological order): and parallel; ; and parallel; and , parallel; .

[0168] Step 2, Quantum Gate Conversion:

[0169] like Figure 3 As shown, two multi-qubit non-CZ gates were identified: and Convert them according to rule 1: .

[0170] The converted circuit (containing only single-bit gates and CZ gates) is as follows: Figure 4 As shown: and , parallel; ; and parallel; ; and , parallel; ; ; .

[0171] Step 3, Quantum Gate Fusion:

[0172] Adjacent single-qubit gate fusion: On qubit 2, H-gates and T-gates can be fused into... On qubit 3, the X gate and H gate can be fused into .

[0173] Step 4: Dynamic Decomposition of Multiple Regions

[0174] like Figure 4 As shown, the qubits are first sorted, and the circuit is adjusted as follows: Figure 4 The structure is shown. Then, the 4-qubit circuit is divided into two regions according to the dotted lines in the diagram. It was cut up.

[0175] Step 5: Implicit decomposition and fusion of quadratic gates:

[0176] The inspection revealed that the door had been cut. The control bit is not subject to any gate operations in subsequent lines. Therefore, the gate satisfies implicit decomposition. The P gate generated on control bit 1 is fused with the preceding gate U2, and the Z gate (I gate) generated on target bit 3 is fused with the preceding gate U3 and the following gate H.

[0177] Step Six: Task Scheduling and Communication Optimization

[0178] The computational tasks for the two regions are each assigned to a classical computer. Due to the small scale of this example, the communication overhead is negligible, but to demonstrate the principle, it is planned that when the results from regions A and B need to be merged to compute the final state, a lightweight MPI_Alltoall exchange of necessary data is performed between the two nodes.

[0179] Step 7: Simulate execution:

[0180] Each node computes its assigned branch in parallel. Data is exchanged through communication, and the results from the two regions are merged to form the intermediate state of the entire 4-qubit system. The remaining gates are then completed in parallel on each node.

[0181] Step 8: Post-processing:

[0182] Unitarity verification: Calculate the final 4-qubit state vector and verify.

[0183] Probability verification: Output the probability of all 16 amplitudes, verifying that the sum is 1.

[0184] Output results: Store the final state vector or the target amplitude value specified by the user, and generate a simulation report. In this example, four branches were generated due to ordinary decomposition, but the computational depth was reduced by gate fusion.

[0185] The large-scale quantum bit simulation method in this embodiment breaks through the limitation that implicit decomposition is only applicable to CZ gates, and extends to commonly used 2-qubit gates and 3-qubit gates; it features flexible dynamic partitioning, making it suitable for ultra-large-scale quantum circuits; and it reduces the number of gates and depth of quantum circuits, further reducing the computational complexity of the simulation.

[0186] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0187] See Figure 6 As shown in this embodiment of the invention, a large-scale qubit simulation system based on quantum circuit decomposition is provided. This system is deployed on a classical supercomputer platform and achieves efficient and high-precision simulation of large-scale, deep quantum circuits through hardware and software co-optimization. The system adopts a hierarchical and modular design, with its core architecture as follows: Figure 6 As shown, the system mainly includes: an input module, a circuit preprocessing module, a gate conversion and fusion module, a multi-region dynamic programming module, an implicit decomposition and communication optimization module, a post-processing and verification module, an output module, and a parallel cluster. These modules are connected in series through a standardized intermediate data interface to form a complete automated optimization pipeline. Specifically, this large-scale quantum bit simulation system includes:

[0188] The input module is used to receive the input quantum circuit description;

[0189] The circuit preprocessing module, connected to the input module, is used to analyze the input quantum circuit, remove redundant gates, and sort the time sequence to obtain a regularized quantum circuit.

[0190] The gate conversion and fusion module, connected to the circuit preprocessing module, is used to convert the multi-qubit gates in the regularized quantum circuit into a combination of single-qubit gates and two-qubit CZ gates, and to fuse adjacent single-qubit gates on the same qubit to obtain a simplified quantum circuit.

[0191] A multi-region dynamic planning module, connected to the gate conversion and fusion module, is used to dynamically partition and optimize the simplified quantum circuit, dividing the circuit into multiple regions and identifying the CZ gates that cross regions.

[0192] The implicit decomposition and quadratic gate fusion module is connected to the multi-region dynamic programming module. It is used to perform implicit decomposition or ordinary decomposition operations on cross-region CZ gates and perform secondary fusion on the single-qubit gates generated by the decomposition to generate an optimized scheme that includes partitioned computing tasks and implicit decomposition configuration.

[0193] The task scheduling and communication optimization module, connected to the implicit decomposition and quadratic gate fusion module, is used to map the computing tasks of each partition to computing nodes according to the optimization scheme, and plan the data exchange and communication strategies between nodes.

[0194] The parallel cluster, consisting of multiple computing nodes, is connected to the task scheduling and communication optimization module and is used to perform the evolution calculation of quantum states in each partition in parallel.

[0195] The post-processing and verification module, connected to the parallel cluster, is used to collect and merge the calculation results of each node, perform unitarity and probability verification, and generate a simulation report.

[0196] The output module, connected to the post-processing and verification module, is used to output the final simulation result file and simulation report.

[0197] In this embodiment, the line preprocessing module is specifically used for:

[0198] The number of qubits, gate type, and operation sequence of the quantum circuit are analyzed to generate a structured circuit description file;

[0199] Identify and remove redundant quantum gates from the circuit;

[0200] The gate sequences are sorted according to the operation timing of the qubits, and gate operations that can be executed in parallel are marked.

[0201] In this embodiment, the gate conversion and fusion module includes:

[0202] The gate conversion unit is used to traverse the normalized quantum circuit, identify all non-CZ gate multi-qubit gates, and apply a preset conversion rule to convert them into a combined structure consisting of a single-qubit gate and a two-qubit CZ gate. The multi-qubit gate includes at least a two-qubit CNOT gate, a SWAP gate, and a three-qubit Toffoli gate, a CCZ gate, and a Fredkin gate.

[0203] The gate fusion unit is used to perform matrix multiplication on adjacent single-qubit gates that act on the same qubit in the converted circuit and the original circuit, and merge them into an equivalent single-qubit SU(2) gate.

[0204] In this embodiment, the multi-region dynamic planning module is specifically used for:

[0205] Based on the structure, depth and simulation target of the simplified quantum circuit, an initial partitioning scheme is generated to divide the circuit into multiple input regions and at least one output region, and to ensure that the cross-region gates are only CZ gates.

[0206] Dynamic optimization search is performed under the condition of satisfying partition constraints, which include: balancing the number of qubits in each region, minimizing the number of CZ gates to be cut, and maximizing the number of control qubits generated after the cut without subsequent gate operations.

[0207] Output the final partitioning scheme and the list of CZ gates to be partitioned.

[0208] In this embodiment, the implicit decomposition and quadratic gate fusion module includes:

[0209] The condition judgment unit is used to determine, for each identified cross-region CZ gate, whether its control qubit has no subsequent gate operation in the remaining lines of its respective partition;

[0210] The decomposition execution unit is used to perform implicit decomposition on CZ gates that meet the conditions, and absorb the branch index generated by the decomposition into the state index of the control qubit; and to perform ordinary decomposition on CZ gates that do not meet the conditions, generating projection gates P and Z.

[0211] The secondary fusion unit is used to perform matrix multiplication fusion of the projection gate P generated in the implicit decomposition or the Z gate generated in the ordinary decomposition with the single-qubit gate adjacent to the active qubit.

[0212] In this embodiment, the task scheduling and communication optimization module is specifically used for:

[0213] The output state vectors of each partition are divided into data slices according to the locality of their qubit indices, and the sliced ​​data is mapped to each computing node of the parallel cluster.

[0214] The traditional centralized data collection and communication mode is reconstructed into a packet parallel global data exchange and communication mode based on the message passing interface MPI.

[0215] Before initiating communication, the data in the local fragments of the node is preprocessed by memory alignment and sorting to meet the data transmission requirements of the efficient communication library.

[0216] In this embodiment, the grouped parallel global data exchange communication mode is a communication mode based on the MPI_Alltoall operation.

[0217] In this embodiment, the post-processing and verification module is specifically used for:

[0218] Calculate the total probability of the final output state vector and verify whether it is normalized;

[0219] Based on user needs, the partial state vectors of the distributed storage can be assembled into a complete state vector file, or the specified target amplitude can be calculated and output.

[0220] Record key performance indicators and verification results during the simulation process, and generate structured simulation reports.

[0221] This invention presents a large-scale qubit simulation method and system based on quantum circuit decomposition, which overcomes the limitation that implicit decomposition is only applicable to CZ gates and extends to commonly used 2-qubit and 3-qubit gates; it features flexible dynamic partitioning, making it suitable for ultra-large-scale quantum circuits; and it reduces the number of gates and depth of quantum circuits, further reducing the computational complexity of the simulation.

[0222] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for simulating large-scale qubits based on quantum circuit decomposition, characterized in that, Includes the following steps: The input quantum circuit is preprocessed to obtain a regularized quantum circuit; The normalized quantum circuit is subjected to quantum gate conversion, which transforms the multi-qubit gates in the circuit, except for the two-qubit CZ gate, into a combined structure composed of single-qubit gates and two-qubit CZ gates, thus obtaining a standardized quantum circuit. In the standardized quantum circuit, gate fusion is performed on adjacent single-qubit gates acting on the same qubit to obtain a simplified quantum circuit; Based on a preset partitioning principle, the simplified quantum circuit is dynamically partitioned into multiple regions, dividing the circuit into multiple input regions and at least one output region. An implicit decomposition operation is performed on the cross-partition CZ gates generated after partitioning, and the single-qubit gates generated by the decomposition operation are fused again. Based on the partitioned and merged circuits, task scheduling and parallel simulation computation are performed on classical computing devices to obtain the simulation results of quantum circuits.

2. The large-scale qubit simulation method based on quantum circuit decomposition as described in claim 1, characterized in that, The input quantum circuit is preprocessed, including the following steps: Circuit analysis and gate type identification: Analyze the number of qubits, gate type, operation sequence and qubit mapping relationship of the quantum circuit to generate a structured circuit description file; Redundant gate removal: Identify and remove invalid or redundant quantum gates from the quantum circuit; Gate timing sorting: Sort the gate sequence according to the operation timing of the qubits, mark the parallel gate operations of different qubits, and output the preprocessed quantum circuit.

3. The large-scale qubit simulation method based on quantum circuit decomposition as described in claim 1, characterized in that, The quantum gate transformation of the regularized quantum circuit includes the following steps: The two-qubit CNOT gate is converted into a combination of "preorder H gate on the target bit + CZ gate + postorder H gate on the target bit"; The two-qubit SWAP gate is converted into a combination of three CNOT gates, and then the conversion rule of CNOT gate is applied to each CNOT gate to convert it into a CZ gate; Convert the three-qubit Toffoli gate into four on the target bit. The combination of the door and three CZ doors; The three-qubit CCZ gate is converted into a combination of a single-qubit H gate and a Tooffoli gate. Then, the Tooffoli gate conversion rule is applied to the Tooffoli gate part to decompose the CCZ gate into a combination of a single-qubit gate and a CZ gate, thus completing the dimensionality reduction adaptation of the CCZ gate. The three-qubit Fredkin gate is converted into a combination of a two-qubit CNOT gate, a three-qubit Tofoli gate, and a two-qubit CNOT gate. Then, the CNOT gate and Tofoli gate parts are decomposed into combinations of single-qubit gates and CZ gates by applying the corresponding conversion rules, thus completing the dimensionality reduction adaptation of the Fredkin gate.

4. The large-scale qubit simulation method based on quantum circuit decomposition as described in claim 3, characterized in that, The gate fusion is specifically as follows: for multiple adjacent single-qubit gates on the same qubit, they are merged into an equivalent single-qubit SU(2) gate by matrix multiplication. After fusion, the original gate sequence is deleted and only the equivalent fused gate is retained.

5. The large-scale qubit simulation method based on quantum circuit decomposition as described in claim 1, characterized in that, The preset partitioning principles include: The error in the number of qubits in the regions divided according to spatial dimensions is less than a preset threshold; CZ gates between regions defined solely by spatial dimensions are treated as cross-regional gates for cutting; There is no cut-off CZ gate between the input and output regions; The input region ends with one or more cut CZ gates.

6. The large-scale qubit simulation method based on quantum circuit decomposition as described in claim 1, characterized in that, The implicit decomposition operation is performed on the cross-partition CZ gates generated after partitioning, and the single-qubit gates generated by the decomposition operation are then fused again, including the following steps: For each cross-partition CZ gate, determine whether its control qubit has no subsequent gate operations in the remaining lines of its partition; If so, then perform implicit decomposition on the CZ gate and absorb the branch index generated by the decomposition into the state index of the control qubit; If not, perform normal decomposition on the CZ gate to generate a projection gate P that acts on the control bits and a Z gate that acts on the target bits; The projection gate P used to mark branches in the implicit decomposition, or the Z gate generated by the ordinary decomposition, is fused by matrix multiplication with the preceding or following single-qubit gates adjacent to the active qubit.

7. The large-scale qubit simulation method based on quantum circuit decomposition as described in claim 6, characterized in that, Performing task scheduling and parallel simulation computation on classical computing devices includes the following steps: Data partitioning and distribution: The output state vectors of each partition are partitioned according to the locality of the qubit index and distributed to multiple computing nodes of the parallel computing cluster; Communication optimization: Reconstruct the centralized data collection communication mode into a packet-parallel global data exchange communication mode; Parallel computing: Each computing node performs parallel computation of the quantum state evolution of the segment it is responsible for, and exchanges necessary data through optimized communication methods to merge the results of each partition and complete the simulation of the entire circuit; Post-processing: Verify the unitarity and probability distribution of the quantum states obtained from the simulation calculation, and output a simulation result file with verification information.

8. A large-scale qubit simulation system based on quantum circuit decomposition, used to execute the large-scale qubit simulation method based on quantum circuit decomposition as described in any one of claims 1-7, characterized in that, The system is deployed on a classic computing cluster, including: The input module is used to receive the input quantum circuit description; The circuit preprocessing module, connected to the input module, is used to analyze the input quantum circuit, remove redundant gates, and sort the time sequence to obtain a regularized quantum circuit. The gate conversion and fusion module, connected to the circuit preprocessing module, is used to convert the multi-qubit gates in the regularized quantum circuit into a combination of single-qubit gates and two-qubit CZ gates, and to fuse adjacent single-qubit gates on the same qubit to obtain a simplified quantum circuit. A multi-region dynamic planning module, connected to the gate conversion and fusion module, is used to dynamically partition and optimize the simplified quantum circuit, dividing the circuit into multiple regions and identifying the CZ gates that cross regions. The implicit decomposition and quadratic gate fusion module is connected to the multi-region dynamic programming module. It is used to perform implicit decomposition or ordinary decomposition operations on cross-region CZ gates and perform secondary fusion on the single-qubit gates generated by the decomposition to generate an optimized scheme that includes partitioned computing tasks and implicit decomposition configuration. The task scheduling and communication optimization module, connected to the implicit decomposition and quadratic gate fusion module, is used to map the computing tasks of each partition to computing nodes according to the optimization scheme, and plan the data exchange and communication strategies between nodes. The parallel cluster, consisting of multiple computing nodes, is connected to the task scheduling and communication optimization module and is used to perform the evolution calculation of quantum states in each partition in parallel. The post-processing and verification module, connected to the parallel cluster, is used to collect and merge the calculation results of each node, perform unitarity and probability verification, and generate a simulation report. The output module, connected to the post-processing and verification module, is used to output the final simulation result file and simulation report.

9. The large-scale qubit simulation system based on quantum circuit decomposition as described in claim 8, characterized in that, The implicit decomposition and quadratic gate fusion module includes: The condition judgment unit is used to determine, for each identified cross-region CZ gate, whether its control qubit has no subsequent gate operation in the remaining lines of its respective partition; The decomposition execution unit is used to perform implicit decomposition on CZ gates that meet the conditions, and absorb the branch index generated by the decomposition into the state index of the control qubit; and to perform ordinary decomposition on CZ gates that do not meet the conditions, generating projection gates P and Z. The secondary fusion unit is used to perform matrix multiplication fusion of the projection gate P generated in the implicit decomposition or the Z gate generated in the ordinary decomposition with the single-qubit gate adjacent to the active qubit.

Images