Neural network representation of quantum circuits

Abstract

It provides a neural network representation of quantum circuits. [Solution] The method may include obtaining a configuration of a quantum circuit comprising n qubits and k quantum gates. The k quantum gates include at least one of single-qubit gates or two-qubit controlled gates. The method may also include constructing a neural network representing the quantum circuit, the neural network comprising k+1 layers, each containing k pairs of adjacent layers, where each pair of adjacent layers corresponds to one of the k quantum gates. The method may include connecting one or more nodes in each pair of adjacent layers based on the corresponding quantum gate representations from the k quantum gates. The method may include training the neural network using machine learning techniques to obtain an output. The method may include applying the output to the quantum circuit.

Description

[Technical Field]

[0001] This disclosure, in general terms, relates to the neural network representation of quantum circuits. [Background technology]

[0002] Quantum computers can perform quantum computing operations using quantum bits ("qubits") on quantum gates that can represent information as 1, 0, or 1 and 0 simultaneously. Quantum computers can train the parameters of their quantum computing system models to perform certain types of quantum computing operations (e.g., optimization, graph partitioning, quadratic programming, etc.) more efficiently and / or more accurately than classical computers.

[0003] The subject matter claimed in this disclosure is not limited to embodiments that resolve any shortcomings or embodiments that operate only in the environment described above. Rather, this background is provided solely to illustrate exemplary technical fields in which some embodiments described in this disclosure may be implemented. [Overview of the project] [Means for solving the problem]

[0004] According to one aspect of one embodiment, the method may include obtaining a configuration of a quantum circuit comprising n qubits and k quantum gates. The k quantum gates include at least one of single-qubit gates or two-qubit controlled gates. A neural network representing the quantum circuit may be constructed. The neural network comprises k+1 layers, each containing k pairs of adjacent layers, where each pair of adjacent layers corresponds to one of the k quantum gates. One or more nodes within each pair of adjacent layers may be connected based on the corresponding representation of the quantum gates among the k quantum gates. The neural network may be trained using machine learning techniques to obtain an output. The output may be applied to the quantum circuit.

[0005] The objectives and advantages of the embodiments are realized and achieved at least by the elements, features, and combinations specifically indicated in the claims. It should be understood that the above general description and the following detailed description are for illustrative purposes only and do not limit the claimed invention. [Brief explanation of the drawing]

[0006] Exemplary embodiments are described and explained with further specificity and detail through the use of the attached drawings.

[0007] [Figure 1] This figure illustrates an exemplary environment related to training quantum computing system model parameters.

[0008] [Figure 2] A block diagram of an exemplary computing system is shown.

[0009] [Figure 3] An exemplary quantum circuit in a 3-qubit system is shown.

[0010] [Figure 4A] This shows a topology pattern in neural network architectures, such as linear neural networks, used to represent a single qubit gate.

[0011] [Figure 4B] This shows a topology pattern in a neural network architecture used to represent a 2-qubit controlled gate.

[0012] [Figure 4C] This shows another topology pattern in a neural network architecture used to represent a 2-qubit controlled gate.

[0013] [Figure 5A] An exemplary quantum circuit is shown.

[0014] [Figure 5B] An exemplary neural network configured to represent a quantum circuit is shown.

[0015] [Figure 6] This is a flowchart illustrating an exemplary method for training a quantum computing system using a neural network representation of quantum circuits.

[0016] [Figure 7] This is a flowchart illustrating another exemplary method for training a quantum computing system using a neural network representation of quantum circuits. [Modes for carrying out the invention]

[0017] Quantum computers use quantum bits, or "qubits," which can be configured to store values ​​of 0, 1, or a superposition of both 0 and 1. Because qubits can store multiple values / exist in multiple states simultaneously, quantum computers can perform calculations faster and / or more accurately than classical computers that use only classical bits that can store either 0 or 1. As a result, quantum computers can more efficiently train quantum computing system models related to complex calculations and / or improve computing in various technological fields such as physics, chemistry, finance, and machine learning (ML).

[0018] Quantum circuits are designed to perform specific tasks that produce a desired output, enabling quantum computing systems to address real-world problems. For example, quantum circuits can be used to solve optimization problems such as selecting a stock portfolio to achieve a target gain. Traditionally, achieving a desired output involves proposing and testing multiple quantum circuits to identify the most effective solution. However, this process requires considerable quantum resources, as each proposed circuit is implemented on quantum hardware for evaluation. Thus, resources spent on circuits that are not selected can be effectively wasted. This process can lead to inefficiencies in the quantum circuit design process.

[0019] This disclosure describes a system and / or method that can help improve the evaluation and implementation of quantum circuits, and thereby help overcome the aforementioned inefficiencies. The system and / or method described herein recognizes that quantum circuits, such as parameterized quantum circuits (PQCs), can be similar in some respects to machine learning models. As a result, classical neural networks can be used to represent the proposed quantum circuits. For example, layers of the neural network can represent quantum gates in the quantum circuit. Based on this representation, classical neural networks can be trained on a classical computer using machine learning algorithms. After the neural network is trained, the trained configuration of the neural network can be, in turn, applied to determine the configuration of the quantum circuit. This approach can help enable efficient evaluation and optimization of quantum circuits and reduce the waste of quantum resources.

[0020] Embodiments of the present disclosure will be described with reference to the accompanying drawings. Figure 1 shows an exemplary environment 120 related to training quantum computing system model parameters according to one or more embodiments of the present disclosure. Environment 120 may include a quantum computing system 100, parameter values ​​102, a dataset 104, and a gateset ansatz 106. The quantum computing system 100 may take the parameter values ​​102, the dataset 104, and the gateset ansatz 106 as input and be configured to update one or more of the parameter values ​​102 with specific trained values.

[0021] In some embodiments, the quantum computing system 100 may include quantum hardware 108. For example, the quantum hardware 108 may include a quantum processor that includes one or more qubits and the ability to house the qubits. In some embodiments, the qubits may be physically implemented using, for example, photons, trapped ions, electrons, one or more nuclei, superconducting circuits, and / or quantum dots. For example, the qubits may be physically implemented in a variety of ways, including the polarization state of a single photon, the spatial optical path of a single photon, two different energy states of an atom or ion, and / or the spin orientation of a particle or multiple particles such as a nucleus. In some embodiments, the quantum processor may include at least two qubits and at least one coupler that can connect those qubits. Householding the qubits may include, for example, supercooling the qubits to maintain them in an environment suitable for quantum computation.

[0022] In some embodiments, the quantum hardware 108 may include a quantum circuit 110. The quantum circuit 110 may be formed by a suitable arrangement of quantum gates and may act on qubits contained in the quantum hardware 108. The quantum circuit 110 may determine the properties of electromagnetic waves that can be applied to the qubits of the quantum hardware 108 to adjust the state of the qubits. The quantum circuits 300 and 500 shown in Figures 3 and 5A, respectively, may be examples of the quantum circuit 110.

[0023] In general, a quantum computing system, such as quantum computing system 100, can operate to perform quantum computations using a set of quantum gates that act on the quantum bits of the quantum computing system, for example, qubits. Generally, quantum gates are configured to manipulate the quantum states of qubits. The quantum states of a qubit may include a basic state, a superposition state that can be represented by any point on the surface of a sphere (where two opposing points on the sphere represent the qubit's 1 and 0 ground states), and an entangled state where the qubit state is based on the state of another qubit. The quantum states of a qubit can be tuned. For example, a quantum gate can tune the superposition state of a qubit by rotating the qubit's state from a first position to a second position. In these and other embodiments, quantum gates may represent operations that can be performed on qubits. Thus, quantum gates can be implemented by controlling the quantum hardware 108 that encodes the qubits, for example, by manipulating the energy levels of atoms, ions, photons, or superconducting circuits that form the quantum hardware. In these and other embodiments, the quantum hardware 108 may be controlled by the application of electromagnetic waves, such as lasers, microwaves, or other electromagnetic waves.

[0024] In these and other embodiments, how a quantum gate tunes a qubit may be determined based on parameter values ​​102 representing the values ​​of the quantum gate's parameters. For example, a gate may be configured to tune the superposition of qubits. In this example, the gate's parameters may indicate operators applied to the qubits by the gate, such as the angle of rotation of the qubits. In another example, a gate may be configured to tune the intensity of entanglement between one qubit and another. Thus, each quantum gate may have one or more distinct parameters that can be tuned. A symbolic unitary matrix U may be used to represent a single-qubit quantum gate represented by the following equation (1).

number

[0025] Different parameters of a quantum gate can be implemented by tuning one or more properties of an electromagnetic wave applied to the quantum hardware. For example, the amplitude, pulse shape, duration, wavelength, or phase of an electromagnetic wave, or other properties, can be set to specific settings to achieve different parameters of the quantum gate. For instance, a microwave pulse with a specific duration can be applied to a qubit to rotate it by a specific amount, such as 45 degrees, around a particular idealized axis. In these and other embodiments, other properties of the microwave pulse may be set to specific settings to help achieve the correct tuning of the qubit. Thus, the properties of an electromagnetic wave that can be applied to the quantum hardware can be tuned to tune the parameters of a quantum gate.

[0026] Quantum gates can be organized in specific ways to implement quantum applications. For example, quantum applications can be developed to perform specific tasks to solve real-world problems. For instance, the task may be a quantum Fourier transform or optimization problem, such as how to select stocks to form a portfolio that achieves a desired gain and risk tolerance. The optimization problem may be encoded into a quantum algorithm. A quantum algorithm can be represented by a specific set of quantum gates organized in a specific way that encodes the variables and operations of the quantum algorithm into a sequence of quantum gates. A set of quantum gates organized in a specific sequence may be called a gate set Ansatz 106.

[0027] The gate set Ansatz 106 may contain quantum gates for solving an optimization problem. However, the quantum gate set Ansatz 106 does not have to contain values ​​for the parameters of the quantum gates in the quantum gate set Ansatz. Parameter training can achieve the selection of specific parameter values ​​for each quantum gate in the quantum gate set Ansatz. Parameter training may involve sequentially and iteratively adjusting the gate parameters using optimization techniques. In general, before training, none of the parameter values ​​102 for the quantum gates may be known. Thus, each of the parameter values ​​102 can be initialized to zero, a random number, or some other selected value. During training, values ​​from the dataset 104 are provided to the quantum gates, and results can be generated. The generated results can be compared with known results for the values. Based on the difference between the generated results and the known results, the parameter values ​​102 can be adjusted or updated as indicated by arrow 130. For example, the quantum computing system 100 can update one or more of the parameter values ​​102 with specific trained values ​​based on computations performed by the quantum computing system 100. Updating the parameter values ​​102 may result in the adjustment of one or more characteristics of the electromagnetic wavelength applied to the qubits of the quantum hardware 108 to produce the results. For example, based on a known gradient method or a no-gradient method, the parameters may be updated to minimize or maximize a value calculated from the generated output. Training may continue until the difference between the generated result and a known result falls within a certain threshold, or until some other result occurs, such as a limit on the number of sequential iterations or processing time.

[0028] The processing system 112 may be any configuration of a non-quantum processing device and / or system. For example, the processing system 112 may include one or more elements of the computing system 200. In these and other embodiments, the processing system 112 may be configured to control the quantum hardware 108, provide data to the quantum hardware 108, retrieve data from the quantum hardware 108, and / or interact with the quantum hardware 108 to assist the quantum hardware 108 in performing its functions. The processing system 112 may also be configured to train parameter values ​​for quantum gates using a neural network, such as the neural network 510 shown in Figure 5B.

[0029] In some embodiments, the parameter values ​​102, the dataset 104, and / or the gateset ansatz 106 may be provided to the retrieval / quantum computing system 100 via one or more physical networks, cloud networks, random access memory (RAM) drives, flash memory devices (e.g., solid-state memory devices), and / or any other means by which data can be transferred between devices and / or systems.

[0030] An example of using a quantum computing system 100 to solve an optimization problem is provided here. A quantum circuit 110 may be designed and configured according to a gate set ansatz 106 to solve a real-world problem such as an optimization problem. A processing system 112 may form a neural network representation of the gate set ansatz 106 according to one or more embodiments of the present disclosure. The quantum computing system 100 may perform one or more operations to train the parameters of the gate set ansatz 106 represented by the neural network. For example, a neural network representing the gate set ansatz 106 may be trained. Elements resulting from the neural network, such as edge weights or other aspects of the neural network, may be used to select the parameters of one or more quantum gates in the gate set ansatz. In these and other embodiments, the quantum computing system 100 may update the parameter values ​​102 for the quantum gates with specific trained values.

[0031] After selecting the parameters, the data is provided to the quantum hardware 108 and can be processed to generate an output. To process the data, the qubit state can be set using electromagnetic waves with specific properties. The output may be the solution to an optimization problem given the data provided to the quantum hardware 108.

[0032] Without departing from the scope of this disclosure, modifications, additions, or omissions may be made to the environment 120. For example, the quantum computing system 100 may include one or more additional components. Alternatively or additionally, the quantum computing system 100 may not include the processing system 112. In these and other embodiments, the processing system 112 is separate from the quantum computing system 100 and may be networked with the quantum computing system 100. Alternatively or additionally, the environment 120 may include one or more additional components.

[0033] Figure 2 shows a block diagram of an exemplary computing system according to one or more embodiments of the present disclosure. The computing system 200 may include a processor 202, memory 204, data storage 206, and / or a communication unit 208, all of which may be communicatively coupled. For example, the processing system 112 in Figure 1 may include one or more components of the computing system 200.

[0034] Generally, the processor 202 may include any suitable dedicated or general-purpose computer, computing entity, or processing device, including various computer hardware or software modules, and may be configured to execute instructions stored in any applicable computer-readable storage medium. For example, the processor 202 may include a microprocessor, microcontroller, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or any other digital or analog circuitry configured to interpret and / or execute program instructions and / or process data.

[0035] Although shown as a single processor, it will be understood that processor 202 may include any number of processors distributed across any number of networks or physical locations, configured to individually or collectively perform any number of operations described in this disclosure. In some embodiments, processor 202 may interpret and / or execute program instructions and / or process data stored in memory 204, data storage 206, or memory 204 and data storage 206. In some embodiments, processor 202 may fetch program instructions from data storage 206 and load program instructions into memory 204.

[0036] After the program instructions are loaded into memory 204, the processor 202 may execute program instructions such as instructions that cause the computing system 200 to perform some of the operations of methods 600 and 700 in Figures 6 and 7.

[0037] The memory 204 and data storage 206 may include computer-readable storage media or one or more computer-readable storage media for storing computer-executable instructions or data structures. Such computer-readable storage media may be any available media that can be accessed by a general-purpose or dedicated computer, such as a processor 202. In some embodiments, the computing system 200 may or may not include either the memory 204 or the data storage 206.

[0038] Such computer-readable storage media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM®), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory devices (e.g., solid-state memory devices), or any other storage media that can be used to store desired program code in the form of computer-executable instructions or data structures and can be accessed by a general-purpose or dedicated computer. Combinations of the above may also be included within the scope of computer-readable storage media. Computer-executable instructions may include, for example, instructions and data configured to cause processor 202 to perform a particular operation or group of operations.

[0039] The communication unit 208 may include any component, device, system, or combination thereof configured to transmit or receive information over a network. In some embodiments, the communication unit 208 may communicate with other devices located at other locations, at the same location, or with other components within the same system. For example, the communication unit 208 may include modems, network cards (wireless or wired), optical communication devices, infrared communication devices, wireless communication devices (such as antennas), and / or chipsets (such as Bluetooth® devices, 802.6 devices (e.g., Metropolitan Area Network (MAN)), WiFi devices, WiMAX devices, cellular communication equipment, etc.). The communication unit 208 may enable data to be exchanged with the network and / or any other devices or systems described herein. For example, the communication unit 208 may enable computing system 200 to communicate with other systems such as computing devices and / or other networks.

[0040] A person skilled in the art will recognize, after reviewing this disclosure, that modifications, additions, or omissions may be made to the computing system 200 without departing from the scope of this disclosure. For example, the computing system 200 may include more or fewer components than those expressly illustrated and described.

[0041] Figure 3 shows an exemplary quantum circuit 300 in a 3-qubit system according to one or more embodiments of the present disclosure. The quantum circuit 300 may be an example of the quantum circuit in Figure 1. The quantum circuit 300 includes three qubits, indicated as qubit 1, qubit 2, and qubit 3. Qubit 1 consists of three single-qubit gates indicated as U1, U2, and U3. In these and other embodiments, the single-qubit gates can adjust the angle of rotation of the qubit. Qubit 2 includes two single-qubit gates indicated as U4 and U5, and a 2-qubit control gate indicated as U6. For gate U6, qubit 3 is the control qubit and qubit 2 is the target qubit. On qubit 3 are a single-qubit gate U7 and a 2-qubit control gate U8. For gate U8, qubit 2 is the control qubit and qubit 3 is the target qubit. In these and other embodiments, the two-qubit control gate U8 may be used to create entanglement between the control qubit and the target qubit. The parameters of the two-qubit control gate may be configured to adjust the intensity of the entanglement between the control qubit and the target qubit, and / or other aspects of the entanglement between the control qubit and the target qubit.

[0042] A quantum circuit can represent the unitary evolution through strings of single-qubit gates and two-qubit controlled gates for a given initial state of n qubits. In Non-Patent Document 1 (hereinafter referred to as “Reference 1”), which is incorporated herein by reference in its entirety, the unitary matrix representations for the single-qubit gates and two-qubit controlled gates in a quantum circuit are developed. These representations correspond to the canonical basis of the n-qubit Hilbert space.

Non-Patent Document 1

[0043] Let U be the symbolic unitary matrix representing a single-qubit gate. U may be represented by Equation (1) described above and reproduced below.

Equation

Equation

Equation

[0044] For example, based on equations (2) and (3), the single qubit gate U1 (n = 3, j = 1) of the quantum circuit 300 can be represented by the unitary matrix S1 using the following equation (4). [Mathematics]

[0045] In another example, the single qubit gate U4 (n = 3, j = 2) of the quantum circuit 300 can be represented by the unitary matrix S2 using the following equation (5) obtained from equations (2) and (3). [Mathematics]

[0046] For a two qubit controlled gate in an n qubit system with the i-th qubit as the control qubit and the j-th qubit as the target qubit, the unitary matrix representing the two qubit controlled gate can be separately expressed in two different scenarios. For example, the two different scenarios can be the cases of i < j and i > j. In the case of i < j, the two qubit controlled gate can be represented by the following equation (6). [Mathematics] Here, CU i<j has rank 2 n and [Mathematics] is the identity matrix of rank 2 n-i and [Mathematics] and this represents a 2-sparse matrix having a structure similar to that described by Equation (3) [the U with a hat may be written like this for convenience]. For i > j, the 2-qubit control gate can be represented by Equation (7) below.

Number

Number

[0047] For example, the 2-qubit control gate U8 (n = 3, i = 2, and j = 3) of the quantum circuit 300 corresponds to the scenario of i < j based on the fact that qubit 2 is the control qubit, so i = 2, qubit 3 is the target qubit, so j = 3, and n = 3 since it is a 3-qubit system. Based on Equation (6), U8 can be represented by Equation (8) below.

Number

Number

[0048] In another example, for the 2-qubit control gate in a 5-qubit system (not shown in FIG. 3) with n = 5, i = 2, and j = 3, based on Equation (6), the 2-qubit control gate can be represented by Equation (10) below.

Number

number

[0049] Without departing from the scope of this disclosure, modifications, additions, or omissions may be made to the quantum gates U1 to U8. For example, one or more gates may be added to one of the qubits, or removed from one of the qubits.

[0050] A neural network typically consists of multiple layers organized in a sequential structure. Each layer contains multiple nodes, also called neurons or units. Nodes in adjacent layers are interconnected by edges or connections, each associated with weight parameters. Initially, the weight parameters are assigned initial values, which may be zero, randomly generated, or based on a predefined strategy. An input dataset is provided to the input layer (the first layer) of the neural network, and the data is propagated through the network using an activation function at each node. The final output is produced by the output layer (the last layer). To train the neural network, the output is compared against a desired set of objectives, called the ground truth or target values, using a loss function that quantifies the difference between the predicted output and the target values. The loss function is then minimized by tuning the weight parameters using an optimization algorithm. This process, known as backpropagation, iteratively updates the weight parameters to improve the network's performance and achieve a configuration that can satisfy specific parameters.

[0051] To construct a neural network representation of a quantum circuit, the architecture of the neural network and the connectivity topology between adjacent layers can be defined. The architecture of the neural network includes the number of layers and the number of nodes in each layer. The connectivity topology between adjacent layers specifies how nodes in one layer are connected to nodes in subsequent layers, as well as the associated weight parameters of the connections (edges).

[0052] In some embodiments, linear neural networks can be used to represent quantum circuits. A linear neural network may have the same number of nodes across all layers. A linear neural network may also use a linear activation function. A linear neural network iteratively transforms inputs sequentially through a sequence of simple linear transformations. Details regarding the recursive structure of linear neural networks and the effects of their hyperparameters, such as their initialization scheme, width, and depth, are described in Non-Patent Literature 2, which is incorporated herein by reference in its entirety. [Non-Patent Document 2] The Principles of Deep Learning Theory, Roberts et al., Cambridge University Press Cambridge, MA, USA, 2022

[0053] In some embodiments, a neural network, such as a linear neural network, may be used to represent a parameterized quantum circuit. In these and other embodiments, for an n-qubit quantum circuit containing k quantum gates, the neural network may be constructed with k+1 layers, where each layer is 2 nIt contains k nodes. Each quantum gate can be represented by two adjacent layers in the neural network and the connections between nodes in each of those two adjacent layers. Thus, a linear neural network with k+1 layers can represent k quantum gates. For example, the first quantum gate (k=1) may be represented by the first and second layers and the connections between the first and second layers, and the kth quantum gate may be represented by the kth layer and the (k+1)th layer (the last layer) and the connections between the kth layer and the (k+1)th layer.

[0054] Figure 4A shows a topology pattern in a neural network architecture, such as a linear neural network, used to represent a single qubit gate according to one or more embodiments of the present disclosure. The represented single qubit gate may be applied to the j-th qubit in an n-qubit system. For simplicity, gate U4 (n=3, j=1, k=3) shown in Figure 3 is used as an example. However, the same topology pattern may be generalized to other single qubit gates in a quantum circuit. Gate U4 may also be represented by the fourth and fifth layers of the neural network, as well as the connections between them, where each layer is 2 n It contains several nodes. Part of this representation is shown as block 401 in Figure 4A.

[0055] Block 401 contains two columns of layers corresponding to the fourth layer ("left layer") and the fifth layer ("right layer") of the neural network. Each layer within Block 401 is 2 n-j+1 It contains 1 node. When j=1 (for example, for gates U1, U2, or U3 in Figure 3), block 401 has 2 n-1+1 =2 n It can contain a number of nodes and therefore can represent the entire layer.

[0056] Block 401 is vertically divided into two subblocks labeled as subblocks 411 and 412. Each subblock is divided into two layers. n-jIt contains 1 to 2 nodes. Each node in each layer of each subblock is 1 to 2 based on their vertical position. n-j They are sequentially labeled within the range. For example, in the left layer of subblock 411, node 421 is labeled 1, node 422 is labeled 2, node 423 is labeled 2 n-j It is labeled as follows. In the layer to the right of subblock 411, node 431 is labeled as 1, node 432 is labeled as 2, and node 433 is labeled as 2 n-j They are labeled as follows. Similarly, in subblock 412, nodes 424 and 434 are labeled as 1, nodes 425 and 435 are labeled as 2, and nodes 426 and 436 are labeled as 2 n-j It is labeled as such. Block 401 also forms a bipartite graph containing a left layer and a right layer. The left layer contains all the nodes of the left layer, for example, from the first node 421 to the last node 426. The right layer contains all the nodes of the right layer, for example, from the first node 431 to the last node 436.

[0057] In some embodiments, one or more nodes in the left layer of block 401 may be connected to one or more nodes in the right layer of block 401. In these and other embodiments, each node in the left layer of block 401 may be connected to one or more nodes in the right layer of block 401. Alternatively or additionally, each node in the right layer of block 401 may be connected to one or more nodes in the left layer of block 401. In these and other embodiments, each node in the left layer of block 401 may be connected to two nodes in the right layer of block 401.

[0058] In some embodiments, the connections between nodes in the left and right layers of block 401 can be classified into two categories. In the first category, a first node in the left layer may be connected to a second node in the right layer, and the first and second nodes have the same vertical position within block 401. The same vertical position within the block can be the same number of nodes below the top or first node of block 401. For example, node 421 (labeled 1) in the left layer is connected to node 431 (also labeled 1) in the right layer, and node 426 is connected to node 236 (both 2 n-j (These are labeled as such). These connections are also called "horizontal connections" because they connect two nodes that are in the same vertical position. For horizontal connections in subblock 411, such as the connection between nodes 421 and 431 or between nodes 423 and 433, the weight parameter is u 11 (g) It may also be expressed as follows: For horizontal connections in subblock 412, such as the connection between nodes 426 and 436, the weight parameter is u 22 (g) It may also be expressed as follows. In some embodiments, each node in the left layer may have a horizontal connection with a node in the right layer.

[0059] In the second category, the first node in the left layer of one subblock may be connected to the second node in the right layer of the other subblock, where the first and second nodes have the same vertical position within their respective subblocks. The same vertical position within a subblock can be the same number of nodes below the top or first node of the subblock. Two nodes having the same vertical position in the same or different subblocks may be referred to in this disclosure as “nodes of the same label”. For example, node 421 in subblock 411 may be connected to node 434 of the same label in subblock 412, and node 423 in subblock 411 may be connected to node 436 in subblock 412. The weight parameters for these connections are u 21 (g)It may be expressed as follows. Similarly, the node 424 in the sub-block 412 may be connected to the node 431 with the same label in the sub-block 411, and the node 426 in the sub-block 412 may be connected to the node 433 in the sub-block 411. The weight parameters for these connections are u 12 (g) It may be expressed as follows.

[0060] FIG. 4B shows a topology pattern in a neural network architecture used to represent a two-qubit control gate in the case of i < j according to one or more embodiments of the present disclosure. The two-qubit control gate shown has an i-th qubit as a control qubit and a j-th qubit as a target qubit in an n-qubit system, where i < j. For simplicity, the gate U8 (n = 3, i = 2, j = 3, k = 8) shown in FIG. 3 is used as an example. However, the same topology pattern can be generalized to other two-qubit control gates in a quantum circuit. The gate U8 may be represented by the eighth and ninth layers of the neural network and the connections therebetween, and each layer contains 2 n nodes.

[0061] As described above, the weight matrix CU of Equation (6) i<j can be used to represent the gate U8. CU i<j contains 2 i blocks, and each block is represented by B l where 1 ≤ l ≤ 2 i . Based on Equation (6), when l is odd, B l is the identity matrix

Number

[0062] Figure 4C shows a topology pattern in a neural network architecture used to represent a two-qubit controlled gate for the case i>j according to one or more embodiments of the present disclosure. The represented two-qubit controlled gate is in an n-qubit system where the i-th qubit is the control qubit and the j-th qubit is the target qubit, where i>j. For simplicity, gate U6 (n=3, i=3, j=2, k=6) shown in Figure 3 is used as an example. However, the same topology pattern can be generalized to other two-qubit controlled gates in quantum circuits. Gate U6 may also be represented by the sixth and seventh layers of the neural network, as well as the connections between them, where each layer is 2 n It contains 1 node.

[0063] As mentioned above, the weight matrix CU in equation (7) i>j However, it can be used to represent U6. CU i>j 2 inside j There are blocks, and each block is B l This is shown by, where 1 ≤ l ≤ 2 j Therefore, if l is odd, B l This is the identity matrix.

number

[0064] Each subblock within block 461 is 2 n-i It consists of B nodes. ls This is shown by, where 1 ≤ s ≤ 2 i-j+1 It is -1. If s is even, B ls This includes subblocks 472, 474, and 475, which have horizontal connections. n-iIt is an identity matrix corresponding to the sub-blocks of the nodes. The weight parameters for these connections are 1.

[0065] When s is odd, B ls represents other non-identity matrix sub-blocks such as sub-blocks 471, 473, 475, and 477. The connections between the nodes in the left and right layers of these sub-blocks may also be classified into two categories, which are similar to the topological patterns described for the case of i < j in the first category of connections. All the nodes in the left layer of these sub-blocks can be horizontally connected to the nodes with the same label in the right layer of the same sub-block. The weight parameters for these connections are u 11 (g) if those sub-blocks are within the first group, and are u 22 (g) if those sub-blocks are within the third group.

[0066] In the second category of connections, all the nodes in the left layer of the sub-blocks within the first group can be connected to the nodes with the same label in the right layer of the sub-blocks at the same position within the third group. The weight parameters for these connections are u 21 (g) These connections are shown, for example, between the nodes in the left layer of sub-block 471 and the nodes in the right layer of sub-block 475. Further, all the nodes in the left layer of the sub-blocks within the third group can be connected to the nodes with the same label in the right layer of the sub-blocks at the same position within the first group. The weight parameters for these connections are u 12 (g) These connections are shown, for example, between the nodes in the left layer of sub-block 475 and the nodes in the right layer of sub-block 471.

[0067] Figures 5A and 5B show examples of using a linear neural network to represent a given quantum circuit according to one or more embodiments of the present disclosure. FIG. 5A shows an exemplary quantum circuit 500 according to one or more embodiments of the present disclosure. Quantum circuit 500 may be an example of the quantum circuit of FIG. 1. Quantum circuit 500 is a four-qubit system including four qubits shown as qubits 1 to 4. Gates U1 to U 12 are single-qubit gates, and gates U 13 to U 16 are two-qubit controlled gates.

[0068] FIG. 5B shows an exemplary linear neural network 510 configured to represent quantum circuit 500 according to one or more embodiments of the present disclosure. Quantum circuit 500 includes both single-qubit gates and two-qubit controlled gates. For simplicity and for illustrative purposes, neural network 510 is shown as representing only the four two-qubit controlled gates U 13 to U 16 . Thus, neural network 510 represents a quantum circuit with n = 4 and k = 4. Based on the disclosed embodiments, neural network 510 includes k + 1 = 5 labeled layers 521 to 525, and each layer includes 2 4 = 16 nodes. Each of the two-qubit controlled gates U 13 to U 16 is represented by a connection between two adjacent layers called intermediate layers 531 to 534. Intermediate layer 531 corresponds to gate U 13 , intermediate layer 532 corresponds to gate U 14 , intermediate layer 533 corresponds to gate U 15 , and intermediate layer 534 corresponds to gate U 16 .

[0069] For gate U 13 where i = 1 and j = 2, this is the case where i < j. According to one or more of the foregoing embodiments, within intermediate layer 531 there are 2 iThere are 2 blocks, denoted by blocks B1 to B2. The first block B1 is the identity matrix

Number

[0070] For the gate U where i = 2 and j = 3, this is also the case when i < j. Thus, there are 2 14 = 4 blocks in the intermediate layer 532, denoted by B l (where 1 ≤ l ≤ 4). The first and third blocks B1 and B3 (when l is odd) are the identity matrix i = 4

Number

[0071] For gate U 15 , since this is also the case of i < j, the connections in the middle layer 533 can be constructed similarly based on the topology patterns of the middle layers 531 and 532. For gate U 16 , i = 4 and j = 1, which is the case of i > j. Thus, the connections within the middle layer 534 can be structured based on the topology pattern shown in block 461 of FIG. 4C.

[0072] It should be noted that the quantum circuit 500 includes only single-qubit gates and two-qubit controlled gates, which are provided for illustrative purposes only. Quantum circuits may also include one or more multi-qubit gates acting on more than two qubits. However, multi-qubit gates can be mathematically represented by single-qubit gates and / or two-qubit controlled gates. Therefore, the quantum circuit representation model described herein can function as a universal model for quantum computing. Thus, the quantum circuit representation model described herein can represent any quantum circuit, regardless of the type of quantum gates included in the quantum circuit.

[0073] Without departing from the scope of this disclosure, modifications, additions, or omissions may be made to the quantum circuit 500 and the linear neural network 510. For example, one or more connections may be added to or removed in one of the hidden layers.

[0074] Figure 6 is a flowchart of an exemplary method 600 for training a quantum computing system using a linear neural network representation of a quantum circuit, according to one or more embodiments of the present disclosure. Method 600 can be performed by any suitable system, apparatus, or device. For example, a quantum computing system 100, quantum hardware 108, and / or processing system 112 may perform one or more of the operations associated with Method 600. Although shown in discrete blocks, the steps and operations associated with one or more of the blocks of Method 600 may be divided into additional blocks, combined into fewer blocks, or deleted, depending on the particular implementation.

[0075] Method 600 can begin in block 602, and the quantum circuit can be generated based on a quantum application. Quantum applications can be developed, among other things, to solve real-world problems such as optimization problems in financial portfolio management or logistics. Quantum applications can be developed using quantum algorithms, such as Quantum Approximate Optimization Algorithms (QAOA), to find approximate solutions to optimization problems. A quantum programming framework can be used to define the number of qubits, the type and number of quantum gates, and the circuit structure in order to generate quantum circuits such as quantum circuits 110, 300, and 500 shown in Figures 1, 3, and 5A, respectively. The quantum application can then be encoded into an initial quantum circuit by mapping classical data of the problem (e.g., risk factors) to quantum states. This can be done through amplitude encoding or basis encoding. The quantum circuit can then be constructed by implementing a quantum algorithm and selecting appropriate quantum gates to perform the necessary transformations on the qubits. The quantum circuit can be generated based on the quantum application or the hardware layout of the quantum application.

[0076] In block 604, a neural network representation of the quantum circuit can be formed. Based on the configuration of the quantum circuit generated in block 602, including the number of qubits, the type of quantum gate (single-qubit gate or two-qubit controlled gate), and the position of the quantum gate, the processing system 112 can form a neural network representation of the quantum gate using the embodiments presented in this disclosure. The quantum gate, whether single-qubit or two-qubit, can be represented by equation (1), where u 11 u 12 u 21 u 22represents the parameters of single qubit quantum gates. For example, the neural network representation for a single qubit gate may be shown in FIG. 4A, the two qubit controlled gate with i < j may be shown in FIG. 4B, and the two qubit controlled gate with i > j may be shown in FIG. 4C. Based on these representations, a neural network such as neural network 510 may be constructed using layers corresponding to the number of quantum gates in the quantum circuit and the number of nodes in a layer corresponding to the number of qubits. The connections between nodes are associated with weight parameters such as u 11 , u 12 , u 21 , u 22 or 1, and as shown in FIG. 5B, may be defined by the neural network representation of the quantum gate that represents the parameters of the quantum gate.

[0077] In block 606, the neural network representing the quantum circuit can be trained and evaluated using machine learning techniques. The weight parameters of the neural network, such as u 11 , u 12 , u 21 , u 22 may be initialized with initial values that may be zero or randomly generated, and these parameters may be optimized during training. The training of the neural network can be performed by processing system 112. To train the neural network, a set of training data representing input-output pairs of the quantum circuit can be used. The input data may correspond to classical data encoded in a quantum state, and the output data may correspond to the result of the quantum circuit after application of the quantum gate. The neural network may be trained using machine learning techniques such as backpropagation and gradient descent, and the loss function quantifies the difference between the predicted output of the neural network and the actual quantum circuit output.

[0078] During the training process, the parameters of the neural network may be iteratively adjusted to minimize loss, which improves the accuracy of the network representation of the quantum circuits. The performance of the neural network can be evaluated by testing it on a separate validation dataset that was not seen during training. This validation dataset may contain data from real-world problems and can be used to determine whether the neural network representation can solve real-world problems.

[0079] In block 608, the trained neural network representation can be converted back into a quantum circuit. The trained neural network from block 606, including the trained weight parameters of the quantum gate through machine learning techniques, can be used to construct a new quantum circuit or to tune an existing quantum circuit 110. If the output of the trained neural network from block 606 indicates that a real-world problem can be solved, the neural network representation can be converted back into a quantum circuit 110 in the quantum computing system 100 for further operation and training. To convert the neural network representation into a quantum circuit, the learned weight parameters from the neural network, for example u 11 u 12 u 21 u 22 This can be mapped to the parameters of quantum gates in quantum circuit 110, which may include rotations, phase shifts, or other gate-specific transformations. The quantum circuit can be constructed by sequentially applying quantum gates in an appropriate order based on parameters learned from the neural network. If the output of the trained neural network indicates that the real-world problem cannot be solved, a new quantum circuit may be generated in block 602, and this process may be iterated to identify quantum circuits that may be suitable for solving the real-world problem. This process ensures the discovery of a suitable quantum circuit without unnecessary consumption of quantum resources.

[0080] Method 600 may be modified, added to, or omitted without departing from the scope of this disclosure. Furthermore, Method 600 may include any number of other elements or may be implemented in a system or context other than those described.

[0081] Figure 7 is a flowchart of an exemplary method 700 for training a quantum computing system using a linear neural network representation of a quantum circuit, according to one or more embodiments of the present disclosure. Method 700 can be performed by any suitable system, apparatus, or device. For example, a quantum computing system 100, quantum hardware 108, and / or processing system 112 may perform one or more of the operations related to Method 700. Although shown in discrete blocks, the steps and operations related to one or more of the blocks of Method 700 may be divided into additional blocks, combined into fewer blocks, or deleted, depending on the particular implementation.

[0082] Method 700 provides a specific example of a quantum application generating a probability distribution for solving a real-world problem. Quantum circuits and algorithms may be used to estimate the output of the quantum application, which is often expressed as a probability distribution. A suitable quantum circuit may be selected to generate the desired probability distribution.

[0083] Method 700 may begin in block 702, where an initial and target distribution for a quantum application may be obtained. The initial distribution represents the initial state of a quantum circuit, which may be described by a set of quantum gates encoding a probability distribution of a set of input data for a real-world problem, such as the probability distribution of the value of a particular stock. The target distribution represents the desired probability distribution for a given quantum application, which may be defined by a real-world problem to be solved, such as an optimization problem. The target distribution may be obtained from empirical data and provide an objective that the quantum application aims to achieve, such as a desired percentage of ownership of a particular stock in a financial portfolio.

[0084] In block 704, a quantum circuit may be generated based on a quantum application, and a neural network representation of the quantum circuit may be formed. Block 704 may be executed by processing system 112, which may be consistent with the processes described in blocks 602 and 604 of Figure 6. The quantum application may be formed using a quantum algorithm. Quantum circuits such as quantum circuits 110, 300, and 500 shown in Figures 1, 3, and 5A may be generated based on a quantum algorithm by selecting and arranging quantum gates in an appropriate sequence. A neural network may then be generated to approximate the behavior of the quantum circuit. As previously mentioned, the layers of the neural network correspond to quantum gates. The network parameters are initialized to reflect the structure of the quantum circuit. In one embodiment, the neural network representation may be implemented using the neural network 510 shown in Figure 5B.

[0085] In block 706, a decision may be made as to whether the neural network representation can generate a target distribution. Block 706 may be performed by the processing system 112. Input data having an initial distribution may be applied to a neural network representing a quantum circuit. The neural network then processes the input data, and a probability distribution from the output data may be obtained. This output distribution is compared to a target distribution that defines the desired outcome for the quantum application. In some embodiments, the decision may also include calculating an upper bound on the output probability distribution, which may serve as a metric for evaluating how close the output distribution is to the target distribution. The upper bound may be calculated as the maximum achievable similarity or closeness between the output distribution and the target distribution, which may be formulated using a statistical measure such as the total variation distance. Additionally or alternatively, the decision may also include calculating a loss function for the neural network representation. The loss function quantifies the difference between the output distribution and the target distribution. The loss function can be calculated using methods such as Kullback-Leibler (KL) divergence or mean squared error (MSE), which quantify the difference between the output distribution and the target distribution. Numerical optimization techniques, such as gradient descent, may be applied to minimize the loss function.

[0086] A calculated upper bound or loss function exceeding a threshold may indicate that the neural network representation may not produce the target distribution. The threshold may be determined based on a particular quantum application and an acceptable level of accuracy. For example, the threshold may be determined by analyzing the performance of the neural network across a set of training or test data to identify the point where the output distribution adequately approximates the target distribution. Alternatively, the threshold may be determined based on the expected error tolerance of the quantum circuit or from the statistical limits associated with the target distribution. If the threshold is exceeded, method 700 returns to block 704, where a new quantum circuit may be generated that may reduce the upper bound of the output distribution or loss function, and a corresponding neural network representation may be formed according to the process described in block 704. For example, a new quantum gate may be added, or the parameters of an existing quantum gate may be modified or removed in the previous quantum circuit 110. On the other hand, if the upper bound or loss function is within the threshold and indicates that the neural network representation can produce the target distribution, method 700 proceeds to block 708.

[0087] In block 708, the neural network capable of generating the target distribution may be trained using a learning technique. Supervised learning may be employed, in which the network may be trained using labeled input-output pairs, and the loss function may be minimized to align the output distribution with the target distribution. Unsupervised learning techniques, such as variational autoencoders, may also be used to uncover underlying patterns in the data without requiring labeled outputs. These training techniques align the output distribution with the target distribution by minimizing the weight parameters u 11 u 12 u 21 u 22The parameters of a neural network like this can be refined. Since the output of a quantum process is inherently probabilistic, sufficient sampling is important to ensure that the process produces the desired result. For a quantum circuit with n qubits, at least 2 are needed to define the target distribution. n It may be necessary to sample n data points. For example, in the case of quantum circuit 500 where n=4, a minimum of 16 data points may be sampled. In some embodiments, at least 2 n Multiple samples, each containing a sampled data point, may be used to train and test a neural network to ensure that the quantum circuit representation produces the desired result.

[0088] In block 710, the parameters of the quantum circuit can be generated as the training output. The output of the trained neural network is the weight parameter u 11 u 12 u 21 u 22 These may include learned parameters such as those shown above. These can be mapped to the parameters of quantum gates in the quantum circuit 110. Based on these parameters, new quantum circuits may be constructed, or existing quantum circuits 110 may be tuned in the quantum computing system 100 for further operation and testing.

[0089] Based on the above, Method 700 is not restricted to any particular probability distribution. The present invention can be applied to quantum applications involving a wide range of distributions, such as the normal distribution or the copula distribution. Therefore, Method 700 is a more generalized solution for solving real-world problems.

[0090] Method 700 may be modified, added to, or omitted without departing from the scope of this disclosure. Furthermore, Method 700 may include any number of other elements or may be implemented in a system or context other than those described.

[0091] The foregoing disclosure is not intended to limit this disclosure to the exact form or specific field of use disclosed. Therefore, various alternative embodiments and / or modifications to this disclosure are possible in light of this disclosure, whether expressly described or implied herein. While embodiments of this disclosure have been described in this manner, it should be recognized that modifications in form and detail may be made without departing from the scope of this disclosure. Therefore, this disclosure is limited solely by the claims.

[0092] In some embodiments, the different components, modules, engines, and services described herein may be implemented as objects or processes (for example, as separate threads) running on a computing system. While some of the systems and methods described herein are generally described as being implemented in software (stored in and / or run by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0093] In accordance with common practice, various features shown in the drawings may not be drawn to scale. The examples presented in this disclosure are not intended to be actual drawings of any particular apparatus (e.g., a device, system, etc.) or method, but are merely idealized representations used to illustrate various embodiments of this disclosure. Accordingly, the dimensions of various features may be enlarged or reduced as appropriate for clarity. In addition, some drawings may be simplified for clarity. Accordingly, the drawings may not show all components of a given apparatus (e.g., a device) or all operations of a particular method.

[0094] The terms used herein, and in particular in the appended claims (for example, in the body of the appended claims), are generally intended to be “open” terms (for example, the term “includes” should be interpreted as “includes but not limited to,” the term “has” should be interpreted as “has at least…,” and the term “contains” should be interpreted as “includes but not limited to,” etc.).

[0095] Furthermore, if a specific number of claims to be introduced is intended, such intention is explicitly stated in the claim; if no such statement is present, such intention does not exist. For example, to aid understanding, the claims attached below may include the use of the introductory phrases “at least one” and “one or more” to introduce a claim. However, the use of such phrases should not be interpreted as implying that the introduction of a claim by the indefinite article “a” or “an” limits any particular claim containing such introduced claim to embodiments containing only one such claim, and this is also true if the same claim includes the introductory phrase “one or more” or “at least one” and an indefinite article such as “a” or “an.” (For example, “a” and / or “an” should be interpreted as meaning “at least one” or “one or more.”) The same applies to the use of the definite article used to introduce a claim.

[0096] Furthermore, even if a specific number is explicitly stated in an introduced claim, it should be understood that such a statement should be interpreted as meaning at least that number (for example, the statement “two statements” without other modifiers means at least two statements, or two or more statements). Furthermore, when idiomatic expressions similar to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” are used, such constructions are generally intended to include A only, B only, C only, both A and B, both A and C, both B and C, or all of A, B, and C, etc. For example, the use of the term “and / or” is intended to be interpreted in this way.

[0097] Furthermore, any disjunctive phrase that presents two or more alternative terms should be understood in this paper, the claims, or the drawings as considering the possibility of including one of those terms, either of those terms, or both of those terms. For example, the phrase "A or B" should be understood as including the possibilities of "A" or "B" or "A and B".

[0098] Furthermore, the use of terms such as “first,” “second,” and “third” is not necessarily used in this specification to imply a particular order or number of elements. Generally, terms such as “first,” “second,” and “third” are used as general identifiers to distinguish different elements. Where there is no indication that terms such as “first,” “second,” and “third” mean a particular order, these terms should not be understood to mean a particular order. Furthermore, where there is no indication that terms such as “first,” “second,” and “third” mean a particular number of elements, these terms should not be understood to mean a particular number of elements. For example, a first widget may be described as having a first face, and a second widget may be described as having a second face. The use of the term “second face” in relation to a second widget may be to distinguish such a face of the second widget from the “first face” of the first widget, and does not imply that the second widget has two sides.

[0099] All examples and conditional statements described herein are intended for educational purposes to help readers understand the present invention and the concepts to which the inventors have contributed to advance the art, and should be construed as not being limited to such specifically described examples and conditions. While embodiments of this disclosure have been described in detail, it should be understood that various changes, substitutions, and modifications can be made to this disclosure without departing from the spirit and scope of this disclosure.

[0100] With regard to embodiments including the above examples, the following additional information is disclosed. (Note 1) A step of obtaining the configuration of a quantum circuit comprising n qubits and k quantum gates, wherein the k quantum gates include at least one of a single qubit gate or a two-qubit controlled gate; A step of constructing a neural network representing the quantum circuit, wherein the neural network comprises k+1 layers, each containing k pairs of adjacent layers, and each pair of adjacent layers corresponds to one of the k quantum gates; The steps include connecting one or more nodes in each pair of adjacent layers based on the corresponding quantum gate representation among the k quantum gates; The steps include: training the neural network using machine learning techniques to obtain an output; The steps of applying the output to the quantum circuit and A method that includes this. (Note 2) Each of the k+1 layers is 2 n The quantum circuit includes n nodes, the single qubit gate rests on the j-th qubit of the quantum circuit, and the pair of adjacent layers corresponding to the single qubit gate includes a first connection block, the first connection block is: 2 is part of the first layer of the pair of adjacent layers n-j+1 A first partition containing 1 node; Part of the second layer of the pair of adjacent layers 2 n-j+1 A second partition containing a number of nodes, wherein the second layer is a subsequent layer to the first layer; The 2 in the first partition n-j+1 The first half of the number of nodes is 2 n-j The first group of nodes and the second partition of the 2 n-j+1 The second half of the first half of the node n-j A first subblock containing a group of nodes; The 2 in the first partition n-j+1 The second half of the number of nodes is 2 n-j The third group of nodes and the second partition n-j+1 The second half of the node is 2 n-j A second subblock containing a fourth group of nodes and Includes, 2 n-j the nodes in each of the first, second, third, and fourth groups of the two nodes are sequentially labeled based on the vertical position of the node The method according to Appendix 1 (Appendix 3) 2 n-j Connect the nodes in the first group of the two nodes to the nodes with the same label in the second and fourth groups of the two nodes n-j ; 2 n-j Connect the nodes in the third group of the two nodes to the nodes with the same label in the second and fourth groups of the two nodes n-j ; The method according to Appendix 2, further comprising (Appendix 4) The target qubit of the two-qubit control gate is on the j-th qubit, the control qubit of the two-qubit control gate is on the i-th qubit, i < j, and the pair of adjacent layers corresponding to the two-qubit control gate includes a second connection block, and the second connection block is: 2 i-1 including two block pairs, each block pair including an identity matrix of order 2 n-i and a ^U i<j block, and the ^U i<j block includes the first connection block repeated twice n-j-1 ; The method according to Appendix 2 (Appendix 5) The single-qubit gate is represented by the symbolic unitary matrix [Number] and the method further comprises: 2 n-j Apply u n-j as the weight parameter when connecting the nodes in the first group of the two nodes to the nodes with the same label in the second group of the two nodes 11 ; 2 n-j The nodes in the third group of nodes are divided into two n-j When connecting a node to a node with the same label in the fourth group described above, the weight parameter is u 22 Apply; 2 n-j The nodes in the third group of nodes are divided into two n-j When connecting a node to a node with the same label in the second group described above, the weight parameter is u. 12 Apply; 2 n-j The nodes in the first group of nodes are divided into two groups. n-j When connecting a node to a node with the same label in the fourth group described above, the weight parameter is u 21 Apply The method described in Appendix 3, including the above. (Note 6) The quantum circuit is generated based on a quantum application, according to the method described in Appendix 1. (Note 7) The steps include obtaining the initial and target distributions of the quantum application; The steps include determining whether the neural network representing the quantum circuit can generate the target distribution; The steps include training the neural network in accordance with the determination that the neural network is capable of generating the target distribution, and The method described in Appendix 6, further including the method described in Appendix 6. (Note 8) Determining whether the neural network representing the quantum circuit can generate the target distribution: The upper limit of the output probability distribution of the neural network is calculated; This includes determining that the neural network can generate the target distribution when the upper limit is within a threshold, The method described in Appendix 7. (Note 9) The method according to Appendix 7, further comprising the step of generating the parameters of the quantum circuit as an output. (Note 10) The method according to Appendix 1, wherein the output of the trained neural network is the learned parameters of the neural network. (Note 11) A system having a quantum computing system, wherein the quantum computing system is: Quantum hardware including quantum circuits, and It has a processing system, and the processing system is: A step of obtaining the configuration of a quantum circuit comprising n qubits and k quantum gates, wherein the k quantum gates include at least one of a single qubit gate or a two-qubit controlled gate; A step of constructing a neural network representing the quantum circuit, wherein the neural network comprises k+1 layers, each containing k pairs of adjacent layers, and each pair of adjacent layers corresponds to one of the k quantum gates; The steps include connecting one or more nodes in each pair of adjacent layers based on the corresponding quantum gate representation among the k quantum gates; The steps include: training the neural network using machine learning techniques to obtain an output; The steps of applying the output to the quantum circuit and A system configured to perform the following actions. (Note 12) Each of the k+1 layers is 2 n The quantum circuit includes n nodes, the single qubit gate rests on the j-th qubit of the quantum circuit, and the pair of adjacent layers corresponding to the single qubit gate includes a first connection block, the first connection block is: 2 is part of the first layer of the pair of adjacent layers n-j+1 A first partition containing 1 node; Part of the second layer of the pair of adjacent layers 2n-j+1 A second partition containing a number of nodes, wherein the second layer is a subsequent layer to the first layer; The 2 in the first partition n-j+1 The first half of the number of nodes is 2 n-j The first group of nodes and the second partition of the 2 n-j+1 The second half of the first half of the node n-j A first subblock containing a group of nodes; The 2 in the first partition n-j+1 The second half of the node is 2 n-j The third group of nodes and the second partition n-j+1 The second half of the node is 2 n-j A second subblock containing a fourth group of nodes and Includes, 2 n-j The nodes in each of the first, second, third, and fourth groups of the individual nodes are sequentially labeled based on the vertical position of the node. The system described in Appendix 11. (Note 13) The aforementioned processing system further: 2 n-j The nodes in the first group of nodes are divided into two groups. n-j Connect the nodes of the same label in the second and fourth groups of the nodes; 2 n-j The nodes in the third group of nodes are divided into two n-j Connect the nodes of the same label in the second and fourth groups of the aforementioned nodes. The system described in Appendix 12 is configured as follows. (Note 14) The target qubit of the two-qubit control gate is on the j-th qubit, the control qubit of the two-qubit control gate is on the i-th qubit, i < j, and the pair in the adjacent layer corresponding to the two-qubit control gate includes a second connection block, and the second connection block is: 2 i-1 including block pairs, and each block pair includes an identity matrix of order 2 n-i and ^U i<j blocks, and the ^U i<j block includes the first connection block repeated 2 n-j-1 times. The system according to Appendix 12. (Appendix 15) The single-qubit gate is represented by a symbolic unitary matrix

Number

[0101] 100 Quantum Computing Systems 102 Parameter values 104 datasets 106 Gate Set Ansatz 108 Quantum Hardware 110 Quantum circuit 112 Processing System 200 Computing Systems 202 processors 204 memory 206 Data Storage 208 Communication Unit 602 Generating quantum circuits based on quantum applications 604 Forming a neural network representation of quantum circuits 606 Training and Evaluating Neural Networks Using Classical Deep Learning Techniques 608 Converting the trained neural network representation into a quantum circuit. 702 Obtaining initial and target distributions for quantum applications 704 Generate quantum circuits based on quantum applications and form neural network representations of quantum circuits. 706 Determine whether the neural network representation can generate the target distribution. 708 Training a neural network 710 Generates the parameters of the quantum circuit as the output.

Claims

1. A step of obtaining the configuration of a quantum circuit comprising n qubits and k quantum gates, wherein the k quantum gates include at least one of a single-qubit gate or a two-qubit controlled gate; A step of constructing a neural network representing the quantum circuit, wherein the neural network comprises k+1 layers, each containing k pairs of adjacent layers, and each pair of adjacent layers corresponds to one of the k quantum gates; The steps include: connecting one or more nodes in each pair of adjacent layers based on the corresponding quantum gate representation among the k quantum gates; The steps include: training the neural network using machine learning techniques to obtain an output; The steps of applying the output to the quantum circuit and A method that includes this.

2. Each of the k+1 layers is 2 n The quantum circuit includes n nodes, the single qubit gate rests on the j-th qubit of the quantum circuit, and the pair of adjacent layers corresponding to the single qubit gate includes a first connection block, the first connection block is: 2 is part of the first layer of the pair of adjacent layers n-j+1 A first partition containing 1 node; Part of the second layer of the pair of adjacent layers 2 n-j+1 A second partition containing a number of nodes, wherein the second layer is a subsequent layer to the first layer; The 2 in the first partition n-j+1 The first half of the number of nodes is 2 n-j The first group of nodes and the second partition of the 2 n-j+1 The second of the first half of the number of nodes n-j A first subblock containing a group of nodes; The second half of the two n-j+1 nodes in the first partition, the two n-j nodes in the third group and the two n-j+1 nodes in the second half of the second partition, the two n-j nodes in the fourth group, to form a second sub-block Includes, 2 n-j The nodes in each of the first, second, third, and fourth groups of the individual nodes are sequentially labeled based on the vertical position of the node. The method according to claim 1.

3. 2 n-j The nodes in the first group of nodes are divided into two groups. n-j Connect the nodes of the same label in the aforementioned second and fourth groups of nodes; 2 n-j The nodes in the third group of nodes are divided into two n-j Connect the nodes of the same label in the second and fourth groups of the aforementioned nodes. The method according to claim 2, further comprising the following:

4. The target qubit of the two-qubit control gate lies on the j-th qubit, the control qubit of the two-qubit control gate lies on the i-th qubit, i < j, and the pair of adjacent layers corresponding to the two-qubit control gate includes a second connection block, the second connection block is: 2 i-1 It includes block pairs, and each block pair has 2 floors. n-i The identity matrix of and ^U i<j Includes the block and the ^U i<j The block connects the aforementioned first connection block to the second n-j-1 Including those that have been repeated multiple times, The method according to claim 2.

5. The aforementioned single qubit gate is a symbolic unitary matrix [Math 1] This is expressed by, and the method further: 2 n-j The nodes in the first group of nodes are divided into two groups. n-j When connecting a node to a node with the same label in the second group described above, the weight parameter is u. 11 Apply; 2 n-j The nodes in the third group of nodes are divided into two n-j When connecting a node to a node with the same label in the fourth group described above, the weight parameter is u 22 Apply; 2 n-j The nodes in the third group of nodes are divided into two n-j When connecting a node to a node with the same label in the second group described above, the weight parameter is u. 12 Apply; 2 n-j The nodes in the first group of nodes are divided into two groups. n-j When connecting a node to a node with the same label in the fourth group described above, the weight parameter is u 21 Apply The method according to claim 3, including the following:

6. The method according to claim 1, wherein the quantum circuit is generated based on a quantum application.

7. The steps include: obtaining the initial and target distributions of the quantum application; The steps include determining whether the neural network representing the quantum circuit can generate the target distribution; The steps include training the neural network in accordance with the determination that the neural network is capable of generating the target distribution, and The method according to claim 6, further comprising:

8. Determining whether the neural network representing the quantum circuit can generate the target distribution is: The upper limit of the output probability distribution of the neural network is calculated; This includes determining that the neural network can generate the target distribution when the upper limit is within a threshold, The method according to claim 7.

9. The method according to claim 7, further comprising the step of generating the parameters of the quantum circuit as an output.

10. The method according to claim 1, wherein the output of the trained neural network is the learned parameters of the neural network.

11. A system having a quantum computing system, wherein the quantum computing system is: Quantum hardware including quantum circuits, and It has a processing system, and the processing system is: A step of obtaining the configuration of a quantum circuit comprising n qubits and k quantum gates, wherein the k quantum gates include at least one of a single-qubit gate or a two-qubit controlled gate; A step of constructing a neural network representing the quantum circuit, wherein the neural network comprises k+1 layers, each containing k pairs of adjacent layers, and each pair of adjacent layers corresponds to one of the k quantum gates; The steps include: connecting one or more nodes in each pair of adjacent layers based on the corresponding quantum gate representation among the k quantum gates; The steps include: training the neural network using machine learning techniques to obtain an output; The steps of applying the output to the quantum circuit and A system configured to perform the following actions.

12. Each of the k+1 layers is 2 n The quantum circuit includes n nodes, the single qubit gate rests on the j-th qubit of the quantum circuit, and the pair of adjacent layers corresponding to the single qubit gate includes a first connection block, the first connection block is: 2 is part of the first layer of the pair of adjacent layers n-j+1 A first partition containing 1 node; Part of the second layer of the pair of adjacent layers 2 n-j+1 A second partition containing a number of nodes, wherein the second layer is a subsequent layer to the first layer; The 2 in the first partition n-j+1 The first half of the number of nodes is 2 n-j The first group of nodes and the second partition of the 2 n-j+1 The second of the first half of the number of nodes n-j A first subblock containing a group of nodes; The 2 in the first partition n-j+1 The second half of the number of nodes is 2 n-j The third group of nodes and the second partition n-j+1 The second half of the number of nodes is 2 n-j A second subblock containing a fourth group of nodes and Includes, 2 n-j The nodes in each of the first, second, third, and fourth groups of the individual nodes are sequentially labeled based on the vertical position of the node. The system according to claim 11.

13. The aforementioned processing system further: 2 n-j The nodes in the first group of nodes are divided into two groups. n-j Connect the nodes of the same label in the aforementioned second and fourth groups of nodes; 2 n-j The nodes in the third group of nodes are divided into two n-j Connect the nodes of the same label in the second and fourth groups of the aforementioned nodes. The system according to claim 12, configured as follows.

14. The target qubit of the two-qubit control gate lies on the j-th qubit, the control qubit of the two-qubit control gate lies on the i-th qubit, i < j, and the pair of adjacent layers corresponding to the two-qubit control gate includes a second connection block, the second connection block is: 2 i-1 It includes block pairs, and each block pair has 2 floors. n-i The identity matrix of and ^U i<j Includes the block and the ^U i<j The block connects the aforementioned first connection block to the second n-j-1 Including those that have been repeated multiple times, The system according to claim 12.

15. The aforementioned single qubit gate is a symbolic unitary matrix [Math 2] The processing system is expressed by: 2 n-j The nodes in the first group of nodes are divided into two groups. n-j When connecting a node to a node with the same label in the second group described above, the weight parameter is u. 11 Apply; 2 n-j The nodes in the third group of nodes are divided into two n-j When connecting a node to a node with the same label in the fourth group described above, the weight parameter is u 22 Apply; 2 n-j The nodes in the third group of nodes are divided into two n-j When connecting a node to a node with the same label in the second group described above, the weight parameter is u. 12 Apply; 2 n-j The nodes in the first group of nodes are divided into two groups. n-j When connecting a node to a node with the same label in the fourth group described above, the weight parameter is u 21 Apply The system according to claim 13, configured as described above.

16. The system according to claim 11, wherein the quantum circuit is generated based on a quantum application.

17. The aforementioned processing system further: The steps include: obtaining the initial and target distributions of the quantum application; The steps include determining whether the neural network representing the quantum circuit can generate the target distribution; The steps include training the neural network in accordance with the determination that the neural network is capable of generating the target distribution, and The system according to claim 16, configured to perform the following:

18. Determining whether the neural network representing the quantum circuit can generate the target distribution is: The upper limit of the output probability distribution of the neural network is calculated; This includes determining that the neural network can generate the target distribution when the upper limit is within a threshold, The system according to claim 17.

19. The system according to claim 17, wherein the processing system is further configured to generate the parameters of the quantum circuit as an output.

20. A non-temporary computer-readable medium configured to store instructions for performing an action when executed by a system, wherein the action is: A step of obtaining the configuration of a quantum circuit comprising n qubits and k quantum gates, wherein the k quantum gates include at least one of a single-qubit gate or a two-qubit controlled gate; A step of constructing a neural network representing the quantum circuit, wherein the neural network comprises k+1 layers, each containing k pairs of adjacent layers, and each pair of adjacent layers corresponds to one of the k quantum gates; The steps include: connecting one or more nodes in each pair of adjacent layers based on the corresponding quantum gate representation among the k quantum gates; The steps include: training the neural network using machine learning techniques to obtain an output; The steps of applying the output to the quantum circuit and Non-temporary computer-readable media, including [specific examples of such media].

Images