Interference cancellation circuit and method of operating interference cancellation circuit

Abstract

An interference cancellation circuit and an operation method of the interference cancellation circuit are provided. The interference cancellation circuit includes: an amplitude and phase calculator configured to receive one or more input signals and calculate an amplitude and a phase of the one or more input signals; a phase reconfiguration circuit configured to output an interference phase by reconfiguring a phase of the one or more input signals based on an interference model; and a weight estimator configured to estimate a weight of an interference signal based on the amplitude of the one or more input signals. The interference cancellation circuit is configured to output an interference signal based on an interference phase, a magnitude of the one or more input signals, and a weight. A phase of the kernel model associated with the interference model is different from a phase of the one or more input signals.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0139725, filed on October 14, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to interference cancellation circuits and methods of operating interference cancellation circuits, and more specifically, to interference cancellation circuits for eliminating self-interference of transmitted signals and methods of operating interference cancellation circuits. Background Technology

[0003] Wireless communication systems can employ various techniques to increase throughput. For example, they can utilize carrier aggregation (CA) to increase communication capacity by using multiple antennas, Evolved Universal Terrestrial Radio Access (E-UTRA), New Radio (NR), Dual Connectivity (EN-DC), Multiple-Input Multiple-Output (MIMO), and so on. With the adoption of these throughput-increasing techniques, the transmitting side can send highly complex signals, and the receiving side may need to process these highly complex signals.

[0004] Interference signals can hinder the receiving side from processing signals received through the antenna, and interference signals can be generated in various ways. For example, interference signals can include inter-cell interference (inter-cell interference is a signal received from an adjacent base station at the boundary of the serving base station), intra-cell interference (intra-cell interference corresponds to radio signals from other terminals within the coverage area of ​​the serving base station), channel interference, etc.

[0005] In addition to interference signals received via the antenna, there are also interference signals generated within the terminal by transmitted signals leaking into or coupling to the receiving path. In the case of self-interference signals generated within the terminal, the amplified transmitted signal is fed back as interference, which can significantly degrade receiver sensitivity. Therefore, there is a need for methods to more effectively eliminate self-interference signals generated within the terminal. Furthermore, when multiple transmitted signals are transmitted independently according to transmission techniques (such as CA, EN-DC, and MIMO), the transmission frequencies of the multiple transmitted signals may differ from each other, and interference caused by intermodulation between transmitted signals of different frequencies can occur additionally. Therefore, there is a need for methods to eliminate interference caused by intermodulation. Summary of the Invention

[0006] The embodiments provide an interference cancellation circuit and an operation method of the interference cancellation circuit, and more specifically, relate to an interference cancellation circuit for eliminating self-interference of transmitted signals and an operation method of the interference cancellation circuit.

[0007] According to one aspect of the disclosure, an interference cancellation circuit is provided, comprising: an amplitude and phase calculator configured to: receive one or more input signals and calculate the amplitude and phase of the one or more input signals; a phase reconfiguration circuit configured to: reconfigure the phase of the one or more input signals based on an interference model to output an interference phase; and a weight estimator configured to: estimate the weight of the interference signal based on the amplitude of the one or more input signals. The interference cancellation circuit is configured to output an interference signal based on the interference phase, the amplitude of the one or more input signals, and the weight. The phase of a kernel model associated with the interference model may differ from the phase of the one or more input signals.

[0008] According to another aspect of the disclosure, a method for operating an interference cancellation circuit is provided, the method comprising: receiving one or more input signals and calculating the amplitude and phase of each of the one or more input signals; generating an interference phase by reconfiguring the phases of the one or more input signals based on an interference model; estimating a weight of the interference signal based on the amplitudes of the one or more input signals; and outputting the interference signal based on the interference phase, the amplitudes of the one or more input signals, and the weights. The phase of a kernel model associated with the interference model may differ from the phase of the one or more input signals.

[0009] According to another aspect of the inventive concept, an interference cancellation circuit is provided, comprising a plurality of sub-interference cancellation circuits, each of which is configured to: receive one or more input signals corresponding to a memory order and output a sub-interference signal corresponding to the memory order. The plurality of sub-interference cancellation circuits include: an amplitude and phase calculator configured to: calculate the amplitude and phase of each of the one or more input signals; a phase reconfiguration circuit configured to: reconfigure the phases of each of the one or more input signals based on an interference model, and output an interference phase; a segment index selector configured to: select an index corresponding to the amplitude of the one or more input signals; and a weight selector configured to select a weight for the sub-interference signal based on the index. The interference cancellation circuit is configured to: generate an interference signal by summing all the sub-interference signals. The phase of the kernel model associated with the interference model may be different from the phase of the one or more input signals. Attached Figure Description

[0010] The above and / or other aspects will become clearer from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 This is a diagram illustrating an example of self-interference caused by transmitted signals.

[0012] Figure 2 This is a schematic diagram illustrating a wireless communication device according to an embodiment.

[0013] Figure 3 This is a block diagram of an interference cancellation circuit according to an embodiment.

[0014] Figure 4 This is a block diagram of an interference cancellation circuit that outputs an interference signal for an input signal according to an embodiment.

[0015] Figure 5 This is a table showing the kernel phase function according to an interference model for an input signal, based on an embodiment.

[0016] Figure 6 This is a block diagram of an interference cancellation circuit that outputs interference signals for two input signals according to an embodiment.

[0017] Figure 7 This is a table showing the kernel phase function according to an interference model for two input signals, based on an embodiment.

[0018] Figure 8 This is a block diagram of an interference cancellation circuit that outputs an interference signal for an input signal according to an embodiment.

[0019] Figure 9 This is a block diagram of an interference cancellation circuit that outputs interference signals for two input signals according to an embodiment.

[0020] Figure 10A This is a table showing the H2 interference model, IMD3 interference model, and IMD3+IMD5 interference model.

[0021] Figure 10B This is a graph showing the performance of the interference cancellation circuit for the H2 interference model according to an embodiment.

[0022] Figure 10C This is a diagram illustrating the performance of an interference cancellation circuit for the IMD3 interference model according to an embodiment.

[0023] Figure 10D This is a diagram illustrating the performance of an interference cancellation circuit for an IMD3+IMD5 interference model according to an embodiment.

[0024] Figure 11This is a flowchart of the operation method of the interference cancellation circuit according to an embodiment.

[0025] Figure 12 This is a block diagram of a wireless communication device according to an embodiment. Detailed Implementation

[0026] In the following description, exemplary embodiments are illustrated with reference to the accompanying drawings.

[0027] Figure 1 This is a diagram illustrating an example of self-interference caused by transmitted signals.

[0028] Reference Figure 1 The wireless communication device 10 may include a transmit (TX) antenna and a receive (RX) antenna. A single antenna can be connected to both the transmit radio frequency (RF) chain and the receive RF chain via a duplexer. For example, the wireless communication device 10 can receive wireless signals via the receive RF chain in receive mode and transmit baseband signals to external devices via the transmit RF chain in transmit mode.

[0029] According to various embodiments, when the wireless communication device 10 includes transmit and receive antennas connected to each other via a duplexer, feedback based on the transmit signals from the adjacent transmit and receive antennas can occur. However, because the duplexer is connected to both the transmit and receive RF chains, at least a portion of the transmit signal from the transmit RF chain can leak into the receive RF chain. When the leaked signal is input into the receive RF chain, self-interference can occur.

[0030] According to various embodiments, the receiving antenna can receive wireless signals transmitted by the transmitting antenna as well as wireless signals transmitted by external devices. For example, when the transmitting and receiving antennas correspond to an omnidirectional antenna and are arranged adjacent to each other, a portion of the transmitted wireless signal can be fed back through the receiving antenna. Self-interference can also occur based on the fed-back wireless signal.

[0031] Figure 2 This is a schematic diagram illustrating a wireless communication device 10 according to an embodiment.

[0032] Reference Figure 2 It can transmit a first transmission signal TX1 and a second transmission signal TX2. That is, the wireless communication device 10 can be equipped with two antennas, which can be used for transmitting and receiving signals. The wireless communication device 10 can include various numbers of antennas and is not limited to them. Figure 2 Examples of implementations.

[0033] For example, the desired frequency band can be filtered from the first transmitted signal TX1 using a first transmit filter (e.g., attacker #1) 110, and the first transmitted signal TX1 can be converted from a digital signal to an analog signal using a first digital-to-analog converter (DAC) 111. Next, the transmission frequency of the first transmitted signal TX1 can be up-converted using the LO frequency received from the local oscillator (LO) by the first mixer 112. The first transmitted signal TX1 can be amplified using a first power amplifier (PA) 113, and then transmitted to an external device (e.g., a base station) via an antenna. Similarly, the desired frequency band can be filtered from the second transmitted signal TX2 using a second transmit filter (e.g., attacker #2) 120, and the second transmitted signal TX2 can be converted from a digital signal to an analog signal using a second DAC 121. Next, the transmission frequency of the second transmitted signal TX2 can be up-converted using the LO frequency received by the second mixer 122. The second transmitted signal TX2 can be amplified using a second PA 123, and then transmitted to an external device via an antenna.

[0034] According to various embodiments, the wireless communication device 10 can perform carrier aggregation or dual connectivity, and all of the first transmit filter 110, the second transmit filter 120, and the receive filter (e.g., victim #2) 210 can be turned on. In this case, when self-interference occurs, the first transmit signal TX1 amplified by the first PA 113 can be coupled to the adjacent receive RF chain. For example, the first transmit signal TX1 can be input as a receive signal to the low noise amplifier (LNA) 211 of the receive RF chain. The second transmit signal TX2 can be leaked from the transmit RF chain connected by the duplexer 124. That is, the second transmit signal TX2 can be input as a receive signal to the LNA 211 through the duplexer 124. Due to the nonlinear characteristics of the receive RF chain, the first transmit signal TX1 and the second transmit signal TX2 can generate interference signals close to the receive frequency. The first transmit signal TX1 and the second transmit signal TX2 can be down-converted by the LO frequency received by the third mixer 212 and converted into digital signals by the analog-to-digital converter (ADC) 213. Subsequently, the interference signals generated by the first transmitted signal TX1 and the second transmitted signal TX2 can be eliminated by the interference cancellation circuit 300. In one embodiment, similar to the received RF chain corresponding to the transmitted RF chain including the second transmitted filter 120, the received RF chain corresponding to the transmitted RF chain including the first transmitted filter 110 may include an RX filter (e.g., victim #1).

[0035] The interference cancellation circuit 300 may include a reference generator 310 and a weight estimator 320. The reference generator 310 may be a circuit configured to receive interfering signals (e.g., a first transmitted signal TX1 and a second transmitted signal TX2) and reproduce (or regenerate) an interference model. The reproduced interference model may include both active and passive interfering signals. The weight estimator 320 may estimate the coefficients of a reference generated by the reference generator 310. The weight estimator 320 can generate the interfering signal by estimating the coefficients of the reference (e.g., parameters and weights), and can filter the interfering signal by adding the interfering signal to the received signal or subtracting the interfering signal from the received signal. Regarding this functionality, the weight estimator 320 may be referred to as an adaptive filter.

[0036] For example, the weight estimator 320 may be based on one of the adaptive filter algorithms, such as the least mean square (LMS) algorithm using stochastic gradient descent, the recursive least squares (RLS) algorithm, and the bipartite coordinate descent (DCD)-RLS algorithm.

[0037] Figure 3 This is a block diagram of the interference cancellation circuit 300 according to an embodiment.

[0038] Figure 3 The interference cancellation circuit 300 can be used with Figure 2 The interference cancellation circuit 300 corresponds to this. (Refer to...) Figure 3 The interference cancellation circuit 300 includes a reference generator 310 and a weight estimator 320. The reference generator 310 includes an amplitude and phase calculator 311 and a phase reconfiguration circuit 312. The weight estimator 320 includes a segment index selector 321 and a weight selector 322. The weight estimator 320 may also include a multiplier. Figure 3 As shown in the diagram, the multiplier can be located outside the weight estimator 320.

[0039] The reference generator 310 can receive the input signal x(n). Figure 2 The input signal x(n) may include a first transmitted signal TX1 and a second transmitted signal TX2. Specifically, the amplitude and phase calculator 311 of the reference generator 310 can receive the input signal x(n) and calculate its phase and amplitude. A delayed signal (e.g., x(nm)) (where m is an integer) may be input to the reference generator 310 as an input signal. The amplitude and phase calculator 311 can calculate the amplitude and phase of the input signal x(n). The interference cancellation circuit 300 may also include a delay circuit, and the delay circuit can generate a delayed signal x(nm) by delaying the input signal x(n) in time by m. The amplitude and phase calculator 311 can calculate the phase and amplitude of the delayed signal x(nm).

[0040] The amplitude and phase calculator 311 sends the phase of the input signal x(n) to the phase reconfiguration circuit 312. The phase reconfiguration circuit 312 reconfigures (transforms) the phase of the input signal x(n) based on an interference model. Therefore, the interference cancellation circuit 300 can estimate the interference model based on an amplitude-selective affine (MSA) model while considering the phase changes of the interference due to intermodulation. For example, the phase reconfiguration circuit 312 can output the interference phase by reconfiguring the phase of the input signal x(n) to be the same as the phase of the kernel model. The kernel model can represent a linear combination model used for the interference model.

[0041] Amplitude and phase calculator 311 can send the amplitude of the input signal x(n) to weight estimator 320. The amplitude of the input signal x(n) can be input to segment index selector 321. Segment index selector 321 can select an index for weight selection based on the amplitude of the input signal x(n). Segment index selector 321 can send the selected index to weight selector 322. Weight selector 322 can select weights based on the selected index. Weights and coefficients can be used interchangeably. In other words, weights can be referred to as coefficients. According to an embodiment, weight selector 322 can calculate an affine function by using the selected weights and the amplitude of the input signal x(n). According to another embodiment, as in Figure 4 , Figure 6 , Figure 8 and Figure 9 As in the interference cancellation circuit, the affine function calculation can be performed outside the weight selector 322. (See reference...) Figure 3 The weight estimator 320 can generate the interference signal y(n) by multiplying the calculated affine function with the reconfigured phase.

[0042] The interference cancellation circuit 300 can filter the interference signal y(n) by adding the interference signal y(n) to the received signal or subtracting the interference signal y(n) from the received signal.

[0043] The interference cancellation circuit 300 according to an embodiment includes an amplitude and phase calculator 311, a phase reconfiguration circuit 312, and a weight estimator 320. The amplitude and phase calculator 311 receives one or more input signals and calculates the amplitude and phase of the one or more input signals. The phase reconfiguration circuit 312 outputs an interference phase by reconfiguring the phase of the one or more input signals based on an interference model. The weight estimator 320 estimates the weight of the interference signal based on the amplitude of the one or more input signals. The interference cancellation circuit 300 (e.g., a computation module included in the interference cancellation circuit 300) is configured to output an interference signal based on the interference phase, the amplitude of the one or more input signals, and the weight. The phase of the kernel model associated with the interference model may differ from the phase of the one or more input signals. For example, the interference model and the kernel model can be understood with reference to Table 1 below. In one embodiment, the computation module may include at least one adder (e.g., adders A1 and A2, or adders AA1 and AA2, as described below) and / or at least one multiplier (e.g., multipliers M1 and M2, or multipliers MM1, MM2, and MM3, as described below).

[0044] [Table 1]

[0045] According to an embodiment, the phase reconfiguration circuit 312 can output an interference phase by reconfiguring the phase of one or more input signals to be the same as the phase of the kernel model. Weights may correspond to multiple segments. The weight estimator 320 can select an index of a segment (e.g., one or more segments) from among the multiple segments that corresponds to the amplitude of one or more input signals, and can determine the weights corresponding to the segments corresponding to the amplitude of one or more input signals based on that index. When one or more input signals are a single input signal, the interference model may include at least one of second harmonic (e.g., a second harmonic interference model) and third harmonic (e.g., a third harmonic interference model). When the interference model is second harmonic, the phase reconfiguration circuit 312 can double a function of the phase of one or more input signals (see...). Figure 5 When the interference model is a third harmonic, the phase reconfiguration circuit 312 can amplify the phase of one or more input signals as a function up to three times (see [link]). Figure 5When one or more input signals include a first input signal and a second input signal, the interference model may include second-order intermodulation distortion (IMD2) (e.g., IMD2 interference model), third-order intermodulation distortion (IMD3) (e.g., IMD3 interference model), fourth-order intermodulation distortion (IMD4) (e.g., IMD4 interference model), and fifth-order intermodulation distortion (IMD5) (e.g., IMD5 interference model). The interference model may include a sub-interference model based on a combination of at least one of the first input signal, a conjugate signal of the first input signal, a second input signal, and a conjugate signal of the second input signal (see [link to relevant documentation]). Figure 7 The interference cancellation circuit 300 may also include multiple sub-interference cancellation circuits with different memory orders (or memory indices) (see [reference]). Figure 4 and Figure 6 Each of the plurality of sub-interference cancellation circuits may include at least one amplitude and phase calculator, a phase reconfiguration circuit, and a weight estimator, and may be configured to output a sub-interference signal corresponding to the memory order based on the interference phase, the amplitude of one or more input signals, and weights. Interference cancellation circuit 300 is configured to output an interference signal by summing all the sub-interference signals. Interference cancellation circuit 300 may be configured to delay one or more input signals by an amount corresponding to the memory order, and input the result of the delay as one or more input signals to the plurality of sub-interference cancellation circuits.

[0046] Figure 4 This is a block diagram of an interference cancellation circuit that outputs an interference signal for an input signal according to an embodiment.

[0047] In detail, Figure 4 An example of an interference cancellation circuit 300 associated with a single input signal (such as a second or third harmonic) acting as interference is shown. See also... Figures 1 to 3 To describe Figure 4 And will not be repeated here with reference to the above. Figures 1 to 3 The same description is given Figure 4 The description.

[0048] Reference Figure 4 The interference cancellation circuit 300 may include M sub-interference cancellation circuits 300_0 to 300_(M-1). M is a positive integer, and m represents the memory order. Each of the sub-interference cancellation circuits 300_0 to 300_(M-1) includes an amplitude and phase calculator, a phase reconfiguration circuit, a segment index selector, and a weight selector. For ease of explanation, the sub-interference cancellation circuit 300_0 when the memory order is 0 (m=0) will now be described, and the descriptions of the sub-interference cancellation circuits 300_1 to 300_(M-1) when the memory orders are 1 to (M-1) will be omitted.

[0049] The interference cancellation circuit 300 can receive an input signal x(n) and estimate the interference model generated by the input signal x(n). That is, the interference cancellation circuit 300 can also receive a single variable as an input signal x(n) and output an interference signal y(n) for that single variable.

[0050] The interference signal y(n) can be represented as in Equation 1 below, and the input signal x(n) can be represented as in Equation 2 below.

[0051] [Equation 1]

[0052] [Equation 2]

[0053] In Equations 1 and 2, y(n) indicates the interference signal (output signal). x(n) indicates the input signal. The threshold of the indicator segment. The total number of indicator segments. The index of the indicator segment. m is an integer. Each sub-interference cancellation circuit is indexed by m, therefore, m can be called a memory index. There are a total of M such circuits. In summary, there are M memory indices. x(nm) is the signal obtained by delaying the input signal x(n) by m in time. and Indicator weights (coefficients). Indicator kernel phase function. The amplitude of the input signal can be determined based on the variation of the interference model. To which the section belongs The segment index k. The coefficients can be switched based on k. and . The indication is that the phase of the input signal x(n) is modified to adapt to the phase function of the interference model. Because the interference model in Equation 1 is based on the amplitude-selective affine (MSA) interference model among the general approximators, the number of terms does not change even as the nonlinear order increases. Therefore, the interference cancellation circuit 300 operates like a general approximator, resulting in low complexity and low power consumption. Modeling with a general approximator is a method of dividing the nonlinear model into multiple segments and modeling these segments as linear functions. For example, modeling with a general approximator includes piecewise linear normalization (CPWL), decomposed vector rotation (DVR), and MSA. Although an interference cancellation circuit 300 based on an MSA model has been described, the embodiment is not limited thereto, and the interference model can be applied using the aforementioned general approximator. The operation of the interference cancellation circuit 300 will now be described in detail with reference to Equation 1.

[0054] The amplitude and phase calculator 311_0 of the sub-interference cancellation circuit 300_0 can receive the input signal x(n) and calculate the phase and amplitude of the input signal x(n). The interference cancellation circuit 300 may also include a delay circuit (D) 330. The delay circuit 330 can delay the input signal x(n) by m. The delay circuit 330 can send the input signal x(nm) obtained by delaying the input signal x(n) by m to the amplitude and phase calculator of the m-th sub-interference cancellation circuit 300_m. For example, the delay circuit 330 can send the delayed input signal x(n-1) (i.e., m=1) to the amplitude and phase calculator 311_1 of the sub-interference cancellation circuit 300_1.

[0055] The amplitude and phase calculator 311_0 calculates the amplitude and phase of the input signal x(nm) (where m=0). In the following description of the sub-interference cancellation circuit 300_0, m is 0. The amplitude and phase calculator 311_0 can calculate the phase of the input signal x(n). The signal is sent to the phase reconfiguration circuit 312_0. The phase reconfiguration circuit 312_0 can reconfigure (convert) the phase of the input signal x(n) based on the interference model, and output the phase (or interference phase) of the interference signal y(n). Therefore, the interference cancellation circuit 300 can consider the phase change of interference caused by intermodulation while estimating the interference model based on MSA.

[0056] Amplitude and Phase Calculator 311_0 can calculate the amplitude of the input signal x(n). Send to segment index selector 321_0 (where m=0). The amplitude of the input signal x(n) It can be input to segment index selector 321_0. Segment index selector 321_0 can be based on the amplitude of the input signal x(n). Select the weights. and The index k. The segment index selector 321_0 can input a segment threshold based on k. The segment index selector 321_0 can send the selected index k to the weight selector 322_0. The weight selector 322_0 can select weights based on the selected index k. and The sub-interference cancellation circuit 300_0 may further include multipliers M1 and M2, and adder A1. The sub-interference cancellation circuit 300_0 can be configured using selected weights. and and the amplitude of the input signal x(n) Calculate the affine function. The sub-interference cancellation circuit 300_0 can calculate the affine function. and the reconfigured phase Multiplying these signals generates a sub-interference signal. The interference cancellation circuit 300 may also include an adder A2. The interference cancellation circuit 300 outputs an interference signal y(n) by summing all the sub-interference signals output from sub-interference cancellation circuits 300_0 to 300_(M-1). (Refer to...) Figure 4 Multiplier M1 and adder A1 can be located outside of weight selector 322_0. However, multiplier M1 and adder A1 can be included in weight selector 322_0.

[0057] The interference cancellation circuit 300 can filter the interference signal y(n) by adding the interference signal y(n) to the received signal or subtracting the interference signal y(n) from the received signal.

[0058] Figure 5 This is a table showing the kernel phase function according to an interference model for an input signal, based on an embodiment.

[0059] Reference Figure 4 describe Figure 5 . Reference Figure 5 For the second harmonic interference model, the kernel phase function can be expressed as shown in Equation 3 below.

[0060] [Equation 3] For the third harmonic interference model, the kernel phase function can be expressed as shown in Equation 4 below.

[0061] [Equation 4] As shown above (refer to the reference) Figure 4 The described kernel phase function It is a phase function modified according to an interference model (e.g., second harmonic or third harmonic) using the phase of the input signal x(n). Therefore, the interference cancellation circuit 300 can model the interference signal in a system in which the phase of the interference signal is different from the phase of the input signal.

[0062] Figure 6 This is a block diagram of an interference cancellation circuit that outputs interference signals for two input signals according to an embodiment.

[0063] In detail, Figure 6 An example of an interference cancellation circuit 300 is shown in connection with a situation where two input signals act as interference (such as IMD2 or IMD3).

[0064] Reference Figure 6The interference cancellation circuit 300 may include M sub-interference cancellation circuits 300_0 to 300_(M-1). M is a positive integer, and m represents the memory order. Each of the sub-interference cancellation circuits 300_0 to 300_(M-1) includes an amplitude and phase calculator, a phase reconfiguration circuit, a segment index selector, and a weight selector. For ease of explanation, the sub-interference cancellation circuit 300_0 when the memory order is 0 (m=0) will now be described, and the descriptions of the sub-interference cancellation circuits 300_1 to 300_(M-1) when the memory orders are 1 to (M-1) will be omitted.

[0065] The interference cancellation circuit 300 can receive two input signals x1(n) and x2(n) and can estimate the interference model generated by the two input signals x1(n) and x2(n). That is, the interference cancellation circuit 300 can receive two input signals x1(n) and x2(n) and can output a two-variable interference signal y(n).

[0066] The interference signal y(n) and the two input signals x1(n) and x2(n) can be represented as shown in Equations 5 and 6 below.

[0067] [Equation 5]

[0068] [Equation 6]

[0069] In Equations 5 and 6, y(n) indicates the interference signal (output signal). x1(n) indicates the first input signal, and x2(n) indicates the second input signal. The segment threshold indicating the amplitude of the first input signal x1(n). The segment threshold indicates the amplitude of the second input signal x2(n). m indicates the memory order. K indicates the total number of segments of the first input signal x1(n). k indicates the segment index of the first input signal x1(n). L indicates the total number of segments of the second input signal x2(n). The total number of segments is K×L. l indicates the segment index of the second input signal x2(n). m is an integer, and , and Indicator weights (coefficients). Indicator kernel phase function. Kernel phase function The amplitude of the first input signal can be determined based on the variation of the interference model. To which the section belongs Amplitude of the second input signal To which the section belongs Based on k and l, the switchable coefficients are... , and . The phase function is appropriately modified for the interference model by using the phases of the first input signal x1(n) and the second input signal x2(n). Because the interference model in Equation 5 is based on the MSA model in the universal approximator, the number of terms does not change even when the nonlinear order increases. Therefore, the interference cancellation circuit 300 operates like a universal approximator, resulting in low complexity and low power consumption. The operation of the interference cancellation circuit 300 will now be described in detail with respect to Equation 5.

[0070] The amplitude and phase calculator 311_0 of the sub-interference cancellation circuit 300_0 can receive the first input signal x1(n) and calculate the phase and amplitude of the first input signal x1(n). The interference cancellation circuit 300 may also include a delay circuit 330. The delay circuit 330 can delay the first input signal x1(n) by m. The delay circuit 330 can send the first input signal x1(nm) obtained by delaying the first input signal x1(n) by m to the amplitude and phase calculator of the m-th sub-interference cancellation circuit 300_m. For example, the delay circuit 330 can send the delayed first input signal x1(n-1) (i.e., m=1) to the amplitude and phase calculator 311_1 of the sub-interference cancellation circuit 300_1.

[0071] The amplitude and phase calculator 311'_0 of the sub-interference cancellation circuit 300_0 can receive the second input signal x2(n) and calculate the phase and amplitude of the second input signal x2(n). The delay circuit 330 can delay the second input signal x2(n) by m. The delay circuit 330 can send the second input signal x2(nm) obtained by delaying the second input signal x2(n) by m to the amplitude and phase calculator of the m-th sub-interference cancellation circuit 300_m. For example, the delay circuit 330 can send the delayed second input signal x2(n-1) (i.e., m=1) to the amplitude and phase calculator 311'_1 of the sub-interference cancellation circuit 300_1.

[0072] The amplitude and phase calculator 311_0 calculates the amplitude and phase of the first input signal x1(nm) (where m=0). In the following description of the sub-interference cancellation circuit 300_0, m is 0. The amplitude and phase calculator 311_0 can calculate the phase of the first input signal x1(n). The signal is sent to the phase reconfiguration circuit 312_0. The amplitude and phase calculator 311'_0 calculates the amplitude and phase of the second input signal x2(nm). The amplitude and phase calculator 311'_0 can determine the phase of the second input signal x2(n). The signal is sent to the phase reconfiguration circuit 312_0. The phase reconfiguration circuit 312_0 can reconfigure (convert) the phases of the first input signal x1(n) and the second input signal x2(n) based on the interference model, and output the phase of the interference signal y(n). Therefore, the interference cancellation circuit 300 can estimate the interference model based on the MSA model while taking into account the phase changes of the interference caused by intermodulation.

[0073] Amplitude and phase calculator 311_0 can measure the amplitude of the first input signal x1(n). Send to segment index selector 321_0. The amplitude of the first input signal x1(n) This can be input to the segment index selector 321_0. The amplitude and phase calculator 311'_0 can calculate the amplitude of the second input signal x2(n). The amplitude of the second input signal x2(n) is sent to segment index selector 321_0. It can be input to segment index selector 321_0.

[0074] The segment index selector 321_0 can be based on the amplitude of the first input signal x1(n). The amplitude of the second input signal x2(n) Select the weights. , and The 2-D index (k, l). The segment index selector 321_0 can input a segment threshold. , The segment index selector 321_0 can send the selected 2-D index (k, l) to the weight selector 322_0. The weight selector 322_0 can select weights based on the selected 2-D index (k, l). , and The sub-interference cancellation circuit 300_0 may further include multipliers MM1, MM2, and MM3, and adder AA1. The sub-interference cancellation circuit 300_0 can be configured using selected weights. , and The amplitude of the first input signal x1(n) and the amplitude of the second input signal x2(n) Calculate the affine function. The sub-interference cancellation circuit 300_0 can use the calculated affine function... With the reconfigured phase Multiplying these signals generates a sub-interference signal. The interference cancellation circuit 300 may also include an adder AA2. The interference cancellation circuit 300 outputs an interference signal y(n) by summing all the sub-interference signals output from sub-interference cancellation circuits 300_0 to 300_(M-1). (Refer to...) Figure 6 Multipliers MM1 and MM2 and adder AA1 may be located outside of weight selector 322_0. However, multipliers MM1 and MM2 and adder AA1 may be included in weight selector 322_0.

[0075] The interference cancellation circuit 300 can filter the interference signal y(n) by adding the interference signal y(n) to the received signal or subtracting the interference signal y(n) from the received signal.

[0076] Figure 7 This is a table showing the kernel phase function according to an interference model for two input signals, based on an embodiment.

[0077] Reference Figure 6 right Figure 7 Provide a description. (Refer to...) Figure 7 The IMD2 interference model can be further subdivided into IMD2_1, IMD2_2, and IMD2_3. IMD2_1 can be an interference model associated with the product of the first input signal x1(n) and the second input signal x2(n). IMD2_2 can be a conjugate signal of the first input signal x1(n) and the second input signal x2(n). The interference model associated with the product of the two input signals. IMD2_3 can be the conjugate signal of the second input signal x2(n) and the first input signal x1(n). The IMD3 interference model is associated with the product of IMD2 and IMD3_1, IMD3_2, IMD3_3, and IMD3_4. The subdivision method is similar to that of IMD2, and redundant interpretations are omitted.

[0078] Although Figure 7 The term is omitted, but even in IMD4 or later versions, the interference model and kernel phase function can be used in conjunction with... Figure 7 The same method was used to create it. In certain cases, the IMD2 interference model can also be applied to interference models that are equal to or higher than IMD4.

[0079] As shown above (refer to the reference) Figure 6 The described kernel phase function It is a phase function modified according to an interference model (e.g., IMD2 or IMD3) using the phases of the input signals x1(n) and x2(n). Therefore, the interference cancellation circuit 300 can model the interference signal in a system in which the phase of the interference signal is different from the phase of the input signal.

[0080] Figure 8 This is a block diagram of an interference cancellation circuit that outputs an interference signal for an input signal according to an embodiment.

[0081] Reference Figure 4 right Figure 8 A description will be provided. The relationship with [other entities] will not be described here. Figure 4 The content is the same Figure 8 The content. (Refer to...) Figure 8 The interference signal y(n) can be represented as shown in Equation 7 below.

[0082] [Equation 7]

[0083] Unlike Equation 1, in Equation 7, the amplitude of the input signal can be used for all memory orders m. To determine the segment index k.

[0084] Reference Figure 8 The amplitude and phase calculator 311_0 can calculate the amplitude of the input signal. Send to segment index selector 321_0, and can send the amplitude of input signal. (m=0) is used as the input to multiplier M1. The amplitude and phase calculator 311_m of the sub-interference cancellation circuit 300_m can calculate the amplitude of the input signal. Send to segment index selector 321_m, and can send the amplitude of the input signal. As input to multiplier M1.

[0085] Although the sub-interference cancellation circuit 300_m is in Figure 8 Although not shown, it will be understood that sub-interference cancellation circuit 300_m represents the m-th sub-interference cancellation circuit 300_m among sub-interference cancellation circuits 300_0 to 300_(M-1). Although the amplitude and phase calculator 311_m is in Figure 8 Not shown, but it will be understood that amplitude and phase calculator 311_m represents the m-th amplitude and phase calculator 311_m among amplitude and phase calculators 311_0 to 311_(M-1).

[0086] Figure 9 This is a block diagram of an interference cancellation circuit that outputs interference signals for two input signals according to an embodiment.

[0087] Reference Figure 6 right Figure 9 A description will be provided. The relationship with [other entities] will not be described here. Figure 6 The content is the same Figure 9 The content. (Refer to...) Figure 9The interference signal y(n) can be represented as shown in Equation 8 below.

[0088] [Equation 8]

[0089] Unlike Equation 5, in Equation 8, the amplitude of the first input signal can be used for all memory orders m. Amplitude of the second input signal Determine the segment index (k, l).

[0090] Reference Figure 9 The amplitude and phase calculator 311_0 can measure the amplitude of the first input signal. Send to segment index selector 321_0, and can send the amplitude of input signal. (m=0) is used as the input to multiplier MM1. The amplitude and phase calculator 311'_0 can measure the amplitude of the second input signal. Send to segment index selector 321_0, and can send the amplitude of input signal. (m=0) is used as the input to the multiplier MM2.

[0091] The amplitude and phase calculator 311_m of the m-th sub-interference cancellation circuit 300_m can measure the amplitude of the first input signal. Send to segment index selector 321_m, and can send the amplitude of the input signal. As input to multiplier MM1, the amplitude and phase calculator 311'_m of the m-th sub-interference cancellation circuit 300_m can measure the amplitude of the second input signal. Send to segment index selector 321_m, and can send the amplitude of the input signal. As input to multiplier MM2.

[0092] Although the sub-interference cancellation circuit 300_m is in Figure 9 Although not shown, it will be understood that sub-interference cancellation circuit 300_m represents the m-th sub-interference cancellation circuit 300_m among sub-interference cancellation circuits 300_0 to 300_(M-1). Although amplitude and phase calculators 311_m and 311'_m are in Figure 9 Not shown, but will be understood, amplitude and phase calculator 311_m represents the m-th amplitude and phase calculator 311_m among amplitude and phase calculators 311_0 to 311_(M-1), and amplitude and phase calculator 311'_m represents the m-th amplitude and phase calculator 311'_m among amplitude and phase calculators 311'_0 to 311'_(M-1).

[0093] According to another embodiment, the interference signal y(n) can be represented as shown in Equation 9 below.

[0094] [Equation 9]

[0095] As in Equation 9, when time alignment of the first input signal x1(n) and the second input signal x2(n) is not performed, the delay time d between the first input signal x1(n) and the second input signal x2(n) can be compensated in the second input signal x2(n). In Equation 9, as in Equation 8, the delay time d between the first input signal and the second input signal x2(n) can be compensated for for all memory orders m, based on the amplitude of the first input signal. Amplitude of the second input signal To determine the segment index (k, l). In Equation 9, It is the first input signal to the sub-interference cancellation circuit corresponding to the memory order m. The second input signal is input to the sub-interference cancellation circuit corresponding to the memory order m and compensated by d. The phase correction function between them.

[0096] Figure 10A The H2 interference model, IMD3 interference model, and IMD3+IMD5 interference model are shown. Figure 10B The performance of the interference cancellation circuit for the H2 interference model according to an embodiment is shown. Figure 10C The performance of the interference cancellation circuit for the IMD3 interference model according to an embodiment is shown, and Figure 10D The performance of the interference cancellation circuit for the IMD3+IMD5 interference model according to an embodiment is shown.

[0097] Now, referring to the above description... Figures 10A to 10D . Figure 10A Showing the basis and Figures 10B to 10D The interference models correspond to the respective interference types in each case. H2 can represent the second harmonic. That is, in order to verify the modeling performance of the interference cancellation circuit according to the embodiment, it is assumed that... Figure 10A The interference model shown is added to the received signal and can be verified. Figures 10B to 10D The performance of the interference cancellation circuit according to the embodiment is checked by measuring the uncoded bit error rate (BER) of each of the interference models.

[0098] Reference Figures 10B to 10DNO ITF indicates the absence of interference. NO TSIC indicates the absence of interference cancellation circuitry (i.e., interference cancellation is not performed). MP+LS indicates the case where interference is eliminated by interference cancellation circuitry based on the memory polynomial (MP) method and the least squares (LS) method. MSA+LS indicates the case where interference has been removed by interference cancellation circuitry based on the MSA method and the LS method, and indicates the case where interference has been eliminated by interference cancellation circuitry according to the embodiment.

[0099] Reference Figure 10B For the H2 interference model, the interference cancellation circuit according to the embodiment exhibits the same performance as the MP+LS-based interference cancellation circuit and as when there is no interference (the respective lines of NO ITF, MP+LS and MSA+LS overlap each other).

[0100] Reference Figure 10C For the IMD3 interference model, the interference cancellation circuit according to the embodiment exhibits almost the same performance as the MP+LS-based interference cancellation circuit and as when there is no interference (the respective lines of NO ITF, MP+LS and MSA+LS overlap with each other).

[0101] Reference Figure 10D For the IMD3+IMD5 interference model, the interference cancellation circuit according to the embodiment exhibits almost the same performance as when there is no interference (the corresponding lines of NO ITF and MSA+LS overlap). For the IMD3+IMD5 interference model, it can be seen that the interference cancellation circuit according to the embodiment has better performance in terms of BER than the MP+LS-based interference cancellation circuit. Because the interference cancellation circuit according to the embodiment can perform interference model estimation for higher-order nonlinear models with the same phase, no performance degradation is observed.

[0102] The interference cancellation circuit according to the embodiment can operate like a general approximator and therefore has high performance for nonlinear distortions such as crest factor reduction (CFR) and ADC hard-limiting.

[0103] Figure 11 This is a flowchart of the operation method of the interference cancellation circuit according to an embodiment.

[0104] Reference Figure 11 In operation S101, the interference cancellation circuit can receive one or more input signals and can calculate the amplitude and phase of each of the one or more input signals.

[0105] In operation S103, the interference cancellation circuit can generate an interference phase by reconfiguring the phase of one or more input signals based on an interference model. The phase of the kernel model associated with the interference model may differ from the phase of one or more input signals.

[0106] According to an embodiment, the interference cancellation circuit can generate an interference phase by reconfiguring the phase of one or more input signals to be the same as the phase of the kernel model.

[0107] When one or more input signals are a single input signal, the interference model can include second and third harmonics. When the interference model includes second harmonics, the interference cancellation circuit can generate an interference phase by doubling the function of the phase of one or more input signals. When the interference model includes third harmonics, the interference cancellation circuit can generate an interference phase by tripling the function of the phase of one or more input signals.

[0108] When one or more input signals include a first input signal and a second input signal, the interference model may include IMD2, IMD3, IMD4, and IMD5. The interference model may include a sub-interference model based on a combination of at least one of the first input signal, a conjugate signal of the first input signal, a second input signal, and a conjugate signal of the second input signal.

[0109] The phase of the kernel model can be different from the phase of one or more input signals.

[0110] In operation S105, the interference cancellation circuit can estimate the weight of the interference signal based on the amplitude of one or more input signals. The weight may correspond to multiple segments. According to an embodiment, the interference cancellation circuit can select the index of the segment (e.g., one or more segments) that corresponds to the amplitude of one or more input signals from among the multiple segments. The interference cancellation circuit can determine the weight based on this index.

[0111] In operation S107, the interference cancellation circuit can output an interference signal based on the interference phase, the amplitude of one or more input signals, and their weights.

[0112] The interference cancellation circuit can perform operations S101, S103, S105, for each memory order, to calculate the amplitude and phase of one or more input signals, generate interference phases, and estimate weights.

[0113] The interference cancellation circuit can generate sub-interference signals for each memory order, based on the interference phase, the amplitude of one or more input signals, and weights. The interference cancellation circuit can generate the interference signal by summing all the sub-interference signals and can output the generated interference signal.

[0114] Figure 12This is a block diagram of a wireless communication device 400 according to an embodiment.

[0115] Figure 12 The wireless communication device 400 can communicate with Figure 2 The wireless communication device 10 corresponds to it, and its redundant description will be omitted.

[0116] Reference Figure 12 The wireless communication device 400 may include an application-specific integrated circuit (ASIC) 410, an application-specific instruction set processor (ASIP) 430, a memory 450, a main processor 470, and a main memory 490. At least two of the ASIC 410, ASIP 430, and main processor 470 may communicate with each other. At least two of the ASIC 410, ASIP 430, memory 450, radio frequency integrated circuit (RFIC) 460, main processor 470, and main memory 490 may be embedded in a single chip. For example, as described above, at least two of the ASIC 410, ASIP 430, memory 450, main processor 470, and main memory 490 may be included in a single model chip. The wireless communication device 400 may also include the components described above. Figures 1 to 11 The interference cancellation circuit is described.

[0117] ASIP 430 may be an integrated circuit customized for its intended use. ASIP 430 may support an instruction set specific to the application and may execute instructions included in that instruction set. Memory 450 may communicate with ASIP 430 and may store instructions executed by ASIP 430 as a non-transitory storage device. For example, as a non-limiting example, memory 450 may include any type of memory accessed by ASIP 430 (e.g., random access memory (RAM), read-only memory (ROM), magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof).

[0118] The main processor 470 can execute instructions for controlling the wireless communication device 400. For example, the main processor 470 can control the ASIC 410 and ASIP 430, and can process received data or process user input from the wireless communication device 400. The main memory 490 can communicate with the main processor 470 and can store the instructions executed by the main processor 470 as a non-transitory storage device. For example, as a non-limiting example, the main memory 490 can include any type of memory (e.g., RAM, ROM, magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof) accessible by the main processor 470.

[0119] Including based on the above reference Figures 1 to 11The wireless communication device and its operation method, which include the interference cancellation circuit of the described embodiments, can be implemented by including... Figure 12 The operation is performed by at least one of the components in the wireless communication device 400. According to some embodiments, at least one operation of the interference cancellation circuit operation method described above can be implemented as a plurality of instructions stored in the memory 450. According to some embodiments, the ASIP 430 can perform at least one operation of the above-described operation method by executing the plurality of instructions stored in the memory 450.

[0120] Various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. An interference cancellation circuit, comprising: An amplitude and phase calculator is configured to receive one or more input signals and calculate the amplitude and phase of each of the one or more input signals. The phase reconfiguration circuit is configured to output an interference phase by reconfiguring the respective phases of the one or more input signals based on an interference model. as well as The weight estimator is configured to estimate the weights of the interfering signals based on the respective amplitudes of the one or more input signals. The interference cancellation circuit further includes a calculation module configured to output an interference signal based on the interference phase, the respective amplitudes of the one or more input signals, and their weights. The phase of the kernel model associated with the interference model is different from the phase of each of the one or more input signals.

2. The interference cancellation circuit as described in claim 1, wherein, The phase reconfiguration circuit is configured to output an interference phase by reconfiguring the respective phases of the one or more input signals to be the same as the phase of the kernel model.

3. The interference cancellation circuit as described in claim 1, in, The weight estimator is configured to select the index of a segment from a plurality of segments that corresponds to the respective amplitude of the one or more input signals, and determine the weights based on the index.

4. The interference cancellation circuit according to any one of claims 1 to 3, wherein, Based on the fact that the one or more input signals are a single input signal, the interference model includes at least one of the second harmonic and the third harmonic.

5. The interference cancellation circuit as described in claim 4, wherein, The phase reconfiguration circuit is configured to double the phase of each of the one or more input signals as a function, based on the interference model being a second harmonic.

6. The interference cancellation circuit as described in claim 4, wherein, The phase reconfiguration circuit is configured to increase the phase of each of the one or more input signals by a factor of three, based on the interference model being a third harmonic.

7. The interference cancellation circuit according to any one of claims 1 to 3, wherein, Based on the one or more input signals, including the first input signal and the second input signal, the interference model includes second-order intermodulation distortion, third-order intermodulation distortion, fourth-order intermodulation distortion and fifth-order intermodulation distortion.

8. The interference cancellation circuit as described in claim 7, wherein, The interference model includes a sub-interference model based on a combination of at least one of a first input signal, a first conjugate signal of the first input signal, a second input signal, and a second conjugate signal of the second input signal.

9. The interference cancellation circuit according to any one of claims 1 to 3, further comprising: Multiple sub-interference cancellation circuits, each with a different memory index. Each of the plurality of sub-interference cancellation circuits includes at least one amplitude and phase calculator, a phase reconfiguration circuit, and a weight estimator, and each of the plurality of sub-interference cancellation circuits is configured to: output a sub-interference signal corresponding to a memory index based on the interference phase, the respective amplitudes of the one or more input signals, and their weights; and The calculation module is configured to output an interference signal by summing multiple sub-interference signals, each of which corresponds to a corresponding memory index.

10. The interference cancellation circuit as described in claim 9, further comprising: The delay circuit is configured to delay the one or more input signals by an amount corresponding to a memory index, and to input the result of the delay as the one or more input signals to the plurality of sub-interference cancellation circuits.

11. A method of operating an interference cancellation circuit, the method comprising: Receive one or more input signals; Calculate the amplitude and phase of each of the one or more input signals; An interference phase is generated by reconfiguring the respective phases of the one or more input signals based on an interference model. The weights of the interference signals are estimated based on the respective amplitudes of the one or more input signals. as well as Based on the interference phase, the respective amplitudes of the one or more input signals, and their weights, an interference signal is output. The phase of the kernel model associated with the interference model is different from the phase of each of the one or more input signals.

12. The operating method as described in claim 11, wherein, The step of generating the interference phase includes generating the interference phase by reconfiguring the respective phases of the one or more input signals to be the same as the phase of the kernel model.

13. The operating method as described in claim 11, in, The steps for estimating the weights of interference signals include: Select the index of the segment from a plurality of segments that corresponds to the respective amplitude of the one or more input signals; and Weights are determined based on indexes.

14. The method of operation as described in any one of claims 11 to 13, wherein, Based on the fact that the one or more input signals are a single input signal, the interference model includes at least one of the second harmonic and the third harmonic.

15. The operating method as described in claim 14, wherein, The steps for generating the interference phase include: doubling the function of the respective phase of the one or more input signals, based on the fact that the interference model is a second harmonic.

16. The operating method as described in claim 14, wherein, The steps for generating the interference phase include: based on the interference model being a third harmonic, increasing the function of the respective phase of the one or more input signals by a factor of three.

17. The method of operation as described in any one of claims 11 to 13, wherein, Based on the one or more input signals, including the first input signal and the second input signal, the interference model includes second-order intermodulation distortion, third-order intermodulation distortion, fourth-order intermodulation distortion and fifth-order intermodulation distortion.

18. The operating method as described in claim 17, wherein, The interference model includes a sub-interference model based on a combination of at least one of a first input signal, a first conjugate signal of the first input signal, a second input signal, and a second conjugate signal of the second input signal.

19. The method of operation as described in any one of claims 11 to 13, further comprising: For each of the multiple memory indices, perform the steps of computation, generating the interference phase, and estimating the weights of the interference signal; as well as For each of the plurality of memory indices, a sub-interference signal is output based on the interference phase, the respective amplitudes of the one or more input signals, and their weights. The step of outputting the interference signal includes: summing all the sub-interference signals to output the interference signal.

20. An interference cancellation circuit, the interference cancellation circuit comprising a plurality of sub-interference cancellation circuits, each of the plurality of sub-interference cancellation circuits being configured to: receive one or more input signals corresponding to a memory index, and output a sub-interference signal corresponding to the memory index. in, Each of the plurality of sub-interference cancellation circuits includes: An amplitude and phase calculator is configured to calculate the respective amplitude and phase of the one or more input signals; The phase reconfiguration circuit is configured to output an interference phase by reconfiguring the respective phases of the one or more input signals based on an interference model. A segment index selector is configured to: select an index corresponding to the respective amplitude of the one or more input signals; and The weight selector is configured to select the weights of the interference signals based on the index. The interference cancellation circuit further includes an adder configured to generate an interference signal by summing multiple sub-interference signals, each of which corresponds to a corresponding memory index. The phase of the kernel model associated with the interference model is different from the phase of the respective input signals.

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