Encryption and decryption method and system, computer equipment and storage medium

Abstract

The invention relates to the technical field of data security, in particular to an encryption and decryption method and system, computer equipment and a storage medium. The method comprises the following steps: sequentially storing an initial key in a zeroth register, a first register, a second register, a third register, a sixth register and a seventh register; according to the key length of the initial key, performing iteration round key addition operation iteration on the sub-keys stored in the registers to obtain the sub-keys output by each round of iteration operation, and sequentially storing the sub-keys in the corresponding registers according to a generation sequence; if the round key adding operation meets an iteration target, generating a target key after the initial key is expanded based on each round key in each register; and encrypting or decrypting a target file based on the target key. The invention provides an encryption and decryption method which is shorter in path and higher in efficiency.

Description

Technical Field

[0001] This application relates to the field of data security technology, specifically to an encryption / decryption method, system, computer device, and storage medium. Background Technology

[0002] AES is an advanced encryption method in cryptography, also known as Rijndael encryption. It was released by the National Institute of Standards and Technology (NIST) on November 26, 2001, in FIPS PUB 197, and became an effective standard on May 26, 2002. It was mainly used to replace the original DES (Data Encryption Standard). By 2006, the algorithm had become one of the most popular algorithms in modern symmetric cryptography.

[0003] AES is an iterative block cipher that supports 128-bit plaintext blocks. The number of encryption rounds varies with the key length. Common key lengths include 128 bits, 192 bits, and 256 bits, corresponding to 10, 12, and 14 encryption rounds, respectively. Based on the key length characteristics, this algorithm is also known as AES-128, AES-192, and AES-256. Except for the final round, each round of the AES encryption algorithm consists of four steps: byte substitution, row shifting, column mixing, and round key addition. Round key addition is one of the core components of the AES encryption algorithm, making its security particularly important.

[0004] The AES encryption and decryption process requires the AddRoundKey step, which involves XORing the roundkey with the roundkey. The roundkey is obtained through a key expansion algorithm.

[0005] However, the current key expansion calculation path is relatively long, resulting in low encryption and decryption efficiency. Summary of the Invention

[0006] This application provides an encryption / decryption method, system, computer device, and storage medium.

[0007] A first aspect of this application provides an encryption / decryption method applied to at least eight registers, the eight registers including at least the following sequentially configured registers: a zeroth register, a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, and a seventh register. The encryption / decryption method includes at least the following:

[0008] The initial key is stored sequentially in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register;

[0009] Based on the key length of the initial key, iterative round key addition operation is performed on the subkeys stored in each register to obtain the subkeys output in each round of iteration operation. The subkeys are then stored in their respective registers in the order of generation.

[0010] If the round key addition operation satisfies the iteration target, then the target key, which is an extension of the initial key, is generated based on each round sub-key in each register.

[0011] The target file is encrypted or decrypted based on the target key.

[0012] In one optional embodiment of this application, the step of performing iterative round key addition operations on the subkeys stored in each register according to the key length of the initial key to obtain the subkey output in each round of iteration, and storing each subkey in the corresponding register in the order of generation, includes:

[0013] If the initial key has a key length of 128 bits or 256 bits, then an iterative round key addition operation is performed based on the subkeys stored in the preset first register combination to obtain the subkeys output in each round of iteration operation. The subkeys are then stored in their respective registers in the order of generation. The number of registers in the preset first register combination is a multiple of 4.

[0014] In an optional embodiment of this application, if the key length of the initial key is 128 bits or 256 bits, then an iterative round key addition operation is performed based on the subkeys stored in the preset first register combination to obtain the subkeys output in each round of iteration. The subkeys are then stored in their corresponding registers in the order of generation, including:

[0015] If the initial key has a key length of 128 bits, then the round key addition operation is iterated based on the subkeys stored in the zeroth register, the first register, the second register, and the third register to obtain the result round key output in each round of iteration.

[0016] The resulting round keys obtained in each round are stored sequentially in the zeroth register, the first register, the second register, and the third register according to the generation order.

[0017] If the key length of the initial key is 256 bits, then the round key addition operation is iterated based on the subkeys stored in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the result round key output in each round of iteration.

[0018] The resulting round keys obtained in each round are stored sequentially in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register, according to the generation order.

[0019] In an optional embodiment of this application, if the initial key has a key length of 128 bits, then a round key addition operation is performed iteratively based on the subkeys stored in the zeroth register, the first register, the second register, and the third register to obtain the result round key output in each round of iteration; the result round key obtained in each round is sequentially stored in the zeroth register, the first register, the second register, and the third register according to the generation order, including:

[0020] The initial key is configured in the zeroth register, the first register, the second register, and the third register to obtain the zeroth round key;

[0021] The subkey output from the third register is byte-transformed and then XORed with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and the zeroth subkey is stored in the zeroth register.

[0022] The subkey output by the zeroth XOR logic processor is XORed with the subkey stored in the first register to obtain the first subkey of the current round key, and the first subkey is stored in the first register.

[0023] The subkey output by the first XOR logic processor is XORed with the subkey stored in the second register to obtain the second subkey of the current round key, and the second subkey is stored in the second register.

[0024] The subkey output by the fourth XOR logic processor is XORed with the subkey stored in the third register to obtain the third subkey of the current round key, and the third subkey is stored in the third register.

[0025] In an optional embodiment of this application, if the key length of the initial key is 256 bits, then a round key addition operation is performed iteratively based on the subkeys stored in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the result round key output in each round of iteration; the result round key obtained in each round is sequentially stored in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register according to the generation order, including:

[0026] The initial key is configured in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the zeroth round key;

[0027] The subkey output from the seventh register is byte-transformed and then XORed with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and the zeroth subkey is stored in the zeroth register.

[0028] The subkey output by the zeroth XOR logic processor is XORed with the subkey stored in the first register to obtain the first subkey of the current round key, and the first subkey is stored in the first register.

[0029] The subkey output by the first XOR logic processor is XORed with the subkey stored in the second register to obtain the second subkey of the current round key, and the second subkey is stored in the second register.

[0030] The subkey output by the fourth XOR logic processor is XORed with the subkey stored in the third register to obtain the third subkey of the current round key, and the third subkey is stored in the third register.

[0031] The subkey output from the third register is byte-transformed and then XORed with the subkey stored in the fourth register to obtain the fourth subkey of the current round key, and the fourth subkey is stored in the fourth register.

[0032] The subkey output by the zeroth XOR logic processor is XORed with the subkey stored in the fifth register to obtain the fifth subkey of the current round key, and the fifth subkey is stored in the fifth register.

[0033] The subkey output by the first XOR logic processor is XORed with the subkey stored in the sixth register to obtain the sixth subkey of the current round key, and the sixth subkey is stored in the sixth register.

[0034] The subkey output by the fourth XOR logic processor is XORed with the subkey stored in the seventh register to obtain the seventh subkey of the current round key, and the seventh subkey is stored in the seventh register.

[0035] In one optional embodiment of this application, the step of performing iterative round key addition operations on the subkeys stored in each register according to the key length of the initial key to obtain the subkey output in each round of iteration, and storing each subkey in the corresponding register in the order of generation, includes:

[0036] If the initial key has a key length of 192 bits, then an iterative round key addition operation is performed based on the subkeys stored in the preset second register combination to obtain the subkeys output in each round of iteration operation. The subkeys are then stored in their respective registers in the order of generation. The number of registers in the preset second register combination is a multiple of 6.

[0037] In an optional embodiment of this application, if the initial key has a key length of 192 bits, then an iterative round key addition operation is performed based on the subkeys stored in the preset second register combination to obtain the subkeys output in each round of iteration. Each subkey is then stored in its corresponding register in the order of generation, including:

[0038] The initial key is configured in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register to obtain the zeroth round key;

[0039] The zeroth XOR logic processor performs a byte transformation on the subkey output from the seventh register in the zeroth round key and an XOR operation with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the fourth register;

[0040] The first XOR logic processor performs an XOR operation on the subkey output by the zeroth XOR logic processor and the subkey stored in the first register to obtain the first subkey of the current round key, and stores the first subkey in the fifth register;

[0041] The second XOR logic processor performs an XOR operation on the subkey output by the first XOR logic processor and the subkey stored in the second register to obtain the second subkey of the current round key, and stores the second subkey in the zeroth register;

[0042] The third XOR logic processor performs an XOR operation on the subkey output by the second XOR logic processor and the subkey stored in the third register to obtain the third subkey of the current round key, and stores the third subkey in the first register;

[0043] The fourth XOR logic processor performs an XOR operation between the subkey output by the third XOR logic processor and the subkey stored in the sixth register to obtain the fourth subkey of the current round key, and stores the fourth subkey in the second register;

[0044] The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the seventh register to obtain the fifth subkey of the current round key, and stores the fifth subkey in the third register;

[0045] The zeroth XOR logic processor performs a byte transformation on the subkey output from the third register in the first round key and an XOR operation with the subkey stored in the fourth register to obtain the zeroth subkey of the next round key, and stores the zeroth subkey in the zeroth register.

[0046] The first XOR logic processor performs an XOR operation between the subkey output by the zeroth XOR logic processor and the subkey stored in the fifth register to obtain the first subkey of the next round key, and stores the first subkey in the first register;

[0047] The second XOR logic processor performs an XOR operation between the subkey output by the first XOR logic processor and the subkey stored in the zero register to obtain the second subkey of the next round key, and stores the second subkey in the second register;

[0048] The third XOR logic processor performs an XOR operation between the subkey output by the second XOR logic processor and the subkey stored in the first register to obtain the third subkey for the next round of keys, and stores the third subkey in the third register.

[0049] The fourth XOR logic processor performs an XOR operation between the subkey output by the third XOR logic processor and the subkey stored in the second register to obtain the fourth subkey for the next round of keys, and stores the fourth subkey in the sixth register.

[0050] The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the third register to obtain the fifth subkey for the next round of keys, and stores the fifth subkey in the seventh register.

[0051] A second aspect of this application provides an encryption / decryption system applied to at least eight registers, the eight registers including at least the following sequentially configured registers: a zeroth register, a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, and a seventh register. The encryption / decryption system includes at least:

[0052] A storage module is used to sequentially store the initial key in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register;

[0053] The iteration module is used to perform iterative round key addition operations on the subkeys stored in each register according to the key length of the initial key, to obtain the subkeys output by each round of iteration operations, and to store each subkey in the corresponding register in the order of generation.

[0054] The generation module is used to generate a target key that expands the initial key based on each round sub-key in each register if the round key addition operation satisfies the iteration target.

[0055] The encryption / decryption module is used to encrypt or decrypt the target file based on the target key.

[0056] A third aspect of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0057] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the method as described in any of the above.

[0058] The encryption / decryption method provided in this application embodiment is applied to at least eight registers. The method includes: storing an initial key sequentially in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register; then performing iterative round key addition operations on the subkeys stored in each register according to the key length of the initial key, obtaining the subkey output in each round of iteration; storing each subkey in its corresponding register in the order of generation until the round key addition operation satisfies the iteration target; generating a target key expanded from the initial key based on the round subkeys in each register; and finally encrypting or decrypting the target file based on the target key. When determining the target key, there is no need to configure different circuits for different key lengths. Key expansion for round keys of different lengths, such as 128-bit, 192-bit, and 256-bit, can be implemented in a single integrated circuit, eliminating the need for different circuits for different key lengths (keysize), thus improving compatibility. Furthermore, the scheduling of the eight registers in this application embodiment improves timing performance, significantly reducing the unit cost and quantity cost of the selector, while also reducing the interaction frequency of round key scheduling, shortening the key expansion path, and consequently shortening the encryption / decryption path. In summary, the embodiments of this application provide an encryption / decryption method with higher compatibility, better timing, higher efficiency, and lower cost. Attached Figure Description

[0059] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0060] Figure 1 This is a schematic diagram illustrating an application scenario of the encryption / decryption method provided in one embodiment of this application;

[0061] Figure 2 This is a schematic diagram illustrating an application scenario of the encryption / decryption method provided in one embodiment of this application;

[0062] Figure 3 A flowchart illustrating an encryption / decryption method provided in one embodiment of this application;

[0063] Figure 4 A schematic diagram illustrating the key storage in each register during the encryption process when the key length is 192 in the encryption / decryption method provided in this application embodiment;

[0064] Figure 5 This is a schematic diagram of key storage in each register during the decryption process when the key length is 192 in the encryption / decryption method provided in this application embodiment.

[0065] Figure 6This is a schematic diagram of an encryption / decryption system architecture provided in one embodiment of this application;

[0066] Figure 7 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0067] In developing this application, the inventors discovered that current key expansion calculation paths are quite long, resulting in low encryption and decryption efficiency. To address this problem, embodiments of this application provide an encryption / decryption method, system, computer device, and storage medium. The solutions in these embodiments can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0068] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0069] Please see Figure 1 , Figure 1 This is a schematic block diagram illustrating the structure of the encryption / decryption method provided in this application, which involves key storage and round-key addition operations among the registers. Figure 2 This is a circuit diagram illustrating key storage and round-key addition operations between registers provided in an embodiment of this application. Figure 2 Solid boxes containing numbers represent registers, including register a[0], register a[1], register a[2], register a[3], register a[4], register a[5], register a[6], and register a[7]; dashed boxes represent registers containing the last subkey in the previous round of key addition operations. Figure 2 This includes: the third register a[3] and the seventh register a[7]; the selector Figure 2 Not shown in the image; Figure 2 In the text, “⊕” represents an XOR logic processor or the corresponding XOR operation, such as… Figure 2In the diagram, the X / OR logic processors, from left to right, include: the zeroth X / OR logic processor ⊕0, the first X / OR logic processor ⊕1, the second X / OR logic processor ⊕2, the third X / OR logic processor ⊕3, the fourth X / OR logic processor ⊕4, and the fifth X / OR logic processor ⊕5. The zeroth X / OR logic processor ⊕0 is used to perform round key addition operations iteratively by replacing the bytes of the zeroth register a[0] or the fourth register a[4] of the previous round key with the bytes of the third register a[3] or the seventh register a[7] of the previous round key.

[0070] The encryption / decryption method provided in this application embodiment is applied to at least eight registers, which include at least the following sequentially configured registers: register a[0], register a[1], register a[2], register a[3], register a[4], register a[5], register a[6], and register a[7]; each register can be a word register. A word register is generally a register that can store one machine word of data. The size of a machine word depends on the computer architecture and is usually 16-bit, 32-bit, or 64-bit. For example, in a 32-bit system, a word register can store 32 bits of data.

[0071] In this embodiment of the application, the selection between two registers can be performed by a two-to-one selector. There can be at least six two-to-one selectors, that is, each selector is connected to two registers. The selector is used to select from the two registers to read and write the key. For example, if one of the selectors is connected to the zero register a[0] and the fourth register a[4], then the zero register a[0] and the fourth register a[4] are selected to read and write the key.

[0072] The round key addition operation iteration in this embodiment can be executed by a logic processor. The logic processor is connected to each selector and each register signal. The logic processor is used to perform round key addition operation iteration based on the previous round key output by the selector and the subkey output by the previous stage logic processor, and stores the round key output by iteration in the corresponding register in sequence. The round key addition operation refers to performing an XOR operation on the round key. The three types of round keys involved in this embodiment are: the previous round key refers to the round key output in the previous operation before the current round key addition operation or the initial round key; the registered round key refers to the round key obtained from the current register when performing the round key addition operation on the current register; and the result round key refers to the new round key output after performing the round key addition operation on the current register. The round key refers to a series of subkeys derived from the initial master key through the key expansion algorithm in the block cipher algorithm. These subkeys are used in each "round" of encryption or decryption. In this embodiment, each set of round keys consists of multiple sets of subkeys, and each subkey is distributed in different registers. Round key addition is a core operation in modern block cipher algorithms (especially AES). Essentially, it involves performing a bitwise XOR operation between the current data block (called the "state") and the corresponding round key. Symbolically, this is expressed as: New state = Current state ⊕ Round key, where "⊕" represents the XOR operation.

[0073] In one optional embodiment of this application, at least six 2-to-1 selectors include at least: a zeroth selector S0, a first selector S1, a second selector S2, a third selector S3, a fourth selector S4, and a fifth selector S5 (not shown in the figure). The zeroth selector S0 is connected to the zeroth register a[0], the fourth register a[4], and the logic processor signal, thereby enabling a 2-to-1 selection operation between the zeroth register a[0] and the fourth register a[4]. The first selector S1 is connected to the first register a[1], the fifth register a[5], and the logic processor signal, thereby enabling a 2-to-1 selection operation between the first register a[1] and the fifth register a[5]. The second selector S2 is connected to the zeroth register a[0], the second register a[2], and the logic processor signal, thereby enabling a 2-to-1 selection operation between the zeroth register a[0] and the second register a[2]. The third selector S3 is connected to the first register a[1], the third register a[3], and the logic processor signal, respectively, thereby enabling a two-to-one selection operation between the first register a[1] and the third register a[3]. The fourth selector S4 is connected to the second register a[2], the sixth register a[6], and the logic processor signal, respectively, thereby enabling a two-to-one selection operation between the second register a[2] and the sixth register a[6]. The fifth selector S5 is connected to the third register a[3], the seventh register a[7], and the logic processor signal, thereby enabling a two-to-one selection operation between the third register a[3] and the seventh register a[7].

[0074] Of course, in an optional embodiment of this application, in order to improve the scheduling efficiency of each register and facilitate bidirectional encryption and decryption operations, the number of selectors can be expanded. For example, it may also include: a sixth selector S6, a seventh selector S7, an eighth selector S8, a ninth selector S9, and a tenth selector S10, wherein: the sixth selector S6 is connected to the third register a[3], the seventh register a[7], and the byte transformation logic signal, respectively. This enables a two-to-one selection operation between the third register a[3] and the seventh register a[7]. The seventh selector S7 is connected to the zeroth logic processor output out0, the second logic processor output out2, and the zeroth register a[0] input signal, respectively. This enables a two-to-one selection operation between the zeroth logic processor output out0 and the second logic processor output out2. The eighth selector S8 is connected to the first logic processor output out1, the third logic processor output out3, and the first register a[1] input signal, respectively. This enables a two-to-one selection operation between the first logic processor output out1 and the third logic processor output out3. The ninth selector S9 is connected to the output out2 of the second logic processor, the output out4 of the fourth logic processor, and the input signal of the second register a[2], respectively. This enables a two-to-one selection operation between the output out2 of the second logic processor and the output out4 of the fourth logic processor. The tenth selector S10 is connected to the output out3 of the third logic processor, the output out5 of the fifth logic processor, and the input signal of the third register a[3], respectively. This enables a two-to-one selection operation between the output out3 of the third logic processor and the output out5 of the fifth logic processor.

[0075] In this embodiment, each selector connects to two registers. Only six selectors are needed to perform two-to-one scheduling of eight registers, which greatly reduces the unit cost and quantity cost of selectors. At the same time, it reduces the interaction frequency of round key scheduling, shortens the key expansion path, and improves the key expansion efficiency.

[0076] Please continue reading Figure 2 In an optional embodiment of this application, the logic processor further includes an encryption port enc and a decryption port dec. During encryption, the encryption port enc is connected to each register and the XOR logic processor signal, while the decryption port dec is disconnected; during decryption, the decryption port dec is connected to each register and the XOR logic processor signal, while the encryption port enc is disconnected. This achieves encryption and decryption functions within the same circuit, resulting in better integration.

[0077] Please continue reading Figure 2In an optional embodiment of this application, a module selector K is further included. The module selector K is connected to the first XOR logic processor ⊕1 and the fourth XOR logic processor ⊕4, respectively. The module selector K is used to short-circuit with the second XOR logic processor ⊕2 and the third XOR logic processor ⊕3 when the key length (keysize) of the round key is 128 bits or 256 bits. The second XOR logic processor ⊕2 refers to the XOR logic processor connected to the second selector S2, and the third XOR logic processor ⊕3 refers to the XOR logic processor connected to the third selector S3. When the round key length (keysize) is 128 bits, 4 registers are updated each time; when the round key length (keysize) is 256 bits, 8 registers are updated each time, both being multiples of 4. Therefore, when the round key length (keysize) is 128 bits or 256 bits, only 4 or 8 registers need to be used, and 4 selectors are configured. This greatly reduces the number of selectors and X / OR logic processors used, thereby reducing the cost of the key expansion system and reducing the key expansion path, thus reducing the cost of the encryption and decryption method provided in this application embodiment and improving the encryption and decryption efficiency.

[0078] Please see Figure 3 The encryption / decryption method provided in this application includes at least the following steps 301-304:

[0079] Step 301: Store the initial key sequentially in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register;

[0080] That is, each register stores a subkey of the initial key, which can be understood as a "word".

[0081] Step 302: Perform iterative round key addition operation on the subkeys stored in each register according to the key length of the initial key to obtain the subkey output in each round of iteration operation, and store each subkey in the corresponding register in the order of generation.

[0082] In other words, each round of key addition operation will produce multiple subkeys, which are stored in corresponding registers. The multiple subkeys in this round constitute the "round key" of the current round operation.

[0083] Step 303: If the round key addition operation satisfies the iteration objective, then generate the target key after expanding the initial key based on each round sub-key in each register;

[0084] After the iteration is completed, all the "round keys" together constitute the "target key".

[0085] Step 304: Encrypt or decrypt the target file based on the target key.

[0086] The encryption / decryption method provided in this application embodiment is applied to at least eight registers. The method includes: storing an initial key sequentially in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register; then performing iterative round key addition operations on the subkeys stored in each register according to the key length of the initial key, obtaining the subkey output in each round of iteration; storing each subkey in its corresponding register in the order of generation until the round key addition operation satisfies the iteration target; generating a target key expanded from the initial key based on the round subkeys in each register; and finally encrypting or decrypting the target file based on the target key. When determining the target key, there is no need to configure different circuits for different key lengths. Key expansion for round keys of different lengths, such as 128-bit, 192-bit, and 256-bit, can be implemented in a single integrated circuit, eliminating the need for different circuits for different key lengths (keysize), thus improving compatibility. Furthermore, the scheduling of the eight registers in this application embodiment improves timing performance, significantly reducing the unit cost and quantity cost of the selector, while also reducing the interaction frequency of round key scheduling, shortening the key expansion path, and consequently shortening the encryption / decryption path. In summary, the embodiments of this application provide an encryption / decryption method with higher compatibility, better timing, higher efficiency, and lower cost.

[0087] In an optional embodiment of this application, step 302 above, which involves iteratively performing round key addition operations on the subkeys stored in each register according to the key length of the initial key to obtain the subkeys output in each round of iteration, and storing each subkey in its corresponding register in the order of generation, includes the following two cases:

[0088] In the first case: if the key length of the initial key is 128 bits or 256 bits, then the iterative round key addition operation is performed based on the subkey stored in the preset first register combination to obtain the subkey output in each round of iteration operation, and the subkeys are stored in the corresponding registers in the order of generation; wherein, the number of registers in the preset first register combination is a multiple of 4.

[0089] The second scenario: If the initial key has a key length of 192 bits, then an iterative round key addition operation is performed based on the subkeys stored in the preset second register combination to obtain the subkeys output in each round of iteration. The subkeys are then stored in their respective registers in the order of generation. The number of registers in the preset second register combination is a multiple of 6.

[0090] In traditional round key addition operations: when the round key length (keysize) is 128 bits, 4 registers are updated each time; when the round key length (keysize) is 256 bits, 8 registers are updated each time; and when the round key length (keysize) is 192 bits, 6 registers are updated each time. In an optional embodiment of this application, at least six X / OR logic processors can be used. Each X / OR logic processor corresponds one-to-one with each selector. Each X / OR logic processor is signal-connected to the corresponding selector and the two registers connected to the selector. Each X / OR logic processor is used to perform XOR processing on the previous round key selected and output by the selector and the subkey output by the previous stage logic processor, and output the result round key. The iteratively output result round key is stored sequentially in the corresponding register to facilitate the next round key addition operation, thereby improving the overall key expansion efficiency. At the same time, it greatly reduces the number of X / OR logic processors used, reduces the cost of key expansion, and thus reduces the cost of encryption and decryption.

[0091] In an optional embodiment of this application, for the first case in step 302 above, if the key length of the initial key is 128 bits or 256 bits, then an iterative round key addition operation is performed based on the subkey stored in the preset first register combination to obtain the subkey output in each round of iteration operation. Each subkey is then stored in its corresponding register in the order of generation. This embodiment includes the following two sub-cases:

[0092] First seed case: If the key length of the initial key is 128 bits, then the round key addition operation is iterated based on the subkeys stored in the zeroth register, the first register, the second register, and the third register to obtain the result round key output in each round of iteration.

[0093] The resulting round keys obtained in each round are stored sequentially in the zeroth register, the first register, the second register, and the third register according to the generation order.

[0094] Second seed case: If the key length of the initial key is 256 bits, then the round key addition operation is iterated based on the subkeys stored in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the result round key output in each round of iteration.

[0095] The resulting round keys obtained in each round are stored sequentially in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register, according to the generation order.

[0096] In an optional embodiment of this application, for the first seed case described above, if the key length of the initial key is 128 bits, then a round key addition operation is performed iteratively based on the subkeys stored in the zeroth register, the first register, the second register, and the third register to obtain the result round key output in each round of iteration; the result round key obtained in each round is then stored sequentially in the zeroth register, the first register, the second register, and the third register according to the generation order, including the following steps:

[0097] The initial key is configured in the zeroth register a[0], the first register a[1], the second register a[2] and the third register a[3] to obtain the zeroth round key;

[0098] The zeroth XOR logic processor ⊕0 performs XOR processing on the subkey output by the third register a[3] after byte transformation and the subkey stored in the zeroth register a[0] to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the zeroth register a[0].

[0099] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the first register a[1] to obtain the first subkey of the current round key, and stores the first subkey in the first register a[1].

[0100] The fourth XOR logic processor ⊕4 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the second register a[2] to obtain the second subkey of the current round key, and stores the second subkey in the second register a[2].

[0101] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the third register a[3] to obtain the third subkey of the current round key, and stores the third subkey in the third register a[3].

[0102] In an optional embodiment of this application, for the second seed case described above, if the key length of the initial key is 256 bits, then a round key addition operation is performed iteratively based on the subkeys stored in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the result round key output in each round of iteration; the result round key obtained in each round is then stored sequentially in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register according to the generation order, including the following steps:

[0103] The initial key is configured in the zeroth register a[0], the first register a[1], the second register a[2], the third register a[3], the fourth register a[4], the fifth register a[5], the sixth register a[6], and the seventh register a[7] to obtain the zeroth round key;

[0104] The zeroth XOR logic processor ⊕0 performs XOR processing on the subkey output by the seventh register a[7] after byte transformation and the subkey stored in the zeroth register a[0] to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the zeroth register a[0].

[0105] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the first register a[1] to obtain the first subkey of the current round key, and stores the first subkey in the first register a[1].

[0106] The fourth XOR logic processor ⊕4 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the second register a[2] to obtain the second subkey of the current round key, and stores the second subkey in the second register a[2].

[0107] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the third register a[3] to obtain the third subkey of the current round key, and stores the third subkey in the third register a[3].

[0108] The zeroth XOR logic processor ⊕0 performs XOR processing on the subkey output by the third register a[3] after byte transformation and the subkey stored in the fourth register a[4] to obtain the fourth subkey of the current round key, and stores the fourth subkey in the fourth register a[4].

[0109] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the fifth register a[5] to obtain the fifth subkey of the current round key, and stores the fifth subkey in the fifth register a[5].

[0110] The fourth XOR logic processor ⊕4 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the sixth register a[6] to obtain the sixth subkey of the current round key, and stores the sixth subkey in the sixth register a[6].

[0111] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the seventh register a[7] to obtain the seventh subkey of the current round key, and stores the seventh subkey in the seventh register a[7].

[0112] Regarding the second scenario described above, if the initial key has a key length of 192 bits and iterates for 12 rounds, then based on the subkeys stored in the preset second register combination, iterative key addition operations are performed to obtain the subkeys output in each round of iteration. Each subkey is then stored in its corresponding register in the order of generation. Please refer to [link to relevant documentation]. Figure 4 and Figure 5 , Figure 4 and Figure 5 In this context, "Round" represents the number of iteration rounds. Therefore, the key addition operation iteration between every two consecutive rounds includes:

[0113] Round 1:

[0114] The initial key is configured in the zeroth register a[0], the first register a[1], the second register a[2], the third register a[3], the sixth register a[6], and the seventh register a[7] to obtain the zeroth round key;

[0115] The zeroth XOR logic processor ⊕0 performs a byte transformation on the subkey output by the seventh register a[7] in the zeroth round key and an XOR operation on the subkey stored in the zeroth register a[0] to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the fourth register a[4].

[0116] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the first register a[1] to obtain the first subkey of the current round key, and stores the first subkey in the fifth register a[5].

[0117] The second XOR logic processor ⊕2 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the second register a[2] to obtain the second subkey of the current round key, and stores the second subkey in the zero register a[0].

[0118] The third XOR logic processor ⊕3 performs an XOR operation on the subkey output by the second XOR logic processor ⊕2 and the subkey stored in the third register a[3] to obtain the third subkey of the current round key, and stores the third subkey in the first register a[1].

[0119] The fourth XOR logic processor ⊕4 performs an XOR operation on the subkey output by the third XOR logic processor ⊕3 and the subkey stored in the sixth register a[6] to obtain the fourth subkey of the current round key, and stores the fourth subkey in the second register a[2].

[0120] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the seventh register a[7] to obtain the fifth subkey of the current round key, and stores the fifth subkey in the third register a[3].

[0121] Round Two:

[0122] The zeroth XOR logic processor ⊕0 performs a byte transformation on the subkey output by the third register a[3] in the first round key and an XOR operation on the subkey stored in the fourth register a[4] to obtain the zeroth subkey of the next round key, and stores the zeroth subkey in the zeroth register a[0].

[0123] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the fifth register a[5] to obtain the first subkey of the next round key, and stores the first subkey in the first register a[1].

[0124] The second XOR logic processor ⊕2 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the zero register a[0] to obtain the second subkey of the next round key, and stores the second subkey in the second register a[2].

[0125] The third XOR logic processor ⊕3 performs an XOR operation between the subkey output by the second XOR logic processor ⊕2 and the subkey stored in the first register a[1] to obtain the third subkey of the next round key, and stores the third subkey in the third register a[3].

[0126] The fourth XOR logic processor ⊕4 performs an XOR operation between the subkey output by the third XOR logic processor ⊕3 and the subkey stored in the second register a[2] to obtain the fourth subkey of the next round key, and stores the fourth subkey in the sixth register a[6].

[0127] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the third register a[3] to obtain the fifth subkey of the next round key, and stores the fifth subkey in the seventh register a[7].

[0128] This process continues until all round keys have been iterated or the iteration goal has been reached.

[0129] In traditional round key addition operations: when the round key length (keysize) is 128 bits, 4 registers are updated each time; when the round key length (keysize) is 256 bits, 8 registers are updated each time; and when the round key length (keysize) is 192 bits, 6 registers are updated each time. The key expansion system provided in this application, through 8 registers and 6 selectors, can simultaneously implement key expansion for 128-bit, 192-bit, and 256-bit key lengths in a single circuit. It has higher integration, fewer registers and selectors, and can select a two-to-one selector, which requires less data processing compared to other multiple-to-one selectors, resulting in higher overall efficiency.

[0130] Please see Figure 5 When the key length (keysize) of the round key is 192 bits, the iterative process of the decryption operation is also 12 rounds. The decryption operation is the reverse process of the above encryption operation. Please refer to the above encryption process, which will not be repeated here.

[0131] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0132] Please see Figure 6 One embodiment of this application provides an encryption / decryption system 600 applied to at least eight registers, the eight registers including at least the following sequentially configured registers: zeroth register, first register, second register, third register, fourth register, fifth register, sixth register, and seventh register. The encryption / decryption system 600 includes at least:

[0133] Storage module 610 is used to store the initial key sequentially in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register;

[0134] The iteration module 620 is used to perform iterative round key addition operations on the subkeys stored in each register according to the key length of the initial key, to obtain the subkeys output by each round of iteration operations, and to store each subkey in the corresponding register in the order of generation.

[0135] The generation module 630 is used to generate a target key that expands the initial key based on each round sub-key in each register if the round key addition operation satisfies the iteration target.

[0136] The encryption / decryption module 640 is used to encrypt or decrypt the target file based on the target key.

[0137] In an optional embodiment of this application, the iteration module 620 is specifically used to perform iterative round key addition operations based on the subkeys stored in the preset first register combination if the key length of the initial key is 128 bits or 256 bits, to obtain the subkeys output in each round of iteration operations, and to store each subkey in the corresponding registers in the order of generation; wherein, the number of registers in the preset first register combination is a multiple of 4.

[0138] In an optional embodiment of this application, the iteration module 620 is specifically used to: if the key length of the initial key is 128 bits, perform round key addition operation iteration based on the subkeys stored in the zeroth register, the first register, the second register, and the third register to obtain the result round key output in each round of iteration operation; and store the result round key obtained in each round in the zeroth register, the first register, the second register, and the third register in sequence according to the generation order; if the key length of the initial key is 256 bits, perform round key addition operation iteration based on the subkeys stored in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the result round key output in each round of iteration operation; and store the result round key obtained in each round in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register in sequence according to the generation order.

[0139] In an optional embodiment of this application, the iteration module 620 is specifically configured to: configure the initial key in the zeroth register, the first register, the second register, and the third register to obtain the zeroth round key; perform a byte transformation on the subkey output by the third register and XOR it with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and store the zeroth subkey in the zeroth register; perform an XOR operation on the subkey output by the zeroth X / OR logic processor and the subkey stored in the first register to obtain the first subkey of the current round key, and store the first subkey in the first register; perform an XOR operation on the subkey output by the first X / OR logic processor and the subkey stored in the second register to obtain the second subkey of the current round key, and store the second subkey in the second register; perform an XOR operation on the subkey output by the fourth X / OR logic processor and the subkey stored in the third register to obtain the third subkey of the current round key, and store the third subkey in the third register.

[0140] In an optional embodiment of this application, the iteration module 620 is specifically configured to: configure the initial key in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the zeroth round key; perform XOR operation on the subkey output by the seventh register after byte transformation and the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and store the zeroth subkey in the zeroth register; perform XOR operation on the subkey output by the zeroth X / OR logic processor and the subkey stored in the first register to obtain the first subkey of the current round key, and store the first subkey in the first register; perform XOR operation on the subkey output by the first X / OR logic processor and the subkey stored in the second register to obtain the second subkey of the current round key, and store the second subkey in the second register; perform XOR operation on the subkey output by the fourth X / OR logic processor and the subkey stored in the third register to obtain the third subkey of the current round key, and store the third subkey in the third register.

[0141] The subkey output from the third register is byte-transformed and then XORed with the subkey stored in the fourth register to obtain the fourth subkey of the current round key, and the fourth subkey is stored in the fourth register. The subkey output from the zeroth X / OR logic processor is XORed with the subkey stored in the fifth register to obtain the fifth subkey of the current round key, and the fifth subkey is stored in the fifth register. The subkey output from the first X / OR logic processor is XORed with the subkey stored in the sixth register to obtain the sixth subkey of the current round key, and the sixth subkey is stored in the sixth register. The subkey output from the fourth X / OR logic processor is XORed with the subkey stored in the seventh register to obtain the seventh subkey of the current round key, and the seventh subkey is stored in the seventh register.

[0142] In an optional embodiment of this application, the iteration module 620 is specifically used to perform iterative round key addition operations based on the subkeys stored in the preset second register combination if the key length of the initial key is 192 bits, to obtain the subkeys output in each round of iteration operations, and to store each subkey in the corresponding registers in the order of generation; wherein, the number of registers in the preset second register combination is a multiple of 6.

[0143] In an optional embodiment of this application, the iteration module 620 is specifically configured to: configure the initial key in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register to obtain the zeroth round key; the zeroth XOR logic processor performs a byte transformation on the subkey output from the seventh register in the zeroth round key and XOR it with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the fourth register; the first XOR logic processor performs an XOR it with the subkey output from the zeroth XOR logic processor and the subkey stored in the first register to obtain the current round key. The first subkey of the round key is obtained and stored in the fifth register; the second X / OR logic processor performs an XOR operation between the subkey output by the first X / OR logic processor and the subkey stored in the second register to obtain the second subkey of the current round key, and stores the second subkey in the zeroth register; the third X / OR logic processor performs an XOR operation between the subkey output by the second X / OR logic processor and the subkey stored in the third register to obtain the third subkey of the current round key, and stores the third subkey in the first register; the fourth X / OR logic processor performs an XOR operation between the subkey output by the third X / OR logic processor and the subkey stored in the sixth register. The first XOR processor performs an XOR operation on the stored subkeys to obtain the fourth subkey of the current round key, and stores the fourth subkey in the second register; the fifth XOR logic processor performs an XOR operation on the subkey output by the fourth XOR logic processor and the subkey stored in the seventh register to obtain the fifth subkey of the current round key, and stores the fifth subkey in the third register; the zeroth XOR logic processor performs a byte transformation on the subkey output by the third register in the first round key and an XOR operation on the subkey stored in the fourth register to obtain the zeroth subkey of the next round key, and stores the zeroth subkey in the zeroth register; the first XOR logic processor performs an XOR operation on the subkey output by the third register in the first round key and the subkey stored in the fourth register to obtain the zeroth subkey of the next round key, and stores the zeroth subkey in the zeroth register; the first XOR logic processor performs an XOR operation on the subkey output by the third register in the first round key and the subkey stored in the seventh register. The subkey output by the zero XOR logic processor is XORed with the subkey stored in the fifth register to obtain the first subkey of the next round key, and the first subkey is stored in the first register; the second XOR logic processor XORs the subkey output by the first XOR logic processor with the subkey stored in the zero register to obtain the second subkey of the next round key, and the second subkey is stored in the second register; the third XOR logic processor XORs the subkey output by the second XOR logic processor with the subkey stored in the first register to obtain the third subkey of the next round key, and the third subkey is stored in the third register.

[0144] The fourth XOR logic processor performs an XOR operation on the subkey output by the third XOR logic processor and the subkey stored in the second register to obtain the fourth subkey of the next round key, and stores the fourth subkey in the sixth register; the fifth XOR logic processor performs an XOR operation on the subkey output by the fourth XOR logic processor and the subkey stored in the third register to obtain the fifth subkey of the next round key, and stores the fifth subkey in the seventh register.

[0145] For specific limitations regarding the encryption / decryption system 600, please refer to the limitations on the encryption / decryption methods above, which will not be repeated here. Each module in the encryption / decryption system 600 can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the corresponding operations of each module.

[0146] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 7 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements one of the encryption / decryption methods described above. It includes: memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the encryption / decryption method described above.

[0147] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can perform any of the steps in the encryption / decryption methods described above.

[0148] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0149] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0150] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0151] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0152] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0153] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An encryption / decryption method, characterized in that, The encryption / decryption method is applied to at least eight registers, which include at least the following sequentially configured registers: register zero, register one, register two, register three, register four, register five, register six, and register seven. The encryption / decryption method includes at least the following: The initial key is stored sequentially in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register; Based on the key length of the initial key, iterative round key addition operation is performed on the subkeys stored in each register to obtain the subkeys output in each round of iteration operation. The subkeys are then stored in their respective registers in the order of generation. If the round key addition operation satisfies the iteration target, then the target key, which is an extension of the initial key, is generated based on each round sub-key in each register. The target file is encrypted or decrypted based on the target key.

2. The encryption / decryption method according to claim 1, characterized in that, The step involves iteratively adding subkeys stored in each register according to the key length of the initial key to obtain the subkey output in each iteration, and then storing each subkey in its corresponding register in the order of generation. If the initial key has a key length of 128 bits or 256 bits, then an iterative round key addition operation is performed based on the subkeys stored in the preset first register combination to obtain the subkeys output in each round of iteration operation. The subkeys are then stored in their respective registers in the order of generation. The number of registers in the preset first register combination is a multiple of 4.

3. The encryption / decryption method according to claim 2, characterized in that, If the initial key has a key length of 128 bits or 256 bits, then an iterative round key addition operation is performed based on the subkeys stored in the preset first register combination to obtain the subkeys output in each round of iteration. Each subkey is then stored in its corresponding register in the order of generation, including: If the initial key has a key length of 128 bits, then the round key addition operation is iterated based on the subkeys stored in the zeroth register, the first register, the second register, and the third register to obtain the result round key output by each round of iteration. The resulting round keys obtained in each round are stored sequentially in the zeroth register, the first register, the second register, and the third register according to the generation order. If the initial key has a key length of 256 bits, then the round key addition operation is iterated based on the subkeys stored in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the result round key output by each round of iteration. The resulting round keys obtained in each round are stored sequentially in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register, according to the generation order.

4. The encryption / decryption method according to claim 3, characterized in that, If the initial key has a key length of 128 bits, then the round key addition operation is iterated based on the subkeys stored in the zeroth register, the first register, the second register, and the third register to obtain the result round key output in each round of iteration. The resulting round keys obtained in each round are stored sequentially in the zeroth register, the first register, the second register, and the third register according to the generation order, including: The initial key is configured in the zeroth register, the first register, the second register, and the third register to obtain the zeroth round key; The subkey output from the third register is byte-transformed and then XORed with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and the zeroth subkey is stored in the zeroth register. The subkey output by the zeroth XOR logic processor is XORed with the subkey stored in the first register to obtain the first subkey of the current round key, and the first subkey is stored in the first register. The subkey output by the first XOR logic processor is XORed with the subkey stored in the second register to obtain the second subkey of the current round key, and the second subkey is stored in the second register. The subkey output by the fourth XOR logic processor is XORed with the subkey stored in the third register to obtain the third subkey of the current round key, and the third subkey is stored in the third register.

5. The encryption / decryption method according to claim 3, characterized in that, If the key length of the initial key is 256 bits, then a round key addition operation is performed iteratively based on the subkeys stored in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the result round key output in each round of iteration. The resulting round keys obtained in each round are stored sequentially in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register, according to the generation order, including: The initial key is configured in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the zeroth round key; The subkey output from the seventh register is byte-transformed and then XORed with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and the zeroth subkey is stored in the zeroth register. The subkey output by the zeroth XOR logic processor is XORed with the subkey stored in the first register to obtain the first subkey of the current round key, and the first subkey is stored in the first register. The subkey output by the first XOR logic processor is XORed with the subkey stored in the second register to obtain the second subkey of the current round key, and the second subkey is stored in the second register. The subkey output by the fourth XOR logic processor is XORed with the subkey stored in the third register to obtain the third subkey of the current round key, and the third subkey is stored in the third register. The subkey output from the third register is byte-transformed and then XORed with the subkey stored in the fourth register to obtain the fourth subkey of the current round key, and the fourth subkey is stored in the fourth register. The subkey output by the zeroth XOR logic processor is XORed with the subkey stored in the fifth register to obtain the fifth subkey of the current round key, and the fifth subkey is stored in the fifth register. The subkey output by the first XOR logic processor is XORed with the subkey stored in the sixth register to obtain the sixth subkey of the current round key, and the sixth subkey is stored in the sixth register. The subkey output by the fourth XOR logic processor is XORed with the subkey stored in the seventh register to obtain the seventh subkey of the current round key, and the seventh subkey is stored in the seventh register.

6. The encryption / decryption method according to claim 1, characterized in that, The step involves iteratively adding subkeys stored in each register according to the key length of the initial key to obtain the subkey output in each iteration, and then storing each subkey in its corresponding register in the order of generation. If the initial key has a key length of 192 bits, then an iterative round key addition operation is performed based on the subkeys stored in the preset second register combination to obtain the subkeys output in each round of iteration operation. The subkeys are then stored in their respective registers in the order of generation. The number of registers in the preset second register combination is a multiple of 6.

7. The encryption / decryption method according to claim 6, characterized in that, If the initial key has a key length of 192 bits, then iterative round key addition operations are performed based on the subkeys stored in the preset second register combination to obtain the subkeys output in each round of iteration. Each subkey is then stored in its corresponding register in the order of generation, including: The initial key is configured in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register to obtain the zeroth round key; The zeroth XOR logic processor performs a byte transformation on the subkey output from the seventh register in the zeroth round key and an XOR operation with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the fourth register; The first XOR logic processor performs an XOR operation on the subkey output by the zeroth XOR logic processor and the subkey stored in the first register to obtain the first subkey of the current round key, and stores the first subkey in the fifth register; The second XOR logic processor performs an XOR operation on the subkey output by the first XOR logic processor and the subkey stored in the second register to obtain the second subkey of the current round key, and stores the second subkey in the zeroth register; The third XOR logic processor performs an XOR operation on the subkey output by the second XOR logic processor and the subkey stored in the third register to obtain the third subkey of the current round key, and stores the third subkey in the first register; The fourth XOR logic processor performs an XOR operation between the subkey output by the third XOR logic processor and the subkey stored in the sixth register to obtain the fourth subkey of the current round key, and stores the fourth subkey in the second register; The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the seventh register to obtain the fifth subkey of the current round key, and stores the fifth subkey in the third register; The zeroth XOR logic processor performs a byte transformation on the subkey output from the third register in the first round key and an XOR operation with the subkey stored in the fourth register to obtain the zeroth subkey of the next round key, and stores the zeroth subkey in the zeroth register. The first XOR logic processor performs an XOR operation between the subkey output by the zeroth XOR logic processor and the subkey stored in the fifth register to obtain the first subkey of the next round key, and stores the first subkey in the first register; The second XOR logic processor performs an XOR operation between the subkey output by the first XOR logic processor and the subkey stored in the zero register to obtain the second subkey of the next round key, and stores the second subkey in the second register; The third XOR logic processor performs an XOR operation between the subkey output by the second XOR logic processor and the subkey stored in the first register to obtain the third subkey for the next round of keys, and stores the third subkey in the third register. The fourth XOR logic processor performs an XOR operation between the subkey output by the third XOR logic processor and the subkey stored in the second register to obtain the fourth subkey for the next round of keys, and stores the fourth subkey in the sixth register. The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the third register to obtain the fifth subkey for the next round of keys, and stores the fifth subkey in the seventh register.

8. An encryption / decryption system, characterized in that, The encryption / decryption system applies to at least eight registers, which include at least the following sequentially configured registers: register zero, register one, register two, register three, register four, register five, register six, and register seven. A storage module is used to sequentially store the initial key in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register; The iteration module is used to perform iterative round key addition operations on the subkeys stored in each register according to the key length of the initial key, to obtain the subkeys output by each round of iteration operations, and to store each subkey in the corresponding register in the order of generation. The generation module is used to generate a target key that expands the initial key based on each round sub-key in each register if the round key addition operation satisfies the iteration target. The encryption / decryption module is used to encrypt or decrypt the target file based on the target key.

9. A computer device, comprising: The method includes a memory and a processor, the memory storing a computer program, characterized in that the processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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