PIN junction detector based on N-type germanium substrate and preparation method

Abstract

The invention discloses a PIN junction detector based on an N-type germanium substrate and a preparation method, and relates to the technical field of microelectronics. The detector comprises an N-type Ge substrate; the intrinsic Ge epitaxial layer is positioned on the upper surface of the N-type Ge substrate; the P-type Ge region is positioned in the intrinsic Ge epitaxial layer and is close to the upper surface of the intrinsic Ge epitaxial layer; the first metal electrode and the second metal electrode are located on the upper surface of the P-type Ge region and the lower surface of the N-type Ge substrate respectively. The thin layer intrinsic Ge is epitaxially grown on the heavily doped N-type substrate to serve as the I region of the PIN junction, so that the width of a depletion region is effectively reduced, the dark current of the device is remarkably reduced, meanwhile, the efficient separation effect of the I region on photon-generated carriers is reserved, relatively high responsivity is ensured, optimal balance of low dark current and high responsivity is realized, and the photoelectric conversion efficiency of the device is improved. And the process is compatible with a silicon-based CMOS, and is suitable for low-cost and large-scale photoelectric integration application.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a PIN junction detector based on an N-type germanium substrate and its fabrication method. Background Technology

[0002] Currently, high-performance near-infrared photodetectors mainly employ indium gallium arsenide (IGaAs) materials, exhibiting excellent responsivity and detection sensitivity in the 1550nm communication band. However, these detectors require complex heteroepitaxial fabrication processes, resulting in high costs and poor compatibility with silicon-based CMOS processes, hindering their widespread application in low-cost, large-scale integrated optoelectronic systems. While colloidal quantum dot detectors, which have emerged in recent years, offer advantages such as solution-based fabrication and lower costs, their performance and reliability remain insufficient for commercialization due to limitations such as poor material stability, low carrier mobility, and difficulties in integration with silicon processes.

[0003] Germanium, with its excellent light absorption characteristics in the near-infrared band (up to 1850 nm) and natural compatibility with silicon-based CMOS processes, is considered an ideal candidate material for achieving high-performance, low-cost on-chip optoelectronic integration. However, traditional germanium-based photodetectors still face significant challenges in practical applications: metal-semiconductor-metal structure devices generally suffer from excessive dark current, severely affecting detection sensitivity. While PIN detectors using bulk germanium reduce carrier recombination rates by introducing intrinsic regions, the large thickness of the I-region leads to a sharp increase in dark current, limiting further performance improvements. However, without the I-region, the recombination rate of photogenerated carriers is high, making it difficult to improve device responsivity. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a PIN junction detector based on an N-type germanium substrate and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a PIN junction detector based on an N-type germanium substrate, comprising: N-type Ge substrate; An intrinsic Ge epitaxial layer is located on the upper surface of the N-type Ge substrate; The P-type Ge region is located within the intrinsic Ge epitaxial layer and close to the upper surface of the intrinsic Ge epitaxial layer; The first metal electrode is located on the upper surface of the P-type Ge region and forms an ohmic contact with the P-type Ge region. The second metal electrode is located on the lower surface of the N-type Ge substrate and forms an ohmic contact with the N-type Ge substrate.

[0005] In one embodiment of the present invention, the resistivity of the N-type Ge substrate does not exceed 0.005 Ω·cm.

[0006] In one embodiment of the present invention, the thickness of the N-type Ge substrate is 300-500 μm.

[0007] In one embodiment of the present invention, the thickness of the intrinsic Ge epitaxial layer is 1-2 μm.

[0008] In one embodiment of the present invention, the doping concentration of the p-type Ge region is 1×10⁻⁶. 19 -1×10 20 cm -3 .

[0009] In one embodiment of the present invention, the ion implantation depth of the P-type Ge region is 100-200 nm.

[0010] In one embodiment of the present invention, the materials of the first metal electrode and the second metal electrode are gold, silver or aluminum.

[0011] This invention provides a method for fabricating a PIN junction detector based on an N-type germanium substrate, applicable to the PIN junction detector based on an N-type germanium substrate described in any of the above embodiments. The fabrication method includes: Step 1: Select an N-type Ge substrate; Step 2: An intrinsic Ge epitaxial layer is formed on the upper surface of the N-type Ge substrate using an epitaxial process; Step 3: Perform ion implantation or diffusion on the upper surface of the intrinsic Ge epitaxial layer to form a P-type Ge region; Step 4: Electrode deposition is performed on the upper surface of the P-type Ge region and the lower surface of the N-type Ge substrate to form a first metal electrode and a second metal electrode.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: The PIN junction detector based on an N-type germanium substrate of this invention employs a structure of epitaxially growing a thin layer of intrinsic germanium on a low-resistivity N-type substrate, allowing the thickness of the I-region to be precisely controlled at the micrometer or even submicrometer level. Under the same bias voltage, the thin I-region can achieve complete depletion, establishing a uniform and strong electric field within it. This significantly suppresses dark current dominated by diffusion mechanisms, achieving a reduction in dark current by orders of magnitude. Simultaneously, this fully depleted I-region also serves as a highly efficient region for photogenerated carrier generation and separation, avoiding the rapid carrier recombination problem caused by an excessively narrow depletion region in pure PN junctions, thereby ensuring and improving the device's responsivity and quantum efficiency.

[0013] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a PIN junction detector based on an N-type germanium substrate provided in an embodiment of the present invention; Figure 2 This is a flowchart of a method for fabricating a PIN junction detector based on an N-type germanium substrate, provided by an embodiment of the present invention.

[0015] Icons: 1- N-type Ge substrate; 2- Intrinsic Ge epitaxial layer; 3- P-type Ge region; 4- First metal electrode; 5- Second metal electrode. Detailed Implementation

[0016] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a PIN junction detector based on an N-type germanium substrate and its fabrication method according to the present invention.

[0017] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0018] In a first aspect, embodiments of the present invention provide a PIN junction detector based on an N-type germanium substrate. Its core lies in using epitaxial growth of an I-region germanium layer. By precisely controlling the thickness and material quality of the I-region, dark current is effectively suppressed while retaining the intrinsic region's gain effect on the separation and collection of photogenerated carriers, thereby achieving a good balance between device dark current and responsivity.

[0019] Please see Figure 1 , Figure 1 This is a schematic diagram of a PIN junction detector based on an N-type germanium substrate provided in an embodiment of the present invention. Figure 1As shown, the PIN junction detector based on an N-type germanium substrate in this embodiment includes: an N-type Ge substrate 1, an intrinsic Ge epitaxial layer 2, a P-type Ge region 3, a first metal electrode 4, and a second metal electrode 5. The intrinsic Ge epitaxial layer 2 is located on the upper surface of the N-type Ge substrate 1; the P-type Ge region 3 is located within the intrinsic Ge epitaxial layer 2 and close to its upper surface; the first metal electrode 4 is located on the upper surface of the P-type Ge region 3, forming an ohmic contact with it; and the second metal electrode 5 is located on the lower surface of the N-type Ge substrate 1, forming an ohmic contact with it.

[0020] In this embodiment, the N-type Ge substrate 1 is a highly doped N-type single-crystal germanium wafer with a resistivity not exceeding 0.005 Ω·cm, for example, 0.003 Ω·cm. Optionally, the thickness of the N-type Ge substrate 1 is 300-500 μm, for example, 400 μm. The highly doped N-type Ge substrate 1 helps to reduce the series resistance and ensures good ohmic contact with the bottom second metal electrode 5.

[0021] Alternatively, ohmic contact with the electrode can also be achieved by ion implantation at the bottom of the high resistivity Ge substrate on the N-type Ge substrate.

[0022] In this embodiment, a high-quality intrinsic (i-type) germanium layer can be grown on the upper surface of the N-type Ge substrate 1 by epitaxial processes such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) to form an intrinsic Ge epitaxial layer 2.

[0023] Optionally, the thickness of the intrinsic Ge epitaxial layer 2 is 1-2 μm, for example, the thickness of the intrinsic Ge epitaxial layer 2 can be precisely controlled to 1.5 μm. This thin layer of intrinsic Ge constitutes the I region of the PIN junction, which has high crystal quality and low defect density, and is beneficial to reducing the generation-recombination dark current of the device.

[0024] In this embodiment, an optimized PIN junction is constructed by employing an N-type highly doped (low resistivity) substrate and combining it with a thin-layer epitaxial intrinsic Ge (I-region). The thickness of the epitaxially grown intrinsic Ge layer is precisely controllable and much smaller than the thickness of the I-region in traditional PIN structures based on intrinsic substrates. This significantly shortens the carrier transit path, effectively reduces the diffusion current and generation-recombination current caused by excessive I-region thickness, and thus greatly reduces the device's dark current.

[0025] Although the thickness of the I-region is reduced, its presence allows for rapid separation and collection of photogenerated carriers within the depletion region, avoiding the high recombination rate problem near the PN junction surface. Simultaneously, the heavily doped N-type substrate provides excellent ohmic contact and support. This structural design significantly reduces dark current while maintaining high photocurrent and responsivity, achieving an optimized performance balance.

[0026] In this embodiment, the doping concentration of the p-type Ge region 3 is 1×10⁻⁶. 19 -1×10 20 cm -3 The ion implantation depth is 100-200 nm.

[0027] Optionally, the p-type Ge region 3 can be prepared using an ion implantation process. For example, boron (B) ions are implanted into the upper surface region of the intrinsic Ge epitaxial layer 2 to form a doping concentration of 5 × 10⁻⁶. 19 cm -3 The P-type Ge region 3 has a junction depth of 150 nm. The P-type Ge region 3 constitutes the P region of the PIN junction. It should be noted that after ion implantation, rapid thermal annealing (RTA) is required to activate the dopant and repair lattice damage.

[0028] In other alternative embodiments, a diffusion process can be used to form the p-type Ge region 3. Exemplarily, a boron-containing solid source is used as the dopant source, and diffusion is performed at 800°C to form a doping concentration of approximately 1 × 10⁻⁶. 20 cm -3 3. A P-type Ge region with a junction depth of approximately 100 nm.

[0029] Alternatively, the P-type Ge region can also achieve ohmic contact through a combination of low-concentration ion implantation and high-concentration ion implantation, with the high-concentration ion implantation region being smaller than the low-concentration ion implantation region.

[0030] In this embodiment, the first metal electrode 4 and the second metal electrode 5 are made of gold, silver or aluminum.

[0031] Optionally, on the upper surface of the p-type Ge region 3, a metal layer can be deposited using electron beam evaporation or thermal evaporation (e.g., first depositing 20 nm Ti as an adhesion layer, then depositing 200 nm Au), and a patterned electrode can be formed by photolithography to create an ohmic contact with the p-type Ge region. On the lower surface of the n-type Ge substrate 1, a similar process can be used to deposit metal (e.g., depositing 200 nm Al) to form an ohmic contact.

[0032] In an optional embodiment, both the first metal electrode 4 and the second metal electrode 5 can be made of aluminum as the primary metal material. Aluminum has a good work function match with Ge, and after appropriate alloying processes (such as annealing at 400°C), it can form good ohmic contacts, and it is inexpensive and fully compatible with standard silicon process lines.

[0033] The PIN junction detector based on an N-type germanium substrate in this embodiment has a thickness of more than two orders of magnitude reduced in the I-region compared to traditional PIN detectors using thick intrinsic Ge substrates (typically hundreds of micrometers). One of the main sources of dark current is the generation-recombination centers within and on the surface of the I-region. The significant reduction in the I-region thickness directly reduces the total volume of generation-recombination centers, thereby significantly reducing dark current. Simultaneously, this thin I-region can be completely depleted under reverse bias, forming a moderately strong depletion electric field. When near-infrared light (e.g., 1550 nm) is incident, photogenerated electron-hole pairs are efficiently separated within the depletion region and rapidly drift to the electrode, reducing recombination losses near the P / I junction interface. Furthermore, using a heavily doped N-type substrate as the N-region avoids the complex process of epitaxially growing a thick intrinsic layer on the N-type substrate followed by P-type implantation, simplifying the process and improving process controllability and yield.

[0034] Secondly, embodiments of the present invention provide a method for fabricating a PIN junction detector based on an N-type germanium substrate, applicable to the PIN junction detector based on an N-type germanium substrate proposed in the first aspect.

[0035] Please see Figure 2 , Figure 2 This is a flowchart illustrating a method for fabricating a PIN junction detector based on an N-type germanium substrate, as provided in an embodiment of the present invention. Figure 2 As shown, the fabrication method of the PIN junction detector based on an N-type germanium substrate according to an embodiment of the present invention includes the following steps: Step 1: Select an N-type Ge substrate.

[0036] In this embodiment, the resistivity of the N-type Ge substrate does not exceed 0.005 Ω·cm. This low-resistivity substrate facilitates the formation of low-resistivity ohmic contacts with the metal electrodes, reducing the series resistance of the device. Optionally, the thickness of the N-type Ge substrate is 300-500 μm to provide sufficient mechanical support strength for subsequent processing. The use of a highly doped N-type substrate provides an ideal electron collection terminal for the device, and its low-resistivity characteristics are fundamental to achieving efficient charge extraction and low-power operation.

[0037] It should be noted that after selecting an N-type Ge substrate, standard RCA cleaning is required to remove surface contaminants and the native oxide layer.

[0038] Step 2: An intrinsic Ge epitaxial layer is formed on the upper surface of an N-type Ge substrate using an epitaxial process.

[0039] Optionally, a high-quality intrinsic germanium (i-Ge) epitaxial layer is grown on the upper surface of an N-type germanium substrate using epitaxial processes such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The thickness of the intrinsic Ge epitaxial layer is precisely controlled within the range of 1 μm to 2 μm.

[0040] For example, the cleaned substrate can be placed in an epitaxial furnace (such as a CVD reaction chamber). Using germane (GeH4) as the source gas, an intrinsic Ge epitaxial layer with a thickness of 1-2 μm is grown in a hydrogen (H2) atmosphere at a temperature of 600-700°C. The gas pressure and gas flow rate are strictly controlled during the growth process to obtain a high-quality epitaxial layer with low defect density.

[0041] Compared to traditional techniques using high-resistivity bulk germanium as the I-region, this embodiment utilizes epitaxial processing to precisely and reproducibly fabricate an intrinsic layer with a thickness much smaller than the bulk material's I-region. This significantly shortens carrier transit time, contributing to improved device response speed. Due to the substantial reduction in the I-region thickness (i.e., the intrinsic Ge epitaxial layer), the electric field strength in this region is higher under the same reverse bias, allowing for more efficient depletion. This fundamentally suppresses the diffused dark current caused by excessive I-region thickness and insufficient electric field, resulting in a significant reduction in dark current.

[0042] Step 3: Perform ion implantation or diffusion on the upper surface of the intrinsic Ge epitaxial layer to form a P-type Ge region.

[0043] In this embodiment, photoresist is spin-coated onto the surface of the intrinsic Ge epitaxial layer and photolithography is performed to define the P-region pattern. Then, ion implantation or diffusion processes are performed to form the P-type Ge region.

[0044] For example, boron ions are injected at a dose of 1 × 10⁻⁶. 15 cm -2 The energy is 30 keV. After implantation, the photoresist is stripped and annealed (e.g., 600°C, 1 min) to activate impurities and repair damage, forming a P-type Ge region.

[0045] Alternatively, solid-state source diffusion can be used instead of ion implantation to form the p-type Ge region. For example, in an inert gas atmosphere, a boron-containing solid-state source can be used to diffuse the sample at 800°C, and the desired junction depth and doping concentration can be achieved by controlling the diffusion time. This method avoids the lattice damage that may be caused by ion implantation and can obtain better interface properties.

[0046] In this embodiment, the P-type Ge region, i.e., the heavily doped P-type region, forms a PI junction with the intrinsic Ge epitaxial layer, which is one of the core regions for photoelectric conversion in the device. Furthermore, the heavy doping ensures that the subsequently formed metal electrode can form an excellent ohmic contact with it, rather than a rectifying Schottky contact. This avoids the additional potential barrier and leakage current introduced by Schottky contacts, ensuring that holes can be efficiently extracted to the external circuitry.

[0047] Step 4: Electrode deposition is performed on the upper surface of the P-type Ge region and the lower surface of the N-type Ge substrate to form the first metal electrode and the second metal electrode.

[0048] Optionally, electrode windows can be re-defined by photolithography on the surface of the P-type Ge region, followed by sequential deposition of Ti (20 nm) and Au (200 nm) using electron beam evaporation or sputtering. The first metal electrode is patterned using a lift-off process. Finally, a second metal electrode is formed by bulk evaporation or sputtering of a metal (such as a gold / germanium / nickel alloy or a simple aluminum layer) on the back side of the N-type Ge substrate. After all electrodes are formed, a low-temperature alloying anneal (e.g., 350°C, 10 minutes) can be performed to improve ohmic contact.

[0049] The fabrication method of the PIN junction detector based on an N-type germanium substrate in this invention balances the contradiction between dark current and responsivity in traditional PIN junction detectors through the structural design of an N-type substrate, an epitaxial thin intrinsic layer, and a P-type heavily doped region. The thin intrinsic epitaxial layer effectively reduces dark current, while its depletion region ensures effective separation and collection of photogenerated carriers, avoiding the high recombination rate problem in pure PN junctions, thus achieving high responsivity. The final device exhibits excellent characteristics of high sensitivity, low noise, and compatibility with silicon-based CMOS processes in the near-infrared band (especially in the 1550 nm communication window).

[0050] For details regarding the fabrication method of the PIN junction detector based on an N-type germanium substrate and its corresponding beneficial effects, please refer to the relevant content on the PIN junction detector based on an N-type germanium substrate provided in the first aspect; it will not be repeated here.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0052] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0053] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A PIN junction detector based on an N-type germanium substrate, characterized in that, include: N-type Ge substrate (1); The intrinsic Ge epitaxial layer (2) is located on the upper surface of the N-type Ge substrate (1); The P-type Ge region (3) is located within the intrinsic Ge epitaxial layer (2) and close to the upper surface of the intrinsic Ge epitaxial layer (2); The first metal electrode (4) is located on the upper surface of the P-type Ge region (3) and forms an ohmic contact with the P-type Ge region (3); The second metal electrode (5) is located on the lower surface of the N-type Ge substrate (1) and forms an ohmic contact with the N-type Ge substrate (1).

2. The PIN junction detector based on an N-type germanium substrate according to claim 1, characterized in that, The resistivity of the N-type Ge substrate (1) is no more than 0.005 Ω·cm.

3. The PIN junction detector based on an N-type germanium substrate according to claim 1, characterized in that, The thickness of the N-type Ge substrate (1) is 300-500 μm.

4. The PIN junction detector based on an N-type germanium substrate according to claim 1, characterized in that, The thickness of the intrinsic Ge epitaxial layer (2) is 1-2 μm.

5. The PIN junction detector based on an N-type germanium substrate according to claim 1, characterized in that, The doping concentration of the P-type Ge region (3) is 1×10⁻⁶. 19 -1×10 20 cm -3 .

6. The PIN junction detector based on an N-type germanium substrate according to claim 1, characterized in that, The ion implantation depth of the P-type Ge region (3) is 100-200 nm.

7. The PIN junction detector based on an N-type germanium substrate according to claim 1, characterized in that, The first metal electrode (4) and the second metal electrode (5) are made of gold, silver or aluminum.

8. A method for fabricating a PIN junction detector based on an N-type germanium substrate, characterized in that, The method for fabricating a PIN junction detector based on an N-type germanium substrate according to any one of claims 1-7 comprises: Step 1: Select an N-type Ge substrate; Step 2: An intrinsic Ge epitaxial layer is formed on the upper surface of the N-type Ge substrate using an epitaxial process; Step 3: Perform ion implantation or diffusion on the upper surface of the intrinsic Ge epitaxial layer to form a P-type Ge region; Step 4: Electrode deposition is performed on the upper surface of the P-type Ge region and the lower surface of the N-type Ge substrate to form a first metal electrode and a second metal electrode.

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