Power package configured with additional functionality

Abstract

A device includes a power substrate and a first power device on the power substrate. The housing has housing sides including at least a first housing side and a second housing side, the housing being configured to house at least the power substrate and the first power device. A plurality of power terminals extend from at least one of the housing sides. The plurality of power terminals includes at least a first power terminal and a second power terminal. A plurality of signal terminals extend from at least one of the housing sides. The plurality of signal terminals includes at least a source Kelvin signal terminal, a gate driver signal terminal, and at least one additional signal terminal.

Description

Background Technology

[0001] Power electronic packages typically implement one or more power devices (such as silicon carbide (SiC) power devices) that offer high levels of performance benefits, including high voltage blocking, low on-resistance, high current, fast switching, low switching losses, high junction temperature, and high thermal conductivity. Ultimately, these power device characteristics result in a significant increase in potential power density (i.e., power processed per area or volume). However, common power electronic packages have limited functionality and / or capabilities.

[0002] Therefore, what is needed is a power electronics package that can provide layouts, structures, and / or configurations that can offer increased functionality and / or capabilities. Summary of the Invention

[0003] In one aspect, a power package includes a power substrate. The power package further includes a first power device on the power substrate. The package further includes a housing having housing sides, the housing sides having at least a first housing side and a second housing side, the housing being configured to accommodate at least the power substrate and the first power device. The package also includes a plurality of power terminals extending from at least one of the housing sides. The package further includes a plurality of power terminals, the plurality of power terminals having at least a first power terminal and a second power terminal. The package further includes a plurality of signal terminals extending from at least one of the housing sides. The package further includes a plurality of signal terminals, the plurality of signal terminals having at least a source Kelvin signal terminal, a gate driver signal terminal, and at least one additional signal terminal.

[0004] In one aspect, a power package includes a power substrate. The power package further includes a first power device on the power substrate. The package further includes a housing having housing sides, the housing sides having at least a first housing side and a second housing side, the housing 200 being configured to accommodate at least the power substrate and the first power device. The package also includes a plurality of power terminals extending from at least one of the housing sides. The package further includes a plurality of power terminals, the plurality of power terminals having at least a first power terminal and a second power terminal. The package further includes a plurality of signal terminals extending from at least one of the housing sides. The package further includes a plurality of signal terminals, the plurality of signal terminals having at least a source Kelvin signal terminal and a gate driver signal terminal. The package also includes a common source connection connecting the first power device and the second power device.

[0005] Additional features, advantages, and aspects of this disclosure may be revealed or apparent from consideration of the following detailed description, drawings, and claims. Furthermore, it should be understood that both the foregoing summary of this disclosure and the following detailed description are exemplary and intended to provide further explanation, without limiting the scope of the claimed disclosure. Attached Figure Description

[0006] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated herein by reference and forming part of this specification, illustrate aspects of the disclosure and, together with the detailed embodiments, serve to explain the principles of the disclosure. No attempt is made to show more detailed structural details of the disclosure that may be necessary beyond a basic understanding of the disclosure and various possible ways of practicing it. In the drawings: Figure 1 The illustration shows a top perspective view of the external configuration of a power package according to aspects of this disclosure.

[0007] Figure 2 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0008] Figure 3 The diagram illustrates the following: Figure 1 A top view of the configuration of multiple implementations of power packaging.

[0009] Figure 4 The diagram illustrates the following: Figure 1 A top view of the configuration of multiple implementations of power packaging.

[0010] Figure 5A A partial top view of a power package according to aspects of this disclosure is illustrated.

[0011] Figure 5B The diagram illustrates the following: Figure 5A A partial schematic diagram of the power package.

[0012] Figure 6 The illustration shows a partial top perspective view of a power package according to aspects of this disclosure.

[0013] Figure 7 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0014] Figure 8 The illustration shows a partial top perspective view of a power package according to aspects of this disclosure.

[0015] Figure 9 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0016] Figure 10A partial top view of a power package according to aspects of this disclosure is illustrated.

[0017] Figure 11 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0018] Figure 12 The illustration shows a partial top perspective view of a power package according to aspects of this disclosure.

[0019] Figure 13 The illustrations depict various arrangements of multiple power terminals and / or multiple signal terminals within multiple implementations of a power package according to aspects of this disclosure.

[0020] Figure 14 The diagram illustrates the following: Figure 1 A top view of the configuration of multiple implementations of power packaging.

[0021] Figure 15 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0022] Figure 16 The diagram illustrates the following: Figure 15 A schematic diagram of the power package.

[0023] Figure 17 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0024] Figure 18 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0025] Figure 19 The diagram illustrates the following: Figure 18 A schematic diagram of the power package.

[0026] Figure 20 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0027] Figure 21 The diagram illustrates the following: Figure 1 Top-view perspective of the power package.

[0028] Figure 22 The diagram illustrates the following: Figure 21 Side view of the power package.

[0029] Figure 23 The illustration shows a top view of a power package according to aspects of this disclosure.

[0030] Figure 24 The illustration shows a top view of a power package according to aspects of this disclosure.

[0031] Figure 25 A schematic diagram of a power package according to aspects of this disclosure is shown.

[0032] Figure 26 The illustration shows a partial perspective top view of the package according to the present disclosure.

[0033] Figure 27 The diagram illustrates the following: Figure 26 A 3D view of the encapsulation.

[0034] Figure 28 The diagram illustrates the following: Figure 26 A three-dimensional bottom view of the package.

[0035] Figure 29 The illustration shows a schematic diagram of a common source cascode configuration according to aspects of this disclosure.

[0036] Figure 30 The diagram illustrates the following: Figure 29 A 3D view of the common source and common gate configuration.

[0037] Figure 31 The diagram illustrates the implementation based on Figure 29 A top view of a power package with a common source and common gate configuration.

[0038] Figure 32 The diagram illustrates the implementation based on Figure 29 A partial 3D view of a power package with a common source and common gate configuration.

[0039] Figure 33 The diagram illustrates the implementation based on Figure 29 A partial 3D view of a power package with a common source and common gate configuration.

[0040] Figure 34 The diagram illustrates the implementation based on Figure 29 A top view of a power package with a common source and common gate configuration.

[0041] Figure 35 The diagram illustrates the following: Figure 34 A partial top-view perspective of the power package.

[0042] Figure 36 The illustration shows a perspective view of an implementation of a power substrate according to aspects of the present disclosure.

[0043] Figure 37 A perspective view of another implementation of the power substrate 402 according to aspects of this disclosure is shown.

[0044] Figure 38 The illustration shows a perspective view of an implementation of a power package according to aspects of this disclosure.

[0045] Figure 39 The diagram shows... Figure 38A partial 3D view of the power package.

[0046] Figure 40 The diagram shows... Figure 38 A partial 3D view of the power package.

[0047] Figure 41 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0048] Figure 42 The diagram shows... Figure 41 A partial 3D view of the power package.

[0049] Figure 43 The diagram shows... Figure 41 A partial 3D view of the power package.

[0050] Figure 44 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0051] Figure 45 The diagram shows... Figure 44 A partial 3D view of the power package.

[0052] Figure 46 The diagram shows... Figure 44 A partial 3D view of the power package.

[0053] Figure 47 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0054] Figure 48 The diagram shows... Figure 47 A partial 3D view of the power package.

[0055] Figure 49 The illustration shows a top view of a power package of an aspect of this disclosure.

[0056] Figure 50 The diagram illustrates the following: Figure 49 Side view of the power package.

[0057] Figure 51 The illustration shows the configuration of two implementations of the power package according to aspects of this disclosure.

[0058] Figure 52 The illustration shows a configuration of an implementation of a power package according to aspects of this disclosure.

[0059] Figure 53 The illustration shows a configuration of an implementation of a power package according to aspects of this disclosure.

[0060] Figure 54 The illustration shows configurations of several implementations of power packages according to aspects of this disclosure.

[0061] Figure 55 The illustration shows configurations of several implementations of power packages according to aspects of this disclosure.

[0062] Figure 56 The illustration shows a top perspective view of the configuration of various implementations of power packages according to aspects of this disclosure.

[0063] Figure 57 The diagram illustrates the following: Figure 56 A rear view of the configuration of multiple implementations of the power package.

[0064] Figure 58 The illustration shows a cross-sectional view of the configuration of several implementations of power packages according to aspects of this disclosure.

[0065] Figure 59 The diagram illustrates the following: Figure 58 A 3D diagram showing the configuration of multiple implementations of power packaging.

[0066] Figure 60 The illustration shows a perspective view of an implementation of a power substrate according to aspects of the present disclosure.

[0067] Figure 61 A perspective view of another implementation of a power substrate according to aspects of this disclosure is shown.

[0068] Figure 62 The illustration shows a top view of an implementation of a power package according to aspects of this disclosure.

[0069] Figure 63 The diagram illustrates the following: Figure 62 A 3D diagram illustrating the implementation of power packaging.

[0070] Figure 64 The illustration shows a top view of a power package according to aspects of this disclosure.

[0071] Figure 65 The diagram illustrates the following: Figure 64 Top-view perspective of the power package.

[0072] Figure 66 The illustration shows a top view of a power package according to aspects of this disclosure.

[0073] Figure 67 The diagram illustrates the following: Figure 66 Top-view perspective of the power package.

[0074] Figure 68 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0075] Figure 69 The diagram shows... Figure 68A partial 3D view of the power package.

[0076] Figure 70 The illustration shows a top view of a power package of an aspect of this disclosure.

[0077] Figure 71 The diagram illustrates the following: Figure 70 Side view of the power package.

[0078] Figure 72 The illustration shows the configuration of two implementations of the power package according to aspects of this disclosure.

[0079] Figure 73 The illustration shows a configuration of an implementation of a power package according to aspects of this disclosure.

[0080] Figure 74 The illustration shows the configuration of two implementations of the power package according to aspects of this disclosure.

[0081] Figure 75 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0082] Figure 76 The diagram shows... Figure 75 A partial 3D view of the power package.

[0083] Figure 77 The diagram shows... Figure 75 A partial 3D view of the power package. Detailed Implementation

[0084] The various aspects, features, and advantageous details of this disclosure are explained more fully with reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and detailed in the description below. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and as those skilled in the art will recognize, features of one aspect may be adopted together with other aspects even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted to avoid unnecessarily obscuring aspects of this disclosure. The examples used herein are intended only to facilitate an understanding of how this disclosure may be practiced and to further enable those skilled in the art to practice aspects of this disclosure. Therefore, the examples and aspects herein should not be construed as limiting the scope of this disclosure, which is defined only by the appended claims and applicable law. Furthermore, it should be noted that the same reference numerals denote similar components in several views of the drawings.

[0085] Figure 1 The illustration shows a top perspective view of the external configuration of a power package according to aspects of this disclosure.

[0086] Figure 2 The diagram illustrates the following: Figure 1A top view of the external configuration of the power package. Specifically, Figure 1 A power package 100 is illustrated, which may include a housing 200 having housing sides 210, the housing sides including at least a first housing side 201, a second housing side 202, a third housing side 203, and a fourth housing side 204. In some aspects, the first housing side 201 may be connected to the third housing side 203 and the fourth housing side 204; and the second housing side 202 may be connected to the third housing side 203 and the fourth housing side 204. Furthermore, the housing 200 may be configured to have corner portions between the first housing side 201 and the third housing side 203, between the first housing side 201 and the fourth housing side 204, between the second housing side 202 and the third housing side 203, and between the second housing side 202 and the fourth housing side 204.

[0087] Additionally, the power package 100 may include a plurality of power terminals 300 extending from at least one of the housing side portions 210. The plurality of power terminals 300 may include at least a first power terminal 301 and a second power terminal 302.

[0088] Furthermore, the power package 100 may include a plurality of signal terminals 310 extending from at least one of the housing side portions 210. In some aspects, the plurality of signal terminals 310 may include at least a source Kelvin signal terminal, a gate driver signal terminal, and optionally may include at least one additional signal terminal.

[0089] In one aspect, a first power terminal 301 may extend from a first housing side 201 and a second power terminal 302 may extend from a second housing side 202; and at least one of the plurality of signal terminals 310 may extend from the first housing side 201 and at least one of the plurality of signal terminals 310 may extend from the second housing side 202. In other aspects of the power package 100, the plurality of power terminals 300 and / or the plurality of signal terminals 310 may be implemented in other configurations.

[0090] In some aspects, the power package 100 may implement a plurality of signal terminals 310 to include at least one additional electrical terminal, which may be configured to transmit additional capabilities to the power package 100, including current protection such as overcurrent protection, desaturation protection, etc. Furthermore, the power package 100 may implement at least one additional electrical terminal, which may be configured to transmit additional capabilities such as temperature sensing, current sensing, etc. In some aspects, the at least one additional electrical terminal may be configured to provide further insight into what is happening inside the power package 100.

[0091] In some aspects of the power package 100, the multiple power terminals 300 can be modified in size to allow space for at least one additional electrical terminal. For example, the width of the multiple power terminals 300 can be reduced along the X-axis, such as... Figure 2 As illustrated in the figure. In some aspects, the power package 100 can be implemented as a four-terminal single-switch package implementation of the power package 100.

[0092] refer to Figure 1 and Figure 2 The illustration shows a pin configuration of multiple signal terminals 310 with four potential pin locations that can be used for the features described herein. However, the power package 100 can implement any number of the multiple signal terminals 310 described herein.

[0093] In some embodiments, all pin positions of the plurality of signal terminals 310 of power package 100 may be used, while only some of these pin positions are used for power package 100. In some embodiments, only the necessary pins of power package 100 will be used, with the remaining space used for the plurality of power terminals 300. In other embodiments, all pins are present and used for one function. In other embodiments, all pin positions are present but only some are used for one function.

[0094] Furthermore, additional pins / functionality / flexibility can be used in the disclosed implementation of power package 100. Additionally, any similar general-purpose package layout can be implemented using the disclosed plurality of power terminals 300 and / or plurality of signal terminals 310, along with the associated functions of power package 100.

[0095] In some aspects, a first power terminal 301 may extend from a first housing side 201, and a second power terminal 302 may extend from a second housing side 202. In some aspects, a first power terminal 301 may extend from a second housing side 202, and a second power terminal 302 may extend from a first housing side 201.

[0096] In some aspects, some of the plurality of signal terminals 310 may extend from the first housing side 201, and some of the plurality of signal terminals 310 may extend from the second housing side 202. In some aspects, all of the plurality of signal terminals 310 may extend from the second housing side 202. In some aspects, all of the plurality of signal terminals 310 may extend from the first housing side 201.

[0097] In some aspects, at least two of the plurality of signal terminals 310 may extend from the first housing side 201, and at least two of the plurality of signal terminals 310 may extend from the second housing side 202. In some aspects, at least two of the plurality of signal terminals 310 may extend from the second housing side 202, and at least two of the plurality of signal terminals 310 may extend from the first housing side 201.

[0098] Figure 3 The diagram illustrates the following: Figure 1 A top view of the configuration of multiple implementations of power packaging.

[0099] Specifically, Figure 3 The diagram illustrates multiple bases. Figure 1 A top view of the configuration 102 of the power package 100 implementation. In this regard, additional flexibility can be found in the arrangement of the power package 100 to form topologies such as half-bridge topologies, common-source topologies, etc. In these aspects, the multiple signal terminals 310 can be implemented as single pins and / or pin pairs, depending on the type of electrical connection and isolation required by the configuration 102. Furthermore, aspects of implementing the common-source topology of the power package 100 can include any and all aspects of the common-source topology implementations of the power package 100 described herein.

[0100] like Figure 3 As illustrated, configuration 102 can have multiple implementations of power packages 100. In some aspects, the multiple implementations of power packages 100 can be arranged in a bridge leg configuration topology. In this regard, a first power terminal 301 of one implementation of power package 100 can be connected to a second power terminal 302 of another implementation of power package 100 (e.g., ...). Figure 3 (as illustrated in the diagram) to provide the desired topology implementation.

[0101] In other respects, the power package 100 and / or the configuration of multiple power packages 100 can realize any number of topologies. For example, the power package 100 and / or the configuration of multiple power packages 100 can realize single-switch topologies, half-bridge topologies, full-bridge topologies, common-source topologies, common-drain topologies, three-phase bridge topologies, 3-level inverter T-type topologies, 3-level inverter NPC (neutral point clamping) topologies, 3-level inverter VSC (voltage source converter) topologies, buck topologies, boost topologies, buck-boost topologies, and / or UK topology.

[0102] Figure 4 The diagram illustrates the following: Figure 1 A top view of the configuration of multiple implementations of power packaging.

[0103] Specifically, Figure 4 The diagram illustrates multiple bases. Figure 1 A top view of the configuration 104 for the implementation of the power package 100. (See attached diagram.) Figure 4 As illustrated, the configuration 104 of multiple power package 100 implementations can be arranged in a parallel bridge arm configuration topology. In this regard, the first power terminal 301 of one implementation of the power package 100 can be connected to the second power terminal 302 of another implementation of the power package 100 (e.g., ...). Figure 4 (as illustrated in the diagram) to provide the desired topology implementation.

[0104] Figure 5A A partial top view of a power package according to aspects of this disclosure is illustrated.

[0105] Figure 5B The diagram illustrates the following: Figure 5A A partial schematic diagram of the power package.

[0106] Figure 6 The illustration shows a partial top perspective view of a power package according to aspects of this disclosure.

[0107] Specifically, Figure 5A A partial top view of a power package 100 according to aspects of this disclosure is illustrated. The power package 100 may further include a power substrate 402 and at least one power device 404 on the power substrate 402. Furthermore, the at least one power device 404 may include multiple implementations of the at least one power device 404. Additionally, Figure 1 The housing 200 shown in the diagram (not in) Figure 5A (As shown in the diagram) can be configured to accommodate at least a power substrate 402 and at least one power device 404. Additionally, Figure 5B The diagram illustrates the following: Figure 5A A partial schematic diagram of the power package 100.

[0108] like Figure 5A As further illustrated, the power package 100 may be configured with a plurality of signal terminals 310. In some aspects, at least one implementation of the plurality of signal terminals 310 may be configured as at least one additional signal terminal 312. In some aspects, the at least one additional signal terminal 312 may be configured as an overcurrent / desaturation signal terminal, which is configured to provide an overcurrent signal and / or desaturation signal from the power package 100.

[0109] In some aspects, at least one additional signal terminal 312 may be configured as a signal pin that can be connected to a drain pad 406 on the power substrate 402. In some aspects, at least one additional signal terminal 312 may be configured to allow gate drivers, controllers, measurement / instrumentation circuitry, etc., to monitor the voltage across the switching position of at least one power device 404. In some aspects, the monitored voltage may be used as a protection feature against short-circuit current events associated with the power package 100, overcurrent protection for the power package 100, and / or desaturation protection for the power package 100. In this regard, when at least one power device 404 is turned on, the voltage drop is typically proportional to the current. Depending on the device type and semiconductor characteristics, the relationship is non-linear when at least one power device 404 is saturated. This relationship can be used to predict short-circuit events where the current exceeds a safe threshold.

[0110] exist Figure 5A The diagram illustrates an example of a desaturation pin implemented by at least one additional signal terminal 312. In this regard, only one pin may be required for this function. However, in other implementations, two pins may be used for other reasons, such as symmetry, redundancy, etc. Other embodiments may position at least one additional signal terminal 312 at any location on the other side of the power package 100, depending on the specific configuration of the power package 100.

[0111] In some aspects, at least one additional signal terminal 312 may be electrically connected to the drain pad 406 of the power substrate 402 using an interconnect structure 408. In some aspects, the interconnect structure 408 may be a wire bond between at least one additional signal terminal 312 and the drain pad 406. In some aspects, at least one additional signal terminal 312 may also be configured and arranged to extend across the power substrate 402; and at least one additional signal terminal 312 may be positioned by brazing, soldering, sintering, etc., to form a connection to the power substrate 402. Alternatively, at least one additional signal terminal 312 may also be directly attached to the drain pad 406. In some aspects, the implementation of the interconnect structure 408 described herein may use any type of interconnect configuration and / or interconnect process. In some aspects, the interconnect configuration and / or interconnect process may include various electrical and mechanical connections, including one or more wires, wire bonds, strips, strip bonds, clamps, spring contacts, traces, mechanical fasteners, etc. In addition, interconnect configurations and / or interconnect processes may include welded portions, welding, brazing portions, brazing, adhesives, adhesive portions, conductive epoxy resins, sintering, sintered portions, sintering processes, etc.

[0112] Figure 7 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0113] Specifically, Figure 7 A partial top view of a power package 100 according to aspects of this disclosure is illustrated. Specifically, Figure 7 The illustration shows an implementation of at least one additional signal terminal 312 configured for current sensing. Current sensing can be implemented using a current sensor integrated on at least one power device 404. Alternatively, current sensing can also be measured from the voltage drop across a series shunt resistor circuit implemented within the power package 100. Furthermore, current sensing in the power package 100 can be measured magnetically using a sensor for measuring magnetic fields.

[0114] In some aspects, the power package 100 can implement current sensing using an on-chip current sensor 414. In some aspects, the on-chip current sensor 414 can be implemented using at least one power device 404. In some aspects, the on-chip current sensor 414 can utilize dedicated bonding terminals 416 on the power substrate 402.

[0115] In some aspects, the interconnect structure 408 may extend between the on-chip current sensor 414, dedicated bonding terminals 416, at least one additional signal terminal 312, etc. In other aspects, the interconnect structure 408 may be directly bonded to at least one additional signal terminal 312, and traces on the power substrate 402 may be used as one or more gap jumpers for connection between at least one additional signal terminal 312 and the on-chip current sensor 414 (reducing wire bonding length). Depending on the voltage isolation requirements of the gate driver PCB, drain-side or source-side pins may be used to connect to the on-chip current sensor 414.

[0116] exist Figure 7 In one aspect illustrated, at least one additional signal terminal 312 can be implemented as two pins added to the opposite side of the source side of the power package 100. Furthermore, two bonding pads on at least one power device 404 can be used to connect to an on-chip current sensor 414, which can be wire-bonded to dedicated bonding terminals 416 on the power substrate 402. Alternatively, an interconnect structure 408 can extend from the on-chip current sensor 414 to at least one additional signal terminal 312. In this regard, the specific implementation can depend on the size, location, bonding pad configuration, etc., of at least one power device 404, which can vary across multiple device types and applications. In some aspects, at least one additional signal terminal 312 can also be constructed and arranged to extend across the power substrate 402; and at least one additional signal terminal 312 can be positioned by soldering, welding, sintering, etc., to form a connection to the power substrate 402. Additionally, at least one additional signal terminal 312 can also be directly attached to the drain pad 406.

[0117] Although Figure 7 The illustration shows an implementation using an on-chip current sensor 414, but other implementations using dedicated sensing elements for current measurement are also envisioned. These dedicated sensing elements could be shunts, sensors, etc. Furthermore, the sensing element can be implemented as an add-on component, integrated into at least one power device 404, directly embedded in at least one power device 404, etc., and may include an electrical connection between a dedicated bonding terminal 416 and / or at least one additional signal terminal 312.

[0118] Figure 8 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0119] Figure 9 The illustration shows a partial top perspective view of a power package according to aspects of this disclosure.

[0120] Figure 10 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0121] Specifically, Figure 8 A partial top view of a power package 100 according to aspects of this disclosure is illustrated. Specifically, Figure 8 The illustration shows an implementation of at least one additional signal terminal 312 configured for temperature sensing. Temperature sensing can provide insights into many important factors during the operation of power package 100. Knowing the temperature of at least one power device 404 and / or other components of power package 100 allows for precise control over the current, power, etc., that power package 100 can handle. Furthermore, temperature sensing can be used to detect overcurrent events, overheating events, etc., as a safety mechanism for power package 100. Temperature sensing can also help implement a system for power package 100 that uses calibrated lifetime models, task profiles, etc., to optimally assess product lifetime, aligning product lifetime with the temperature difference of power package 100 under various operating conditions.

[0122] Temperature sensing within the power package 100 can be achieved in various ways. In one aspect, temperature sensing can be achieved using an on-chip temperature sensor 418. In other aspects, the on-chip temperature sensor 418 can be implemented using dedicated bonding terminals 416, interconnect structures 408, etc., which are generally implemented in a manner substantially consistent with the on-chip current sensor 414 described above.

[0123] Figure 11 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0124] Figure 12 The illustration shows a partial top perspective view of a power package according to aspects of this disclosure.

[0125] Specifically, Figure 11 A partial top view of a power package 100 according to aspects of this disclosure is illustrated. Specifically, Figure 11 The illustration shows an implementation of at least one additional signal terminal 312 configured for temperature sensing, where temperature can be sensed using a temperature sensing chip or a temperature sensing device 420 (such as a negative temperature coefficient (NTC) resistor, a resistance temperature device (RTD), a sensor integrated in the power substrate 402, etc.). In some aspects, some temperature sensing devices may have built-in electrical isolation, while some temperature sensing devices may need to be placed on isolation pads on the power substrate 402. In this regard, the temperature sensing device 420 can be implemented as an isolated temperature sensing device, and / or can be implemented as a non-isolated temperature sensing device. Furthermore, the placement of the temperature sensing device 420 may be near the drain contact of at least one power device 404, near the source contact of at least one power device 404, etc., and may include variations in associated structures (such as leadframes and power substrate 402) for the power package 100 to accommodate a specific device format.

[0126] In addition, although the accompanying drawings depict the implementation of the on-chip temperature sensor 418 and the temperature sensing device 420, other implementations for temperature measurement using dedicated sensing elements (such as NTC, RTD, thermistor, etc.) are also envisioned, either as additional components or directly integrated / embedded into the power substrate 402.

[0127] Figure 13 The illustration shows the arrangement of multiple power terminals and / or multiple signal terminals within a power package implementation according to aspects of this disclosure.

[0128] Specifically, Figure 13 The illustration shows the arrangement of multiple power terminals 300 and / or multiple signal terminals 310 within an implementation of power package 100 according to aspects of this disclosure. In this regard, utilizing the four possible pin locations of the multiple signal terminals 310, space may exist on the left side, the right side, or both sides of the housing 200 of power package 100 for implementing the multiple signal terminals 310 as gate and source Kelvin connections.

[0129] These implementations of multiple signal terminals 310 can be found in some implementations of the power package 100 where a low, matched impedance is desired for the signal loops between parallel implementations of the power package 100. Figure 13The diagram illustrates an example configuration of multiple signal terminals 310 and / or multiple power terminals 300 on the housing 200 of the power package 100. In some aspects, the drain power contacts of the multiple power terminals 300 can be modified to provide clearance from the multiple signal terminals 310 when the positions are arranged in series as bridge arms.

[0130] In some aspects, the plurality of signal terminals 310 may be symmetrically arranged on the housing side 210. In some aspects, the plurality of signal terminals 310 may be asymmetrically arranged on the housing side 210. In some aspects, the plurality of signal terminals 310 may be symmetrically arranged on the first housing side 201 or the second housing side 202. In some aspects, all of the plurality of signal terminals 310 may be asymmetrically arranged on the first housing side 201 or the second housing side 202. In some aspects, a first power terminal 301 may extend from the first housing side 201 and a second power terminal 302 may extend from the second housing side 202; and the plurality of signal terminals 310 may originate from the second housing side 202.

[0131] In some aspects, all of the plurality of signal terminals 310 may be located on the first housing side 201 or the second housing side 202; and all of the plurality of signal terminals 310 may be located on one side of one of the plurality of power terminals 300. In some aspects, all of the plurality of signal terminals 310 may be located on the first housing side 201 or the second housing side 202; and all of the plurality of signal terminals 310 may be located on both sides of one of the plurality of power terminals 300.

[0132] Figure 14 The diagram illustrates the following: Figure 1 A top view of the configuration of multiple implementations of power packaging.

[0133] Specifically, Figure 14 The diagram illustrates multiple bases. Figure 1 The diagram shows a top view of a configuration 105 for an implementation of the power package 100. As an example, if two implementations of the power package 100 are preferably connected in parallel for each bridge arm, the right-side implementation of the power package 100 can be paired with the left-side implementation of the power package 100 such that their respective implementations of multiple signal terminals 310 are positioned close together. These implementations of the power package 100 with multiple signal terminals 310 can be defined as signal pin clusters, which can be grouped such that the effective paths from the gate driver to each individual implementation of the power package 100, for example, via signal loops, can be matched as closely as possible. In this respect, configuration 105 also simplifies the routing, layout, etc., of components in a system implementing the power package 100, such as a gate driver PCB.

[0134] In some aspects, the configuration of at least two implementations of the power package 100 can be implemented such that all of the plurality of signal terminals 310 of the at least two implementations of the power package 100 can be arranged to cluster along adjacent corners of the at least two implementations of the power package 100.

[0135] Figure 15 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0136] Figure 16 The diagram illustrates the following: Figure 15 A schematic diagram of the power package.

[0137] Figure 17 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0138] Specifically, the power package 100 is configured to allow power pins and signal pins to be implemented in multiple locations and positions, including the previously discussed implementations of multiple power terminals 300 and multiple signal terminals 310. Furthermore, the power package 100 can be used in other topologies employing multiple switching positions.

[0139] In this regard, Figure 15 The illustration shows an implementation of a power package 100 configured with a common-source module topology. In some aspects, Figure 15 The power package 100 can be implemented in a manner that includes at least two implementations of at least one power device 404 bonded together at their respective source terminals, such as... Figure 16 As shown in the diagram.

[0140] Specifically, Figure 15 The power package 100 can be implemented in a manner that includes multiple power terminals 300 configured as two power terminals and labeled as drain 1 and drain 2. Additionally, Figure 15 The power package 100 can be implemented in a manner that includes multiple signal terminals 310, which are configured as four signal terminals and labeled as source Kelvin 1, source Kelvin 2, gate 1, and gate 2.

[0141] like Figure 15 As illustrated, the power package 100 may be configured with an exemplary external layout such that, for each of the two switching positions, a plurality of signal terminals 310 are arranged on one side of the housing side 210 of the power package 100, and a plurality of power terminals 300 are arranged on the other side of the housing side 210 of the power package 100.

[0142] like Figure 17As illustrated, the power package 100 can alternatively be configured with a plurality of signal terminals 310 arranged at opposite corners of the housing 200. In some aspects, Figure 17 The arrangement of the power package 100 shown in the figure allows for a more rational internal layout and improved manufacturability / footprint utilization.

[0143] In some aspects of the power package 100 configured with a common-source topology, a first power terminal 301 may extend from a first housing side 201; a second power terminal 302 may extend from a second housing side 202; a first implementation of a plurality of signal terminals 310 may extend from the first housing side 201; and a second implementation of the plurality of signal terminals 310 may extend from the second housing side 202. In some aspects of the power package 100, the first implementation of the plurality of signal terminals 310 may be arranged adjacent to a third housing side 203; and the second implementation of the plurality of signal terminals 310 may be arranged adjacent to the third housing side 203. In some aspects of the power package 100, the first implementation of the plurality of signal terminals 310 may be arranged adjacent to the third housing side 203; and the second implementation of the plurality of signal terminals 310 may be arranged adjacent to a fourth housing side.

[0144] Figure 18 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0145] Figure 19 The diagram illustrates the following: Figure 18 A schematic diagram of the power package.

[0146] Figure 20 The diagram illustrates the following: Figure 1 Top view of the external configuration of the power package.

[0147] Specifically, the power package 100 is configured with another potentially useful topology, in this case a half-bridge topology. While two in a single switch position package can be connected in series to form one, in some cases, lower current and a more compact module may be a more desirable solution.

[0148] In this regard, aspects of the power package 100 can be configured to implement at least one power device 404 in four different ways. Therefore, the power package 100 can be configured to accommodate at least one power device 404 to implement a half-bridge topology within the same common footprint. Furthermore, the power package 100 implementing the half-bridge topology may also include a third power terminal 303.

[0149] Figure 19The diagram schematically illustrates the arrangement and connection between a plurality of signal terminals 310, a first power terminal 301, a second power terminal 302 and a third power terminal 303 for implementing a power package 100 with a half-bridge topology.

[0150] like Figure 18 As illustrated, multiple signal terminals 310, a first power terminal 301, a second power terminal 302, and a third power terminal 303 can be configured and arranged for simpler external connections. Figure 18 As illustrated, the power package 100 can be configured such that a plurality of signal terminals 310 are arranged on one side of the housing side 210 of the power package 100, and a first power terminal 301, a second power terminal 302 and a third power terminal 303 are arranged on the other side of the housing side 210 of the power package 100.

[0151] Alternatively, such as Figure 20 As illustrated, multiple signal terminals 310, a first power terminal 301, a second power terminal 302, and a third power terminal 303 can be constructed and arranged together with the power package 100, allowing for a more rational internal layout. The power package 100 can be configured with the flexibility to allow for additional implementations and positions of the multiple signal terminals 310, enabling many implementations of the power package 100. For example... Figure 20 As illustrated, the power package 100 can be configured such that multiple signal terminals 310 are arranged at two opposite corners of the housing 200. Furthermore, although the various figures show the marked arrangement and / or positions of the multiple signal terminals 310 as gates, source Kelvin sources, etc., aspects of the power package 100 can arrange the multiple signal terminals 310 in any manner or position. For example, the implementation and / or positions of the multiple signal terminals 310 as gates, Kelvin sources, etc., can be interchanged.

[0152] In some aspects of the power package 100 configured with a half-bridge topology, a plurality of power terminals 300 may include at least a third power terminal 303; the third power terminal 303 may extend from a first housing side 201; the first power terminal 301 may extend from the first housing side 201; the second power terminal 302 may extend from the second housing side 202; a first implementation of a plurality of signal terminals 310 may extend from the first housing side 201; and a second implementation of a plurality of signal terminals 310 may extend from the second housing side 202.

[0153] In another aspect, the power package 100 may implement a creepage distance extender 212. In some aspects, the creepage distance extender 212 may be located between the second power terminal 302 and the third power terminal 303 to meet voltage safety standards. In some aspects, the creepage distance extender 212 may increase the surface distance along an insulator, which may include a housing 200 and may be implemented as a trench (as shown) or alternatively as a rib. In some aspects, the creepage distance extender 212 may be disposed on the first housing side 201 between the third power terminal 303 and the first power terminal 301. In other aspects, the creepage distance extender 212 may be disposed anywhere on the housing 200, on the housing side 210, between any implementation of the plurality of power terminals 300, between any implementation of the plurality of signal terminals 310, or anywhere on any surface of the power package 100. Furthermore, the creepage distance extender 212 may be present in multiple implementations.

[0154] Figure 21 The diagram illustrates the following: Figure 1 Top-view perspective of the power package.

[0155] Figure 22 The diagram illustrates the following: Figure 21 Side view of the power package.

[0156] In some respects, it can be beneficial to provide additional structural support for the power package 100. In this regard, when multiple power terminals 300 and / or multiple signal terminals 310 are added to multiple sides of the power package 100, the gate driver may apply greater strain to the multiple signal terminals 310 because the pins are all bonded to the same rigid body.

[0157] In this configuration, the "shoulder" of the pin can receive additional support through a bushing structure 220 implemented on the housing 200. Specifically, the bushing structure 220 can be disposed on the housing 200 and can be formed from a molding compound used to form the housing 200. In this regard, the bushing structure 220 can provide mechanical support for the plurality of signal terminals 310 engaging with the body of the housing 200, for example, formed from a molding compound. In some aspects, the bushing structure 220 can be configured to surround and mechanically support at least one of the plurality of signal terminals 310.

[0158] Figure 23 The illustration shows a top view of a power package according to aspects of this disclosure.

[0159] Figure 24 The illustration shows a top view of a power package according to aspects of this disclosure.

[0160] Figure 25A schematic diagram of a power package according to aspects of this disclosure is shown.

[0161] Specifically, in Figure 23 , Figure 24 and Figure 25 The power package 100 illustrated herein can be configured to include additional electrical terminals to accommodate power and signal terminals specific to a common-source topology. Furthermore, the power package 100 may optionally include any other aspects described and illustrated herein.

[0162] In some aspects, the power package 100 may be configured such that a plurality of power terminals 300 are arranged on one side of the housing 200, and at least one of a plurality of signal terminals 310 is arranged on the other side of the housing 200. For example, the plurality of power terminals 300 may be arranged on a first housing side 201, and at least one of the plurality of signal terminals 310 may be arranged on a second housing side 202; or the plurality of power terminals 300 may be arranged on a second housing side 202, and at least one of the plurality of signal terminals 310 may be arranged on a first housing side 201.

[0163] In other aspects, the power package 100 may be configured such that a plurality of power terminals 300 are arranged on two sides of the housing 200, and at least one of a plurality of signal terminals 310 is arranged on both sides of the housing 200. For example, some of the plurality of power terminals 300 may be arranged on a first housing side 201, some of at least one of the plurality of signal terminals 310 may be arranged on the first housing side 201, some of the plurality of power terminals 300 may be arranged on a second housing side 202, and some of at least one of the plurality of signal terminals 310 may be arranged on the second housing side 202.

[0164] In some aspects, the multiple power terminals 300 may be at a high voltage potential and may need to be configured and / or constructed on the housing 200, with appropriate surface distances (creepage) and air distances (gap) between the implementations of the multiple power terminals 300 to meet safety standards based on system voltage levels. In other aspects, the power package 100 may be configured with a creepage distance extender 212 on the housing 200 as previously discussed (not shown). On the other hand, at least one of the multiple signal terminals 310 may be at a low voltage potential and may not require large distances for electrical isolation. Additionally, Figure 23 The implementation method shown in the figure and Figure 24 The implementations illustrated in the diagrams can each be applied to different system-level methods described later in this disclosure. Furthermore, Figure 25 An exemplary schematic diagram of a power package 100 configured with the common-source topology described herein is illustrated.

[0165] Figure 26 The illustration shows a partial perspective top view of the package according to the present disclosure.

[0166] Figure 27 The diagram illustrates the following: Figure 26 A 3D view of the encapsulation.

[0167] Figure 28 The diagram illustrates the following: Figure 26 A three-dimensional bottom view of the package.

[0168] Aspects of the power package 100 may include external features, such as a molded compound housing 200, a creepage distance extender that can increase voltage safety, at least one of a plurality of power terminals 300, and a plurality of signal terminals 310. Aspects of the power package 100 may include internal features, which may include at least one power device 404, a power substrate 402, power interconnects, and signal interconnect structures. It should be noted that specific implementations of the power package 100 may vary in the format and layout of the internal structure. For example, the power package 100 may be implemented using power wire bonding, or power interconnects may be implemented using tape instead of fixtures. Fixtures are used in all examples of this disclosure. However, the power package 100 may utilize implementations with other interconnect methods, including the interconnect configurations and / or interconnect processes described herein.

[0169] Furthermore, the disclosed power package 100 can be configured to enable multiple implementations of the methods and structures described herein. As an example, the power package 100 can be implemented with at least one power device 404 of varying numbers (1, 2, 3, 4, etc.), and can be laid out in at least two ways: the power package 100 can be configured to keep all devices in the same position and fill only the positions required for a given output current demand; and / or the power package 100 can be configured to place the devices in optimal positions within a layout optimized for a given number of at least one power device 404.

[0170] Figure 29 The illustration shows a schematic diagram of a common source cascode configuration according to aspects of this disclosure.

[0171] Figure 30 The diagram illustrates the following: Figure 29 A 3D view of the common source and common gate configuration.

[0172] Figure 31 The diagram illustrates the implementation based on Figure 29 A top view of a power package with a common source and common gate configuration.

[0173] Figure 32 The diagram illustrates the implementation based on Figure 29A partial 3D view of a power package with a common source and common gate configuration.

[0174] Figure 33 The diagram illustrates the implementation based on Figure 29 A partial 3D view of a power package with a common source and common gate configuration.

[0175] Figure 34 The diagram illustrates the implementation based on Figure 29 A top view of a power package with a common source and common gate configuration.

[0176] Figure 35 The diagram illustrates the following: Figure 34 A partial top-view perspective of the power package.

[0177] Specifically, Figure 29 A schematic diagram of a cascode configuration 600 is illustrated. The cascode configuration 600 can be used in any aspect of the power package 100 described herein. Furthermore, the cascode configuration 600 can be used with any implementation type of at least one power device 404 implemented by the power package 100.

[0178] The following example implementations of the cascode configuration 600 in power package 100 may relate to, for example, a specific implementation of at least one power device 404. In this regard, for normally-on devices (such as JFETs (junction field-effect transistors)) and similar depletion-mode devices, the cascode configuration 600 may be configured to add a normally-off low-voltage device 604 (such as a MOSFET (metal-oxide-semiconductor field-effect transistor)) to form a cascode topology. The MOSFET may be connected in series with the JFET such that the source of the JFET is connected to the drain of the MOSFET, and the source of the MOSFET may be connected to the gate of the JFET. When the MOSFET is off, its drain-source voltage exceeds the pinch-off voltage of the JFET. When the MOSFET is on, the JFET is allowed to return to its normally-on state.

[0179] refer to Figure 29 The cascode configuration 600 can be implemented using cascode topologies for JFETs and MOSFETs. However, the cascode configuration 600 can be implemented using other types of devices. Given the expectation of a compact, power-dense footprint, implementing this topology in the power package 100 can be challenging. Furthermore, adding additional devices in high-current paths requires design considerations and trade-offs. This is because the devices are effectively placed in series for power loops, such as JFET drains, JFET sources, MOSFET drains, MOSFET sources, etc.

[0180] Therefore, aspects of the cascode configuration 600 can be implemented using the following configuration and / or method: a normally-off low-voltage device 604 (such as a low-voltage MOSFET) can be stacked on top of at least one power device 404 (such as a high-voltage JFET). This directly interconnects the JFET source with the MOSFET drain, and the connection from the MOSFET source to the JFET drain is implemented using an interconnect structure 408 (such as wire bonding, the interconnect configurations described herein, and / or interconnect processes). Furthermore, the normally-off low-voltage device 604 can be attached to at least one power device 404 using a power attachment 606. The power attachment 606 may include adhesive, solder, etc.

[0181] Figure 30 , Figure 31 , Figure 32 and Figure 33 The illustration shows an implementation of a power package 100 that implements a cascode configuration 600 in an exemplary stacked cascode layout. In this regard, as illustrated, the power package 100 includes four implementations of at least one power device 404. It should be noted that, to achieve parallel connection for each switching position, the signal connections implemented by the interconnect structure 408 can be formed using spliced ​​wire bonds. Spliced ​​wire bonds can bond multiple devices (normally off low-voltage device 604 and / or at least one power device 404) together while avoiding gaps or collisions in the wire bonds during manufacturing. It should be noted that in some embodiments, signal bonds may not be spliced ​​(as shown) and may be individual bonds.

[0182] Figure 34 and Figure 35 An alternative layout for the cascode configuration 600 is illustrated, in which a normally-off low-voltage device 604 and at least one power device 404 can be packaged side-by-side on a power substrate 402. Here, gap pads on the power substrate 402 can be used to form the correct interconnect between the normally-off low-voltage device 604 and the at least one power device 404. Figure 34 and Figure 35 In this embodiment, a fixture 610 can be used to connect the source of at least one power device 404 (such as a high-voltage JFET source) to the drain trace of a normally-off low-voltage device 604 (such as a low-voltage MOSFET on a power substrate 402). In some embodiments, the connection can be formed using wires, strips, similar interconnect methods, and / or the interconnect configurations and / or interconnect processes described herein.

[0183] It should be noted that the cascode configuration 600 is illustrated as a single-device implementation with at least one power device 404 and a normally-off low-voltage device 604 (i.e., a normally-off MOSFET or a normally-on JFET). However, the cascode configuration 600 can be implemented with any type or number of implementations of at least one power device 404 and / or normally-off low-voltage device 604.

[0184] Figure 36 The illustration shows a perspective view of an implementation of a power substrate according to aspects of the present disclosure.

[0185] Figure 37 A perspective view of another implementation of the power substrate 402 according to aspects of this disclosure is shown.

[0186] Figure 38 The illustration shows a perspective view of an implementation of a power package according to aspects of this disclosure.

[0187] Specifically, Figure 38 The illustration shows an implementation of a power package 100 configured such that a plurality of power terminals 300 are arranged on one side of a housing 200 and / or a power substrate 402, while at least one of a plurality of signal terminals 310 is located on the other side of the housing 200 and / or the power substrate 402. The internal layout of the power package 100, along with the external terminal arrangement, can vary based on the number of at least one power device 404, the source Kelvin implementation, performance optimization, etc. While the illustrated layout of the power package 100 described and illustrated can be referenced using an implementation of at least one power device 404 of the same size, other embodiments of the power package 100 utilizing modular layout to optimally meet the power requirements of a given system are possible.

[0188] In some aspects of this disclosure, the power package 100 may implement a fully filled device location of at least one power device 404, a partially filled device location of at least one power device 404, larger and smaller size implementations of at least one power device 404, implementations of at least one power device 404 with different gate and source pad sizes and arrangements, a top-side fixture variation adapted to the gate and source pad configuration of at least one power device 404, power wire bonding / with interconnects instead of a top-side fixture, and / or interconnect configurations and / or interconnect processes described herein.

[0189] Figure 36 An exemplary layout of a power substrate 402 is illustrated, which can be implemented in any aspect of the power package 100 as described herein, including Figure 38 The implementation method is illustrated in the diagram. (For example...) Figure 36As illustrated, the power substrate 402 can be implemented using a main power trace 412. In some aspects, the power substrate 402 can be configured with two implementations of the main power trace 412 for each drain of at least one power device 404. The implementation of at least one power device 404 can be attached to the main power trace 412. In some aspects, the implementation of at least one power device 404 can be attached at the center of the main power trace 412 to minimize thermal resistance by maximizing thermal diffusion effects.

[0190] like Figure 37 As illustrated, in some cases, the power substrate 402 can be implemented such that additional traces 424 are added to the power substrate 402 to accommodate additional functionality. In one case, one or more implementations of the additional traces 424 can be added to the power substrate 402 to act as gaps to reduce wire bond lengths. In other cases, the power substrate 402 can be configured as isolated traces that can be added to the power substrate 402 to accommodate sensing elements, such as the temperature sensor described herein.

[0191] Figure 39 The diagram shows... Figure 38 A partial 3D view of the power package.

[0192] Figure 40 The diagram shows... Figure 38 A partial 3D view of the power package.

[0193] Figure 39 The illustration shows one aspect of a power package 100, which is configured with at least one power device 404 in two implementations. Here, the power substrate 402 can be divided into two configurations of the main power trace 412. Additionally, the power package 100 is also configured with a clamp 426. In some aspects, the clamp 426 can be attached to the top side of at least one power device 404 and configured to form a common source connection.

[0194] At least one power device 404 may be configured with signal pads, which may be configured to be directly wire-bonded to at least one of a plurality of signal terminals 310. In some aspects, this connection may form a true source Kelvin signal loop 428. In other aspects, a fixture 426 may be integrated into an integral lead frame, with the connection portion 430 remaining after the power package 100 is removed from the lead frame assembly. This is possible because the source may be at the same voltage potential as the source Kelvin, thus eliminating the need for voltage creep or gap distance.

[0195] Figure 41 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0196] Figure 42 The diagram shows... Figure 41 A partial 3D view of the power package.

[0197] Figure 43 The diagram shows... Figure 41 A partial 3D view of the power package.

[0198] Specifically, Figure 41 , Figure 42 and Figure 43 The illustration shows an implementation of a power package 100 configured with isolated island traces 432 that can be arranged on a power substrate 402 to act as gaps for bonding, thereby reducing the overall wire bond length. In this aspect of the power package 100, this configuration can improve the manufacturability of wire bonding and prevent wire sweep during molding processes associated with the housing 200. Additionally, if the power package 100 includes two implementations of at least one power device 404, there may be available space. Therefore, true Kelvin connections are possible.

[0199] Figure 44 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0200] Figure 45 The diagram shows... Figure 44 A partial 3D view of the power package.

[0201] Figure 46 The diagram shows... Figure 44 A partial 3D view of the power package.

[0202] refer to Figure 44 , Figure 45 and Figure 46 In some implementations of the power package 100, a pseudo-source Kelvin configuration 436 may be sufficient for operation. Therefore, additional metal surrounding at least one power device 404 can be used to enhance thermal diffusion. This additional metal can form an enhanced thermal region 434. Here, only gate bonding and their associated bonding islands may be necessary, which can be achieved via additional traces 424.

[0203] Figure 47 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0204] Figure 48 The diagram shows... Figure 47 A partial 3D view of the power package.

[0205] refer to Figure 47 and Figure 48In some aspects of the power package 100, at least one power device 404 in another row may be configured. This configuration of the power package 100 can significantly increase the output power.

[0206] In addition, such as Figure 48 As illustrated, the power package 100 may also include source contacts 438. Additionally, the source contacts 438 may have a undulating structure 480 to connect to the upper row of at least one power device 404. It should be noted that while each implementation of at least one power device 404 in the figure may be configured with an individual gate bond, in some cases it may be useful to stitch the gate bonds of each switching location of the power package 100 together.

[0207] Figure 49 The illustration shows a top view of the power package of various aspects of this disclosure.

[0208] Figure 50 The diagram illustrates the following: Figure 49 Side view of the power package.

[0209] Specifically, Figure 49 and Figure 50 The illustration shows an implementation of power package 100, in which multiple power terminals 300 can be offset such that two adjacent implementations of power package 100 can be placed back-to-back to effectively parallel the switching positions of power package 100, thereby increasing the total output current. In some aspects, the offset 440 can arrange one implementation of multiple power terminals 300 to be spaced apart from another implementation of multiple power terminals 300 along the X-axis, such as... Figure 50 As shown in the diagram.

[0210] Offset 440 allows for staggering between power terminals in adjacent implementations of the power package 100, while facilitating easy electrical and mechanical connections via soldering, brazing, etc. Additionally, the multiple power terminals 300 can be configured with bends 442. In some aspects, the bends 442 may be spring-like bends incorporated into the multiple power terminals 300 to act as strain relief for the two implementations of the power package 100 joined together.

[0211] Figure 51 The illustration shows the configuration of two implementations of the power package according to aspects of this disclosure.

[0212] Specifically, Figure 51 The illustration shows configurations 106 of two implementations of the power package 100 according to aspects of this disclosure. In this regard, Figure 49The diagram illustrates a set of two implementations of power package 100. In configuration 106, the two implementations of power package 100 may have interleaved power connections 444 formed by corresponding implementations of a plurality of power terminals 300. In some aspects, the implementations of the plurality of power terminals 300 may be configured such that a higher-height contact from one implementation of power package 100 engages with a lower-height contact implementation of a plurality of power terminals 300 from another implementation of power package 100.

[0213] Figure 52 The illustration shows a configuration of an implementation of a power package according to aspects of this disclosure.

[0214] Specifically, Figure 52 The illustration shows configuration 107 when a larger output current is required. Specifically, configuration 107 illustrates additional parallel connection that can be achieved using a linear array of power packages 100.

[0215] This represents a very high level of modularity and scalability, where each power package 100 can be configured internally (device count and size) and externally (parallel packaging) to best meet the needs of implementing the system of configuration 107.

[0216] Figure 53 The illustration shows a configuration of an implementation of a power package according to aspects of this disclosure.

[0217] Specifically, Figure 53 The illustration shows configuration 108, which may include multiple single-switch implementations of a power package 100 that can be configured as a T-topology. In configuration 108, a drain connection of multiple power terminals 300 implemented by a common-source configuration of the power package 100 can be connected to an intermediate output connection of multiple power terminals 300 in a half-bridge configuration of the power package 100. This allows for three level shifters with numerous system-level benefits. Multiple power terminals 300 in a side configuration of the power package 100 may be particularly well-suited for this, as the interconnection between implementations of the power package 100 can be more direct. In some aspects of configuration 108, an interconnect external bus may connect the drain 1 implementation of multiple power terminals 300 to the midpoint of a battery or capacitor bank, and the drain 2 implementation of multiple power terminals 300 may connect to the output of a bridge configuration of the power package 100.

[0218] Figure 54 The illustration shows configurations of various power package implementations according to aspects of this disclosure.

[0219] Specifically, Figure 54The illustration shows configuration 109, which may include multiple single-switch implementations of power package 100 that can be further paralleled and configured into a T-topology. This paralleling can increase phase output current or introduce additional phases, such as a three-phase inverter.

[0220] Figure 55 The illustration shows configurations of various power package implementations according to aspects of this disclosure.

[0221] Specifically, Figure 55 The diagram illustrates a configuration 110 that can be implemented in the system. Specifically, multiple implementations of the power package 100 can be thermally attached to a heatsink, cold plate 700, etc. In some aspects, the multiple implementations of the power package 100 can be configured in a T-type three-phase topology. Additionally, the cold plate 700 or associated cooling system can be scaled to match the number of implementations of the power package 100 in the array.

[0222] Figure 56 The illustration shows a top view of various configurations of power packages according to aspects of this disclosure.

[0223] Figure 57 The diagram illustrates multiple bases. Figure 56 Another side view of the configuration of the power package implementation.

[0224] Specifically, Figure 56 and Figure 57 The illustration shows a configuration 111 in which the top and bottom surfaces of the cold plate 700 can be used for cooling. In this regard, in some system approaches, the two sides of the cold plate 700 can be inlaid with power packages 100. While this may introduce more complex manufacturing methods, it could result in very compact, power-intensive solutions.

[0225] This is illustrated for a three-phase T-type topology, in which, as... Figure 56 As illustrated, the power package 100 has multiple half-bridge arm topologies arranged on the top side of the cold plate 700, and as shown in the diagram. Figure 57 As illustrated, multiple common source topologies of the power package 100 are arranged on the bottom side of the cold plate 700. In this regard, placing the power package 100 on both sides of the cold plate 700 can be a compact way to connect more packages in parallel within a small footprint.

[0226] Figure 58 Cross-sectional views of various configurations of power packages according to aspects of this disclosure are shown.

[0227] Figure 59 The diagram illustrates multiple bases. Figure 58 A 3D diagram showing the configuration of the power packaging implementation.

[0228] Specifically, Figure 58 and Figure 59 The illustration shows a configuration 112 of multiple implementations of the power package 100 arranged on both sides of the cold plate 700. Furthermore, the interconnection between the top and bottom implementations of the power package 100 can be achieved using a wound busbar or cable.

[0229] In other aspects, to minimize inductance and weight, configuration 112 can be implemented using a "through" conductor (not shown) that can connect to a corresponding implementation of the plurality of power terminals 300 in other corresponding implementations of power package 100. In some aspects, cold plate 700 can be configured with through-holes 702 in cold plate 700. For example, for a T-type inverter, the drain connection of the plurality of power terminals 300 in the common-source configuration of power package 100 can be extended with an isolated busbar to the AC output terminals in the bridge arm configuration of power package 100.

[0230] Figure 60 The illustration shows a perspective view of an implementation of a power substrate according to aspects of the present disclosure.

[0231] Figure 61 A perspective view of another implementation of a power substrate according to aspects of this disclosure is shown.

[0232] Figure 62 The illustration shows a top view of an implementation of a power package according to aspects of this disclosure.

[0233] Figure 63 The diagram illustrates the following: Figure 62 A 3D diagram illustrating the implementation of power packaging.

[0234] Specifically, Figure 62 The illustration shows an implementation of a power package 100, which may include at least one of a plurality of power terminals 300 and a plurality of signal terminals 310 on two sides of the power package 100. The internal layout accompanying the external terminal arrangement of the power package 100 may vary based on the number of at least one power device 404, the source Kelvin implementation, performance optimization, etc.

[0235] While the illustrated layout of the power package 100 shown and described can be referenced using an implementation of at least one power device 404 of the same size, other implementations of the power package 100 that utilize the modularity of the layout of the power package 100 to optimally meet the power requirements of a given system are possible. In some aspects, the power package 100 may be configured with a fully filled device location of at least one power device 404, a partially filled device location of at least one power device 404, larger and smaller device size implementations of at least one power device 404, implementations of at least one power device 404 configured with different gate pad sizes and source pad sizes and arrangements, a top-side fixture variation accommodating the gate and source pad configurations, and / or power wire bonding / interconnects replacing the top-side fixture.

[0236] Figure 60 An exemplary layout of a power substrate 402 is illustrated, which can be implemented in any aspect of the power package 100 as described herein, including Figure 62 The implementation method is illustrated in the diagram. (For example...) Figure 60 As illustrated, the power substrate 402 can be implemented using a main power trace 412. In some aspects, the power substrate 402 can be configured with two implementations of the main power trace 412 for each drain of at least one power device 404. The implementation of at least one power device 404 can be attached to the main power trace 412. In some aspects, the implementation of at least one power device 404 can be attached at the center of the main power trace 412 to minimize thermal resistance by maximizing thermal diffusion effects.

[0237] like Figure 61 As illustrated, in some cases, the power substrate 402 can be implemented such that additional traces 424 are added to the power substrate 402 to accommodate additional functionality. In one case, one or more implementations of the additional traces 424 can be added to the power substrate 402 to act as gaps to reduce wire bond lengths. In other cases, the power substrate 402 can be configured as isolated traces that can be added to the power substrate 402 to accommodate sensing elements, such as the temperature sensor described herein.

[0238] like Figure 62As further illustrated, the power package 100 can have two implementations of a configuration for at least one power device 404. Here, the power substrate 402 can be divided into two implementations of a main power trace 412. Additionally, the power package 100 can be implemented using a source clamp 448. In some aspects, the source clamp 448 can be attached to the top side of at least one power device 404 to form a common source connection 450. In some aspects, signal pads on at least one power device 404 can be directly wire-bonded to at least one of a plurality of signal terminals 310 to form a true source Kelvin signal loop. The source clamp 448 can be a standalone component or joined to an external leadframe via a connector (not shown). Furthermore, the source clamp 448 can also be configured using the wire bonding, strip, interconnect configurations, and / or interconnect processes described herein.

[0239] Figure 64 The illustration shows a top view of a power package according to aspects of this disclosure.

[0240] Figure 65 The diagram illustrates the following: Figure 64 Top-view perspective of the power package.

[0241] Specifically, Figure 64 and Figure 65 The illustration shows one aspect of a power package 100, which may also include isolation island traces 452 on a power substrate 402. These isolation island traces can be configured to act as gaps for bonding, thereby reducing the overall wire bond length. This can be useful for improving the manufacturability of wire bonding and preventing gold wire misalignment during molding processes for the housing 200. True Kelvin bonding may be possible by utilizing the space available on the power substrate 402 through two implementations using only at least one power device 404.

[0242] Figure 66 The illustration shows a top view of a power package according to aspects of this disclosure.

[0243] Figure 67 The diagram illustrates the following: Figure 66 Top-view perspective of the power package.

[0244] Specifically, Figure 66 and Figure 67 The illustration shows one aspect of a power package 100, which may also include a single island trace 454. In some implementations of the power package 100, one of the signal bonds may be short enough that it will not require a gap island, while other signal bonds may require one. In this case, only a single island trace 454 may be needed, and for the other, direct bonding can be used, such as... Figure 67As shown in the diagram. This can be used to increase the amount of copper surrounding the device to enhance heat diffusion and thermal performance. It should also be used to free up space for adding sensing elements and their associated terminals and bonding.

[0245] Figure 68 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0246] Figure 69 The diagram shows... Figure 68 A partial 3D view of the power package.

[0247] refer to Figure 68 and Figure 69 In some aspects of the power package 100, at least one power device 404 in another row may be configured. This configuration of the power package 100 can significantly increase the output power.

[0248] In addition, such as Figure 68 As illustrated, the power package 100 may also include a source clamp 448. Additionally, the source clamp 448 may have an undulating structure 460 to connect to at least one power device 404 in the previous row. It should be noted that while each implementation of at least one power device 404 in the figure may be configured with an individual gate bond, in some cases it may be useful to stitch the gate bonds of each switching location of the power package 100 together.

[0249] Figure 70 The illustration shows a top view of a power package of an aspect of this disclosure.

[0250] Figure 71 The diagram illustrates the following: Figure 70 Side view of the power package.

[0251] Specifically, Figure 70 and Figure 71 The illustration shows an implementation of a power package 100 in which multiple power terminals 300 can be offset such that two adjacent implementations of the power package 100 can be placed back-to-back to effectively parallel the switching positions of the power package 100, thereby increasing the total output current. Offset allows for staggering between the multiple power terminals 300 of adjacent implementations of the power package 100, while facilitating easy electrical and mechanical connections via soldering, brazing, etc. Additionally, the multiple power terminals 300 can be configured with bends 442. In some aspects, the bends 442 can be spring-like bends incorporated into the multiple power terminals 300 to act as strain relief for the two implementations of the power package 100 joined together.

[0252] Figure 72 The illustration shows the configuration of two implementations of the power package according to aspects of this disclosure.

[0253] Specifically, Figure 72 The illustration shows configurations 113 of two implementations of the power package 100 according to aspects of this disclosure. In this regard, Figure 70 The diagram illustrates a set of two implementations of power package 100. In configuration 113, the two implementations of power package 100 may have interleaved power connections 444 formed by corresponding implementations of a plurality of power terminals 300. In some aspects, the implementations of the plurality of power terminals 300 may be configured such that a higher-height contact from one implementation of power package 100 engages with a lower-height contact implementation of a plurality of power terminals 300 from another implementation of power package 100.

[0254] Figure 73 The illustration shows a configuration of an implementation of a power package according to aspects of this disclosure.

[0255] Specifically, Figure 73 The illustration shows configuration 120 when a larger output current is required. Specifically, configuration 120 illustrates additional parallel connection that can be achieved using a linear array of power packages 100.

[0256] This represents a very high level of modularity and scalability, where each power package 100 can be configured internally (device count and size) and externally (parallel packaging) to best meet the needs of implementing the system of configuration 120.

[0257] Figure 74 The illustration shows the configuration of two implementations of the power package according to aspects of this disclosure.

[0258] Specifically, Figure 74 The illustration depicts configuration 114 when a larger output current is required. Specifically, configuration 114 illustrates additional parallel connection using a linear array implemented with power package 100. More specifically, Figure 74 The diagram illustrates a set of two implementations of the power package 100. An interleaved power connection is also depicted, wherein a higher-height contact implementation of a plurality of power terminals 300 from one implementation of the power package 100 engages with a lower-height contact implementation of a plurality of power terminals 300 from another implementation of the power package 100.

[0259] Figure 75 A partial top view of a power package according to aspects of this disclosure is illustrated.

[0260] Figure 76 The diagram shows... Figure 75 A partial 3D view of the power package.

[0261] Figure 77The diagram shows... Figure 75 A partial 3D view of the power package.

[0262] refer to Figure 75 , Figure 76 and Figure 77 In some implementations of the power package 100, sensors can be added to improve product functionality and provide more insight into what is happening inside the power package 100, as previously discussed. These sensors may include, but are not limited to, overcurrent / desaturation sensors, temperature sensors, current sensors, strain sensors, etc.

[0263] Sensors come in a wide variety of forms; some require electrical isolation, while others have their own isolation. Most require one or two dedicated signal pins to operate. It should be noted that the specific implementation will depend on the type of sensor. In some cases, voltage gaps and creepage distances are not necessary because it is biased to the same voltage as other signal pins. In other cases, it may require isolation.

[0264] like Figure 75 As illustrated, the power package 100 may include a sensor bonding portion 464 disposed on the sensor 462. Additionally, the sensor 462 may be connected to one or more implementations of the plurality of signal terminals 310 discussed previously.

[0265] Therefore, this disclosure describes a power electronic package that implements a layout, structure, and / or configuration that can provide increased functionality and / or capabilities.

[0266] The following are several non-limiting examples of various aspects of this disclosure.

[0267] An example: A power package includes a power substrate. The power package further includes a first power device on the power substrate. The package further includes a housing having housing sides, the housing sides including at least a first housing side and a second housing side, the housing being configured to accommodate at least the power substrate and the first power device. The package also includes a plurality of power terminals extending from at least one of the housing sides. The package further includes a plurality of power terminals, the plurality of power terminals including at least a first power terminal and a second power terminal. The package further includes a plurality of signal terminals extending from at least one of the housing sides. The package further includes a plurality of signal terminals, the plurality of signal terminals having at least a source Kelvin signal terminal, a gate driver signal terminal, and at least one additional signal terminal.

[0268] The examples mentioned above may also include any one or a combination of the following examples: The power package of the above example: a first power terminal extends from a first housing side and a second power terminal extends from a second housing side; and at least one of a plurality of signal terminals extends from the first housing side and at least one of a plurality of signal terminals extends from the second housing side. The power package of the above example: a first power terminal extends from a first housing side and a second power terminal extends from a second housing side; and at least two of a plurality of signal terminals extend from the first housing side and at least two of a plurality of signal terminals extend from the second housing side. The configuration of the above example: multiple implementations of the power package are arranged in a bridge arm configuration topology. The configuration of the above example: multiple implementations of the power package are arranged in multiple parallel bridge arm configuration topologies. The power package of the above example: at least one implementation of at least one additional signal terminal is configured as an overcurrent / desaturation signal terminal, the overcurrent / desaturation signal terminal being configured to provide an overcurrent signal and / or a desaturation signal. The power package of the above example: the overcurrent / desaturation signal terminal is connected to a drain pad on a power substrate. In the power packages of the above examples: an overcurrent / desaturation signal terminal is configured to allow the gate driver and / or measurement / instrumentation circuitry to monitor the voltage across the switch position. In the power packages of the above examples: at least one implementation of at least one additional signal terminal is configured as a current sensing signal terminal; and the current sensing signal terminal is connected to a current sensor. In the power packages of the above examples: the current sensing signal terminal includes two current sensing terminals. In the power packages of the above examples: the current sensor includes an integrated current sensor implemented using at least one implementation of the first power device. In the power packages of the above examples: the current sensor includes an on-chip current sensor implemented in at least one implementation of the first power device. In the power packages of the above examples: at least one implementation of at least one additional signal terminal is configured as a temperature sensing terminal. In the power packages of the above examples: the temperature sensing terminal includes two temperature sensing terminals. In the power packages of the above examples: the temperature sensing terminal is connected to a temperature sensor, which includes an on-chip temperature sensor, an isolated temperature sensor, a non-isolated temperature sensor, and / or a temperature sensing device integrated with a power substrate, implemented using at least one implementation of the first power device. The following power packages in the above examples: at least one implementation of at least one additional signal terminal is connected to the strain gauge. The following power packages in the above examples: a plurality of signal terminals are symmetrically arranged on the housing side. The following power packages in the above examples: a plurality of signal terminals are asymmetrically arranged on the housing side. The following power packages in the above examples: all of the plurality of signal terminals are symmetrically arranged on the first housing side or the second housing side. The following power packages in the above examples: all of the plurality of signal terminals are asymmetrically arranged on the first housing side or the second housing side.The power package of the above example has the following configuration: a first power terminal extends from a first housing side and a second power terminal extends from a second housing side; and all of the plurality of signal terminals extend from the second housing side. The power package of the above example has the following configuration: all of the plurality of signal terminals are on either the first housing side or the second housing side; and all of the plurality of signal terminals are on the side of one of the plurality of power terminals. The power package of the above example has the following configuration: all of the plurality of signal terminals in at least two implementations of the power package are arranged to cluster along adjacent corners of at least two implementations of the power package. The power package of the above example is also configured with the following common-source topology: a first power terminal extends from the first housing side; a second power terminal extends from the second housing side; a first implementation of the plurality of signal terminals extends from the first housing side; and a second implementation of the plurality of signal terminals extends from the second housing side. The power package of the above examples includes: a first implementation of a plurality of signal terminals arranged adjacent to a third housing side; and a second implementation of the plurality of signal terminals arranged adjacent to a third housing side. The power package of the above examples also includes: a first implementation of a plurality of signal terminals arranged adjacent to a third housing side; and a second implementation of the plurality of signal terminals arranged adjacent to a fourth housing side. The power package of the above examples is further configured with the following half-bridge topology: the plurality of power terminals includes at least a third power terminal; the third power terminal extends from a first housing side; a first power terminal extends from a first housing side; a second power terminal extends from a second housing side; the first implementation of the plurality of signal terminals extends from a first housing side; and the second implementation of the plurality of signal terminals extends from a second housing side. The power package of the above examples includes a creepage distance extender disposed on a first housing side between the third power terminal and the first power terminal. The power package of the above examples includes a support bushing configured to surround and mechanically support at least one of the plurality of signal terminals. The power package of the above examples is also configured with a common-source topology. The power package of the above example includes: a first power terminal extending from a first housing side; a second power terminal extending from a first housing side; and a plurality of signal terminals extending from a second housing side. The power package of the above example also includes: a first implementation of the plurality of signal terminals extending from a first housing side; a second implementation of the plurality of signal terminals extending from a second housing side; the first implementation of the plurality of signal terminals being arranged adjacent to a third housing side; and the second implementation of the plurality of signal terminals being arranged adjacent to a third housing side. The power package of the above example includes a cascode configuration including at least one cascode transistor connected in series with a first power device.The following power packages in the above examples: At least one cascode transistor is stacked on a first power device. The following power packages in the above examples: A cascode configuration includes an electrical connection between the cascode transistor and the first power device. The following power packages in the above examples: A power substrate includes a first power trace and a second power trace; a first power device includes a first power device on the first power trace; and a second power device includes a second power device on the second power trace. The following power packages in the above examples: The power substrate also includes a first signal trace and a second signal trace; and the first and second signal traces are configured to reduce wire bond length. The following power packages in the above examples: The first and second signal traces are configured as gate bond pads. The following power packages in the above examples: The first and second signal traces are configured to adapt to a sensing element. The following power packages in the above examples: The first and second signal traces are at opposite ends of the power substrate. The following power packages in the above examples: A plurality of power terminals include laterally extending offset portions. The following power packages in the above examples: Multiple power terminals are further arranged at different heights for interconnection with another power package. The following power packages in the above examples: The interconnection with another power package includes interleaved power connections. The following power packages in the above examples: The multiple power terminals also include bent stress-relief portions. The following T-topology configurations in the above examples: The T-topology configuration includes: multiple implementations of a power package configured with a common-source topology; and multiple implementations of a power package configured with a half-bridge topology. The following systems in the above examples: Multiple implementations of the T-topology configuration are arranged in parallel. The system in the above examples includes a cold plate, wherein multiple implementations of the power package are on the cold plate. The following power packages in the above examples: Multiple implementations of the power package are on multiple sides of the cold plate. The following power packages in the above examples: The cold plate also includes through-holes configured to allow extension of one or more of the multiple power terminals of the multiple implementations of the power package. The power package in the above examples includes a source clamp, wherein the source clamp is configured to connect between a first implementation of a first power device and a second implementation of the first power device. The power package of the above examples includes a source clamp configured to connect between a plurality of first implementations of the first power device and a plurality of second implementations of the first power device. The power package of the above examples implements a source Kelvin signal terminal using a true source Kelvin configuration. The power package of the above examples implements a source Kelvin signal terminal using a pseudo-source Kelvin configuration. The power package of the above examples includes a first power device comprising at least one of the following: at least one MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), at least one IGBT (Insulated Gate Bipolar Transistor), and / or at least one JFET (Junction Field-Effect Transistor).The power package in the above example is also configured to implement one of the following topologies: single-switch topology, half-bridge topology, full-bridge topology, common-source topology, common-drain topology, three-phase bridge topology, 3-level inverter T-type topology, 3-level inverter NPC (neutral point clamp) topology, 3-level inverter VSC (voltage source converter) topology, buck topology, boost topology, buck-boost topology, or. UK topology.

[0269] An example: A power package includes a power substrate. The power package further includes a first power device on the power substrate. The package also includes a housing having housing sides, the housing sides including at least a first housing side and a second housing side, the housing 200 being configured to accommodate at least the power substrate and the first power device. The package also includes a plurality of power terminals extending from at least one of the housing sides. The package further includes a plurality of power terminals, the plurality of power terminals including at least a first power terminal and a second power terminal. The package further includes a plurality of signal terminals extending from at least one of the housing sides. The package also includes a plurality of signal terminals, the plurality of signal terminals including at least a source Kelvin signal terminal and a gate driver signal terminal. The package also includes a common source connection connecting the first power device and the second power device.

[0270] The examples mentioned above may also include any one or a combination of the following examples: The power package of the above examples includes: a first power terminal extending from a first housing side; a second power terminal extending from a first housing side; and a plurality of signal terminals extending from a second housing side. The power package of the above examples includes: a first power terminal extending from a first housing side and a second power terminal extending from a second housing side; and at least one of the plurality of signal terminals extending from a first housing side and at least one of the plurality of signal terminals extending from a second housing side. The power package of the above examples includes: a first implementation of the plurality of signal terminals extending from a first housing side; a second implementation of the plurality of signal terminals extending from a second housing side; the first implementation of the plurality of signal terminals being arranged adjacent to a third housing side; and the second implementation of the plurality of signal terminals being arranged adjacent to a third housing side. The power package of the above examples includes a cascode configuration including at least one cascode transistor connected in series with a first power device. The power package of the above examples includes: at least one cascode transistor stacked on a first power device. The power package of the above examples includes: a cascode configuration including an electrical connection between the cascode transistor and the first power device. In the power package of the above example: the power substrate includes a first power trace and a second power trace; a first power device includes a first power device disposed on the first power trace; and the first power device includes a second power device disposed on the second power trace. In the following power package of the above example: the power substrate further includes a first signal trace and a second signal trace; and the first and second signal traces are configured to reduce wire bond length. In the following power package of the above example: the first and second signal traces are configured as gate bonding pads. In the following power package of the above example: the first and second signal traces are configured to adapt to sensing elements. In the following power package of the above example: the first and second signal traces are at opposite ends of the power substrate. In the following power package of the above example: multiple power terminals include laterally extending offset portions. In the following power package of the above example: multiple power terminals are further arranged at different heights for interconnection with another power package. In the following power package of the above example: the interconnection with another power package includes interleaved power connections. In the following power package of the above example: multiple power terminals also include bent stress-relief portions. The above examples include the following T-type topology configurations: The T-type topology configuration includes: multiple implementations of a power package configured with a common-source topology; and multiple implementations of a power package configured with a half-bridge topology. The above examples also include the following systems: multiple implementations of the T-type topology configuration are arranged in parallel. The above examples include a cold plate, wherein multiple implementations of the power package are located on the cold plate. The above examples also include the following power packages: multiple implementations of the power package are located on multiple sides of the cold plate. The above examples further include the following power packages: the cold plate also includes through-holes configured to allow extensions of one or more of the multiple power terminals of the multiple implementations of the power package.The power package of the above examples includes a source clamp configured to connect between a first implementation of the first power device and a second implementation of the first power device. The power package of the above examples includes a source clamp configured to connect between multiple first implementations of the first power device and multiple second implementations of the first power device. The power package of the above examples includes: a first power terminal extending from a first housing side and a second power terminal extending from a second housing side; and wherein at least two of a plurality of signal terminals extend from the first housing side and at least two of a plurality of signal terminals extend from the second housing side. The above examples include: multiple implementations of the power package arranged in a bridge arm configuration topology. The above examples include: multiple implementations of the power package arranged in multiple parallel bridge arm configuration topologies. The above examples include: the plurality of signal terminals further including at least one additional signal terminal; and at least one implementation of the at least one additional signal terminal is configured as an overcurrent / desaturation signal terminal, the overcurrent / desaturation signal terminal being configured to provide an overcurrent signal and / or a desaturation signal. In the power packages of the above examples: an overcurrent / desaturation signal terminal is connected to a drain pad on a power substrate. In the power packages of the above examples: the overcurrent / desaturation signal terminal is configured to allow a gate driver and / or measurement / instrumentation circuitry to monitor the voltage across a switch position. In the power packages of the above examples: the plurality of signal terminals further includes at least one additional signal terminal; and at least one implementation of the at least one additional signal terminal is configured as a current-sensing signal terminal; and the current-sensing signal terminal is connected to a current sensor. In the power packages of the above examples: the current-sensing signal terminal includes two current-sensing terminals. In the power packages of the above examples: the current sensor includes an integrated current sensor implemented using at least one implementation of a first power device. In the power packages of the above examples: the current sensor includes an on-chip current sensor implemented in at least one implementation of a first power device. In the power packages of the above examples: the plurality of signal terminals further includes at least one additional signal terminal; and at least one implementation of the at least one additional signal terminal is configured as a temperature-sensing terminal. In the power packages of the above examples: the temperature-sensing terminal includes two temperature-sensing terminals. The power packages in the above examples include: a temperature sensing terminal connected to a temperature sensor, which includes an on-chip temperature sensor, an isolated temperature sensor, a non-isolated temperature sensor, and / or a temperature sensing device integrated with a power substrate, implemented using at least one implementation of a first power device. The power packages in the above examples also include: a plurality of signal terminals further including at least one additional signal terminal; and at least one implementation of the at least one additional signal terminal is configured as a temperature sensing terminal. Finally, the power packages in the above examples have: a plurality of signal terminals symmetrically arranged on the side of the housing.The power packages in the above examples have the following configurations: Multiple signal terminals are asymmetrically arranged on the housing side. All of the multiple signal terminals are symmetrically arranged on either the first or second housing side. All of the multiple signal terminals are asymmetrically arranged on either the first or second housing side. A first power terminal extends from the first housing side and a second power terminal extends from the second housing side; and all of the multiple signal terminals extend from the second housing side. All of the multiple signal terminals are on either the first or second housing side; and all of the multiple signal terminals are on the side of one of the multiple power terminals. All of the multiple signal terminals are on either the first or second housing side; and all of the multiple signal terminals are on both sides of one of the multiple power terminals. In the above examples, all of the multiple signal terminals in at least two implementations of the power package are arranged to cluster along adjacent corners of at least two implementations of the power package. The power package of the above examples is further configured with the following common-source topology: a first power terminal extends from a first housing side; a second power terminal extends from a second housing side; a first implementation of a plurality of signal terminals extends from the first housing side; and a second implementation of a plurality of signal terminals extends from the second housing side. The power package of the above examples further includes: the first implementation of a plurality of signal terminals is arranged adjacent to a third housing side; and the second implementation of a plurality of signal terminals is arranged adjacent to the third housing side. The power package of the above examples further includes: the first implementation of a plurality of signal terminals is arranged adjacent to a third housing side; and the second implementation of a plurality of signal terminals is arranged adjacent to a fourth housing side. The power package of the above examples is further configured with the following half-bridge topology: the plurality of power terminals includes at least a third power terminal; the third power terminal extends from the first housing side; the first power terminal extends from the first housing side; the second power terminal extends from the second housing side; the first implementation of a plurality of signal terminals extends from the first housing side; and the second implementation of a plurality of signal terminals extends from the second housing side. The power package of the above examples includes a creepage distance extender located on a first housing side between a third power terminal and a first power terminal. The power package of the above examples includes a support bushing configured to surround and mechanically support at least one of a plurality of signal terminals. The following power packages of the above examples implement source Kelvin signal terminals using a true source Kelvin configuration. The following power packages of the above examples implement source Kelvin signal terminals using a pseudo-source Kelvin configuration.The power package of the above example includes at least one of the following: at least one MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), at least one IGBT (Insulated Gate Bipolar Transistor), and / or at least one JFET (Junction Field-Effect Transistor).

[0271] Furthermore, the power package 100 can be implemented in a variety of circuit topologies, including single-switch configuration, half-bridge configuration, full-bridge configuration, three-phase bridge configuration (also known as a six-package), buck configuration, boost configuration, buck-boost configuration, and so on. UK configuration, common source configuration, common drain configuration, neutral point clamp configuration, etc. Applications of the Power Package 100 can include power systems, motor systems, automotive motor systems, charging systems, automotive charging systems, vehicle systems, industrial motor drivers, embedded motor drivers, uninterruptible power supplies, AC-DC power supplies, soldering machine power supplies, military systems, inverters, inverters, converters, motor drivers, solar inverters, circuit breakers, protection circuits, DC-DC converters, etc., for wind turbines, solar panels, tidal power plants, and electric vehicles (EVs).

[0272] The aspects of this disclosure have been described above with reference to the accompanying drawings, in which various aspects of this disclosure are illustrated. However, it should be understood that this disclosure may be embodied in many different forms and should not be construed as limited to the aspects described above. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, the various aspects described may be implemented individually. Additionally, one or more of the various aspects described may be combined. Throughout the specification, similar reference numerals refer to similar elements.

[0273] It should be understood that although the terms first, second, etc., are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0274] The terminology used herein is for the purpose of describing particular aspects only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should also be understood that the terms “comprising,” “including,” “covering,” and / or “having,” when used herein, specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0275] It should be understood that when a component (such as a layer, region, or substrate) is referred to as being "on" or extending "on" another component, it may be directly on or directly extending onto the other component, or an intermediary component may be present. Conversely, when a component is referred to as being "directly on" or "directly" extending "on" another component, no intermediary component is present. It should also be understood that when a component is referred to as being "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or an intermediary component may be present. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, no intermediary component is present.

[0276] Relative terms (such as "below" or "above," or "upper" or "lower," or "top" or "bottom") may be used herein to describe the relationship between one element, layer, or region illustrated in the figures and another element, layer, or region. It should be understood that these terms are intended to cover different orientations of the device other than those depicted in the figures.

[0277] Aspects of this disclosure are described herein with reference to cross-sectional views, which are schematic illustrations of idealized embodiments (and intermediate structures) of this disclosure. For clarity, the thicknesses of the layers and regions in the figures may be exaggerated. Furthermore, variations from the illustrated shapes are contemplated due to factors such as manufacturing techniques and / or tolerances.

[0278] Typical aspects of this disclosure have been disclosed in the accompanying drawings and description, and although specific terms have been used, they are used in a general and descriptive sense only and not for limiting purposes. The scope of this disclosure is defined by the following claims.

[0279] While this disclosure has been described in exemplary aspects, those skilled in the art will recognize that modifications can be made to practice this disclosure within the spirit and scope of the appended claims. The examples given above are merely illustrative and are not intended to be an exhaustive list of all possible designs, aspects, applications, or modifications of this disclosure. In this regard, various aspects, features, parts, elements, modules, arrangements, circuits, etc., are contemplated to be interchangeable, mixed, matched, combined, etc. In this regard, the different features of this disclosure are modular and can be mixed and matched with each other.

Claims

1. A power package, comprising: Power substrate; A first power device is disposed on the power substrate; A housing having housing sides, the housing sides including at least a first housing side and a second housing side, the housing being configured to at least accommodate the power substrate and the first power device; Multiple power terminals extend from at least one of the sides of the housing. The plurality of power terminals include at least a first power terminal and a second power terminal; Multiple signal terminals extend from at least one of the sides of the housing, and The plurality of signal terminals include at least a source Kelvin signal terminal, a gate driver signal terminal, and at least one additional signal terminal.

2. The power package according to claim 1, in, The first power terminal extends from the side of the first housing and the second power terminal extends from the side of the second housing; and At least one of the plurality of signal terminals extends from the side of the first housing, and at least one of the plurality of signal terminals extends from the side of the second housing.

3. The power package according to claim 1, in, The first power terminal extends from the side of the first housing and the second power terminal extends from the side of the second housing; and At least two of the plurality of signal terminals extend from the side of the first housing, and at least two of the plurality of signal terminals extend from the side of the second housing.

4. A configuration of multiple implementations of the power package according to claim 1, wherein, The implementations of multiple power packages are arranged in a bridge arm configuration topology.

5. A configuration of multiple implementations of the power package according to claim 1, wherein, The implementation of multiple power packages is arranged in a topology of multiple parallel bridge arms.

6. The power package according to claim 1, in, At least one implementation of the at least one additional signal terminal is configured as an overcurrent / desaturation signal terminal, the overcurrent / desaturation signal terminal being configured to provide an overcurrent signal and / or a desaturation signal.

7. The power package according to claim 6, wherein, The overcurrent / desaturation signal terminal is connected to the drain pad on the power substrate.

8. The power package according to claim 6, wherein, The overcurrent / desaturation signal terminal is configured to allow the gate driver and / or measurement / instrumentation circuitry to monitor the voltage across the switch position.

9. The power package according to claim 1, in, At least one implementation of the at least one additional signal terminal is configured as a current sensing signal terminal; and The current sensing signal terminal is connected to the current sensor.

10. The power package according to claim 9, wherein, The current sensing signal terminal includes two current sensing terminals.

11. The power package according to claim 9, wherein, The current sensor includes an integrated current sensor, which is implemented using at least one implementation of the first power device.

12. The power package according to claim 9, wherein, The current sensor includes an on-chip current sensor, which is implemented in at least one embodiment of the first power device.

13. The power package according to claim 1, wherein, At least one implementation of the at least one additional signal terminal is configured as a temperature sensing terminal.

14. The power package of claim 13, wherein, The temperature sensing terminal includes two temperature sensing terminals.

15. The power package according to claim 13, wherein, The temperature sensing terminal is connected to a temperature sensor, which includes: an on-chip temperature sensor, an isolated temperature sensor, a non-isolated temperature sensor, and / or a temperature sensing device integrated with the power substrate, implemented using at least one implementation of the first power device.

16. The power package according to claim 1, wherein, At least one implementation of the at least one additional signal terminal is connected to the strain gauge.

17. The power package according to claim 1, wherein, The plurality of signal terminals are symmetrically arranged on the side of the housing.

18. The power package according to claim 1, wherein, The plurality of signal terminals are arranged asymmetrically on the side of the housing.

19. The power package according to claim 1, wherein, All of the plurality of signal terminals are symmetrically arranged on the side of the first housing or symmetrically arranged on the side of the second housing.

20. The power package according to claim 1, wherein, All of the plurality of signal terminals are asymmetrically arranged on the side of the first housing or asymmetrically arranged on the side of the second housing.

21. The power package according to claim 1, in, The first power terminal extends from the side of the first housing and the second power terminal extends from the side of the second housing; and All of the plurality of signal terminals extend from the side of the second housing.

22. The power package according to claim 1, in, All of the plurality of signal terminals are located on the first housing side or all are located on the second housing side; and All of the plurality of signal terminals are located on one side of one of the plurality of power terminals.

23. The power package according to claim 1, in, All of the plurality of signal terminals are located on the first housing side or all are located on the second housing side; and All of the plurality of signal terminals are located on both sides of one of the plurality of power terminals.

24. A configuration of at least two implementations of the power package according to claim 1, in, All of the signal terminals in the implementation of at least two power packages are arranged to cluster along adjacent corners of the implementation of the at least two power packages.

25. The power package of claim 1, further configured with a common-source topology, wherein: The first power terminal extends from the side of the first housing; The second power terminal extends from the side of the second housing; The first implementation of the plurality of signal terminals extends from the side of the first housing; The second implementation of the plurality of signal terminals extends from the side of the second housing.

26. The power package according to claim 25, in, The first implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing; and The second implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing.

27. The power package according to claim 25, in, The first implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing; and The second implementation of the plurality of signal terminals is arranged adjacent to the side of the fourth housing.

28. The power package of claim 1, further configured with a half-bridge topology, wherein: The plurality of power terminals also includes at least a third power terminal; The third power terminal extends from the side of the first housing; The first power terminal extends from the side of the first housing; The second power terminal extends from the side of the second housing; The first implementation of the plurality of signal terminals extends from the side of the first housing; and The second implementation of the plurality of signal terminals extends from the side of the second housing.

29. The power package of claim 28 further includes a creepage distance extender disposed on the side of the first housing and between the third power terminal and the first power terminal.

30. The power package of claim 1, further comprising a support bushing configured to surround and mechanically support at least one of the plurality of signal terminals.

31. The power package of claim 1 is further configured with a common source topology.

32. The power package of claim 1 is further configured with a half-bridge topology.

33. The power package of claim 1 is further configured with a single-switch position topology.

34. The power package of claim 1 is further configured with a common-drain topology.

35. The power package according to claim 1, wherein: The first power terminal extends from the side of the first housing; The second power terminal extends from the side of the first housing; and The plurality of signal terminals extend from the side of the second housing.

36. The power package according to claim 1, wherein: The first implementation of the plurality of signal terminals extends from the side of the first housing; The second implementation of the plurality of signal terminals extends from the side of the second housing; The first implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing; and The second implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing.

37. The power package of claim 1 further includes a cascode configuration, the cascode configuration including at least one cascode transistor connected in series with the first power device.

38. The power package of claim 37, wherein, The at least one common-source cascode transistor is stacked on the first power device.

39. The power package of claim 37, wherein, The common-source, common-gate configuration includes the electrical connection between the common-source, common-gate transistor and the first power device.

40. The power package of claim 1, further comprising a second power device, in: The power substrate includes a first power trace and a second power trace; The first power device is on the first power trace; and The second power device is on the second power trace.

41. The power package of claim 1, further comprising a second power device, in: The power substrate includes a first power trace and a second power trace; The first power device includes multiple implementations of the first power device on the first power trace; and The second power device includes multiple implementations of the second power device on the second power trace.

42. The power package according to claim 1, in, The power substrate further includes a first signal trace and a second signal trace; The first signal trace and the second signal trace are configured to reduce the wire bonding length.

43. The power package according to claim 42, wherein, The first signal trace and the second signal trace are configured as gate bonding pads.

44. The power package of claim 42, wherein, The first signal trace and the second signal trace are configured to adapt to the sensing element.

45. The power package according to claim 1, in, The plurality of power terminals include laterally extending offset portions.

46. ​​The power package according to claim 1, wherein, The plurality of power terminals are also arranged at different heights for interconnection with another power package.

47. The power package of claim 46, wherein, Interconnection with the other power package includes interleaved power connections.

48. The power package according to claim 1, wherein, The plurality of power terminals also include a bending stress relief section.

49. A T-topology configuration for parallel implementation of multiple power packages according to claim 1, the T-topology configuration comprising: Implementation methods for multiple power packages configured with common source topology; as well as Multiple implementations of power packages configured with half-bridge topologies.

50. A system comprising multiple implementations of the T-topology configuration according to claim 49, wherein, Multiple implementations of the aforementioned T-shaped topology configurations are arranged in parallel.

51. A system comprising multiple implementations of the power package according to claim 1, the system further comprising a cold plate. in, Multiple implementations of the power packages are located on the cold plate.

52. The power package according to claim 51, wherein, The power packages are implemented on multiple sides of the cold plate.

53. The power package according to claim 52, wherein, The cold plate also includes through-holes configured to allow one or more extensions of a plurality of power terminals in a plurality of implementations of the power package.

54. The power package according to claim 42, wherein, The first signal trace and the second signal trace are located at opposite ends of the power substrate.

55. The power package according to claim 1, further comprising a source clamp, wherein, The source clamp is configured to connect between a first implementation of the first power device and a second implementation of the first power device.

56. The power package according to claim 1, further comprising a source clamp, wherein, The source clamp is configured to connect between a plurality of first implementations of the first power device and a plurality of second implementations of the first power device.

57. The power package according to claim 1, wherein, The source Kelvin signal terminal is implemented using a real source Kelvin configuration.

58. The power package according to claim 1, wherein, The source Kelvin signal terminal is implemented using a pseudo-source Kelvin configuration.

59. The power package according to claim 1, wherein, The first power device includes at least one of the following: at least one MOSFET (metal-oxide-semiconductor field-effect transistor), at least one IGBT (insulated-gate bipolar transistor), and / or at least one JFET (junction field-effect transistor).

60. The power package of claim 1 is further configured to implement one of the following topologies: single-switch topology, half-bridge topology, full-bridge topology, common-source topology, common-drain topology, three-phase bridge topology, 3-level inverter T-type topology, 3-level inverter NPC (neutral point clamp) topology, 3-level inverter VSC (voltage source converter) topology, buck topology, boost topology, buck-boost topology, or UK topology.

61. The power package according to claim 1, wherein, The first power device includes multiple implementations of the first power device.

62. A power package configured to include: Power substrate; A first power device is disposed on the power substrate; A housing having housing sides, the housing sides including at least a first housing side and a second housing side, the housing being configured to at least accommodate the power substrate and the first power device; Multiple power terminals extend from at least one of the sides of the housing; The plurality of power terminals include at least a first power terminal and a second power terminal; Multiple signal terminals extend from at least one of the sides of the housing, and The plurality of signal terminals include at least a source Kelvin signal terminal and a gate driver signal terminal; as well as A common source connection is provided between the first power device and the second power device.

63. The power package of claim 62, wherein: The first power terminal extends from the side of the first housing; The second power terminal extends from the side of the first housing; and The plurality of signal terminals extend from the side of the second housing.

64. The power package according to claim 62, in, The first power terminal extends from the side of the first housing and the second power terminal extends from the side of the second housing; and At least one of the plurality of signal terminals extends from the side of the first housing, and at least one of the plurality of signal terminals extends from the side of the second housing.

65. The power package of claim 62, wherein: The first implementation of the plurality of signal terminals extends from the side of the first housing; The second implementation of the plurality of signal terminals extends from the side of the second housing; The first implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing; and The second implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing.

66. The power package of claim 62 further includes a cascode configuration, the cascode configuration including at least one cascode transistor connected in series with the first power device.

67. The power package of claim 66, wherein, The at least one common-source cascode transistor is stacked on the first power device.

68. The power package of claim 66, wherein, The common-source, common-gate configuration includes the electrical connection between the common-source, common-gate transistor and the first power device.

69. The power package of claim 62, further comprising a second power device, in: The power substrate includes a first power trace and a second power trace; The first power device is on the first power trace; and The second power device is on the second power trace.

70. The power package of claim 62, further comprising a second power device, in: The power substrate includes a first power trace and a second power trace; The first power device includes multiple implementations of the first power device on the first power trace; and The second power device includes multiple implementations of the second power device on the second power trace.

71. The power package according to claim 62, in, The power substrate further includes a first signal trace and a second signal trace; The first signal trace and the second signal trace are configured to reduce the wire bonding length.

72. The power package according to claim 71, wherein, The first signal trace and the second signal trace are configured as gate bonding pads.

73. The power package according to claim 71, wherein, The first signal trace and the second signal trace are configured to adapt to the sensing element.

74. The power package according to claim 62, in, The plurality of power terminals include laterally extending offset portions.

75. The power package of claim 62, wherein, The plurality of power terminals are also arranged at different heights for interconnection with another power package.

76. The power package of claim 75, wherein, Interconnection with the other power package includes interleaved power connections.

77. The power package of claim 62, wherein, The plurality of power terminals also include a bending stress relief section.

78. A T-topology configuration for parallel implementation of multiple power packages according to claim 62, the T-topology configuration comprising: Implementation methods for multiple power packages configured with common source topology; as well as Multiple implementations of power packages configured with half-bridge topologies.

79. A system comprising multiple implementations of the T-topology configuration according to claim 78, wherein, Multiple implementations of the aforementioned T-shaped topology configurations are arranged in parallel.

80. A system comprising multiple implementations of the power package according to claim 62, the system further comprising a cold plate. in, Multiple implementations of the power packages are located on the cold plate.

81. The power package according to claim 80, wherein, The power packages are implemented on multiple sides of the cold plate.

82. The power package according to claim 81, wherein, The cold plate also includes through-holes configured to allow one or more extensions of a plurality of power terminals in a plurality of implementations of the power package.

83. The power package according to claim 71, wherein, The first signal trace and the second signal trace are located at opposite ends of the power substrate.

84. The power package of claim 62, further comprising a source clamp, wherein, The source clamp is configured to connect between a first implementation of the first power device and a second implementation of the first power device.

85. The power package of claim 62, further comprising a source clamp, wherein, The source clamp is configured to connect between a plurality of first implementations of the first power device and a plurality of second implementations of the first power device.

86. The power package according to claim 62, in, The first power terminal extends from the side of the first housing and the second power terminal extends from the side of the second housing; and At least two of the plurality of signal terminals extend from the side of the first housing, and at least two of the plurality of signal terminals extend from the side of the second housing.

87. A configuration of multiple implementations of the power package according to claim 62, wherein, The implementations of multiple power packages are arranged in a bridge arm configuration topology.

88. A configuration of multiple implementations of the power package according to claim 62, wherein, The implementation of multiple power packages is arranged in a topology of multiple parallel bridge arms.

89. The power package according to claim 62, in, The plurality of signal terminals further includes at least one additional signal terminal; and Wherein, at least one implementation of the at least one additional signal terminal is configured as an overcurrent / desaturation signal terminal, and the overcurrent / desaturation signal terminal is configured to provide an overcurrent signal and / or a desaturation signal.

90. The power package of claim 89, wherein, The overcurrent / desaturation signal terminal is connected to the drain pad on the power substrate.

91. The power package according to claim 89, wherein, The overcurrent / desaturation signal terminal is configured to allow the gate driver and / or measurement / instrumentation circuitry to monitor the voltage across the switch position.

92. The power package according to claim 62, in, The plurality of signal terminals also includes at least one additional signal terminal; Wherein, at least one implementation of the at least one additional signal terminal is configured as a current sensing signal terminal; and The current sensing signal terminal is connected to the current sensor.

93. The power package according to claim 92, wherein, The current sensing signal terminal includes two current sensing terminals.

94. The power package according to claim 92, wherein, The current sensor includes an integrated current sensor, which is implemented using at least one implementation of the first power device.

95. The power package according to claim 92, wherein, The current sensor includes an on-chip current sensor, which is implemented in at least one embodiment of the first power device.

96. The power package according to claim 62, in, The plurality of signal terminals further includes at least one additional signal terminal; and In this embodiment, at least one implementation of the at least one additional signal terminal is configured as a temperature sensing terminal.

97. The power package of claim 96, wherein, The temperature sensing terminal includes two temperature sensing terminals.

98. The power package according to claim 96, wherein, The temperature sensing terminal is connected to a temperature sensor, which includes: an on-chip temperature sensor implemented in at least one manner of the first power device, an isolated temperature sensor, a non-isolated temperature sensor, and / or a temperature sensing device integrated with the power substrate.

99. The power package according to claim 62, in, The plurality of signal terminals further includes at least one additional signal terminal; and In this embodiment, at least one additional signal terminal is connected to the strain gauge.

100. The power package of claim 62, wherein, The plurality of signal terminals are symmetrically arranged on the side of the housing.

101. The power package according to claim 62, wherein, The plurality of signal terminals are arranged asymmetrically on the side of the housing.

102. The power package according to claim 62, wherein, All of the plurality of signal terminals are symmetrically arranged on the side of the first housing or symmetrically arranged on the side of the second housing.

103. The power package according to claim 62, wherein, All of the plurality of signal terminals are asymmetrically arranged on the side of the first housing or asymmetrically arranged on the side of the second housing.

104. The power package according to claim 62, in, The first power terminal extends from the side of the first housing and the second power terminal extends from the side of the second housing; and All of the plurality of signal terminals extend from the side of the second housing.

105. The power package according to claim 62, in, All of the plurality of signal terminals are located on either the first housing side or the second housing side; and All of the plurality of signal terminals are located on one side of one of the plurality of power terminals.

106. The power package according to claim 62, in, All of the plurality of signal terminals are located on either the first housing side or the second housing side; and All of the plurality of signal terminals are located on both sides of one of the plurality of power terminals.

107. A configuration of at least two implementations of the power package according to claim 62, in, All of the signal terminals in the implementation of at least two power packages are arranged to cluster along adjacent corners of the implementation of the at least two power packages.

108. The power package of claim 62, further configured with a common-source topology, wherein: The first power terminal extends from the side of the first housing; The second power terminal extends from the side of the second housing; The first implementation of the plurality of signal terminals extends from the side of the first housing; The second implementation of the plurality of signal terminals extends from the side of the second housing.

109. The power package according to claim 108, in, The first implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing; and In this embodiment, the plurality of signal terminals are arranged adjacent to the side of the third housing.

110. The power package according to claim 108, in, The first implementation of the plurality of signal terminals is arranged adjacent to the side of the third housing; and The second implementation of the plurality of signal terminals is arranged adjacent to the side of the fourth housing.

111. The power package of claim 62, further configured with a half-bridge topology, wherein: The plurality of power terminals also includes at least a third power terminal; The third power terminal extends from the side of the first housing; The first power terminal extends from the side of the first housing; The second power terminal extends from the side of the second housing; The first implementation of the plurality of signal terminals extends from the side of the first housing; and The second implementation of the plurality of signal terminals extends from the side of the second housing.

112. The power package of claim 111 further includes a creepage distance extender located on the first housing side between the third power terminal and the first power terminal.

113. The power package of claim 62 further includes a support bushing configured to surround and mechanically support at least one of the plurality of signal terminals.

114. The power package of claim 62, wherein, The source Kelvin signal terminal is implemented using a real source Kelvin configuration.

115. The power package according to claim 62, wherein, The source Kelvin signal terminal is implemented using a pseudo-source Kelvin configuration.

116. The power package of claim 62, wherein, The first power device includes at least one of the following: at least one MOSFET (metal-oxide-semiconductor field-effect transistor), at least one IGBT (insulated-gate bipolar transistor), and / or at least one JFET (junction field-effect transistor).

117. The power package of claim 62, wherein: The first power device includes multiple implementations of the first power device.

118. The power package of claim 62 is further configured with a common source topology.

119. The power package of claim 62 is further configured with a half-bridge topology.

120. The power package of claim 62 is further configured with a single-switch position topology.

121. The power package of claim 62 is further configured with a common-drain topology.

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