Impedance measurement device and method based on weak signal processing

Abstract

The application discloses an impedance measurement device and method based on weak signal processing, comprising an impedance measurement bridge and a weak signal detection module; the impedance measurement bridge comprises an excitation source module, a range resistance module and a balance adjustment module; the weak signal detection module comprises a vector ratio acquisition unit, a multi-stage signal amplification unit, a clock synchronization unit and a plurality of analog-to-digital conversion units; the vector ratio acquisition unit is used for acquiring a first analog voltage signal of a to-be-measured impedance and a second analog voltage signal of the range resistance module; the clock synchronization unit outputs a plurality of equally-spaced synchronous clock signals to the plurality of analog-to-digital conversion units; and the plurality of analog-to-digital conversion units convert the analog voltage signals into a plurality of digital signals based on the plurality of equally-spaced synchronous clock signals and output the plurality of digital signals. In the embodiment of the application, the noise suppression of signal extraction and multi-stage amplification of the balance bridge is combined, and the weak voltage signal in strong noise is detected with fidelity.

Description

Technical Field

[0001] This application relates to the field of impedance measurement technology, and in particular to an impedance measurement device and method based on weak signal processing. Background Technology

[0002] In the field of modern science and technology and engineering applications, impedance measurement technology is widely used in scenarios such as electronic component characteristic analysis and material electrical property characterization, and improving measurement accuracy has always been one of the core requirements of this field.

[0003] In practical applications, the balanced bridge method is often used to measure the impedance of the target. However, the impedance-related electrical signal output by the balanced bridge is often weak, with extremely low signal amplitude and often submerged by complex noise. Conventional measurement methods are unable to effectively extract the useful signal, and additional noise is easily introduced during signal transmission and processing. Conventional amplification and detection methods are difficult to balance noise suppression and signal fidelity, resulting in insufficient accuracy and stability of impedance measurement, which is difficult to meet the requirements of high-precision scenarios. Summary of the Invention

[0004] To address the existing technical problems, this invention provides an impedance measurement device and method based on weak signal processing. The method extracts parameter signals related to the impedance under test using an impedance measurement bridge, and then a weak signal detection module amplifies, synchronously samples, and performs analog-to-digital conversion on the extracted weak voltage signal to achieve impedance measurement. By combining signal extraction from a balanced bridge with noise suppression through multi-stage amplification, it achieves high-fidelity detection of weak voltage signals in strong noise. A clock synchronization unit provides a phase-matched synchronous clock for multi-analog-to-digital conversion, avoiding measurement errors caused by phase signal sampling misalignment. The multi-stage signal amplification unit supports amplification control at different factors, is compatible with detecting weak signals of different amplitudes, and enhances the versatility of the solution.

[0005] In a first aspect, embodiments of this application provide an impedance measurement device based on weak signal processing, including an impedance measurement bridge and a weak signal detection module;

[0006] The impedance measurement bridge includes an excitation source module, a range resistor module, and a balance adjustment module. The excitation source module provides excitation source signals for the impedance to be measured and the range resistor module. The balance adjustment module balances the impedance measurement bridge based on the unbalanced current between the impedance to be measured and the range resistor module and the excitation source signal.

[0007] The weak signal detection module includes a vector ratio acquisition unit, a multi-stage signal amplification unit, a clock synchronization unit, and multiple analog-to-digital conversion units. The vector ratio acquisition unit is used to acquire the first analog voltage signal of the impedance to be measured and the second analog voltage signal of the range resistor module. The multi-stage signal amplification unit is used to amplify the first and second analog voltage signals by different factors based on the amplification control signal. The clock synchronization unit is connected to the multiple analog-to-digital conversion units and is used to output multiple equally spaced synchronous clock signals to the multiple analog-to-digital conversion units respectively. The multiple analog-to-digital conversion units are used to convert the amplified first and second analog voltage signals into multiple digital signals based on the multiple equally spaced synchronous clock signals and output them.

[0008] In one alternative embodiment, the multi-stage signal amplification unit includes a selective amplification link and a multi-stage amplification link;

[0009] The selection amplification link includes a first switching switch, a first amplification link, a second amplification link, and a second switching switch; the first switching switch and the second switching switch connect the first amplification link or the second amplification link to the multi-stage amplification link based on the selection control signal; the selection control signal is determined based on the amplitude of the first analog voltage signal and the second analog voltage signal.

[0010] In one optional embodiment, the multi-stage amplification link includes a first-stage amplification link, a second-stage amplification link, and a third-stage amplification link;

[0011] The first-stage amplification link includes a first relay, a first amplification element, and a first peripheral resistor structure; the first relay is used to receive and connect different first peripheral resistor structures to the first amplification element based on the first amplification control signal, so that the first amplification element amplifies the signal by different factors.

[0012] The second-stage amplification link includes a second relay, a second amplification element, and a second peripheral resistor structure. The second relay is used to receive and connect different second peripheral resistor structures to the second amplification element based on the second amplification control signal, so that the second amplification element amplifies the signal by different factors.

[0013] The third-stage amplification link includes a third relay, a third amplifying element, and a third peripheral resistor structure. The third relay is used to receive and connect different third peripheral resistor structures to the third amplifying element based on the third amplification control signal, so that the third amplifying element amplifies the signal by different factors.

[0014] In one optional embodiment, the clock synchronization unit includes a clock input structure and a clock tree structure;

[0015] The clock tree structure includes a clock tree root and multi-level fan-out buffers; each level of fan-out buffer includes deterministic time error and uncertain time error; the clock tree root receives the original clock signal input from the clock input structure, inputs it into the multi-level fan-out buffers, and forms multiple synchronous clock signals, which are respectively connected to multiple analog-to-digital conversion units.

[0016] In one optional embodiment, the balance adjustment module includes a zero-position detector, a first direction circuit, a second direction circuit, and an operational amplifier;

[0017] The zero-position detector is used to detect the unbalanced current between the impedance to be measured and the range resistance, and decomposes it into a first-direction signal and a second-direction signal.

[0018] The first direction circuit includes a first multiplier, a first integrator circuit, and a second multiplier. The first multiplier is used to multiply the first direction signal with the first reference direction signal to obtain a component in the same direction, which is then input into the first integrator circuit for filtering. The second multiplier is used to multiply the filtered component in the same direction with the excitation source signal to obtain a first compensation signal.

[0019] The second direction circuit includes a third multiplier, a second integrator circuit, and a fourth multiplier. The third multiplier is used to multiply the second direction signal with the second reference direction signal to obtain an orthogonal component, which is then input into the second integrator circuit for filtering. The fourth multiplier is used to multiply the filtered in-direction component with the phase-shifted excitation source signal to obtain the second compensation signal.

[0020] The operational amplifier is used to receive the first compensation signal and the second compensation signal, and the vector path resistor module outputs the compensation signal.

[0021] In one optional embodiment, the vector ratio acquisition unit includes a third switching switch and a phase detector;

[0022] The first input terminal of the third switching switch is connected between the impedance to be measured and the excitation source, the second input terminal is connected between the output terminals of the range resistor module and the balance adjustment module, and the output terminal is connected to the phase detector. It is used to acquire the first analog voltage signal or the second analog voltage signal based on the third switching control signal.

[0023] A phase detector is used to detect the phase value of a first analog voltage signal or a second analog voltage signal.

[0024] In one optional embodiment, the vector ratio acquisition unit further includes a first buffer structure and a second buffer structure; the first buffer structure is disposed between the first input terminal of the third switching switch and the impedance to be measured, and the second buffer structure is disposed between the second input terminal of the third switching switch and the range resistor module.

[0025] In one optional embodiment, the range resistor module includes multiple reference resistors with different resistance values ​​and multiple range switches; each reference resistor is connected in series with a range switch; and multiple sets of series-connected reference resistors are connected in parallel with the range switches.

[0026] Secondly, embodiments of this application provide an impedance measurement method, characterized in that it is applied to the impedance measurement device based on weak signal processing as described in the first aspect, comprising:

[0027] When the impedance measurement bridge reaches equilibrium, the first analog voltage signal and the second analog voltage signal are detected.

[0028] Receives manual automatic gain control commands; manual automatic gain control commands include preset levels;

[0029] Switch the multi-stage signal amplification unit to the preset level;

[0030] Adjust the preset gear to the target gear based on the magnitudes of the first and second analog voltage signals;

[0031] Based on the target gear, the first analog voltage signal and the second analog voltage signal are amplified to obtain the first amplified signal and the second amplified signal;

[0032] The impedance value of the impedance to be measured is determined based on the first amplified signal and the second amplified signal.

[0033] In one optional embodiment, adjusting a preset level to a target level based on the magnitudes of a first analog voltage signal and a second analog voltage signal includes:

[0034] Obtain the output signal corresponding to the current gear;

[0035] If the output signal is saturated, the multi-stage signal amplification unit is controlled to increase the current gear by one level, and the increased gear is used as the current gear; or, if the output signal is unsaturated, the current gear is determined as the target gear.

[0036] Thirdly, embodiments of this application provide an impedance measurement apparatus, the apparatus comprising:

[0037] The detection module is used to detect the first analog voltage signal and the second analog voltage signal when the impedance measurement bridge reaches equilibrium.

[0038] The receiving module is used to receive manual automatic gain control commands; the manual automatic gain control commands include preset gears.

[0039] The gear switching module is used to switch the multi-stage signal amplification unit to a preset gear.

[0040] The gear adjustment module is used to adjust the preset gear to the target gear based on the magnitude of the first analog voltage signal and the second analog voltage signal.

[0041] An amplification module is used to amplify a first analog voltage signal and a second analog voltage signal based on a target range to obtain a first amplified signal and a second amplified signal.

[0042] The determination module is used to determine the impedance value of the impedance to be measured based on the first amplified signal and the second amplified signal.

[0043] Fourthly, embodiments of this application provide an electronic device, which includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The processor loads and executes the at least one instruction, at least one program, code set, or instruction set to implement the impedance measurement method of the first aspect.

[0044] Fifthly, embodiments of this application provide a computer-readable storage medium storing at least one instruction or at least one program, wherein the at least one instruction or at least one program is loaded and executed by a processor to implement the impedance measurement method of the first aspect.

[0045] Sixthly, embodiments of this application provide a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the impedance measurement method of the first aspect.

[0046] The impedance measurement device and method based on weak signal processing provided in this application have the following technical effects:

[0047] The impedance measurement device based on weak signal processing includes an impedance measurement bridge and a weak signal detection module. The impedance measurement bridge includes an excitation source module, a range resistor module, and a balance adjustment module. The excitation source module provides excitation source signals for the impedance to be measured and the range resistor module. The balance adjustment module balances the impedance measurement bridge based on the unbalanced current between the impedance to be measured and the range resistor module and the excitation source signal. The weak signal detection module includes a vector ratio acquisition unit, a multi-stage signal amplification unit, a clock synchronization unit, and multiple analog-to-digital conversion units. The vector ratio acquisition unit acquires first analog voltage signals of the impedance to be measured and second analog voltage signals of the range resistor module at different phases. The multi-stage signal amplification unit amplifies the first and second analog voltage signals by different factors based on an amplification control signal. The clock synchronization unit is connected to multiple analog-to-digital conversion units and outputs multiple equally spaced synchronous clock signals to the multiple analog-to-digital conversion units. The multiple analog-to-digital conversion units convert the amplified first and second analog voltage signals into multiple digital signals based on the multiple equally spaced synchronous clock signals and output them. In this embodiment, an impedance measurement bridge is used to extract parameter signals related to the impedance under test. Then, a weak signal detection module amplifies, synchronously samples, and performs analog-to-digital conversion on the extracted weak voltage signal to achieve impedance measurement. By combining signal extraction from a balanced bridge with noise suppression through multi-stage amplification, the system achieves high-fidelity detection of weak voltage signals in strong noise. The clock synchronization unit provides a phase-matched synchronous clock for multi-analog-to-digital conversion, avoiding measurement errors caused by phase signal sampling misalignment. The multi-stage signal amplification unit supports amplification control of different factors, is compatible with detecting weak signals of different amplitudes, and enhances the versatility of the solution. Attached Figure Description

[0048] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of a module of an impedance measurement device based on weak signal processing provided in an embodiment of this application;

[0050] Figure 2 This is a schematic diagram of an impedance measurement bridge provided in an embodiment of this application. Figure 1 ;

[0051] Figure 3 This is a schematic diagram of an impedance measurement bridge provided in an embodiment of this application. Figure 2 ;

[0052] Figure 4 This is a schematic diagram of a multi-stage signal amplification unit provided in an embodiment of this application;

[0053] Figure 5 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 1 ;

[0054] Figure 6 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 2 ;

[0055] Figure 7 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 3 ;

[0056] Figure 8 This is a schematic diagram illustrating the effect of selecting an amplified link according to an embodiment of this application. Figure 1 ;

[0057] Figure 9 This is a schematic diagram illustrating the effect of selecting an amplified link according to an embodiment of this application. Figure 2 ;

[0058] Figure 10 This is a circuit diagram of a first-stage amplification link provided in an embodiment of this application;

[0059] Figure 11 This is a schematic diagram illustrating the effect of a first-stage amplification link provided in an embodiment of this application. Figure 1 ;

[0060] Figure 12 This is a schematic diagram illustrating the effect of a first-stage amplification link provided in an embodiment of this application. Figure 2 ;

[0061] Figure 13 This is a circuit diagram of a second-stage amplification link provided in an embodiment of this application;

[0062] Figure 14 This is a schematic diagram illustrating the effect of a second-stage amplification link provided in an embodiment of this application. Figure 1 ;

[0063] Figure 15 This is a schematic diagram illustrating the effect of a second-stage amplification link provided in an embodiment of this application. Figure 2 ;

[0064] Figure 16 This is a circuit diagram of a third-stage amplification link provided in an embodiment of this application;

[0065] Figure 17 This is a schematic diagram illustrating the effect of a third-level amplification link provided in an embodiment of this application. Figure 1 ;

[0066] Figure 18 This is a schematic diagram illustrating the effect of a third-level amplification link provided in an embodiment of this application. Figure 2 ;

[0067] Figure 19 This is a schematic diagram of an analog-to-digital conversion unit and a clock synchronization unit provided in an embodiment of this application;

[0068] Figure 20 This is a schematic diagram of a clock synchronization unit provided in an embodiment of this application;

[0069] Figure 21 This is a schematic diagram of a multi-stage signal amplification unit, a clock synchronization unit, and an analog-to-digital conversion unit provided in an embodiment of this application;

[0070] Figure 22 This is a flowchart illustrating an impedance measurement method provided in an embodiment of this application. Figure 1 ;

[0071] Figure 23 This is a flowchart illustrating an impedance measurement method provided in an embodiment of this application. Figure 2 ;

[0072] Figure 24 This is a schematic diagram of the structure of an impedance measurement device provided in an embodiment of this application;

[0073] Figure 25 This is a hardware structure block diagram of a server for an impedance measurement method provided in an embodiment of this application. Detailed Implementation

[0074] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0075] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices.

[0076] Figure 1 This is a schematic diagram of an impedance measurement device based on weak signal processing provided in an embodiment of this application, including an impedance measurement bridge 100 and a weak signal detection module 200.

[0077] In one optional embodiment, the impedance measurement bridge 100 includes an excitation source module 110, a range resistor module 130, and a balance adjustment module 140, forming an automatic balance bridge for measuring the impedance to be measured 120.

[0078] The excitation source module 110 provides excitation source signals to the impedance to be measured 120 and the range resistor module 130. The first signal of the excitation source module 110 is connected to the impedance to be measured 120, and the second signal of the excitation source module 110 is connected to the range resistor module 130 through the balance adjustment module 140. The balance adjustment module 140 is used to adjust the second signal of the excitation source module 110 based on the unbalanced current between the impedance to be measured 120 and the range resistor module 130 and the excitation source signal, so that the impedance measurement bridge 100 reaches balance.

[0079] Figure 2 This is a schematic diagram of an impedance measurement bridge provided in an embodiment of this application. Figure 1 ,like Figure 2 As shown, the core principle of the balanced bridge impedance measurement is that, in the balanced state of the bridge, the electrical parameters of the impedance to be measured 120 are equivalently matched with those of the range resistor module 130 with known parameters. The excitation source module 110 provides a stable excitation signal, such as a sinusoidal signal, which acts simultaneously on the branch of the impedance to be measured 120 and the branch of the range resistor module 130, forming the two core branches of the bridge. Since the parameters of the impedance to be measured 120 are unknown, the impedances of the two branches are initially mismatched, resulting in an unbalanced current.

[0080] The balance adjustment module 140 captures this unbalanced current and, combined with the amplitude and phase information of the excitation source signal, generates a compensation signal through vector modulation or other methods. This compensation signal then adjusts the equivalent parameters of the range resistor module 130 in reverse until the unbalanced current in the balanced bridge approaches zero, at which point the bridge reaches a balanced state. Since the parameters of the range resistor module 130 are known, the specific value of the impedance to be measured 120 can be deduced by reading the parameters of the range resistor module 130 in the balanced state or the compensation parameters of the balance adjustment module 140, thus achieving impedance measurement.

[0081] In one alternative embodiment, the range resistor module 130 includes multiple reference resistors with different resistance values ​​and multiple range switches. The resistance values ​​of the reference resistors may be 10Ω, 100Ω, 1kΩ, 10kΩ, etc.

[0082] Each reference resistor is connected in series with the range switch, and multiple sets of series-connected reference resistors are connected in parallel with the range switch. Multiple reference resistors with different resistance values ​​cover a wide range and can match various test objects from low impedance to high impedance, avoiding the problem that a single reference resistor cannot meet the measurement requirements of different impedances.

[0083] Continue as Figure 1 As shown, in one optional embodiment, the weak signal detection module 200 includes a vector ratio acquisition unit 210, a multi-stage signal amplification unit 220, a clock synchronization unit 230, and multiple analog-to-digital conversion units 240.

[0084] The vector ratio acquisition unit 210 is used to acquire the first analog voltage signal of the impedance to be measured 120 and the second analog voltage signal of the range resistor module 130 at different phases.

[0085] The multi-stage signal amplification unit 220 is used to amplify the first analog voltage signal and the second analog voltage signal by different factors based on the amplification control signal.

[0086] The clock synchronization unit 230 is connected to multiple analog-to-digital converters 240, and is used to output multiple synchronous clock signals with different phases and equal intervals to the multiple analog-to-digital converters 240 respectively, to ensure that the sampling times of the multiple signals are strictly aligned. The multiple analog-to-digital converters 240 are used to convert the amplified first analog voltage signal and the second analog voltage signal into multiple digital signals and output them based on the multiple synchronous clock signals with different phases and equal intervals.

[0087] In this embodiment, the impedance measurement bridge 100 is used to extract the parameter signals related to the impedance to be measured 120. Then, the weak signal detection module 200 amplifies, synchronously samples, and performs analog-to-digital conversion on the extracted weak voltage signal to achieve impedance measurement. By combining the signal extraction of the balanced bridge with the noise suppression of multi-stage amplification, the detection of weak voltage signals in strong noise is achieved with high fidelity. The clock synchronization unit 230 provides a phase-matched synchronous clock for multi-analog-to-digital conversion, avoiding measurement errors caused by phase signal sampling misalignment. The multi-stage signal amplification unit supports amplification control of different multiples, is compatible with the detection of weak signals of different amplitudes, and enhances the versatility of the solution.

[0088] Figure 3 This is a schematic diagram of an impedance measurement bridge provided in an embodiment of this application. Figure 2 The core of the automatic balancing bridge is virtual ground and vector compensation. By detecting the unbalanced current between the impedance to be measured 120 and the range resistor module 130 and generating a reverse compensation signal, the bridge is balanced, that is, the zero-position detector output is 0. Finally, the impedance to be measured 120 is calculated by the voltage ratio.

[0089] First, a virtual ground needs to be established. The IV converter can make the potential of the low potential end of the impedance under test 120DUT approximately 0, which is a virtual ground. At this time, the feedback current Ir flowing through the range resistor module 130Rr is equal to the test current Ix flowing through the DUT. Ir=Ix, so the output voltage of the IV converter Vr=Ir×Rr=Ix×Rr.

[0090] The test current Ix is determined by the impedance Zx of the DUT and the voltage Vx across the DUT, that is, Ix = Vx / Zx.

[0091] Therefore, the formula for calculating the impedance Zx of the 120Ω DUT is Zx=(Vx / Vr)×Rr. That is, you only need to measure the ratio of Vx to Vr and then multiply it by the known resistance value of the reference resistor to obtain the impedance Zx of the DUT, thus realizing the measurement of the 120Ω impedance.

[0092] In the embodiments of this application, such as Figure 3 As shown, the balance adjustment module 140 includes a zero-position detector, a first direction circuit, a second direction circuit, and an operational amplifier.

[0093] In this embodiment of the application, the zero-position detector is used to detect the unbalanced current between the impedance to be measured 120 and the range resistor, and decomposes it into a first direction signal and a second direction signal.

[0094] The zero-position detector monitors the unbalanced current between the measured impedance 120 and the range resistor in real time, and decomposes it into two orthogonal signals: a first direction signal of 0° and a second direction signal of 90°.

[0095] like Figure 3 As shown, the first direction circuit includes a first multiplier, a first integrator circuit, and a second multiplier. The first multiplier is used to multiply the first direction signal with the first reference direction signal to obtain a component in the same direction, which is then input into the first integrator circuit for filtering. The second multiplier is used to multiply the filtered component in the same direction with the excitation source signal to obtain a first compensation signal.

[0096] The first multiplier receives the first direction signal and the 0° first reference direction signal. Through multiplication, it retains only the amplitude error information consistent with the reference direction, extracting the in-direction component. The in-direction component is input to the first integrator circuit to filter out high-frequency noise and smooth the signal, obtaining a stable DC error signal. The second multiplier multiplies the filtered DC error signal with the original excitation source signal, modulating it to generate the first compensation signal.

[0097] like Figure 3 As shown, the second direction circuit includes a third multiplier, a second integrator circuit, and a fourth multiplier. The third multiplier is used to multiply the second direction signal with the second reference direction signal to obtain an orthogonal component, which is then input into the second integrator circuit for filtering. The fourth multiplier is used to multiply the filtered in-direction component with the phase-shifted excitation source signal to obtain the second compensation signal.

[0098] The third multiplier receives the second direction signal and the second reference direction signal at 90°. Through multiplication, it retains only the phase error information perpendicular to the reference direction, extracts the quadrature component, and inputs the quadrature component into the second integrator circuit to filter out high-frequency noise and smooth the signal, obtaining a stable DC error signal. The fourth multiplier multiplies the filtered DC error signal with the -90° phase-shifted excitation source signal, modulating it to generate the second compensation signal.

[0099] The operational amplifier is used to receive the first compensation signal and the second compensation signal, combine them into one channel and output the compensation signal through the range resistor module 130, adjust the equivalent parameters of the range resistor, and finally cancel the amplitude and phase difference between the measured impedance 120 and the range resistor, so that the bridge reaches a balanced state.

[0100] After the bridge circuit reaches balance, the ratio of Vx to Vr is measured. To avoid tracking errors between the two voltmeters, Vx and Vr can be measured by alternating between individual vector voltmeters, such as... Figure 3 As shown. The circuit module containing the input channel selector and the vector voltmeter is called a vector ratio detector, named after its function of measuring the vector ratio of Vx and Vr.

[0101] By maintaining the low-side potential at zero volts through balancing, the input impedance of the IV converter drops to almost zero when measuring the impedance of the 120DUT, thus having no impact on the measurement results. At the same time, the distributed capacitance of the test cable does not affect the measurement results because there is no potential difference between the inner and outer shielding conductors of the (Lp and Lc) cable, and the protection technology can be used to eliminate stray capacitance effects.

[0102] Continue as Figure 3 As shown, in an optional embodiment, the vector ratio acquisition unit 210 includes a third switching switch and a phase detector.

[0103] The first input terminal of the third switching switch is connected between the impedance to be measured 120 and the excitation source, the second input terminal is connected between the output terminals of the range resistor module 130 and the balance adjustment module 140, and the output terminal is connected to the phase detector, which is used to acquire the first analog voltage signal Vx or the second analog voltage signal Vr based on the third switching control signal.

[0104] The phase detector is used to detect the phase value of the first analog voltage signal or the second analog voltage signal. Specifically, the selected voltage signal Vx or Vr enters the phase detector, and the phase detector receives a 0° or 90° reference signal provided by the excitation source. By performing coherent detection such as multiplying the voltage signal to be measured with the reference signal, the phase value of the voltage signal relative to the reference signal can be obtained, thereby completing the voltage phase measurement.

[0105] In an optional embodiment, the vector ratio acquisition unit 210 further includes a first buffer structure and a second buffer structure. The first buffer structure is disposed between the first input terminal of the third switching switch and the impedance to be measured 120, and the second buffer structure is disposed between the second input terminal of the third switching switch and the range resistor module 130. The first and second buffer structures serve as isolation and fidelity preservation modules for the two signals, respectively connected in series between the two input terminals of the third switching switch and the corresponding signal sources. Utilizing the high input impedance and low output impedance characteristics of the buffers, the front-end circuits such as the impedance to be measured 120 and the range resistor module 130 are isolated from the subsequent switching switches and phase detectors, preventing the load of the subsequent stage from affecting the amplitude and phase of the front-end signal, and ensuring that the acquired voltage signal truly reflects the original circuit state.

[0106] After acquiring the weak first analog voltage signal Vx or the second analog voltage signal Vr, the analog voltage signal needs to be amplified by a multi-stage signal amplification unit 220 and converted into digital signals by multiple parallel analog-to-digital conversion units 240 to obtain a precise and calculable digital signal, and finally the impedance to be measured 120Zx is calculated.

[0107] In this embodiment, the multi-stage signal amplification unit 220 includes a selective amplification link with two branches and a multi-stage amplification link that allows for flexible selection of amplification factor.

[0108] Figure 4 This is a schematic diagram of a multi-stage signal amplification unit provided in an embodiment of this application, as shown below. Figure 4 As shown, the selected amplification link includes a first switching switch, a first amplification link, a second amplification link, and a second switching switch. The first switching switch and the second switching switch connect the first amplification link or the second amplification link to the multi-stage amplification link based on the selection control signal.

[0109] The selection control signal is determined based on the amplitudes of the first analog voltage signal and the second analog voltage signal.

[0110] If the analog voltage signal is a large signal, the selection control signal controls the first and second switching switches to connect the first amplification link with the multi-stage amplification link.

[0111] If the analog voltage signal is a small signal, the selection control signal controls the first and second switching switches to connect the second amplification link to the multi-stage amplification link.

[0112] Figure 5 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 1 , Figure 5 This is the schematic diagram of the first amplification link. The amplifying element in the first amplification link is an OPA656. The large signal input that needs to be amplified is pins 3 and 4 of the OPA656, and the signal output is pin 1 of the OPA656. The gain is 0dB.

[0113] like Figure 5 As shown, pin 5 (+VS) of the amplifying component OPA656 is connected to a +5.5V power supply, and pin 2 (-VS) is connected to a -5.5V power supply, providing dual power supply for the op-amp. Pin 3, the non-inverting input IN+, is connected to the input protection circuit, specifically including resistors R678, R681, R676, and protection diode D36. The front end of resistor R678 is grounded through R681 and connected to the middle pin of protection diode D36. The two ends of D36 are connected to the +5.5V and -5.5V power supplies respectively. The middle pin of D36 is also connected via resistor R676 to the external input signal U3+ (the positive terminal of the third output signal in the diagram), forming an input overvoltage protection and voltage divider link. Pin 1 outputs the conditioned signal and connects to pin 4, the inverting input IN-, which is then connected to the U4+ node of the subsequent circuit (the positive terminal of the fourth output signal in the diagram).

[0114] Figure 6This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 2 , Figure 6 This is the schematic diagram of the second amplification link. The amplifying element in the second amplification link is LSK389-ADA4897. The small signal input that needs to be amplified is pins 4 and 8 of LSK389, and the signal output is pins 1 and 9 of ADA4897. The gain is 20dB.

[0115] like Figure 6 As shown, the second amplification link includes two JFET (Junction Field-Effect Transistor) differential structures, which respectively receive the U2-ch1 signal and the U2+ch1 signal (that is, the negative and positive terminals of the second input signal channel in the figure). Specifically, the JFET differential structure receiving U2-ch1 includes N-channel junction field-effect transistors Q1 and Q2. U2-ch1 is connected to the gate of Q2, and the gate and drain of Q1 are shorted to form a diode-connected JFET, which serves as an active load. The JFET differential structure also includes R658, one end of which is connected to the drain of Q2 and the drain of Q1, and the other end is grounded. Similarly, the JFET differential structure receiving U2+ch1 includes N-channel junction field-effect transistors Q3 and Q4, and U2+ch1 is connected to the gate of Q4.

[0116] The small signals that need to be amplified, namely the U2-ch1 signal and the U2+ch1 signal, are passed through two JFET differential structures to suppress noise and improve the signal-to-noise ratio before being input to pins 4 and 8 of the LSK389.

[0117] The second amplification link also includes a power supply filtering structure. Specifically, the power supply filtering structure includes two LC low-pass filter networks. Each LC low-pass filter network includes an inductor and two parallel capacitors. The positive power supply (+5.5V) and the negative power supply (-4.5V) are respectively connected to an LC low-pass filter network.

[0118] The power supply filtering structure also includes a π-type LC low-pass filter network to filter and decouple the positive power supply (+5.5V), providing a clean power supply for the subsequent analog circuitry. The π-type LC low-pass filter network consists of two inductors and four capacitors, with the midpoint between the two sets of capacitors grounded. The function of the power supply filtering structure is to purify the power signal, providing a stable and clean DC voltage to the circuit.

[0119] Figure 7 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 3 , Figure 7 This is a schematic diagram of the first switching switch. The first switching switch is specifically configured as a relay. The fourth relay in the diagram controls the selection of whether the amplification link uses a large signal input or a small signal input.

[0120] like Figure 7 As shown, the 8 pins of relay K24 are respectively connected to... Figure 5-6 Connect to the corresponding interface in the [system / platform].

[0121] When the common pins 3 and 6 of relay K24 are connected to pins 4 and 5 respectively, the selected amplification link branch is LSK389-ADA4897, which is the small signal amplification link; when the common pins 3 and 6 of relay K24 are connected to pins 2 and 7 respectively, the selected amplification link branch is OPA656, which is the large signal amplification link.

[0122] The two selective amplification links have different base gains, which can avoid the inability of a single link to cover the range of extremely weak to relatively weak signals, effectively increasing the signal processing range.

[0123] Figure 8 This is a schematic diagram illustrating the effect of selecting an amplified link according to an embodiment of this application. Figure 1 , Figure 8 This is the output waveform after amplification of 0dB for a 100kHz, 1Vpp sine wave input when the second amplification link is OPA656 (large signal). Figure 9 This is a schematic diagram illustrating the effect of selecting an amplified link according to an embodiment of this application. Figure 2 , Figure 9 The output waveform is when the second amplification link is LSK389-ADA4897 (small signal), the input is a 100KHz, 10mVpp sine wave, and the amplification is 20dB.

[0124] In one alternative embodiment, the multi-stage amplification link includes a first-stage amplification link, a second-stage amplification link, and a third-stage amplification link.

[0125] Figure 10 This is a circuit diagram of a first-stage amplification link provided in an embodiment of this application. The first-stage amplification link includes a first relay, a first amplifying element, and a first peripheral resistor structure. The first relay is used to receive and connect different first peripheral resistor structures to the first amplifying element based on a first amplification control signal (the control signal AB of the sixth relay in the figure), so that the first amplifying element amplifies the signal by different factors.

[0126] The first amplifying element in this application is configured as a high-speed differential operational amplifier ADA4932. The signal input is pins 2 and 3 of the ADA4932, and the signal output is pins 10 and 11 of the ADA4932. The amplification is different, that is, the gain is 0dB or 20dB.

[0127] The first relay K27 is used to switch the gain between 0dB and 20dB. When the common pins 3 and 6 of relay K27 are connected to pins 2 and 7 respectively, the feedback resistors of the first-stage amplifier link are R691 and R662 in the figure, and the input resistors are R683, R687, R688 and R689. Therefore, the gain is (R683 / / R687+R688+R689) / (R691+R662) = (1M / / 1K+1.5K+130Ω) / (100Ω+100Ω) = 20dB.

[0128] When the common pins 3 and 6 of relay K27 are connected to pins 4 and 5 respectively, the feedback resistors of the first-stage amplification link are R691, R662, R683 and R687 in the figure, and the input resistors are R688 and R689. Therefore, the gain is (R688+R689) / (R691+R662+R683 / / R687) = (1.5K+130Ω) / (100Ω+100Ω+1M / / 1K) = 0dB.

[0129] like Figure 10 As shown, the first-stage amplification link also includes two power supply filter circuits. Both the positive and negative power supply pins of the ADA4932 component are connected to a power supply filter circuit. Specifically, the power supply filter circuit includes two capacitors in parallel and a Schottky diode in parallel. The combination of the two high-frequency and low-frequency capacitors suppresses ripple and noise on the power lines, ensuring the stability of the chip's power supply. The Schottky diode prevents irreversible damage to the chip from reverse power connection or transient reverse voltage, achieving reverse protection. The function of the power supply filter circuit is to purify the power signal, providing a stable and clean DC voltage for the circuit.

[0130] Figure 11 This is a circuit diagram of a first-stage amplification link provided in an embodiment of this application. Figure 1 , Figure 11 It is the output waveform after amplifying a 100kHz, 1Vpp sine wave by 0dB when the first-stage link gain is 0dB. Figure 12 This is a circuit diagram of a first-stage amplification link provided in an embodiment of this application. Figure 2 , Figure 12 It is the output waveform after amplifying a 100kHz, 10mVpp sine wave by 20dB when the first-stage link gain is 20dB.

[0131] Figure 13This is a circuit diagram of a second-stage amplification link provided in an embodiment of this application. The second-stage amplification link includes a second relay, a second amplifying element, and a second peripheral resistor structure. The second relay is used to receive and connect different second peripheral resistor structures to the second amplifying element based on the second amplification control signal (the control signal AB of the seventh relay in the figure), so that the second amplifying element amplifies the signal by different factors.

[0132] The second amplifying element in this application is configured as a high-speed differential operational amplifier ADA4932, with signal inputs at pins 10 and 11 of ADA4932, signal outputs at pins 3 and 6 of relay K26, and a gain of 0dB or -10dB.

[0133] When the common pins 3 and 6 of relay K26 are connected to pins 4 and 5 respectively, the feedback resistor of the second-stage amplification link is R690 in the figure, the input resistor is R710 in the figure, and the gain is R710 / R690=100Ω / 100Ω=0dB.

[0134] When the common pins 3 and 6 of relay K26 are connected to pins 2 and 7 respectively, the feedback resistor of the second-stage amplification link is R694 in the figure, the input resistor is R710 in the figure, and the gain is R710 / R694=100Ω / 267Ω=-10dB.

[0135] like Figure 13 As shown, the second-stage amplification link also includes two power supply filter circuits to purify the power supply signal and provide a stable and clean DC voltage for the circuit.

[0136] Figure 14 This is a schematic diagram illustrating the effect of a second-stage amplification link provided in an embodiment of this application. Figure 1 , Figure 14 It is the output waveform after amplifying a 100kHz, 1Vpp sine wave by 0dB when the second-stage link gain is 0dB. Figure 15 This is a schematic diagram illustrating the effect of a second-stage amplification link provided in an embodiment of this application. Figure 2 , Figure 15 It is the output waveform after amplifying a 100kHz, 1Vpp sine wave by -10dB when the second-stage link gain is -10dB.

[0137] Figure 16 This is a circuit diagram of a third-stage amplification link provided in an embodiment of this application. The third-stage amplification link includes a third relay, a third amplifying element, and a third peripheral resistor structure. The third relay is used to receive and connect different third peripheral resistor structures to the third amplifying element based on the third amplification control signal (the control signal AB of the eighth relay in the figure), so that the third amplifying element amplifies the signal by different factors.

[0138] The third amplifying element in this application is configured as a high-speed differential operational amplifier ADA4932 input amplification link schematic diagram. The signal input is pins 2 and 3 of ADA4932, the signal output is pins 10 and 11 of ADA4932, and the gain is 0dB or 20dB.

[0139] The third relay K28 is used to switch the gain between 0dB and 20dB. When the common pins 3 and 6 of relay K28 are connected to pins 2 and 7 respectively, the feedback resistors of the third-stage amplifier link are R710 and R690 in the figure, the input resistors are R711 and R712 in the figure, and the gain is (R711+R712) / (R710+R690) = (909Ω+909Ω) / (100Ω+100Ω) = 20dB.

[0140] When the common pins 3 and 6 of relay K28 are connected to pins 4 and 5 respectively, the feedback resistors of the third-stage amplification link are R711, R710 and R690 in the figure, the input resistor is R712 in the figure, and the gain is R712 / (R711+R710+R690)=909Ω / (909Ω+100Ω+100Ω)=0dB.

[0141] like Figure 16 As shown, the third-stage amplification link also includes two power supply filter circuits to purify the power supply signal and provide a stable and clean DC voltage for the circuit.

[0142] The third-stage amplification link also includes an output filtering circuit. This circuit comprises a low-pass filter network for the differential signal, consisting of two completely symmetrical branches, corresponding to the negative terminal (ADA4932_OUT-_ch1) and positive terminal (ADA4932_OUT+_ch1) of the first channel of the differential output signal from the ADA4932, respectively. Specifically, the output filtering circuit includes inductors L101 and L102, resistors R714 and R716, and capacitors C859, C860, and C861. One end of inductor L101 is connected to the negative terminal of the differential output, ADA4932_OUT-_ch1, and the other end is connected to resistor R714. The other end of resistor R714 is connected to the negative output pin (-OUT) of the ADA4932. Capacitor C859 is connected between the midpoint between inductor L101 and resistor R714 and ground. One end of inductor L102 is connected to resistor R716, and the other end is connected to the positive terminal of the differential output ADA4932_OUT+_ch1. The other end of R716 is connected to the positive output pin (+OUT) of ADA4932. A capacitor C861 is connected between the midpoint of inductor L102 and resistor R716 and ground. C860 is connected in parallel with one end of R716 and R714. The function of the output filter circuit is to filter out noise, improve the signal-to-noise ratio of the output signal, and make the useful signal cleaner.

[0143] Figure 17 This is a schematic diagram illustrating the effect of a third-level amplification link provided in an embodiment of this application. Figure 1 , Figure 17 It is the output waveform after amplifying a 100kHz, 1Vpp sine wave by 0dB when the third-level link gain is 0dB. Figure 18 This is a schematic diagram illustrating the effect of a third-level amplification link provided in an embodiment of this application. Figure 2 , Figure 18 This is the output waveform after amplifying a 100kHz, 10mVpp sine wave by 20dB when the third-level link gain is 20dB.

[0144] By selecting the combination of the amplification link and the three-stage amplification link, eight different gain levels can be achieved, including the following:

[0145] 3V setting: Select the gain of the amplification link as 0dB, the gain of the first-stage amplification link as 0dB, the gain of the second-stage amplification link as -10dB, the gain of the third-stage amplification link as 0dB, and the total gain as 0dB + 0dB - 10dB + 0dB = -10dB.

[0146] 1V setting: Select the gain of the amplification link as 0dB, the gain of the first-stage amplification link is 0dB, the gain of the second-stage amplification link is 0dB, the gain of the third-stage amplification link is 0dB, and the total gain is 0dB+0dB+0dB+0dB=0dB.

[0147] 300mV range: Select the gain of the amplification link as 0dB, the gain of the first-stage amplification link as 20dB, the gain of the second-stage amplification link as -10dB, the gain of the third-stage amplification link as 0dB, and the total gain as 0dB + 20dB - 10dB + 0dB = 10dB.

[0148] 100mV range: Select the gain of the amplification link as 0dB, the gain of the first-stage amplification link as 20dB, the gain of the second-stage amplification link as 0dB, the gain of the third-stage amplification link as 0dB, and the total gain as 0dB + 20dB + 0dB + 0dB = 20dB.

[0149] 30mV range: Select a gain of 20dB for the amplification link, a gain of 20dB for the first stage amplification link, a gain of -10dB for the second stage amplification link, and a gain of 0dB for the third stage amplification link. The total gain is 20dB + 20dB - 10dB + 0dB = 30dB.

[0150] 10mV range: Select a gain of 20dB for the amplification link, a gain of 20dB for the first stage amplification link, a gain of 0dB for the second stage amplification link, a gain of 0dB for the third stage amplification link, and a total gain of 20dB + 20dB + 0dB + 0dB = 40dB.

[0151] 3mV range: Select a gain of 20dB for the amplification link, a gain of 20dB for the first stage amplification link, a gain of -10dB for the second stage amplification link, and a gain of 0dB for the third stage amplification link. The total gain is 20dB + 20dB - 10dB + 20dB = 50dB.

[0152] 1mV range: Select a gain of 20dB for the amplification link, a gain of 20dB for the first stage amplification link, a gain of 0dB for the second stage amplification link, a gain of 20dB for the third stage amplification link, and a total gain of 20dB + 20dB + 0dB + 20dB = 60dB.

[0153] Figure 19 This is a schematic diagram of an analog-to-digital conversion unit and a clock synchronization unit provided in an embodiment of this application. In a parallel analog-to-digital converter (ADC) acquisition architecture, designing a multi-channel low-jitter sampling clock system is crucial for ensuring system performance. In conventional implementations, the clock signal coordinating the collaborative operation of multiple ADCs is usually generated using a clock distribution chip. From a hardware implementation perspective, this method has the advantage of relative simplicity. However, in the actual circuit board design stage, factors such as the wiring layout of the printed circuit board (PCB) and manufacturing errors inherent in the electronic components themselves will inevitably cause a certain degree of jitter in the output clock signal, thus significantly increasing the uncertainty of the clock signal. In addition, these electronic components are highly susceptible to interference from external environmental factors, such as fluctuations in power supply voltage, changes in operating temperature, and process deviations in the manufacturing process of specific components. These factors will further exacerbate the uncertainty of the clock signal, ultimately leading to timing deviations in the ADC. For parallel ADC structures with extremely stringent requirements for clock signal accuracy, such timing deviations are intolerable and will seriously affect the performance and stability of the entire system.

[0154] Figure 20 This is a schematic diagram of a clock synchronization unit provided in an embodiment of this application. In an optional embodiment, in order to meet the requirements of a multi-channel parallel ADC system for low jitter and high-precision clock signals, the clock synchronization unit 230 includes a clock input structure and a clock tree structure.

[0155] The clock tree topology is as follows: Figure 20As shown, the clock tree structure includes a clock tree root and multi-level fan-out buffers, exhibiting high flexibility and scalability, and can flexibly configure the number of clock signal output channels according to the needs of actual application scenarios.

[0156] Each fan-out buffer stage includes deterministic time error and uncertain time error. The deterministic time error is represented by t1 and t2 in the figure, and the uncertain time error is represented by Δt1 and Δt2 in the figure.

[0157] The deterministic timing error originates from the inherent timing characteristics of each component in the clock tree and can be accurately corrected through subsequent data processing algorithms. The uncertain timing error, however, is caused by a combination of factors, including PCB routing parasitic parameters, component performance fluctuations, and environmental interference. Therefore, the high-performance dual-loop integer N-division jitter attenuator HMC7044 serves as the root node of the clock tree. This chip supports sending Serial Peripheral Interface (SPI) commands or Synchronization Request (SYNC) signals via host computer software to achieve precise phase alignment of the output clock signal. During this process, the chip's built-in general-purpose reference signal timer is synchronously reset, ensuring high-precision synchronization of all clock output dividers. Furthermore, the HMC7044 supports generating a specific number of output pulses via host computer software as internal reference signal pulses, providing a reliable reference for the synchronization of multi-channel clock signals. The proposed solution effectively compensates for skew errors between output stages and errors caused by inconsistent line lengths at each output stage during subsequent PCB fabrication. The proposed clock tree structure significantly reduces the uncertainty error of the clock signal, providing a high-precision, low-jitter clock signal guarantee for the parallel ADC system.

[0158] The clock tree root receives the original clock signal from the clock input structure, inputs it into a multi-stage fan-out buffer, and forms multiple synchronous clock signals. These multiple synchronous clock signals are connected to multiple analog-to-digital conversion units respectively.

[0159] After receiving the original clock signal through the clock input structure and clock tree structure, the signal is processed by the clock tree root HMC7044 chip and multi-level fan-out buffers to generate multiple synchronous clock signals, which are then distributed to multiple analog-to-digital converters to meet the clock requirements of multi-channel parallel sampling.

[0160] For the two types of time errors in the clock tree, precise control is achieved through hardware selection and algorithm cooperation. Deterministic time errors caused by the inherent timing characteristics of components can be corrected by subsequent data processing algorithms; while uncertain time errors caused by PCB routing, environmental interference, etc. are significantly suppressed by the jitter attenuation function of the HMC7044 chip, while compensating for errors such as inconsistent line length and output skew.

[0161] Meanwhile, by using the SPI command or SYNC signal control of the HMC7044 chip, the phase alignment of multiple output clocks is achieved. The built-in timer synchronous reset ensures high-precision synchronization of all clock dividers, providing a unified reference for multi-channel analog-to-digital conversion, avoiding phase signal distortion caused by sampling time misalignment, and ensuring that weak voltage signals with different phases and equal intervals still maintain their original phase relationship after conversion.

[0162] Furthermore, the clock tree structure offers high flexibility and scalability, allowing for flexible configuration of the number of clock signal output channels based on actual application needs, adapting to different numbers of analog-to-digital converters, and enhancing the versatility of the solution.

[0163] Figure 21 This is a schematic diagram of a multi-stage signal amplification unit, a clock synchronization unit, and an analog-to-digital conversion unit provided in an embodiment of this application.

[0164] The following describes a specific embodiment of an impedance measurement method according to this application. Figure 22 This is a flowchart illustrating an impedance measurement method provided in an embodiment of this application. Figure 1 This specification provides method operation steps as shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only execution order. In actual system or server products, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment). Specifically, as shown in the embodiments or drawings... Figure 22 As shown, this method, applied to the aforementioned impedance measurement device based on weak signal processing, may include:

[0165] S201: When the impedance measurement bridge reaches equilibrium, detect the first analog voltage signal and the second analog voltage signal.

[0166] S202: Receives manual automatic gain control commands; manual automatic gain control commands include preset gears.

[0167] S203: Switch the multi-stage signal amplification unit to the preset level.

[0168] S204: Adjust the preset gear to the target gear based on the magnitude of the first analog voltage signal and the second analog voltage signal.

[0169] S205: Amplify the first analog voltage signal and the second analog voltage signal based on the target gear to obtain the first amplified signal and the second amplified signal.

[0170] S206: Determine the impedance value of the impedance to be measured based on the first amplified signal and the second amplified signal.

[0171] Figure 23 This is a flowchart illustrating an impedance measurement method provided in an embodiment of this application. Figure 2 The method may include:

[0172] S301: When the impedance measurement bridge reaches equilibrium, detect the first analog voltage signal and the second analog voltage signal.

[0173] After the impedance measurement bridge reaches a balanced state, the vector ratio acquisition unit detects and acquires the first analog voltage signal Vx corresponding to the impedance under test and the second analog voltage signal Vr corresponding to the range resistor module. At this point, the imbalance interference between the two signals has been eliminated, providing a stable and accurate original signal for subsequent amplification.

[0174] S302: Receives manual automatic gain control commands; manual automatic gain control commands include preset gears.

[0175] Users can specify the initial range as 1V or 3V based on experience or the approximate range of the impedance to be measured.

[0176] S303: Switches the multi-stage signal amplification unit to the preset level.

[0177] S304: Adjust the preset gear to the target gear based on the magnitude of the first analog voltage signal and the second analog voltage signal.

[0178] In one optional embodiment, adjusting a preset level to a target level based on the magnitudes of a first analog voltage signal and a second analog voltage signal includes:

[0179] S3041: Obtain the output signal corresponding to the current gear.

[0180] S3042: Determine whether the output signal is in a saturated state. If yes, execute S3043; otherwise, execute S3044.

[0181] S3043: Controls the multi-stage signal amplification unit to increase the current gear by one level, and uses the increased gear as the current gear.

[0182] S3044: Determine the current gear as the target gear.

[0183] In one possible embodiment, if the output signal is saturated, it means that the current gear gain is too high. The multi-stage signal amplification unit is controlled to increase the current gear by one level, that is, to reduce the gain, and the increased gear is used as the current gear.

[0184] In another possible embodiment, if the output signal is in a non-saturated state, it indicates the magnitude of the gain adaptation signal for the current gear, and the current gear is determined to be the target gear.

[0185] By adjusting the gear positions as described above, it can be ensured that the output signal is neither saturated nor distorted, and that it can meet the requirements of subsequent conversion.

[0186] S305: Amplify the first analog voltage signal and the second analog voltage signal based on the target gear to obtain the first amplified signal and the second amplified signal.

[0187] S306: Determine the impedance value of the impedance to be measured based on the first amplified signal and the second amplified signal.

[0188] Finally, by multiplying the ratio of the amplified first analog voltage signal Vx and the second analog voltage signal Vr by the known resistance value of the reference resistor, the impedance value Zx of the impedance to be measured is obtained.

[0189] This application also provides an impedance measurement device. Figure 24 This is a schematic diagram of the structure of an impedance measurement device provided in an embodiment of this application, as shown below. Figure 24 As shown, the device 400 includes:

[0190] Detection module 401 is used to detect the first analog voltage signal and the second analog voltage signal when the impedance measurement bridge reaches equilibrium;

[0191] Receiver module 402 is used to receive manual automatic gain control commands; the manual automatic gain control commands include preset levels;

[0192] The gear switching module 403 is used to switch the multi-stage signal amplification unit to a preset gear.

[0193] The gear adjustment module 404 is used to adjust the preset gear to the target gear based on the magnitude of the first analog voltage signal and the second analog voltage signal.

[0194] Amplification module 405 is used to amplify the first analog voltage signal and the second analog voltage signal based on the target range to obtain the first amplified signal and the second amplified signal;

[0195] The determination module 406 is used to determine the impedance value of the impedance to be measured based on the first amplified signal and the second amplified signal.

[0196] In one alternative implementation, it further includes:

[0197] The acquisition module is used to acquire the output signal corresponding to the current gear.

[0198] The first determining module is used to control the multi-stage signal amplification unit to increase the current gear by one level if the output signal is in a saturated state, and to use the increased gear as the current gear; or, if the output signal is in a non-saturated state, to determine the current gear as the target gear.

[0199] The apparatus and method embodiments in this application are based on the same application concept.

[0200] The methods and embodiments provided in this application can be executed on a computer terminal, server, or similar computing device. Taking running on a server as an example, Figure 25 This is a hardware structure block diagram of a server for an impedance measurement method provided in an embodiment of this application. Figure 25 As shown, the server 500 can vary significantly due to different configurations or performance. It may include one or more Central Processing Units (CPUs) 510 (CPUs 510 may include, but are not limited to, microprocessors such as MCUs or programmable logic devices such as FPGAs), a memory 530 for storing data, and one or more storage media 520 (e.g., one or more mass storage devices) for storing application programs 523 or data 522. The memory 530 and storage media 520 may be temporary or persistent storage. The program stored in the storage media 520 may include one or more modules, each module may include a series of instruction operations on the server. Furthermore, the CPU 510 may be configured to communicate with the storage media 520 and execute the series of instruction operations stored in the storage media 520 on the server 500. Server 500 may also include one or more power supplies 560, one or more wired or wireless network interfaces 550, one or more input / output interfaces 540, and / or one or more operating systems 521, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0201] The input / output interface 540 can be used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of server 500. In one example, the input / output interface 540 includes a network interface controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the input / output interface 540 may be a radio frequency (RF) module used for wireless communication with the Internet.

[0202] Those skilled in the art will understand that Figure 25 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, server 500 may also include... Figure 25 The more or fewer components shown, or having the same Figure 25The different configurations shown.

[0203] This application provides an electronic device, which includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The processor loads and executes the at least one instruction, at least one program, code set, or instruction set to implement the above-described data processing method.

[0204] Embodiments of this application also provide a computer-readable storage medium, which can be disposed in a server to store at least one instruction, at least one program, code set, or instruction set related to implementing an impedance measurement method in the method embodiment. The at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the impedance measurement method described above.

[0205] Optionally, in this embodiment, the storage medium may be located at at least one of the multiple network servers in a computer network. Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0206] As can be seen from the embodiments of the impedance measurement method, apparatus, electronic device, or storage medium provided in this application, the parameter signals related to the impedance to be measured are extracted by the impedance measurement bridge, and then the weak signal detection module amplifies, synchronously samples, and performs analog-to-digital conversion on the extracted weak voltage signal to achieve impedance measurement. The combination of signal extraction by the balanced bridge and noise suppression by multi-stage amplification enables the high-fidelity detection of weak voltage signals in strong noise. The clock synchronization unit provides a phase-matched synchronous clock for multi-analog-to-digital conversion, avoiding measurement errors caused by phase signal sampling misalignment. The multi-stage signal amplification unit supports amplification control of different factors, is compatible with the detection of weak signals of different amplitudes, and enhances the versatility of the solution.

[0207] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0208] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0209] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0210] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An impedance measurement device based on weak signal processing, characterized in that, Includes an impedance measurement bridge and a weak signal detection module; The impedance measurement bridge includes an excitation source module, a range resistor module, and a balance adjustment module; the excitation source module is used to provide an excitation source signal to the impedance to be measured and the range resistor module; the balance adjustment module is used to balance the impedance measurement bridge based on the unbalanced current between the impedance to be measured and the range resistor module and the excitation source signal. The weak signal detection module includes a vector ratio acquisition unit, a multi-stage signal amplification unit, a clock synchronization unit, and multiple analog-to-digital conversion units. The vector ratio acquisition unit is used to acquire a first analog voltage signal of the impedance to be measured and a second analog voltage signal of the range resistor module. The multi-stage signal amplification unit is used to amplify the first analog voltage signal and the second analog voltage signal by different factors based on an amplification control signal. The clock synchronization unit is connected to the multiple analog-to-digital conversion units and is used to output multiple equally spaced synchronous clock signals to the multiple analog-to-digital conversion units. The multiple analog-to-digital conversion units are used to convert the amplified first analog voltage signal and the second analog voltage signal into multiple digital signals based on the multiple equally spaced synchronous clock signals and output them. The multi-stage signal amplification unit includes a selective amplification link and a multi-stage amplification link. The selective amplification link includes a first amplification link and a second amplification link. The first amplification link is used to amplify a first signal, and the second amplification link is used to amplify a second signal. The first signal is greater than the second signal. The clock synchronization unit includes a clock input structure and a clock tree structure; the clock tree structure includes a clock tree root and a multi-level fan-out buffer; each level of the fan-out buffer includes deterministic time error and uncertain time error; the clock tree root receives the original clock signal input from the clock input structure and inputs it into the multi-level fan-out buffer to form multiple synchronous clock signals, which are respectively connected to the multiple analog-to-digital conversion units.

2. The impedance measurement device based on weak signal processing according to claim 1, characterized in that, The selected amplification link includes a first switching switch, a first amplification link, a second amplification link, and a second switching switch; the first switching switch and the second switching switch connect the first amplification link or the second amplification link to the multi-stage amplification link based on a selection control signal.

3. The impedance measurement device based on weak signal processing according to claim 2, characterized in that, The multi-stage amplification link includes a first-stage amplification link, a second-stage amplification link, and a third-stage amplification link; The first-stage amplification link includes a first relay, a first amplification element, and a first peripheral resistor structure; the first relay is used to receive and, based on a first amplification control signal, connect different first peripheral resistor structures to the first amplification element, so that the first amplification element amplifies the signal by different factors. The second-stage amplification link includes a second relay, a second amplification element, and a second peripheral resistor structure; The second relay is used to receive and, based on the second amplification control signal, connect different second peripheral resistor structures to the second amplification element, so that the second amplification element amplifies the signal by different factors; The third-stage amplification link includes a third relay, a third amplification element, and a third peripheral resistor structure; The third relay is used to receive and, based on the third amplification control signal, connect different third peripheral resistor structures to the third amplification element, so that the third amplification element amplifies the signal by different factors.

4. The impedance measurement device based on weak signal processing according to claim 1, characterized in that, The balance adjustment module includes a zero-position detector, a first direction circuit, a second direction circuit, and an operational amplifier; The zero-position detector is used to detect the unbalanced current between the impedance to be measured and the range resistor, and decomposes it into a first direction signal and a second direction signal. The first direction circuit includes a first multiplier, a first integrator, and a second multiplier. The first multiplier is used to multiply the first direction signal with the first reference direction signal to obtain a co-directional component, which is then input into the first integrator for filtering. The second multiplier is used to multiply the filtered co-directional component with the excitation source signal to obtain a first compensation signal. The second direction circuit includes a third multiplier, a second integrator circuit, and a fourth multiplier. The third multiplier is used to multiply the second direction signal with the second reference direction signal to obtain an orthogonal component, which is then input into the second integrator circuit for filtering. The fourth multiplier is used to multiply the filtered in-direction component with the phase-shifted excitation source signal to obtain a second compensation signal. The operational amplifier is used to receive the first compensation signal and the second compensation signal, and output the compensation signal to the range resistor module.

5. The impedance measurement device based on weak signal processing according to claim 1, characterized in that, The vector ratio acquisition unit includes a third switching switch and a phase detector; The first input terminal of the third switching switch is connected between the impedance to be measured and the excitation source, the second input terminal is connected between the output terminal of the range resistor module and the balance adjustment module, and the output terminal is connected to the phase detector, for acquiring the first analog voltage signal or the second analog voltage signal based on the third switching control signal; The phase detector is used to detect the phase value of the first analog voltage signal or the second analog voltage signal.

6. The impedance measurement device based on weak signal processing according to claim 5, characterized in that, The vector ratio acquisition unit further includes a first buffer structure and a second buffer structure; the first buffer structure is disposed between the first input terminal of the third switching switch and the impedance to be measured, and the second buffer structure is disposed between the second input terminal of the third switching switch and the range resistor module.

7. The impedance measurement device based on weak signal processing according to claim 1, characterized in that, The range resistor module includes multiple reference resistors with different resistance values ​​and multiple range switches; each reference resistor is connected in series with the range switch; multiple sets of series-connected reference resistors are connected in parallel with the range switches.

8. An impedance measurement method, characterized in that, An impedance measurement device based on weak signal processing as described in any one of claims 1-7, comprising: When the impedance measurement bridge reaches equilibrium, the first analog voltage signal and the second analog voltage signal are detected. Receives manual automatic gain control commands; the manual automatic gain control commands include preset levels; Switch the multi-stage signal amplification unit to the preset level; Adjust the preset gear to the target gear based on the magnitudes of the first and second analog voltage signals; Based on the target gear, the first analog voltage signal and the second analog voltage signal are amplified to obtain the first amplified signal and the second amplified signal; The impedance value of the impedance to be measured is determined based on the first amplified signal and the second amplified signal.

9. An impedance measurement method according to claim 8, characterized in that, Adjusting the preset gear to the target gear based on the magnitudes of the first and second analog voltage signals includes: Obtain the output signal corresponding to the current gear; If the output signal is saturated, the multi-stage signal amplification unit is controlled to increase the current gear by one level, and the increased gear is taken as the current gear; or, if the output signal is unsaturated, the current gear is determined as the target gear.

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