Driving circuit and driving method suitable for reverse charge pump
By improving the charge pump drive circuit design and adopting multiple drive branches and current mirror technology, the problem of insufficient soft-start capability of the reverse charge pump during startup is solved, and effective voltage boost and current limiting protection under low voltage are achieved, reducing chip cost and energy loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNISEMI POWER INC
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-17
AI Technical Summary
Existing charge pump drive circuits suffer from problems such as insufficient soft-start capability, poor load-carrying capacity, and high cost during reverse charging, especially under low voltage conditions where it is difficult to effectively boost voltage and suppress overcharge current.
The design employs a drive circuit that includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor. It achieves soft start and current limiting protection through multiple drive branches and switching circuits, and provides strong drive capability by combining current mirror technology.
It achieves soft-start of reverse charge pump, suppresses overcharge current, provides greater soft-start drive capability, and successfully boosts voltage at low voltage, reducing chip cost and energy loss.
Smart Images
Figure CN121886907A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application belong to the field of circuit technology, and in particular relate to a driving circuit and driving method suitable for a reverse charge pump. Background Technology
[0002] like Figure 1 As shown, current mainstream 2:1 charge pump products generally only support forward buck charging for fast charging of electronic devices. However, there is an increasing demand for using portable devices to provide higher voltages to external loads (such as wireless reverse charging of another device, or providing programming / erasing voltage for memory devices, or providing high voltage for source and gate driving of LCD / OLED screens). In other words, reverse charging of charge pumps is becoming a trend.
[0003] For forward 2:1 charging, the design is relatively simple since there is a power supply plugged into the input terminal vin. For reverse 1:2 charging, initially only vout is powered by the battery, and the input terminal acts as the load terminal. Therefore, vout needs to be used to generate the internal power supply of the chip, as well as the power supply for the large transistor drive module. The second transistor Q1 to the fifth transistor Q4 are generally NMOS power transistors, and their gate voltage needs to be higher than their source voltage. In particular, the second transistor Q1 and the third transistor Q2 are high-side transistors, requiring even higher drive voltages. The design of the power supply unit becomes particularly important. The traditional approach is to use vout to generate the internal charge pump VCP voltage of 3*vout, which requires a very strong internal charge pump (mA level) and external capacitors to enhance the drive capability.
[0004] During startup, since the initial voltage at the VIN terminal is 0 and a voltage regulator capacitor larger than 10uF is connected, a soft start is required to suppress inrush current. The conventional approach is to connect a MOSFET in series at the VIN terminal for current limiting, but this increases chip cost and reduces efficiency. Simultaneously, it is desirable to maximize the drive capability during soft start. Existing methods generally have poor load-carrying capacity for soft start, failing to start above 10mA.
[0005] In addition, it is desirable to boost the voltage for low voltage vout, which places higher demands on the design of the drive circuit, as too much drive voltage cannot be lost.
[0006] Existing charge pump drive circuits require a series MOSFET for soft-start, which increases chip cost and reduces efficiency during normal operation. Alternatively, an additional current mirror can be used for current-limiting startup, which suppresses the load-carrying capacity during soft-start.
[0007] Furthermore, existing driver circuit designs typically use diodes and clamping MOSFETs to provide power to the driver circuit, resulting in drive voltage loss and making it less suitable for low-voltage start-up. Alternatively, additional off-chip capacitors can be added to create a separate charge pump to provide stronger drive capability, but this increases cost. Summary of the Invention
[0008] To solve or alleviate the technical problems in the prior art, embodiments of this application provide a driving circuit suitable for a reverse charge pump, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor;
[0009] The source of the first transistor is connected to the load to be charged, the drain of the first transistor is connected to the drain of the second transistor, the source of the second transistor is connected to the drain of the third transistor, the source of the third transistor is connected to the drain of the fourth transistor, the source of the fourth transistor is connected to the drain of the fifth transistor, and the source of the fifth transistor is grounded.
[0010] The first common terminal between the source of the second transistor and the drain of the third transistor is connected to the lower plate of the first capacitor;
[0011] The second common terminal between the source of the third transistor and the drain of the fourth transistor is connected to the input terminal of the internal charge pump.
[0012] The upper plate of the second capacitor is connected to the lower plate of the first capacitor, and the third common terminal between the source of the fourth transistor and the drain of the fifth transistor is connected to the lower plate of the second capacitor.
[0013] The gate of the first transistor is connected to the first driving branch, the gate of the second transistor is connected to the second driving branch, the gate of the third transistor is connected to the third driving branch, the gate of the fourth transistor is connected to the fourth driving branch through the first switch, and the gate of the fifth transistor is connected to the fifth driving branch through the second switch.
[0014] The internal charge pump outputs a first power supply and a second power supply through a switching circuit. A third switch is provided between the switching circuit and the upper plate of the first capacitor. When the third switch is closed, the first power supply charges the first capacitor. The first power supply is also used to supply power to the second drive branch. The ground terminal of the second drive branch is connected to the source of the second transistor.
[0015] The third driving branch is also connected to the fourth common terminal through the fourth switch. When the fourth switch is open, the third driving branch is powered by the second power supply. When the fourth switch is closed, the third driving branch is powered by the fourth common terminal between the drain of the first transistor and the drain of the second transistor. The ground terminal of the third driving branch is connected to the source of the third transistor.
[0016] The fourth driving branch is connected to the first common terminal, and the first common terminal supplies power to the fourth driving branch. The ground terminal of the fourth driving branch is connected to the source of the fourth transistor.
[0017] The fifth driving branch is connected to the second common terminal, and the second common terminal supplies power to the fifth driving branch. The ground terminal of the fifth driving branch is connected to the source of the fifth transistor.
[0018] The gate of the fourth transistor is also connected to the first current generating circuit via a fifth switch; the gate of the fifth transistor is also connected to the second current generating circuit via a sixth switch.
[0019] In a preferred embodiment of this application, the first current generating circuit includes a sixth transistor, a first current source, and a first control circuit; the second current generating circuit includes a seventh transistor, a second current source, and a second control circuit.
[0020] The gate of the fourth transistor is also connected to the gate drain of the sixth transistor through the fifth switch. The source of the sixth transistor is connected to the third common terminal. When the first switch is open and the fifth switch is closed, the sixth transistor and the fourth transistor form a current mirror. The gate drain of the sixth transistor is connected to the first current source. The first current source is also connected to the first control circuit. The first control circuit controls whether the current flowing out of the first current source flows through the sixth transistor.
[0021] The gate of the fifth transistor is also connected to the gate drain of the seventh transistor through the sixth switch. The source of the seventh transistor is grounded. When the second switch is open and the sixth switch is closed, the seventh transistor and the fifth transistor form a current mirror. The gate drain of the seventh transistor is connected to the second current source. The second current source is also connected to the second control circuit. The second control circuit controls whether the current flowing out of the second current source flows through the seventh transistor.
[0022] As a preferred embodiment of this application, the switching circuit includes: a seventh switch, an eighth switch, and a ninth switch;
[0023] The output terminal of the internal charge pump is connected to the seventh switch, and the seventh switch is connected to the eighth and ninth switches. When the seventh and eighth switches are closed, the internal charge pump outputs a first power supply; when the seventh and ninth switches are closed, the internal charge pump outputs a second power supply.
[0024] As a preferred embodiment of this application, it also includes an eighth transistor;
[0025] The gate of the eighth transistor is connected to the third driving branch, the drain of the eighth transistor is connected to the first common terminal, and the source of the eighth transistor is connected to the second common terminal. The aspect ratio of the eighth transistor is greater than that of the third transistor.
[0026] In a second aspect, embodiments of this application provide a method for driving a reverse external charge pump, the method being applied to the circuit described in any one of the first aspects, the method comprising:
[0027] When the external charge pump is in reverse working mode, the internal charge pump starts to work until the voltage at the output terminal of the internal charge pump is greater than the voltage at the input terminal of the internal charge pump. Then, the first and second switches are closed, and the third, fourth, fifth, sixth, seventh, eighth and ninth switches are turned off.
[0028] The first transistor is turned on by the first drive branch, and the first, second, third, seventh, eighth and ninth switches are closed; the fourth, fifth and sixth switches are turned off, and the first capacitor is charged by the internal charge pump.
[0029] The third and eighth transistors are controlled to turn on, the second and fourth transistors are controlled to turn off, the third, seventh, eighth, ninth, first, and sixth switches are controlled to close, and the second, fourth, and fifth switches are controlled to turn off. The second control circuit controls the current flowing out of the second current source to drive the seventh transistor to turn on and provide a bias voltage for the fifth transistor. The fifth transistor is in current mirror working mode. The third drive branch is powered by the second power supply. The voltage of the second capacitor is detected. If the voltage of the second capacitor is greater than the third preset threshold, the second capacitor is successfully charged.
[0030] The third, seventh, ninth, fifth, and sixth switches are controlled to close, while the first, second, fourth, and eighth switches are turned off. The fourth common terminal is charged by controlling the three transistors, the fifth transistor, the second transistor, and the fourth transistor to alternately turn on and off.
[0031] The system controls the first, second, third, and fourth switches to close, and controls the fifth, sixth, seventh, eighth, and ninth switches to close. Power is supplied to the second drive branch through the first capacitor, and power is supplied to the third drive branch through the fourth common terminal. The fourth and fifth transistors are in non-current mirror operating mode. The third and eighth transistors enter fully open mode. By controlling the third, fifth, second, and fourth transistors to alternately open and close, the system charges the load to be charged.
[0032] In a preferred embodiment of this application, after charging the first capacitor, the following steps are included:
[0033] Voltage detection is performed on the source of the first transistor and the upper plate of the first capacitor; if the difference between the fourth common terminal and the source of the first transistor is greater than a first set threshold, the load to be charged can be overloaded; if the difference between the upper plate and the lower plate of the first capacitor is less than a second set threshold, the first capacitor is successfully charged.
[0034] Compared with the prior art, the embodiments of this application realize the startup timing design of the external charge pump reverse 1:2 charge pump by adding a first drive branch, a second drive branch, a third drive branch, a fourth drive branch and a fifth drive branch; by using the corresponding drive circuit scheme of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor to meet the requirements of low voltage startup, this application realizes the soft start of the reverse boost charge pump, suppresses overcharging current, and provides as much soft start drive capability as possible, and provides current limiting protection during the soft start process. If the design threshold is exceeded, the startup will be stopped. Attached Figure Description
[0035] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0036] Figure 1 This is an architecture diagram of a current-technology charge pump;
[0037] Figure 2 This is the timing diagram for a charge pump operating normally in a 2:1 forward direction;
[0038] Figure 3 This is the circuit diagram for the charge pump drive;
[0039] Figure 4This is a timing diagram of the charge pump operating normally in reverse 1:2. Detailed Implementation
[0040] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.
[0041] It should be noted that the main function of the charge pump in the circuit is to generate the various medium-to-high driving voltages and operating voltages required by the chip. The specific application scenario in this application is: providing higher voltages to external loads via portable electronic devices (such as mobile phones) (e.g., wireless reverse charging of another electronic device (such as a mobile phone), or providing programming / erasing voltages for memory devices, or providing high voltages for the source and gate driving of LCD / OLED screens, etc.).
[0042] like Figure 3 As shown, this application embodiment provides a driving circuit suitable for a reverse charge pump, characterized in that it includes: a first transistor Q0, a second transistor Q1, a third transistor Q2S, a fourth transistor Q3, a fifth transistor Q4, a first capacitor CBST, and a second capacitor CFLY; specifically, the first transistor Q0, the second transistor Q1, the third transistor Q2S, the fourth transistor Q3, and the fifth transistor Q4 are all NMOS transistors, and the first transistor Q0, the second transistor Q1, the third transistor Q2S, the fourth transistor Q3, the fifth transistor Q4, the first capacitor CBST, and the second capacitor CFLY are inherent structures of the charge pump.
[0043] The source of the first transistor Q0 is connected to the load to be charged, the drain of the first transistor Q0 is connected to the drain of the second transistor Q1, the source of the second transistor Q1 is connected to the drain of the third transistor Q2S, the source of the third transistor Q2S is connected to the drain of the fourth transistor Q3, the source of the fourth transistor Q3 is connected to the drain of the fifth transistor Q4, and the source of the fifth transistor Q4 is connected to a zero potential point; specifically, the zero potential point is ground.
[0044] The first common terminal between the source of the second transistor Q1 and the drain of the third transistor Q2S is connected to the lower plate of the first capacitor CBST.
[0045] The second common terminal between the source of the third transistor Q2S and the drain of the fourth transistor Q3 is connected to the input terminal of the internal charge pump.
[0046] The upper plate of the second capacitor CFLY is connected to the lower plate of the first capacitor CBST, and the third common terminal between the source of the fourth transistor Q3 and the drain of the fifth transistor Q4 is connected to the lower plate of the second capacitor CFLY.
[0047] The gate of the first transistor Q0 is connected to the first driving branch, the gate of the second transistor Q1 is connected to the second driving branch, the gate of the third transistor Q2S is connected to the third driving branch, the gate of the fourth transistor Q3 is connected to the fourth driving branch through the first switch S3, and the gate of the fifth transistor Q4 is connected to the fifth driving branch through the second switch S5.
[0048] The internal charge pump outputs a first power supply and a second power supply through a switching circuit. A third switch S1 is provided between the switching circuit and the upper plate of the first capacitor CBST. When the third switch S1 is closed, the first power supply charges the first capacitor CBST. The first power supply is also used to supply power to the second drive branch. The ground terminal of the second drive branch is connected to the source of the second transistor Q1.
[0049] The common terminal between the drain of the first transistor Q0 and the drain of the second transistor Q1 is the fourth common terminal.
[0050] The third driving branch is also connected to the fourth common terminal through the fourth switch S2. When the fourth switch S2 is open, the third driving branch is powered by the second power supply. When the fourth switch S2 is closed, the third driving branch is powered by the power supplied by the fourth common terminal. The ground terminal of the third driving branch is connected to the source of the third transistor Q2S.
[0051] The fourth drive branch is connected to the first common terminal, and the power provided by the first common terminal powers the fourth drive branch. The ground terminal of the fourth drive branch is connected to the source of the fourth transistor Q3.
[0052] The fifth drive branch is connected to the second common terminal, and the power provided by the second common terminal supplies power to the fifth drive branch. The ground terminal of the fifth drive branch is connected to the source of the fifth transistor Q4.
[0053] The gate of the fourth transistor Q3 is also connected to the first current generating circuit through the fifth switch S4; the gate of the fifth transistor Q4 is also connected to the second current generating circuit through the sixth switch S6.
[0054] In a preferred embodiment of this application, the first current generating circuit includes a sixth transistor M4, a first current source, and a first control circuit; the second current generating circuit includes a seventh transistor M4, a second current source, and a second control circuit.
[0055] The gate of the fourth transistor Q3 is also connected to the gate and drain of the sixth transistor M4 through the fifth switch S4. The source of the sixth transistor M4 is connected to the ground terminal. When the first switch S3 is open and the fifth switch S4 is closed, the sixth transistor M4 and the fourth transistor Q3 form a current mirror. The gate and drain of the sixth transistor M4 are connected to the first current source. The first current source is also connected to the first control circuit. The first control circuit controls whether the current flowing out of the first current source flows through the sixth transistor M4.
[0056] The gate of the fifth transistor Q4 is also connected to the gate and drain of the seventh transistor M4 through the sixth switch S6. The source of the seventh transistor M4 is connected to the ground terminal. When the second switch S5 is open and the sixth switch S6 is closed, the seventh transistor M4 and the fifth transistor Q4 form a current mirror. The gate and drain of the seventh transistor M4 are connected to the second current source. The second current source is also connected to the second control circuit. The second control circuit controls whether the current flowing out of the second current source flows through the seventh transistor M4.
[0057] As a preferred embodiment of this application, the switching circuit includes: a seventh switch S7, an eighth switch S8, and a ninth switch S9;
[0058] The output terminal of the internal charge pump is connected to the seventh switch S7. The seventh switch S7 is connected to the eighth switch S8 and the ninth switch S9. When the seventh switch S7 and the eighth switch S8 are closed, the internal charge pump outputs a first power supply. When the seventh switch S7 and the ninth switch S9 are closed, the internal charge pump outputs a second power supply.
[0059] As a preferred embodiment of this application, it also includes an eighth transistor Q2B;
[0060] The gate of the eighth transistor Q2B is connected to the third driving branch, the drain of the eighth transistor Q2B is connected to the first common terminal, the source of the eighth transistor Q2B is connected to the second common terminal, and the aspect ratio of the eighth transistor Q2B is greater than that of the third transistor Q2S.
[0061] Figure 1 This is a schematic diagram of a 2:1 charge pump. When used for forward 2:1 step-down, VIN = 2 * VOUT is required, and the VOUT terminal is generally connected to the battery terminal. Figure 2This is the timing diagram for normal operation in a 2:1 forward configuration. It operates alternately in two stages. In the first stage (ph1), the third transistor Q2 and the fifth transistor Q4 are turned on. At this time, the upper plate BST of the first capacitor CBST is connected to VIN, and the first capacitor CBST is in charge mode. The second capacitor CFLY is connected in parallel with VOUT. In the second stage (ph2), the second transistor Q1 and the fourth transistor Q3 are turned on. At this time, the upper plate BST of the first capacitor CBST is bootstrapped to 2*VIN-VOUT, and the first capacitor CBST is in discharge mode, driving the second transistor Q1 to turn on. Meanwhile, the second capacitor CFLY is connected in series with VOUT.
[0062] If set Figure 1 When the charge pump operates in a reverse 1:2 ratio, initially only VOUT is powered, with the power source being the battery of the electronic device. The VIN terminal is the load to be charged, requiring a proper power-on sequence to allow VIN to slowly power up to approximately 2*VOUT before normal switching can begin. Without a soft-start process, normal switching will begin immediately. Once switching to the second stage (ph2), the second transistor Q1 and the fourth transistor Q3 will connect, generating a large overcharge current that powers the PIMD (PMID typically has a 10uF capacitor). This large current can easily cause thermal damage to the power transistors, even burning them out. To suppress the startup overcharge current, a reasonable drive circuit and timing are needed. Furthermore, a suitable drive circuit is required to ensure successful startup even at low voltage VOUT.
[0063] Figure 3The drive circuit architecture is shown. The first transistor Q0 prevents VOUT from backflowing into VIN. The second transistor Q1, third transistor Q2, fourth transistor Q3, and fifth transistor Q4 are switching power transistors. The second drive branches drv1, drv2, drv3, and drv4 provide drive signals to the second transistor Q1, third transistor Q2, fourth transistor Q3, and fifth transistor Q4, respectively. The second capacitor CFLY is an external flying capacitor connected between the first common terminal CFH and the third common terminal CFL. The first capacitor CBST is an external drive capacitor connected between the upper plate BST of the first capacitor CBST and the first common terminal CFH. The first control circuit drv5 and the second control circuit drv6 control whether the currents I3 and I4 flow through the sixth transistor M3 and the seventh transistor M4, i.e., whether the gates of the sixth transistor M3 and the seventh transistor M4 are driven by current or pulled down to the reference ground. The gate voltage of the first transistor Q0 is modulated by the current acquired by the first drive branch gate_ctrl. The first power supply, boot_clamp, powers the second drive branch drv1. The second power supply, pmid_clamp, powers the third drive branch drv2. The first common terminal, CFH, powers the fourth drive branch drv3, and the second common terminal, VOUT, powers the fifth drive branch drv4. The internal charge pump cp generates a voltage, vcp = 2 * VOUT, which powers the second drive branch drv1 and the third drive branch drv2.
[0064] Specifically, the internal charge pump operates in reverse 1:2 mode. When the external charge pump is set to reverse mode, the first step is to start the internal charge pump CP. The second step is the soft-start stage of the first transistor Q0 and the pre-charge stage of the first capacitor CBST. The third step is the pre-charge stage of the second capacitor CFLY. The fourth step is to perform a soft start using a switching method. The fifth step is the normal operation stage.
[0065] Combination Figure 3 and Figure 4 This allows for a more detailed description of the behavior at each step.
[0066] like Figure 4Before time t0, the chip is in standby mode, VOUT provides system power, the initial capacitance of the second capacitor CFLY and the first capacitor CBST is 0, the first common terminal CFH is connected to the second common terminal VOUT through the diode in the third transistor Q2, and the initial CFH (voltage of the first common terminal) = VOUT (voltage of the second common terminal) - VDIODE (voltage of the parasitic diode of Q2), the fourth common terminal PMID is connected to VOUT through the diodes in the second transistor Q1 and the third transistor Q2, and the initial PMID = VOUT - 2 * VDIODE (voltage of the parasitic diodes of Q1 and Q2); the first common terminal CFL and the upper plate BST of the first capacitor CBST are initially equal to the first common terminal CFH, that is, VOUT - VDIODE (voltage of the parasitic diode of Q2);
[0067] After t0, when the chip is set to reverse working mode, the first step is that the internal charge pump cp starts to work. The output voltage vcp of the internal charge pump cp is later established to 2*vout. The first switch S3 and the second switch S5 are closed, and all other switches are turned off.
[0068] After t1, the second step begins: the soft-start stage of the first transistor Q0 and the pre-charge stage of the first capacitor CBST. In this step, the first transistor Q0 is turned on, and the fourth common terminal PMID pulls up the VIN voltage through the first transistor Q0. The current I_Q0 of the first transistor Q0 is also detected. Once I_Q0 exceeds the preset first threshold Iocp1, the gate of the first transistor Q0 is pulled down. Simultaneously, the pre-charge of the first capacitor CBST begins. The third switch S1, the seventh switch S7, the eighth switch S8, the ninth switch S9, the first switch S3, and the second switch S5 are closed, while the other switches are open. The internal charge pump cp outputs voltage vcp. The first capacitor CBST will be charged until the voltage of the upper plate BST of the first capacitor CBST is fully charged to 2*VOUT. At this time, the voltage of the first capacitor CBST = VOUT + VDIODE (the voltage of the parasitic diode of Q2S). After a period of time, VIN voltage detection and the voltage of the upper plate BST of the first capacitor CBST need to be performed. If PMID-VIN is found to exceed the set threshold, a VIN short circuit will be reported, which means that VIN has not risen to the target value, equivalent to overload. If BST-CFH is found to be lower than the set threshold, a short circuit will be reported across the first capacitor CBST, which means that the pre-charging of the first capacitor CBST has failed. Only when neither VIN short circuit nor short circuit across the first capacitor CBST is reported is the second step considered successful. After that, the first transistor Q0 will enter the linear region and start working, proceeding to the third step.
[0069] After t2, the third step begins: the charging stage of the second capacitor CFLY. In this step, the third transistor Q2S and the eighth transistor Q2B are turned on together, while the second transistor Q1 and the fourth transistor Q3 are turned off. Switches S1, S7, S8, S9, S3, and S6 are closed, and the other switches are open. At this time, the seventh transistor M4 is driven by current I4, providing a bias voltage to the fifth transistor Q4, allowing Q4 to operate in current mirror mode. The third drive branch drv2 is powered by the second power supply pmid_clamp, which is provided by vcp and BST. After a period of time, CFL is pulled low to ground, and CFH is pulled to VOUT. Before t3, the voltage of the second capacitor CFLY is checked. If CFL is found to be lower than the preset value, a short-circuit fault is reported across the second capacitor, indicating a failure of the second capacitor CFLY pre-charging. If this fault is not triggered, the second capacitor CFLY pre-charging is considered successful, and the process can proceed to the next step.
[0070] After t3, the fourth step begins, a soft start is performed using a switching mechanism. In this step, switches S1, S7, S9, S4, and S6 are closed, while all other switches are open, initiating the soft start switching. The two stages alternate. Since the first capacitor CBST and the second capacitor CFLY were already charged before t3, CBST can power the second drive branch drv1, CFH can power the first control circuit drv5, and VCP can power the third drive branch drv2. In the second stage ph1, the second transistor Q1 is turned on, the sixth transistor M3 is driven by I3, and then a bias voltage is provided to the fourth transistor Q3. The fourth transistor Q3 operates in current mirror mode, the third transistor Q2S and the fifth transistor Q4 are turned off, and the fourth transistor Q3 operates in the saturation region. VOUT, in series with the second capacitor CFLY, charges PMID, and the charging current depends on the value of I3. In the first stage ph2, the second transistor Q1 and the fourth transistor Q3 are turned off, the third transistor Q2S is turned on, the eighth transistor Q2B is turned off, the seventh transistor M4 is driven by the current I4, which provides bias to the fifth transistor Q4, allowing the fifth transistor Q4 to operate in current mirror mode. VOUT and the second capacitor CFLY are connected in parallel. VOUT charges the second capacitor CFLY in a current-limited manner. The magnitude of the current depends on the size of I4. After several cycles, VIN and PMID will be charged to 2*vout.
[0071] In this step, it's important to note that since both the fourth transistor Q3 and the fifth transistor Q4 operate as current mirrors, the voltage establishment time for Q3 and Q4 each time they are turned on depends on the establishment time of the operating points of the sixth transistor M3 and the seventh transistor M4, typically requiring 2-3 µs. Therefore, the switching frequency needs to be set to a low frequency, such as less than 100 kHz, to ensure complete establishment and sufficient charging and discharging time when switching between the second stage (ph1) and the first stage (ph2). In the second stage (ph1), the second capacitor CFLY discharges to PMID. To prevent excessive power loss in a single cycle from affecting the power supply to the first control circuit drv5, I3 needs to be set to a reasonable value.
[0072] The specific calculation method can be based on:
[0073] I3 = CFLY * ΔV_CFLY / 0.5 * T, where ΔV_CFLY is the acceptable power drop. For example, for a 3V VOUT, in order to ensure that the first control circuit drv5 can work normally, it is recommended to set ΔV_CFLY = 0.5V so that CFH-CFL has a minimum voltage of 2.5V.
[0074] In the first stage, ph2, it's necessary to limit the current supplied to the second capacitor CFLY. The fifth transistor Q4 operates as a current mirror, and I4 can be set to a value comparable to I3. Since the third transistor Q2S is powered by pmid_clamp, which originates from vcp, and vcp has relatively weak drive capability (~100uA), to ensure Q2S turns on promptly, only Q2S should be turned on while the eighth transistor Q2B remains off. This can be achieved by setting N = (Q2B / Q2S) (the ratio of the two transistor widths, since they are the same length). For example, if the current to Q2S is limited by the fifth transistor Q4 to 1 / 10 of its normal operating current, then N can be around 9. In this case, its power is equivalent to 1 / 10 of its normal operating power, ensuring that the power flowing through Q2S does not exceed the limit.
[0075] To ensure safe startup, before the set time for soft-start in switch mode ends, check if PIMD reaches approximately 2*VOUT to ensure the soft-start is complete. If it doesn't, it's considered overloaded, and the output of the fourth common terminal PMID is not close to the steady-state value, even if it's near 2*VOUT, thus preventing progress to the next step. If it does reach the steady-state value, proceed to the next step. The detection threshold can be reasonably designed based on the actual load capacity.
[0076] After step t4, the fifth step is the normal operation phase. In this step, the third switch S1, the fourth switch S2, the first switch S3, and the second switch S5 are closed, while all other switches are open. BST supplies power to the second drive branch drv1, and PMID supplies power to drv2. The fourth transistor Q3 and the fifth transistor Q4 enter the non-current mirror mode, i.e., the normal switching mode. The third transistor Q2S and the eighth transistor Q2B enter the fully on mode (the fully on mode of transistors is usually called the switching mode or linear region operating state), with the third transistor Q2S and the eighth transistor Q2B simultaneously on and off. In the second phase Ph1, the second transistor Q1 and the fourth transistor Q3 are on, while the third transistor Q2S, the eighth transistor Q2B, and the fifth transistor Q4 are off. In the first phase Ph2, the third transistor Q2S, the eighth transistor Q2B, and the fifth transistor Q4 are on, while the second transistor Q1 and the fourth transistor Q3 are off. The switching states are consistent with the forward 2:1 mode switching states.
[0077] It is worth noting that if the VIN needs to carry a heavy load (e.g., 4A), it should generally be connected after step five. Connecting the heavy load prematurely will trigger the overcurrent protection to start.
[0078] This scheme allows for the reasonable setting of the current limiting threshold for the first transistor Q0 in step two and the detection threshold for the output fourth common terminal PMID in step four, close to the steady-state value, while balancing startup load requirements and chip safety. Simultaneously, the driver circuit design ensures successful reverse startup even with a VOUT as low as 3V.
[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A drive circuit suitable for use in a charge pump of the inverted type, characterized in that, include: First transistor, second transistor, third transistor, fourth transistor, fifth transistor, first capacitor and second capacitor; The source of the first transistor is connected to the load to be charged, the drain of the first transistor is connected to the drain of the second transistor, the source of the second transistor is connected to the drain of the third transistor, the source of the third transistor is connected to the drain of the fourth transistor, the source of the fourth transistor is connected to the drain of the fifth transistor, and the source of the fifth transistor is grounded. The first common terminal between the source of the second transistor and the drain of the third transistor is connected to the lower plate of the first capacitor; The second common terminal between the source of the third transistor and the drain of the fourth transistor is connected to the input terminal of the internal charge pump. The upper plate of the second capacitor is connected to the lower plate of the first capacitor, and the third common terminal between the source of the fourth transistor and the drain of the fifth transistor is connected to the lower plate of the second capacitor. The gate of the first transistor is connected to the first driving branch, the gate of the second transistor is connected to the second driving branch, the gate of the third transistor is connected to the third driving branch, the gate of the fourth transistor is connected to the fourth driving branch through the first switch, and the gate of the fifth transistor is connected to the fifth driving branch through the second switch. The internal charge pump outputs a first power supply and a second power supply through a switching circuit. A third switch is provided between the switching circuit and the upper plate of the first capacitor. When the third switch is closed, the first power supply charges the first capacitor. The first power supply is also used to supply power to the second drive branch. The ground terminal of the second drive branch is connected to the source of the second transistor. The third driving branch is also connected to the fourth common terminal through the fourth switch. When the fourth switch is open, the third driving branch is powered by the second power supply. When the fourth switch is closed, the third driving branch is powered by the fourth common terminal between the drain of the first transistor and the drain of the second transistor. The ground terminal of the third driving branch is connected to the source of the third transistor. The fourth driving branch is connected to the first common terminal, and the first common terminal supplies power to the fourth driving branch. The ground terminal of the fourth driving branch is connected to the source of the fourth transistor. The fifth driving branch is connected to the second common terminal, and the second common terminal supplies power to the fifth driving branch. The ground terminal of the fifth driving branch is connected to the source of the fifth transistor. The gate of the fourth transistor is also connected to the first current generating circuit via a fifth switch; the gate of the fifth transistor is also connected to the second current generating circuit via a sixth switch.
2. A drive circuit for a charge pump of the type defined in claim 1, characterized in that The first current generating circuit includes a sixth transistor, a first current source, and a first control circuit; the second current generating circuit includes a seventh transistor, a second current source, and a second control circuit. The gate of the fourth transistor is also connected to the gate drain of the sixth transistor through the fifth switch. The source of the sixth transistor is connected to the third common terminal. When the first switch is open and the fifth switch is closed, the sixth transistor and the fourth transistor form a current mirror. The gate drain of the sixth transistor is connected to the first current source. The first current source is also connected to the first control circuit. The first control circuit controls whether the current flowing out of the first current source flows through the sixth transistor. The gate of the fifth transistor is also connected to the gate drain of the seventh transistor through the sixth switch. The source of the seventh transistor is grounded. When the second switch is open and the sixth switch is closed, the seventh transistor and the fifth transistor form a current mirror. The gate drain of the seventh transistor is connected to the second current source. The second current source is also connected to the second control circuit. The second control circuit controls whether the current flowing out of the second current source flows through the seventh transistor.
3. A drive circuit for a charge pump of the type defined in claim 1, characterized in that The switching circuit includes: a seventh switch, an eighth switch, and a ninth switch; The output terminal of the internal charge pump is connected to the seventh switch, and the seventh switch is connected to the eighth and ninth switches. When the seventh and eighth switches are closed, the internal charge pump outputs a first power supply; when the seventh and ninth switches are closed, the internal charge pump outputs a second power supply.
4. A drive circuit suitable for a reverse charge pump as described in claim 1, characterized in that, It also includes the eighth transistor; The gate of the eighth transistor is connected to the third driving branch, the drain of the eighth transistor is connected to the first common terminal, and the source of the eighth transistor is connected to the second common terminal. The aspect ratio of the eighth transistor is greater than that of the third transistor.
5. A method for driving a reverse charge pump, characterized in that, The method is applied to the circuit as described in any one of claims 1 to 4, and the method includes: When the external charge pump is in reverse working mode, the internal charge pump starts to work until the voltage at the output terminal of the internal charge pump is greater than the voltage at the input terminal of the internal charge pump. Then, the first and second switches are closed, and the third, fourth, fifth, sixth, seventh, eighth and ninth switches are turned off. The first transistor is turned on by the first drive branch, and the first, second, third, seventh, eighth and ninth switches are closed; the fourth, fifth and sixth switches are turned off, and the first capacitor is charged by the internal charge pump. The third and eighth transistors are controlled to turn on, the second and fourth transistors are controlled to turn off, the third, seventh, eighth, ninth, first, and sixth switches are controlled to close, and the second, fourth, and fifth switches are controlled to turn off. The second control circuit controls the current flowing out of the second current source to drive the seventh transistor to turn on and provide a bias voltage for the fifth transistor. The fifth transistor is in current mirror working mode. The third drive branch is powered by the second power supply. The voltage of the second capacitor is detected. If the voltage of the second capacitor is greater than the third preset threshold, the second capacitor is successfully charged. The third, seventh, ninth, fifth, and sixth switches are controlled to close, while the first, second, fourth, and eighth switches are turned off. The fourth common terminal is charged by controlling the three transistors, the fifth transistor, the second transistor, and the fourth transistor to alternately turn on and off. The system controls the first, second, third, and fourth switches to close, and controls the fifth, sixth, seventh, eighth, and ninth switches to close. Power is supplied to the second drive branch through the first capacitor, and power is supplied to the third drive branch through the fourth common terminal. The fourth and fifth transistors are in non-current mirror operating mode. The third and eighth transistors enter fully open mode. By controlling the third, fifth, second, and fourth transistors to alternately open and close, the system charges the load to be charged.
6. A method for driving a reverse charge pump as described in claim 5, characterized in that, After charging the first capacitor, the following steps are included: Voltage detection is performed on the source of the first transistor and the upper plate of the first capacitor; if the difference between the fourth common terminal and the source of the first transistor is greater than a first set threshold, the load to be charged can be overloaded; if the difference between the upper plate and the lower plate of the first capacitor is less than a second set threshold, the first capacitor is successfully charged.