A resistance measuring structure, a resistance measuring method, and an integrated circuit
By setting rectifier junctions with opposite conduction directions and test lead resistors of different lengths in the resistance measurement structure, the error problem when using two test pads to measure the resistance of the chip is solved, achieving accurate resistance measurement and results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-03-24
- Publication Date
- 2026-06-16
Smart Images
Figure CN121899493B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a resistance measurement structure, measurement method, and integrated circuit. Background Technology
[0002] Wafer Acceptance Test (WAT), a critical step before chip packaging and testing, plays an indispensable role in evaluating the stability of wafer manufacturing processes and ensuring product quality. WAT involves accurately measuring the resistance values of line resistance and chip resistance to determine whether these values meet the required standards.
[0003] When using the Kelvin method to measure on-resistance, the influence of extraneous factors such as the resistance of connecting wires can be effectively eliminated, resulting in more accurate test results. However, at least four test pads are required for on-resistance measurement. Using two test pads to measure chip resistance can save on the number of test pads needed for other test structures and reduce the number of probe movements. However, when using two test pads to measure chip resistance, the external resistance of the probes and external instruments, as well as the internal resistance of vias and metal layers, introduce errors into the measured chip resistance, affecting the test results. Summary of the Invention
[0004] The purpose of this invention is to provide a resistance measurement structure, measurement method, and integrated circuit, which can solve the problem that the measured chip resistance has errors when using two test pads to measure chip resistance, thus affecting the test results.
[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:
[0006] This invention provides a resistance measurement structure, comprising:
[0007] First test pad, second test pad, first connecting structure, and second connecting structure;
[0008] A first test circuit includes a first test lead resistor and a first rectifier junction. The two ends of the first test lead resistor are connected to the first test pad and the second test pad via a first connection structure and a second connection structure. The first rectifier junction is connected in series with the first test lead resistor.
[0009] The second test circuit includes a second test line resistor and a second rectifier junction. The two ends of the second test line resistor are connected to the first test pad and the second test pad through the first connection structure and the second connection structure. The second rectifier junction is connected in series in the second test line resistor.
[0010] The length of the second test line resistor is greater than the length of the first test line resistor, and the conduction directions of the first rectifier junction and the second rectifier junction are opposite.
[0011] In one embodiment of the present invention, the first rectifier junction includes a P-type doped region and an N-type doped region. The P-type doped region of the first rectifier junction is connected to the first test pad through the first test line resistor, and the N-type doped region of the first rectifier junction is connected to the second test pad through the first test line resistor.
[0012] The second rectifier junction includes a P-type doped region and an N-type doped region. The P-type doped region of the second rectifier junction is electrically connected to the second test pad through the second test line resistor, and the N-type doped region of the second rectifier junction is connected to the first test pad through the second test line resistor.
[0013] In one embodiment of the present invention, the first test line resistor and the second test line resistor are disposed within the metal interconnect structure.
[0014] In one embodiment of the present invention, both the first connection structure and the second connection structure include a metal layer and a through hole.
[0015] The present invention also provides a method for measuring resistance, characterized in that it uses the resistance measuring structure described in any one of the preceding claims, and the method for measuring resistance includes:
[0016] A test current is input between the first test pad and the second test pad to turn on the first test circuit. The first voltage across the first test circuit is measured to obtain the first equivalent resistance of the first test circuit.
[0017] A test current is input between the second test pad and the first test pad to turn on the second test circuit. The second voltage across the second test circuit is measured to obtain the second equivalent resistance of the second test circuit.
[0018] The resistance value of the sheet resistor is obtained based on the difference between the second equivalent resistance and the first equivalent resistance and the difference between the lengths of the second test line resistance and the first test line resistance.
[0019] In one embodiment of the present invention, the first equivalent resistance is obtained by the following formula:
[0020] R1=(U1-U PN1 ) / I1;
[0021] Where R1 is the first equivalent resistance, U1 is the first voltage, and U PN1 I0 is the voltage across the first rectifier junction; I1 is the test current.
[0022] In one embodiment of the present invention, the second equivalent resistance is obtained by the following formula:
[0023] R2=(U2-U PN2 ) / I1;
[0024] Wherein, R2 is the second equivalent resistance, U2 is the second voltage, and U PN2 I0 is the voltage across the second rectifier junction; I1 is the test current.
[0025] In one embodiment of the present invention, the resistance value of the chip resistor is obtained by the following formula:
[0026] R P =(R2-R1) / (L2-L1);
[0027] Among them, R P R1 is the resistance value of the sheet resistor, R2 is the first equivalent resistance, R2 is the second equivalent resistance, L1 is the length of the first test lead resistor, and L2 is the length of the second test lead resistor.
[0028] In one embodiment of the present invention, the method for measuring resistance further includes obtaining the resistance value of the line resistance, wherein the resistance value of the line resistance is equal to the length of the line resistance multiplied by the resistance value of the sheet resistance.
[0029] The present invention also provides an integrated circuit including a resistance measurement structure as described in any of the above claims.
[0030] In summary, the method for fabricating a resistance measurement structure provided by this invention has the following unexpected effect: When measuring sheet resistance and line resistance, a first test line resistor and a second test line resistor are respectively set in the first test circuit and the second test circuit, and rectifier junctions with opposite conduction directions are set in the two test line resistors, so that when the first test circuit and the second test circuit have different current directions, only one test circuit is conducting. Simultaneously, both ends of the first test line resistor and both ends of the second test line resistor are connected to the first test pad and the second test pad, ensuring that when measuring the first equivalent resistance of the first test circuit and the second equivalent resistance of the second test circuit, under the same input current, the external resistance from the pins and external instruments, and the internal resistance from the through holes and metal layers in the first and second equivalent resistances are the same. Furthermore, by setting the lengths of the first test line resistor and the second test line resistor to be different, the voltage across the line resistor in the first equivalent resistance of the first test circuit and the second equivalent resistance of the second test circuit are different. Finally, by dividing the difference between the second equivalent resistance and the first equivalent resistance by the difference in length between the second test line resistor and the first test line resistor, the resistance value of the sheet resistance can be accurately obtained. This application can accurately obtain the resistance value using only two test pads and two test lead resistors, thus reducing the number of test pads while accurately obtaining the resistance value.
[0031] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description
[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a schematic diagram of a resistance measurement structure with only one test lead resistor.
[0034] Figure 2 For measurement Figure 1 The equivalent circuit diagram when the resistance of the test line is measured.
[0035] Figure 3 This is a schematic diagram of the resistance measurement structure in one embodiment of this application.
[0036] Figure 4 For this application Figure 3 Cross-sectional view at point A-A'.
[0037] Figure 5 Measurement in one embodiment of this application Figure 4 and Figure 5 The equivalent circuit diagram when the resistance of the test line is measured.
[0038] Figure 6 This is a flowchart of a resistance measurement method in one embodiment of this application.
[0039] Label Explanation:
[0040] 101. Test line resistance; 1011. First test line resistance; 1012. Second test line resistance; 10121. First segment; 10122. Second segment; 10123. Third segment; 102. Metal layer; 103. Through-hole; 104. Test pad; 1041. First test pad; 1042. Second test pad; 105. Probe card; 1061. First rectifier junction; 1062. Second rectifier junction; 1063. First doped region; 1064. Second doped region; 107. Conductive plug. Detailed Implementation
[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0043] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.
[0044] Please combine Figure 1As shown, in semiconductor integrated circuits, multiple semiconductor devices are integrated onto a single silicon wafer. After forming multiple semiconductor devices on the silicon wafer, a metal interconnect layer needs to be formed on the semiconductor devices. This metal interconnect layer includes multiple metal layers 102, multiple vias 103, and a dielectric layer. The metal layers 102 and vias 103 can be formed using a damascus structure. Dielectric layers are disposed between adjacent metal layers 102, between metal layers within the same layer 102, and between adjacent vias 103 to prevent signal crosstalk between adjacent metal layers 102. The metal layers 102 and vias 103 work together to electrically connect each semiconductor device according to the designed circuit.
[0045] Please see Figure 1 As shown, a resistance sensing structure, such as test line resistor 101, is provided in the metal interconnect layer. Test line resistor 101 is disposed in the metal interconnect layer, and its linewidth and depth are identical to those of the structure under test (DUT) in the integrated circuit. During wafer acceptability testing, the resistance of test line resistor 101 can be measured to determine whether the electrical requirements of the DUT in the integrated circuit meet the design conditions.
[0046] Please see Figure 1 As shown, when using probe card 105 to measure the resistance of test line 101 from two test pads 104, a test current is passed from the two test pads 104 to the test line resistance 101, and the voltage between the two test pads 104 is measured. The equivalent resistance of test line 101 is obtained by combining the value of the passed test current and the measured voltage. Please refer to... Figure 2 As shown, the equivalent resistance of the test line resistor 101 obtained at this time includes the line resistance R of the test line resistor 101. L The external resistance R of needle insertion and external instruments W and the internal resistance R of the via 103 and the metal layer 102. N Therefore, if the equivalent resistance of the test line resistor 101 measured at this time is taken as the resistance value of the test line resistor 101, it will result in an excessive deviation between the measured resistance value of the test line resistor 101 and the actual resistance value.
[0047] Please see Figure 3 and Figure 4 As shown, this application provides a resistance measurement structure, measurement method, and integrated circuit, which can accurately measure the resistance value using two test pads, saving the number of test pads while accurately measuring the resistance.
[0048] Please see Figure 3 and Figure 4As shown, in one embodiment of the present invention, the measurement structure includes a first test pad 1041, a second test pad 1042, a first connection structure, a second connection structure, a first test circuit, and a second test circuit. The first test circuit includes a first test line resistor 1011 and a first rectifier junction 1061. The two ends of the first test line resistor 1011 are connected to the first test pad 1041 and the second test pad 1042 through the first and second connection structures. The first rectifier junction 1061 is connected in series with the first test line resistor 1011. The second test circuit includes a second test line resistor 1012 and a second rectifier junction 1062. The two ends of the second test line resistor 1012 are connected to the first test pad 1041 and the second test pad 1042 through the first and second connection structures. The second rectifier junction 1062 is connected in series with the second test line resistor 1012. Furthermore, the length of the second test line resistor 1012 is greater than the length of the first test line resistor 1011, and the conduction directions of the first rectifier junction 1061 and the second rectifier junction 1062 are opposite.
[0049] Please see Figure 1 , Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the first test pad 1041 and the second test pad 1042 are disposed on the surface of the integrated circuit. In some embodiments, the first test pad 1041 and the second test pad 1042 may be disposed in a dicing channel. When measuring the resistance 101 of the test line, a test current can be input between the first test pad 1041 and the second test pad 1042, and the voltage between the first test pad 1041 and the second test pad 1042 can be tested using a probe card 105.
[0050] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the first connection structure and the second connection structure are configured with a metal layer 102 and a via 103 disposed in a metal interconnect layer, and include a damascus structure formed by the metal layer 102 and the via 103. This application does not limit the number of metal layers 102 and vias 103 in the first and second connection structures, and can set them according to the integrated circuit formed and the position of the test line resistor 101. When the test line resistor 101 is disposed on the same layer as the bottommost metal layer 102, the first connection structure and the second connection structure include the via 103 and the metal layer 102, excluding the bottommost metal layer 102. When the test line resistor 101 is disposed on the same layer as the topmost metal layer 102, the first and second connection structures can be omitted, and the first test line resistor 1011 and the second test line resistor 1012 can be directly connected to the first test pad 1041 and the second test pad 1042.
[0051] Please see Figure 3 and Figure 4As shown, in one embodiment of the present invention, the first test circuit includes a first test line resistor 1011 and a first rectifier junction 1061. One end of the first test line resistor 1011 is connected to a first test pad 1041 through a first connection structure, and the other end is connected to a second test pad 1042 through a second connection structure.
[0052] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the first test line resistor 1011 is disposed within the metal interconnect structure, and the first test line resistor 1011 can be disposed in any metal layer 102. In other embodiments, the first test line resistor 1011 can also be disposed at any position in the dielectric layer within the metal interconnect layer, as long as the first test line resistor 1011 has a preset distance from the metal layer 102 and the via 103 required by the semiconductor device. Figure 4 In the illustrated embodiment, four metal layers 102 and three vias 103 are provided, and the first test line resistor 1011 is located in the first metal layer. In this application, the linewidth of the first test line resistor 1011 is the same as the linewidth of the structure under test. Furthermore, this application does not limit the shape and length of the first test line resistor 1011. The first test line resistor 1011 can be arranged in a straight line, a broken line, or a curve. The first test line resistor 1011 has a first length, and the specific range of the first length is not limited.
[0053] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the first rectifier junction 1061 is connected in series with the first test line resistor 1011. That is, the first test line resistor 1011 is divided into two segments by the first rectifier junction 1061, and the two ends of the first rectifier junction 1061 connect the two segments of the first test line resistor 1011.
[0054] Please see Figure 3 and Figure 4 As shown, it should be noted that this application does not limit the type of the first rectifier junction 1061, as long as the first rectifier junction 1061 performs unidirectional conduction. In some embodiments, the first rectifier junction 1061 is a PN junction. In other embodiments, the first rectifier junction 1061 can also be a potential barrier formed by the contact between a metal and a semiconductor.
[0055] Please see Figure 3 and Figure 4As shown, in one embodiment of the present invention, the first rectifier junction 1061 is a PN junction, and the first rectifier junction 1061 includes a first doped region 1063 and a second doped region 1064. The first doped region 1063 and the second doped region 1064 are disposed in a silicon substrate, and the first doped region 1063 and the second doped region 1064 are connected to the two ends of the first test line resistor 1011 through conductive plugs 107. The first doped region 1063 is, for example, a P-type doped region, and the second doped region 1064 is, for example, an N-type doped region. Figure 5 As shown, the first rectifier junction 1061 is equivalent to the first diode D1. The first doped region 1063 is connected to the first test pad 1041 through the first test line resistor 1011, and the second doped region 1064 is connected to the second test pad 1042 through the first test line resistor 1011. When current is applied between the first test pad 1041 and the second test pad 1042, i.e., when the direction of the input current is from the first test pad 1041 to the second test pad 1042, the first rectifier junction 1061 is forward biased, and the first test circuit is turned on. If the direction of the input current is opposite, the first rectifier junction 1061 is reverse biased, and the first test circuit is turned off.
[0056] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the second test circuit includes a second test line resistor 1012 and a second rectifier junction 1062. One end of the second test line resistor 1012 is connected to the first test pad 1041 via a first connection structure, and the other end is connected to the second test pad 1042 via a second connection structure.
[0057] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the second test line resistor 1012 is disposed within the metal interconnect structure, and the second test line resistor 1012 can be disposed in any metal layer 102. In other embodiments, the second test line resistor 1012 can also be disposed at any position in the dielectric layer within the metal interconnect layer, as long as the second test line resistor 1012 has a preset distance from the metal layer 102 and the via 103 required by the semiconductor device. Figure 4 In the illustrated embodiment, four metal layers 102 and three vias 103 are provided, and the second test line resistor 1012 is located in the first metal layer. In this application, the linewidth of the second test line resistor 1012 is the same as the linewidth of the structure under test. This application does not limit the shape and length of the second test line resistor 1012. The second test line resistor 1012 can be arranged in a straight line, a broken line, or a curve. The second test line resistor 1012 has a second length, and the second length is greater than the first length, but the specific range of the second length is not limited.
[0058] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the first test line resistor 1011 is configured as a straight line, and its two ends are connected to the first test pad 1041 and the second test pad 1042 respectively through a first connection structure and a second connection structure. At this time, the orthographic projections of the first test pad 1041 and the second test pad 1042 onto the plane containing the first test line resistor 1011 overlap with the two ends of the first test line resistor 1011. The second test line resistor 1012 includes a first segment 10121, a second segment 10122, and a third segment 10123. Specifically, the second segment 10122 is the middle segment of the second test line resistor 1012, parallel to the first test line resistor 1011, and its length is equal to the length of the first test line resistor 1011. One end of the first segment 10121 is connected to one end of the second segment 10122, and the other end is connected to the first test pad 1041 through the first connection structure. One end of the third segment 10123 is connected to the other end of the second segment 10122, and the other end is connected to the second test pad 1042 through the second connection structure.
[0059] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the second rectifier junction 1062 is connected in series in the second segment 10122 of the second test line resistor 1012, and the conduction direction of the second rectifier junction 1062 is opposite to the conduction direction of the first rectifier junction 1061. That is, the second segment 10122 of the second test line resistor 1012 is divided into two segments by the second rectifier junction 1062, and the two ends of the second rectifier junction 1062 connect the two segments of the second segment 10122. In other embodiments, the second rectifier junction 1062 may also be connected in series in the first segment 10121 or the third segment 10123.
[0060] Please see Figure 3 and Figure 4 As shown, it should be noted that this application does not limit the type of the second rectifier junction 1062, as long as the second rectifier junction 1062 performs unidirectional conduction. In some embodiments, the second rectifier junction 1062 is a PN junction. In other embodiments, the second rectifier junction 1062 can also be a potential barrier formed by the contact between a metal and a semiconductor.
[0061] Please see Figure 3 and Figure 4As shown, in one embodiment of the present invention, the second rectifier junction 1062 is a PN junction, and the second rectifier junction 1062 includes a first doped region 1063 and a second doped region 1064. The first doped region 1063 and the second doped region 1064 are disposed in a silicon substrate, and the first doped region 1063 and the second doped region 1064 are connected to the two ends of the second test line resistor 1012 through conductive plugs 107. The first doped region 1063 is, for example, a P-type doped region, and the second doped region 1064 is, for example, an N-type doped region. Figure 5 As shown, the first rectifier junction 1061 is equivalent to the second diode D2. Since the conduction direction of the second rectifier junction 1062 is opposite to that of the first rectifier junction 1061, the first doped region 1063 is connected to the second test pad 1042 through the second test line resistor 1012, and the second doped region 1064 is connected to the first test pad 1041 through the second test line resistor 1012. When current is applied between the second test pad 1042 and the first test pad 1041, i.e., when the direction of the input current is from the second test pad 1042 to the first test pad 1041, the second rectifier junction 1062 is forward biased, and the second test circuit is turned on. If the direction of the input current is opposite, the second rectifier junction 1062 is reverse biased, and the second test circuit is turned off.
[0062] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the first doped region 1063 in the second test circuit and the first doped region 1063 in the first test circuit have the same depth and the same ion doping concentration. The second doped region 1064 in the second test circuit and the second doped region 1064 in the first test circuit have the same depth and the same ion doping concentration. This results in the same voltage across the first rectifier junction 1061 and the second rectifier junction 1062.
[0063] Please see Figure 6 As shown, the present invention also provides a method for measuring resistance, using the resistance measuring structure provided in the above embodiment. Furthermore, the resistance measuring method provided in this application includes steps S101 to S103.
[0064] Step S101: Input a test current between the first test pad and the second test pad to turn on the first test circuit, measure the first voltage across the first test circuit, and obtain the first equivalent resistance of the first test circuit.
[0065] Step S102: Input a test current between the second test pad and the first test pad to turn on the second test circuit, measure the second voltage across the second test circuit, and obtain the second equivalent resistance of the second test circuit.
[0066] Step S103: Obtain the resistance value of the sheet resistor based on the difference between the second equivalent resistance and the first equivalent resistance and the difference between the lengths of the second test line resistance and the first test line resistance.
[0067] Please see Figures 3 to 6 As shown, in one embodiment of the present invention, when obtaining the first equivalent resistance of the first test circuit and inputting a test current between the first test pad 1041 and the second test pad 1042, the current can be input from the first test pad 1041 and output from the second test pad 1042 through the probe card 105. At this time, the current flows from the first test pad 1041 to the second test pad 1042, the first rectifier junction 1061 is turned on, and the voltage across the first test circuit is the first voltage. The first equivalent resistance is then obtained using the following formula:
[0068] R1=(U1-U PN1 ) / I1;
[0069] Where R1 is the first equivalent resistance, U1 is the first voltage, and U PN1 I1 is the voltage across the first rectifier junction 1061; I2 is the test current.
[0070] Please combine Figure 5 As shown, it should be noted that the first equivalent resistance obtained at this time includes the line resistance R of the first test circuit. L1 External resistance R W Internal resistance R N The equivalent resistance R of the first rectifier junction 1061 D1 Furthermore, when the first test circuit is turned on, the second test circuit is cut off because the second rectifier junction 1062 is in the off state, and no current flows through it. At this time, the second test circuit is an open circuit.
[0071] Please see Figures 3 to 6 As shown, in one embodiment of the present invention, when obtaining the second equivalent resistance of the second test circuit, and inputting a test current between the second test pad 1042 and the first test pad 1041, the current can be input from the second test pad 1042 and output from the first test pad 1041 through the probe card 105. At this time, the current flows from the second test pad 1042 to the first test pad 1041, the second rectifier junction 1062 is turned on, and the measured voltage across the second test circuit is the second voltage. The second equivalent resistance is then obtained using the following formula:
[0072] R2=(U2-U PN2 ) / I1;
[0073] Where R2 is the second equivalent resistance, U2 is the second voltage, and U PN2 I0 is the voltage across the second rectifier junction; I1 is the test current.
[0074] Please combine Figure 5 As shown, it should be noted that the second equivalent resistance obtained at this time includes the line resistance R of the second test circuit. L2 External resistance R W Internal resistance R N The equivalent resistance R of the second rectifier junction 1062 D2 Furthermore, when the second test circuit is turned on, the first test circuit is cut off because the first rectifier junction 1061 is in the off state, and no current flows through it. At this time, the first test circuit is an open circuit.
[0075] Please see Figures 3 to 6 As shown, in one embodiment of the present invention, after obtaining the first equivalent resistance and the second equivalent resistance, the resistance value of the chip resistor is obtained based on the difference between the second equivalent resistance and the first equivalent resistance and the difference between the lengths of the second test line resistance 1012 and the first test line resistance 1011. Specifically, the resistance value of the chip resistor is obtained using the following formula:
[0076] R P =(R2-R1) / (L2-L1);
[0077] Among them, R P R1 is the resistance value of the sheet resistor, R2 is the first equivalent resistance, R2 is the second equivalent resistance, L1 is the length of the first test line resistor 1011, and L2 is the length of the second test line resistor 1012.
[0078] That is, R P =(U2-U PN2 ) / I1-(U1-U PN1 ) / I1) / (L2-L1);
[0079] Among them, U PN2 U is the voltage across the second rectifier junction 1062. PN1 The voltage across the first rectifier junction 1061 is U. During the fabrication process, since the doped ions and doping concentrations of the first doped region 1063 and the second doped region 1064 in the first and second test circuits are the same, U... PN1 =U PN2 .but:
[0080] R P =((U2-U1) / I1) / (L2-L1);
[0081] The lengths of the first test line resistor 1011 and the second test line resistor 1012 are predetermined during manufacturing; therefore, the lengths L1 and L2 of the first and second test line resistors 1011 and 1012 are known quantities. The test current I1 is a known input test current, and the second voltage U2 and the first voltage U1 are measured voltages. The unknown external resistance R... W Internal resistance R N The equivalent resistance R of the first rectifier junction 1061 D1 The equivalent resistance R of the second rectifier junction 1062 D2 All of these values are removed from the difference between the second equivalent resistance and the first equivalent resistance. Therefore, the resistance value of the chip resistor obtained in this application is not affected by the external circuit resistance, the internal circuit resistance, or the equivalent resistance R of the first rectifier junction 1061. D1 The equivalent resistance R of the second rectifier junction 1062 D2 This reduces the measurement error of the chip resistor. Specifically, since the doped ions and doping concentrations of the first doped region 1063 and the second doped region 1064 in the first and second test circuits are the same, the equivalent resistance R of the first rectifier junction 1061 is... D1 Equal to the equivalent resistance R of the second rectifier junction 1062 D2 .
[0082] It is important to note that a chip resistor is a resistor per unit length, and its resistance value is the same as the resistance per unit length. The unit length can be determined by a specific evaluation system, for example, it could be 1 nm or 1 mm.
[0083] Please see Figures 3 to 6 As shown, in one embodiment of the present invention, the resistance measurement method further includes obtaining the resistance value of the line resistance. In this application, the resistance value of the line resistance is equal to the sheet resistance multiplied by the length of the line resistance. Specifically, the first test line resistance 1011 and the second test line resistance 1012 are obtained by the following formula:
[0084] R L1 =R P ×L1;
[0085] R L2 =R P ×L2;
[0086] Among them, R P L1 is the resistance value of the sheet resistor, L2 is the length of the first test lead resistor 1011, and L2 is the length of the second test lead resistor 1012.
[0087] In summary, this invention provides a resistance measurement structure, measurement method, and integrated circuit. The resistance measurement structure includes: a first test circuit, comprising a first test line resistor and a first rectifier junction, wherein the two ends of the first test line resistor are connected to a first test pad and a second test pad via a first connection structure and a second connection structure, and the first rectifier junction is connected in series in the first test line resistor; and a second test circuit, comprising a second test line resistor and a second rectifier junction, wherein the two ends of the second test line resistor are connected to the first test pad and the second test pad via the first connection structure and the second connection structure, and the second rectifier junction is connected in series in the second test line resistor; wherein the length of the second test line resistor is greater than the length of the first test line resistor, and the conduction directions of the first rectifier junction and the second rectifier junction are opposite. An unexpected effect is that when measuring sheet resistance and line resistance, by setting the first test line resistor and the second test line resistor respectively in the first test circuit and the second test circuit, and setting rectifier junctions with opposite conduction directions in the two test line resistors, it is ensured that when the directions of the current flowing into the first test circuit and the second test circuit are different, only one test circuit is conducting. Simultaneously, both ends of the first test lead resistor and both ends of the second test lead resistor are connected to the first test pad and the second test pad, ensuring that when measuring the first equivalent resistance of the first test circuit and the second equivalent resistance of the second test circuit, under the same input current, the external resistance from the pins and external instruments, and the internal resistance from the through holes and metal layers in the first and second equivalent resistances are the same. By setting different lengths for the first and second test lead resistors, the voltage across the line resistors in the first and second equivalent resistances of the first and second test circuits is different. Then, by dividing the difference between the second and first equivalent resistances by the difference in length between the second and first test lead resistors, the resistance value of the chip resistor can be accurately obtained. This application can accurately obtain the resistance value using only two test pads and two test lead resistors, reducing the number of test pads while accurately obtaining the resistance value.
[0088] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A resistance measuring structure, characterized in that, include: First test pad, second test pad, first connecting structure, and second connecting structure; The first test circuit includes a first test line resistor and a first rectifier junction. The two ends of the first test line resistor are connected to the first test pad and the second test pad through the first connection structure and the second connection structure. The first rectifier junction is connected in series in the first test line resistor. as well as The second test circuit includes a second test line resistor and a second rectifier junction. The two ends of the second test line resistor are connected to the first test pad and the second test pad through the first connection structure and the second connection structure. The second rectifier junction is connected in series in the second test line resistor. The length of the second test line resistor is greater than the length of the first test line resistor, and the conduction directions of the first rectifier junction and the second rectifier junction are opposite.
2. The resistance measuring structure according to claim 1, characterized in that, The first rectifier junction includes a P-type doped region and an N-type doped region. The P-type doped region of the first rectifier junction is connected to the first test pad through the first test line resistor, and the N-type doped region of the first rectifier junction is connected to the second test pad through the first test line resistor. The second rectifier junction includes a P-type doped region and an N-type doped region. The P-type doped region of the second rectifier junction is electrically connected to the second test pad through the second test line resistor, and the N-type doped region of the second rectifier junction is connected to the first test pad through the second test line resistor.
3. The resistance measuring structure according to claim 1, characterized in that, The first test line resistor and the second test line resistor are disposed within the metal interconnect structure.
4. The resistance measuring structure according to claim 1, characterized in that, Both the first connection structure and the second connection structure include a metal layer and a through hole.
5. A method for measuring resistance, characterized in that, The method of measuring resistance using the resistance measurement structure as described in any one of claims 1 to 4, and the resistance measurement method comprising: A test current is input between the first test pad and the second test pad to turn on the first test circuit. The first voltage across the first test circuit is measured to obtain the first equivalent resistance of the first test circuit. A test current is input between the second test pad and the first test pad to turn on the second test circuit. The second voltage across the second test circuit is measured to obtain the second equivalent resistance of the second test circuit. The resistance value of the sheet resistor is obtained based on the difference between the second equivalent resistance and the first equivalent resistance and the difference between the lengths of the second test line resistance and the first test line resistance.
6. The resistance measurement method according to claim 5, characterized in that, The first equivalent resistance is obtained by the following formula: R1=(U1-U PN1 ) / I1; Where R1 is the first equivalent resistance, U1 is the first voltage, and U PN1 I0 is the voltage across the first rectifier junction; I1 is the test current.
7. The resistance measurement method according to claim 5, characterized in that, The second equivalent resistance is obtained by the following formula: R2=(U2-U PN2 ) / I1; Wherein, R2 is the second equivalent resistance, U2 is the second voltage, and U PN2 I0 is the voltage across the second rectifier junction; I1 is the test current.
8. The resistance measurement method according to claim 5, characterized in that, The resistance value of the sheet resistor is obtained by the following formula: R P =(R2-R1) / (L2-L1); Among them, R P R1 is the resistance value of the sheet resistor, R2 is the first equivalent resistance, R2 is the second equivalent resistance, L1 is the length of the first test lead resistor, and L2 is the length of the second test lead resistor.
9. The resistance measurement method according to claim 5, characterized in that, The method for measuring resistance further includes obtaining the resistance value of the line resistance, wherein the resistance value of the line resistance is equal to the length of the line resistance multiplied by the resistance value of the sheet resistance.
10. An integrated circuit, characterized in that, The measuring structure includes the resistance as described in any one of claims 1 to 4.