Test system and method for realizing analog excitation and digital communication multiplexing based on VI source channel

Abstract

The application discloses a kind of test system and method based on VI source channel implementation analog excitation and digital communication multiplexing, belong to semiconductor automatic test equipment technical field.The existing test system interface resource is intended to solve the problem of shortage, high cost, insufficient flexibility.Testing machine and the device board to be measured are connected by VI source channel, and the digital communication signal is modulated and superimposed to VI source analog excitation channel on testing machine side, and the digital signal is separated and parsed on the device board to be measured side;Local sampling circuit and relay control circuit are provided on the device board to be measured side, and sampling data and receiving control instruction are returned through multiplexing channel.The application realizes analog and digital signal multiplexing transmission, reduces pogopin occupation, reduces testing machine cost and volume, improves measurement accuracy and system flexibility, and is suitable for automatic test of high pin count semiconductor device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor automatic test equipment technology, specifically relating to a test system and method based on VI source channel to realize analog excitation and digital communication multiplexing, which is applicable to automatic test scenarios for power supply, excitation, measurement and control signal transmission of semiconductor devices. Background Technology

[0002] With the continuous increase in the integration and functional complexity of semiconductor devices, automated test equipment needs to simultaneously provide various test resources such as power supply excitation, voltage and current measurement, functional control, and status acquisition when performing electrical performance tests on devices under test (DUTs). Among these, the VI source, as a core unit, undertakes the key functions of providing voltage / current excitation to the DUT and measuring electrical parameters, and is widely used in various chip testing scenarios.

[0003] In existing technologies, VI sources are typically connected to the device under test (DUT) via a separate test channel, used only for the transmission and measurement of DC or low-frequency analog signals. To ensure test accuracy, an additional independent Sense circuit is required to compensate for errors caused by the connection lines and contact resistance. However, with the increasing number of pins on the DUT and the expansion of test items, pogo pin resources in the test interface are becoming increasingly scarce. Competition for limited physical connection resources by power, force, sense, and control signals leads to complex test interface structures, increased costs, and decreased reliability.

[0004] On the other hand, existing automated test equipment typically features high-precision, high-bandwidth analog measurement circuits and analog-to-digital conversion resources centrally configured on the test bench side to adapt to the testing needs of different types of devices under test. However, different devices under test vary significantly in terms of testing accuracy, frequency, and functional complexity. The uniformly configured high-performance analog resources are difficult to fully utilize in most application scenarios, resulting in increased test bench size, power consumption, and manufacturing costs, which is not conducive to the flexible expansion and on-demand configuration of the system.

[0005] Furthermore, in existing test systems, functions such as relay control and power channel switching rely on independent control boards and control signal channels. These control signals also consume physical connection resources, and their generic design makes it difficult to flexibly tailor them for specific devices under test, further exacerbating resource waste and structural complexity. Meanwhile, long-distance transmission of independent sense lines is prone to introducing coupling noise, making it difficult to balance measurement accuracy and resource consumption in testing high-pin-count devices. The centralized architecture of the test system also results in insufficient flexibility in adapting to different types of devices under test.

[0006] In summary, existing VI source testing systems have significant shortcomings in terms of test interface resource utilization, simulation resource utilization efficiency, measurement accuracy assurance, control flexibility, and system configurability. There is an urgent need for a new testing system architecture that can reduce dependence on physical connection resources and improve system flexibility and scalability while ensuring testing accuracy. Summary of the Invention

[0007] This invention provides a test system and method for multiplexing analog excitation and digital communication based on VI source channels, addressing the problems of existing semiconductor automatic test systems, such as limited interface physical resources, low utilization of analog measurement resources, difficulty in balancing Sense circuitry and measurement accuracy, waste of relay control resources, and insufficient system adaptability.

[0008] The core technology of this invention is to superimpose a digital communication signal that satisfies DC balance characteristics on the VI source channel to realize the multiplexing and transmission of analog excitation and digital control / measurement signals. Combined with local sampling on the device under test and relay control function, a simplified and general-purpose test instrument and a customized device under test board are constructed to cooperate in a test system.

[0009] In a first aspect, the present invention provides a test system for multiplexing analog excitation and digital communication based on a VI source channel, including a test bench and a device under test board, wherein the test bench and the device under test board are connected through at least one VI source channel and a corresponding pogo interface.

[0010] The testing equipment includes:

[0011] The control logic device contains a VI source loop controller and a digital communication controller. The VI source loop controller is used to generate and regulate the analog output signal of the VI source, and the digital communication controller is used to generate digital communication data and perform protocol control.

[0012] A digital-to-analog converter, connected to the VI source loop controller, is used to convert digital setpoints into analog signals;

[0013] A VI source is used to output analog excitation signals of voltage or current to the pins of the device under test.

[0014] The first digital carrier circuit, connected to the digital communication controller, is used to modulate digital communication data into a communication signal in a predetermined frequency band.

[0015] The first coupler, located in the output path of the VI source, is used to superimpose the communication signal onto the output channel of the VI source to form a composite signal of analog signal and digital communication signal;

[0016] The board under test includes:

[0017] The second coupler is used to separate digital communication signals from the VI source channel;

[0018] The second digital carrier circuit is used to demodulate the separated communication signals;

[0019] The second digital communication controller is used to parse control commands from the test machine or to encode and transmit the data under test back.

[0020] The pin under test is directly connected to the VI source channel to receive analog excitation signals;

[0021] The function execution module, connected to the second digital communication controller, is used to perform test control, measurement, or data acquisition functions.

[0022] Furthermore, the digital communication signal adopts a DC balanced or positive-negative symmetrical encoding method, and the encoding method is one or more combinations of Manchester encoding, differential encoding, return-to-zero code, 8b / 10b encoding, and NRZ encoding with scrambling code.

[0023] Furthermore, the modulation methods used by the first digital carrier circuit and the second digital carrier circuit are one or more combinations of amplitude shift keying, frequency shift keying, and phase shift keying, and the frequency band of the digital communication signal is higher than the bandwidth of the VI source loop.

[0024] Furthermore, the first coupler and the second coupler are one or more combinations of capacitive coupling structure, transformer coupling structure or active coupling structure;

[0025] The first coupler is placed after the VI source output stage and before the pogo interface stage, and the second coupler is placed after the pogo interface stage.

[0026] Furthermore, the function execution module includes a Sense sampling circuit, which is located close to the pin under test and is used to collect the electrical parameters of the pin under test, including voltage or current.

[0027] Furthermore, the Sense sampling circuit includes at least one of the following: an input protection and current limiting module, a buffer and range matching module, a filtering and frequency band isolation module, an analog-to-digital conversion module, and a calibration and compensation module.

[0028] Furthermore, the function execution module includes a relay control circuit, which is used to drive a relay or switch array to switch test paths according to the control instructions parsed by the second digital communication controller.

[0029] Furthermore, the test equipment and the device under test (DUT) board achieve bidirectional communication through time-division multiplexing. The communication cycle includes downlink time slots, guard time slots, and uplink time slots. The downlink time slots are used for the test equipment to send control commands, and the uplink time slots are used for the DUT board to transmit data back.

[0030] Furthermore, a sampling silence window is provided in the communication cycle. During the sampling silence window, the digital carrier remains silent or transmits a predetermined training sequence. The analog-to-digital conversion module of the device under test completes sampling during the sampling silence window.

[0031] Secondly, this invention provides a test method for multiplexing analog excitation and digital communication based on a VI source channel, applied to the aforementioned digital multiplexing communication test system, comprising the following steps:

[0032] The VI source loop controller of the test machine generates an analog excitation signal, which is output to the VI source channel via the VI source;

[0033] The digital communication controller of the test equipment generates digital communication data, which is modulated by the first digital carrier circuit and superimposed onto the VI source channel through the first coupler to form a composite signal;

[0034] The composite signal is transmitted to the device under test board via the pogo interface. The second coupler separates the digital communication signal from the composite signal. The second digital carrier circuit demodulates the signal and then analyzes it by the second digital communication controller.

[0035] The functional execution module of the device under test board performs corresponding operations based on the analysis results, collects the test data, and feeds it back to the second digital communication controller.

[0036] The second digital communication controller encodes the test data, modulates it through the second digital carrier circuit, superimposes it onto the VI source channel through the second coupler, and then transmits it back to the test machine.

[0037] The test equipment receives and transmits data for monitoring or VI source closed-loop control.

[0038] The main contributions and innovations of this invention are as follows:

[0039] 1. Significantly reduces test interface resource consumption by replacing traditional independent Sense lines and control lines with VI source channel reuse, greatly reducing the number of pogopins required and simplifying the test interface structure;

[0040] 2. Reduce the cost and size of the test equipment by moving some measurement and control resources to the board of the device under test, reducing redundant configuration of high-performance analog resources on the test equipment side. Hardware costs can be reduced by 20% to 35%, and board space occupied can be reduced by 10% to 25%.

[0041] 3. Maintain and improve measurement accuracy by shortening the signal path and reducing the equivalent area of ​​the Sense loop through local sampling on the device under test, significantly reducing magnetic field coupling noise and improving anti-interference capability by about 60dB;

[0042] 4. Enhance system flexibility and configurability; sampling accuracy, bandwidth, and relay control structure can be customized according to the type of device under test to adapt to different testing requirements.

[0043] 5. Eliminate the physical connection requirement of the CBIT board on the test machine side, and send relay control commands through the VI source channel to further save interface resources and reduce structural complexity;

[0044] 6. Supports bidirectional communication between the test equipment and the device under test, and transmits status information, calibration data and measurement results in real time, improving the controllability and automation level of the test system;

[0045] 7. Adapts to the testing needs of semiconductor devices with high pin counts and multi-functional integration, while also supporting future testing scenarios for wafer-level, chiplet, or SiP packaged devices.

[0046] Details of one or more embodiments of the present invention are set forth in the following drawings and description, so that other features, objects and advantages of the invention will be more readily understood. Attached Figure Description

[0047] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0048] Figure 1 This is a diagram of the analog-digital multiplexing communication architecture of the VI source channel according to an embodiment of the present invention;

[0049] Figure 2 This is an architecture diagram of a VI source test system without independent Sense circuits according to an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the Sense local sampling circuit structure according to an embodiment of the present invention;

[0051] Figure 4 This is a test system architecture diagram of a CBIT relay-free control according to an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of the relay control circuit structure according to an embodiment of the present invention;

[0053] Figure 6 This is a timing diagram of digital communication TDM when the VI source is continuously output according to an embodiment of the present invention;

[0054] Figure 7 This is a timing diagram of digital communication TDM with sampling silent window according to an embodiment of the present invention. Detailed Implementation

[0055] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with one or more embodiments of this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

[0056] It should be noted that the steps of the corresponding methods are not necessarily performed in the order shown and described in this specification in other embodiments. In some other embodiments, the methods may include more or fewer steps than described in this specification. Furthermore, a single step described in this specification may be broken down into multiple steps in other embodiments; and multiple steps described in this specification may be combined into a single step in other embodiments.

[0057] The following is in conjunction with the appendix Figure 1-7 The technical solution of the present invention will be described in detail through multiple independent and progressive embodiments.

[0058] Example 1: VI Source Channel Analog-Digital Signal Multiplexing Test System (Basic Example)

[0059] This embodiment mainly describes the "VI source channel multiplexing" scheme, which realizes the co-line transmission of analog excitation and digital communication, providing a foundation for subsequent Sense-less and CBIT-less control architectures. (See attached diagram.) Figure 1 , 6 7. It mainly consists of two parts: the VI source module on the main unit of the automatic test equipment (ATE) and the interface board of the device under test (DUT Board or Loadboard). The two are connected by only a few physical connections (i.e., the VI source multiplexing transmission channel), eliminating the traditional Sense feedback line and the dedicated CBIT digital control cable.

[0060] The purpose is to verify the feasibility of simultaneously transmitting analog excitation signals and digital communication signals through the VI source channel, ensuring that the superposition of digital signals does not affect the accuracy of the analog output, and achieving bidirectional communication functionality. The system structure includes a test bench and a device under test (DUT) board, connected via one VI source channel and a corresponding pogo interface.

[0061] 1. Test machine side

[0062] Control logic device: FPGA chip (model XC7K325T) is used, which integrates VI source loop controller and digital communication controller. The VI source loop controller generates digital setpoints for 0~50V DC analog excitation. The digital communication controller implements a bidirectional communication protocol, and the data encoding adopts DC balanced encoding (e.g., Manchester encoding) to reduce the impact on DC accuracy.

[0063] Digital-to-analog converter (DAC): A 20-bit resolution DAC chip (model DAC11001B) is selected and connected to the VI source loop controller to output high-resolution setpoints and drive the VI source module.

[0064] VI source: A linear VI source module (e.g., output voltage 0~50V, current 0~500mA, loop bandwidth 5kHz) is used to provide DC voltage / current excitation to the pin under test.

[0065] The first digital carrier circuit uses a broadband PLC line analog front-end AFE chip (model 88LX2720) for high-frequency transmission drive and reception front-end processing of the VI channel; baseband frame processing, protocol encapsulation, and encoding / decoding are implemented on the FPGA side. The communication signal frequency band is in the MHz range (the example center frequency is about 25MHz), which can form frequency band isolation with the DC / low-frequency operating bandwidth of the VI source.

[0066] First coupler: It adopts a capacitive coupling structure, using a 10nF ceramic capacitor (with a withstand voltage of 200V) in series with a 10Ω damping resistor, and is equipped with a DC blocking / current limiting network. It is arranged between the VI source output terminal and the POGO interface to superimpose high-frequency communication signals onto the VI source channel, while reducing the impact on the stability of DC output.

[0067] 2. Board side of the device under test

[0068] Test pin (DUT Pin): A spring probe structure that connects to the pin of the device under test, with a contact resistance ≤5mΩ.

[0069] Second coupler: With the same structure as the first coupler, it is arranged after the POGO interface and is used to extract the high-frequency communication components in the channel and send them to the receiving link.

[0070] The second digital carrier circuit uses a broadband PLC line analog front-end AFE chip (model 88LX2720) to match the test machine side, and is used to complete the line receiving front-end and transmission drive; the board-side baseband processing is completed by the digital communication controller.

[0071] The second digital communication controller uses an MCU chip (model STM32F103) to parse the control commands issued by the test machine, drive the peripheral circuits to perform actions, and encode and transmit the execution results back.

[0072] Peripheral circuitry: Controlled execution modules used to verify communication functions, such as LED indicators, switch outputs, or simple GPIO expansion circuits; their inputs are connected to the second digital communication controller to respond to control commands such as "light up / light down / change state", and can feed back status information to the second digital communication controller for feedback.

[0073] 3. Work Process

[0074] Analog excitation output: The VI source loop controller generates a digital setpoint for a 20V DC excitation, which is converted into an analog setpoint by the DAC11001B and output from the VI source to the VI source channel and applied to the pin under test via POGO.

[0075] Digital signal superposition: The digital communication controller generates a control command to "light up the peripheral circuit LED", which is then encoded by baseband (e.g., Manchester encoding) and output by the first digital carrier circuit (88LX2720) as a high-frequency communication signal. This signal is then superimposed onto the VI source channel through the first coupler to form a composite signal of "20V DC + MHz level communication signal".

[0076] Signal transmission and analysis: The composite signal is transmitted to the device under test board via the POGO interface. The second coupler extracts the communication component. After the second digital carrier circuit completes the receiving front-end processing, the second digital communication controller parses the signal to obtain the control command and drives the peripheral circuit to execute (e.g., LED lighting).

[0077] Status feedback: The second digital communication controller reads the execution status of the peripheral circuit (e.g., GPIO level or status register), generates "lit" feedback data, and sends it after being encoded on the board and modulated by the second digital carrier circuit. The data is then superimposed onto the VI source channel through the second coupler and sent back to the test machine. The test machine completes the decoding and verification to confirm that the communication link is working properly.

[0078] Accuracy verification: During the digital communication overlay and peripheral control transceiver process, the DC output voltage of the VI source is measured and compared (e.g., near the target value of 20V) to confirm that the overlay communication signal does not introduce significant DC deviation.

[0079] 4. Timing control

[0080] Time Division Multiplexing (TDM) timing (see attached) Figure 6This allows for the multiplexing of downlink commands and uplink return directions on the same physical channel. An example communication cycle is 5ms: a 1.5ms downlink time slot (test equipment sends commands), a 0.5ms guard time slot (direction switching isolation, carrier off or entering silent / training state), and a 3ms uplink time slot (data return from the device under test). These parameters are examples and can be adjusted according to link speed, frame length, and anti-interference requirements.

[0081] In high-precision verification scenarios, enable the sampling silent window (see attached). Figure 7 ): A 0.3ms silent window is set between the downlink and uplink time slots (which can be merged with or partially overlapped with the guard time slot). During the silent window, the carrier is paused or kept silent to reduce the transient impact of superimposed communication on the stability of DC measurement.

[0082] Communication data is transmitted in frames as the basic unit. Each frame includes: a preamble, a frame header (including at least one or a combination of address / channel number, command type, and data length), a data area (payload), and a checksum area (e.g., CRC / checksum). In some implementations, the frame header may also include a timestamp or sequence number to ensure the correspondence between the returned data and the test steps and to detect packet loss.

[0083] 5. Technical Effects

[0084] This embodiment realizes the multiplexing transmission of analog excitation and digital communication signals on the VI source channel: while the VI source outputs DC excitation (e.g., 20V), reliable bidirectional communication and peripheral control feedback can still be achieved by coupling and superimposing MHz-level communication signals, and the impact of communication superposition on the DC output accuracy is controllable.

[0085] The example verification results are as follows: under the condition of communication superposition, the DC output accuracy deviation of the VI source is ≤ ±0.005%; with the cooperation of frame verification and necessary retransmission mechanism, the system-level bit error rate of bidirectional communication can be designed to be ≤1×10^-7, thus verifying the feasibility of VI source channel multiplexing and providing a foundation for subsequent implementations of Senseless and CBITless architectures.

[0086] Example 2: VI Source Testing System Without Sense Circuit (Core Function Example)

[0087] This embodiment mainly describes the "no independent sense line" solution. Based on Embodiment 1, a local sampling circuit is added to the board side of the device under test (DUT). The measurement results are transmitted back through a multiplexed channel to replace the traditional sense line. (Corresponding attached...) Figure 2 , 3 4.

[0088] In traditional technologies, to compensate for the voltage drop and contact resistance caused by the contact between the Force line and the POGO, two Sense lines need to be routed back from the DUT pins to the ATE equipment to form a Kelvin measurement / closed loop. To reduce POGO resources and decrease the coupling of the Sense line loop to external interference, this invention sets up a local sampling circuit near the DUT pins on the DUT board. This circuit converts the actual voltage (or current / combined quantity) at the DUT terminal into a digital quantity and sends it back to the test equipment through a VI source multiplexing channel. The test equipment then performs closed-loop correction based on the returned measurement value, thereby eliminating the need for a separate Sense line.

[0089] 1. System Structure

[0090] Based on Example 1, the board-side of the device under test (DUT) is optimized, while the test equipment side only adds the "sampling data parsing and closed-loop correction" function, with the rest of the structure remaining unchanged. The system still connects to the POGO interface through one VI source multiplexing channel.

[0091] The following components are added / replaced on the board side of the device under test:

[0092] (1) Function execution module: Sense sampling circuit (attached) Figure 3 ), located close to the pin being tested, including:

[0093] Input protection and current limiting module: 100Ω current limiting resistor + TVS diode (e.g., SMBJ60CA) to suppress electrostatic discharge / surge and protect downstream devices;

[0094] Buffer and range matching module: Operational amplifiers (such as OPA211) form a voltage follower / buffer stage, which enables the sampling node to have high input impedance and low output impedance, and can be configured with voltage divider / range matching network as needed to adapt to the ADC input range;

[0095] Filtering and band isolation module: Used to suppress the impact of MHz-level communication components superimposed on the VI channel on sampling. Preferably, a two-stage RC low-pass filter (each stage R=1kΩ, C=100nF, cutoff frequency approximately 1.6kHz) and / or a band-stop (notch filter) network is placed near the communication center frequency to significantly attenuate the coupling components of the communication band to the sampling channel;

[0096] Analog-to-digital converter (ADC): Uses a 20-bit SAR ADC chip (model ADS8900B) with a sampling rate of 1MSPS, used to sample the buffered / filtered DUT terminal voltage;

[0097] Calibration and compensation module: EEPROM (e.g., AT24C02) stores zero-point and gain calibration parameters, and the board-side controller compensates and corrects the sampling results before transmission.

[0098] (2) Data return and communication module:

[0099] The second digital carrier circuit still uses a broadband PLC line analog front-end AFE chip (model 88LX2720) to perform high-frequency communication signal transmission and reception front-end processing on the VI channel;

[0100] The second digital communication controller: MCU (e.g., STM32F103) is responsible for sampling data encapsulation, frame format organization, CRC verification and return; the returned data fields can use DC balanced encoding (e.g., Manchester encoding) to reduce the risk of DC drift.

[0101] New features added to the testing equipment:

[0102] The control logic device (XC7K325T) adds "sampled data analysis and closed-loop correction logic" to the original digital communication analysis: it analyzes the measured values ​​returned from the DUT and fine-tunes the VI source set value (output by DAC11001B) to form closed-loop control.

[0103] 2. Work Process

[0104] Simulated excitation application: The test instrument outputs a 30V DC excitation from the VI source, which is transmitted to the pin under test via the VI source channel and POGO.

[0105] Local sampling: The Sense sampling circuit acquires the actual voltage signal near the DUT pin. After input protection, buffering and filtering / band-stop isolation, it is sampled and converted by ADS8900B. The board compensates and corrects the sampled value according to the zero-point / gain parameters stored in EEPROM to obtain the actual voltage measurement value at the DUT terminal (e.g., 29.998V, as an example).

[0106] Data feedback: The board-side controller encapsulates the compensated sampled data into a communication frame (including channel number / sequence number / CRC, etc.), and superimposes it onto the VI source channel via the board-side 88LX2720 and coupler for uplink feedback; the test machine receives and parses the sampled data from the same VI channel.

[0107] Closed-loop control: After the digital communication controller of the test instrument parses the sampled data, the VI source loop controller fine-tunes the output setpoint (updated via DAC11001B) based on the difference between the actual voltage of the DUT terminal and the target value, so that the actual voltage of the tested pin is stabilized within the target range, for example, stabilized at 30.000V±0.002V (example).

[0108] 3. Comparative Test

[0109] Traditional solution (independent Sense line): Because the Sense line is led back to the machine from the DUT, it forms a large loop area (e.g., about 50cm²). 2 It is more sensitive to external magnetic fields / electromagnetic interference, easily induces noise voltage in the Sense circuit (e.g., on the order of 0.1mV, as an example), and requires an additional 2 Sense pogo pins.

[0110] In this embodiment (without a separate sense line): the local sampling circuit is placed close to the DUT pins, significantly reducing the sampling loop area (e.g., approximately 0.05 cm²). 2 (For example, the noise level can be reduced to the order of 0.0001mV), thereby significantly reducing external interference coupling; under the same interference environment, the sampling link noise voltage can be reduced to the order of 0.0001mV (for example), corresponding to a noise reduction of about 60dB; at the same time, two Sense pogo pins can be reduced.

[0111] Note: The above values ​​are comparative examples used to illustrate the trend of reduced loop area and improved anti-interference capability. Actual values ​​may vary depending on wiring, shielding and filtering design.

[0112] 4. Technical Effects

[0113] This embodiment replaces the traditional independent Sense line with a method of "DUT local sampling + multiplexed channel backhaul + equipment-side closed-loop correction" to achieve the following:

[0114] (1) Eliminate the independent Sense line to reduce POGO pin usage;

[0115] (2) The local sampling loop is close to the DUT end, the loop area is significantly reduced, the anti-interference ability is improved, and the coupling noise of the traditional Sense line loop is reduced;

[0116] (3) Under the condition of superimposed communication signals, the stability of sampling measurement and closed-loop correction is ensured by filtering / band-stop isolation and optional sampling silent window strategy, so that the actual voltage at the DUT terminal can be stabilized within the target range;

[0117] (4) No need to bring back high-precision Sense lines at the machine end, which can reduce the complexity of system wiring and improve configurability, providing a basis for configuring sampling and functional circuits on different Loadboards as needed.

[0118] Example 3: Test System Without CBIT Relay Control (Core Function Example)

[0119] This embodiment mainly describes the "CBIT board-free" solution. Based on Embodiment 1, the relay control function is moved to the device under test board, eliminating the need for a CBIT board on the test bench side. (Corresponding attached...) Figure 4 , 5In traditional architectures, ATE equipment requires dedicated CBIT boards to control the relay matrix on the DUT board via multiple digital control lines and dedicated pogo pins. This results in high interface resource consumption, complex wiring, and difficulty in flexibly expanding for different products.

[0120] In this embodiment, both the relay drive circuit and the relay array are located on the board side of the device under test (DUT) and are directly controlled by the board-side slave digital communication controller. Relay control commands are sent and verified via the VI source multiplexing channel, thereby eliminating the need for the CBIT board and its dedicated control pogo pin, improving control flexibility, and reducing the hardware cost of the testing equipment.

[0121] 1. System Structure

[0122] Based on Example 1, the following optimizations are made to both the test equipment side and the device under test board side:

[0123] Test equipment side optimization:

[0124] The independent CBIT control board has been removed; the digital communication controller on the test machine side has been updated with a "relay control command generation and scheduling" function, which is used to generate relay switching commands according to the test process, wait for execution receipts, and perform abnormal retry / alarm.

[0125] Add / replace components on the board side of the device under test:

[0126] Functional execution module: Relay control circuit (attached) Figure 5 ),include:

[0127] Control interface module: The control interface connected to the second digital communication controller can adopt one of SPI, GPIO parallel or serial shift methods; in this embodiment, the SPI interface is preferred for transmitting the relay target status word and verification information;

[0128] Driver-level module: The DRV8860PWPR relay driver chip is used to drive the relay coil to engage / disengage; the board-side controller outputs control signals to realize relay logic control (e.g., defining "1 = engaged and closed, 0 = disengaged and open").

[0129] Freewheeling and protection module: A transient suppression and absorption network is configured at the coil end or the drive end to suppress the reverse induced voltage and EMI generated when the coil is de-energized; a combination of TVS / RC absorption and other methods can be used, and the parameters are determined according to the coil current and the supply voltage;

[0130] Status detection module: used to confirm whether the relay action is completed. Preferred methods include (at least one): coil current detection, contact readback or auxiliary contact detection; in this embodiment, a small resistance sampling resistor (e.g., 0.1Ω~1Ω) can be used in conjunction with an operational amplifier / comparator or MCU ADC to detect the coil current in order to determine the energized state.

[0131] Relays: TQ2-5V signal relays are used to form a test path switching array (e.g., expandable to 2 / 4 / 8 channels) to switch VI source excitation or other test resources to different pins under test or test networks.

[0132] Communication module (same as in Example 1):

[0133] Both the board and the machine end include couplers and digital carrier circuits. The digital carrier circuit uses 88LX2720, and the communication signals are transmitted bidirectionally through the VI source channel in a MHz-level superposition manner. The second digital communication controller on the board is responsible for parsing control commands and sending back the execution status.

[0134] 2. Work Process

[0135] Control command generation: According to the test procedure, the test machine generates a control command for "switching to test path 2" by the digital communication controller (the command includes the target relay bitmap, hold time, verification field, etc.).

[0136] Command transmission: After being encapsulated by the communication link at the machine end, the control command is superimposed on the VI source channel through the digital carrier circuit and coupler at the machine end; during this process, the VI source can simultaneously output DC excitation (e.g., 10V) to maintain the working state of the device under test.

[0137] Command parsing and execution: The communication component is extracted by the coupler on the board side of the device under test. After being processed by the digital carrier circuit on the board, the relay control command is parsed by the second digital communication controller and sent to the relay control circuit through the control interface (e.g., SPI). The DRV8860PWPR applies a driving voltage to the TQ2-5V relay coil according to the control signal, so that the relay is engaged or disengaged, thereby completing the test path switching.

[0138] Status feedback: The status detection module detects changes in coil current or contact readback results to confirm that the relay action is complete; the second digital communication controller generates "path switching complete / failed" feedback data and transmits it back to the test machine through the same VI source channel.

[0139] Test execution: The VI source excitation is transmitted to the pin under test via the switched test path, and the test machine performs measurement and judgment according to the predetermined test items.

[0140] 3. Comparative Test

[0141] Traditional solution: The test equipment needs to be equipped with an independent CBIT control board, which occupies a number of CBIT control pogo pins (e.g., ≥3 pins, which increase with the number of relays and control methods).

[0142] In this embodiment, the CBIT control board and its dedicated control pogo pin on the test bench side are eliminated; the relay control circuit and relay array are integrated on the board side of the device under test, and the number and topology of relays (2-way, 4-way, 8-way, etc.) can be flexibly configured according to the specific test requirements of the device under test, and the test path can be dynamically switched through communication commands.

[0143] 4. Technical Effects

[0144] This embodiment achieves the following by bringing the relay control function down to the board side of the device under test and using the VI source multiplexing channel to send / return relay control commands:

[0145] (1) Eliminate the CBIT board and dedicated control pogo pin on the test machine side to reduce interface resource occupation and wiring complexity;

[0146] (2) The relay control is bound to the board of the device under test. The number of relays and the topology can be customized according to the product under test, which improves the flexibility of the test system configuration.

[0147] (3) Reliability is improved by implementing a status feedback mechanism, which can detect and retry abnormal relay operation;

[0148] (4) Reduce the hardware cost and size of the test equipment and improve the system scalability.

[0149] Example 4: Comprehensive Functional Testing System (Complete Solution Example)

[0150] This embodiment is a complete solution, combining the functions of Embodiment 2 and Embodiment 3 to realize a comprehensive test system without independent Sense circuits, without CBIT boards, and with multiple channels multiplexed.

[0151] 1. Purpose of the Implementation Example

[0152] Verify the feasibility of the complete technical solution of this invention in the testing scenario of high pin count (e.g., 32 channels) semiconductor devices: Simultaneously realize analog excitation and digital communication multiplexing on 32 VI source channels; realize local Sense sampling on the DUT board side and transmit it back through the multiplexed channel for machine closed-loop correction; at the same time, push the relay control down to the DUT board side and issue control commands through the multiplexed channel to eliminate the occupation of POGO resources by the traditional Sense line and CBIT control line.

[0153] 2. System Structure

[0154] The system includes a test bench and a device under test board, which are connected through 32 VI source channels and corresponding POGO interfaces.

[0155] (1) Test machine side (32 channels)

[0156] 32-channel VI source: Each channel outputs 0~50V, 0~500mA (example), used to provide DC / low-frequency analog excitation to different pins under test;

[0157] 32-channel digital-to-analog converter (DAC): Each channel is equipped with a 20-bit DAC chip (model DAC11001B) for outputting VI source setpoints or control values;

[0158] 32-channel first coupler: Each channel adopts a capacitive coupling structure (e.g., a 10nF, 200V ceramic capacitor in series with a 10Ω damping resistor, and a DC blocking / current limiting network) to superimpose digital communication signals onto the VI source channel of that channel;

[0159] 32-channel first digital carrier circuit: Each channel uses a broadband PLC line analog front-end AFE chip (model 88LX2720) to complete the line transmission drive and reception front-end processing of the communication signal of that channel; the communication signal is in the MHz band (approximately 25MHz in the example center), forming a frequency band isolation with the DC / low frequency operating bandwidth of the VI source;

[0160] Control logic devices: An FPGA chip (e.g., XC7K410T) is used to implement 32-channel VI source setting, 32-channel communication protocol processing and parallel scheduling, and to implement sampled data parsing and closed-loop correction (corresponding to Embodiment 2) and relay control command generation (corresponding to Embodiment 3). Data frames use DC balanced encoding (e.g., Manchester encoding) and CRC check, and TDM timing management is used for uplink / downlink direction switching and silent window.

[0161] (2) Test device board side (32 channels + relay array)

[0162] 32-channel second coupler: Consistent with the structure on the test bench side, it is arranged after each POGO interface and is used to extract / superimpose the communication component of that channel;

[0163] 32-channel second digital carrier circuit: each channel uses an 88LX2720, matched with the test equipment side;

[0164] Board-side digital communication controller: This can be implemented using a multi-controller array or a centralized control structure. An example solution uses multiple MCUs (e.g., an STM32F103 array) to manage several channels (e.g., each MCU manages N channels), used for parsing communication frames, organizing the returned data, and issuing local control commands.

[0165] 32 pins under test: Connect to the corresponding pins of the device under test;

[0166] 32-channel Sense sampling circuit: Each channel is located close to the corresponding DUT pin and includes input protection / buffering / filtering and frequency band isolation modules, as well as a 20-bit 1MSPS SAR ADC (model ADS8900B). The sampling results can be locally calibrated and compensated (zero-point / gain parameters are stored in EEPROM) before being transmitted back.

[0167] Relay control circuit: An 8-channel relay control unit (example) is used. Each control unit contains a switching array consisting of a relay driver chip DRV8860PWPR and several TQ2-5V relays. The example configuration is that each control unit implements 4-channel relay switching, forming a total of 32 test path switching resources. The relay control commands are received and executed by the board-side controller, and the execution status is returned.

[0168] 3. Work Process

[0169] Multi-channel excitation output: The test instrument has 32 VI sources that output DC excitations ranging from 5V to 50V (example), which are transmitted to the corresponding pins under test via their respective VI source channels and POGO.

[0170] Multiple command issuance: The test machine generates 32 sampling request / range configuration commands and relay switching commands according to the test process. These commands are then superimposed on the corresponding VI source channels via each 88LX2720 and coupler to control the board-side sampling and relay switching.

[0171] Parallel execution: The device under test (DUT) executes commands in parallel on the board side.

[0172] Sense sampling: Each Sense sampling circuit acquires the actual voltage (or current / combined quantity) at the corresponding DUT terminal, and obtains the measured value after filtering and calibration compensation; when closed-loop control is required, it is preferred to send back "key measurement results of each channel (e.g., average value / sampled value / steady-state value)" rather than all the original high-speed waveforms, so as to ensure that the multi-channel system can be realized in terms of communication bandwidth and scheduling;

[0173] Relay switching: The 8-channel relay control unit drives the TQ2-5V relay to complete the test path switching and generate status information (engagement confirmation / abnormal detection).

[0174] Data feedback and closed-loop correction: The board sends the 32 key sampling results and relay status back to the test equipment in packets; after parsing, the test equipment fine-tunes the settings of each VI source to form a closed-loop correction, so that the actual voltage of the corresponding DUT terminal is stabilized within the target range, while monitoring the relay status and performing retry or alarm for abnormalities.

[0175] Global monitoring and automated testing: The test equipment performs unified scheduling of 32 channels to ensure that the uplink and downlink of each TDM channel do not conflict with each other. In high-precision scenarios, a silent window / protection time slot strategy is enabled for key sampling moments to reduce the impact of communication superposition on accuracy verification.

[0176] 4. Technical Effects

[0177] (1) Interface resource saving: The traditional 32-channel Kelvin structure requires 2 sense pogo pins per channel, totaling 64 pins; the traditional CBIT control usually requires multiple dedicated control pogo pins (for example, based on 8 control units, each unit has 3 control lines, totaling 24 pins). This embodiment eliminates the independent sense line and CBIT control line, saving a total of 88 POGO resources.

[0178] (2) Functional integration: All 32 VI source channels realize analog excitation and digital communication multiplexing, and the board realizes local sampling feedback and relay path switching. The test machine only retains unified closed-loop and scheduling control, thereby reducing the number of dedicated boards and dedicated wiring on the machine side.

[0179] (3) Cost and volume optimization: By eliminating the CBIT board and a large number of dedicated cables / connectors on the machine side, and sinking some functions to the board side of the device under test, the overall hardware cost and board space occupied by the system can be significantly reduced (exemplary evaluation: cost reduction of about 35% and space reduction of about 25%, depending on the number of channels, relay scale and implementation method).

[0180] (4) Test accuracy: Through local sampling and feedback at the board end and closed-loop correction of the machine, the target voltage deviation of the DUT end of 32 parallel tests can be controlled within ≤±0.01% (example), which is suitable for the automated testing requirements of high pin count semiconductor devices.

[0181] Example 5: Key Component Alternative Implementation

[0182] Coupler: Can be replaced with a 1:1 ratio transformer coupling structure (model EE16, operating bandwidth 10MHz~30MHz, isolation withstand voltage 200V), suitable for scenarios with high isolation requirements.

[0183] Encoding method: Digital communication signals can use 8b / 10b encoding (to replace Manchester encoding) to improve anti-interference ability and adapt to higher communication rates (1Mbps~10Mbps).

[0184] ADC selection: For low-precision scenarios, a 12-bit ADC (model ADS1115) can be used, which reduces costs by 50%; for high-frequency scenarios, a 16-bit ADC (model ADS8320) with a sampling rate of 1MSPS can be used to adapt to high-frequency signal sampling.

[0185] Relay replacement: Solid-state relays (model SSR-10DA) can be used to replace electromagnetic relays, increasing switching speed to 1ms and extending lifespan by 10 times.

[0186] Example 6: Communication Protocol and Signal Modulation

[0187] To ensure reliable data transmission on the DC VI source channel without affecting DC output accuracy, this invention employs a communication mechanism of "high-frequency superposition + DC balanced coding + time-division multiplexing".

[0188] Physical Layer: The communication link uses a MHz-level high-frequency signal superimposed on a DC Force line. Couplers and broadband line analog front-ends (e.g., 88LX2720) are set on the test bench side and the device under test (DUT) board side, respectively. The controller (FPGA / MCU) completes baseband modulation / demodulation and frame processing, while the 88LX2720 completes line transmission drive and receiver front-end processing. The communication frequency band is separated from the DC / low-frequency operating bandwidth of the VI source (e.g., the center frequency is approximately 25MHz, which can be configured according to system constraints). Capacitive coupling is preferred as the coupling method, and damping / current limiting and filtering isolation networks are set on the superposition path to suppress the impact of high frequencies on the DUT power supply and VI source loop.

[0189] Link Layer: Defines a dedicated data frame structure, including at least: a preamble / synchronization sequence (for receiver synchronization), a frame header (address / channel number, command type, data length), a data area (parameter values ​​or measured values), and a checksum (CRC). To avoid introducing DC bias, the data area uses DC balanced coding (e.g., Manchester coding). Communication uses TDM directional multiplexing, including downlink time slots, guard time slots, and uplink time slots. In high-precision sampling or accuracy verification scenarios, a silent window can be set at the uplink / downlink switching point. During the silent window, the carrier is paused or remains silent to reduce the transient impact of superimposed communication on the stability of DC measurements.

[0190] Through the aforementioned two-way communication, the system can issue control commands such as voltage / current setting, range configuration, and relay switching, and send back board-side execution status, measurement results, or board-level management information (such as temperature / status words), thereby enabling configurable and monitorable board-level testing and management.

[0191] Through the above-described embodiments, the technical solution of the present invention has been fully verified, from basic signal multiplexing to core Senseless and CBIT-free control, and then to complete multi-channel integrated testing, covering different application scenarios and ensuring that those skilled in the art can implement the technical solution of the present invention according to actual needs.

[0192] Those skilled in the art should understand that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0193] The above embodiments are merely illustrative of several implementations of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims

1. A test system for multiplexing analog excitation and digital communication based on a VI source channel, characterized in that, The test equipment includes a test bench and a device under test board, wherein the test bench and the device under test board are connected through at least one VI source channel and a corresponding pogo interface; The testing equipment includes: The control logic device internally includes a VI source loop controller and a digital communication controller. The VI source loop controller is used to generate and regulate the analog output signal of the VI source, and the digital communication controller is used to generate digital communication data and perform protocol control. A digital-to-analog converter, connected to the VI source loop controller, is used to convert digital setpoints into analog signals; A VI source is used to output analog excitation signals of voltage or current to the pins of the device under test. A first digital carrier circuit, connected to the digital communication controller, is used to modulate digital communication data into a communication signal in a predetermined frequency band. The first coupler is located in the output path of the VI source and is used to superimpose the communication signal onto the output channel of the VI source to form a composite signal of the analog excitation signal and the communication signal. The device under test board includes: A second coupler is used to separate the communication signal from the composite signal of the VI source channel; The second digital carrier circuit is used to demodulate the separated communication signal to obtain the corresponding digital communication data; The second digital communication controller is used to parse control commands from the test machine or to encode and transmit the data under test back. The pin under test is directly connected to the VI source channel to receive analog excitation signals; The function execution module is connected to the second digital communication controller and is used to perform test control, measurement or data acquisition functions.

2. The testing system according to claim 1, characterized in that, The digital communication signal adopts a DC balanced or positive-negative symmetrical encoding method, which is one or more combinations of Manchester encoding, differential encoding, return-to-zero code, 8b / 10b encoding, and NRZ encoding with scrambling code.

3. The testing system according to claim 1, characterized in that, The modulation methods used by the first digital carrier circuit and the second digital carrier circuit are one or more combinations of amplitude shift keying, frequency shift keying, and phase shift keying, and the frequency band of the digital communication signal is higher than the VI source loop bandwidth.

4. The testing system according to claim 1, characterized in that, The first coupler and the second coupler are one or more combinations of capacitive coupling structure, transformer coupling structure or active coupling structure; The first coupler is positioned after the VI source output stage and before the pogo interface stage, and the second coupler is positioned after the pogo interface stage.

5. The testing system according to claim 1, characterized in that, The function execution module includes a Sense sampling circuit, which is located close to the pin under test and is used to collect the electrical parameters of the pin under test, including voltage or current.

6. The testing system according to claim 5, characterized in that, The Sense sampling circuit includes at least one of the following: an input protection and current limiting module, a buffer and range matching module, a filtering and frequency band isolation module, an analog-to-digital conversion module, and a calibration and compensation module.

7. The testing system according to claim 1, characterized in that, The function execution module includes a relay control circuit, which is used to drive a relay or switch array to switch test paths according to the control instructions parsed by the second digital communication controller.

8. The testing system according to claim 1, characterized in that, The test instrument and the device under test (DUT) board achieve bidirectional communication through time-division multiplexing. The communication cycle includes downlink time slots, guard time slots, and uplink time slots. The downlink time slots are used for the test instrument to send control commands, and the uplink time slots are used for the DUT board to transmit data back.

9. The testing system according to claim 8, characterized in that, The communication cycle also includes a sampling silence window, during which the digital carrier remains silent or transmits a predetermined training sequence, and the analog-to-digital conversion module of the device under test completes sampling within the sampling silence window.

10. A test method for multiplexing analog excitation and digital communication based on a VI source channel, characterized in that, The test system applied to any one of claims 1-9 includes the following steps: The VI source loop controller of the test machine generates an analog excitation signal, which is output to the VI source channel via the VI source; The digital communication controller of the test equipment generates digital communication data, which is modulated by the first digital carrier circuit and superimposed onto the VI source channel through the first coupler to form a composite signal; The composite signal is transmitted to the device under test board via the pogo interface. The second coupler separates the communication signal from the composite signal. The second digital carrier demodulates the separated communication signal to obtain the corresponding digital communication data, which is then parsed by the second digital communication controller. The functional execution module of the device under test board performs corresponding operations based on the analysis results, collects the test data, and feeds it back to the second digital communication controller. After the second digital communication controller encodes the test data into the digital communication data, it is modulated by the second digital carrier circuit, superimposed by the second coupler onto the VI source channel, and then transmitted back to the test machine. The test equipment receives and transmits data for monitoring or VI source closed-loop control.

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