A cache consistency maintenance method, apparatus, device, medium and program product
By having the master node in a multi-core processor system return a response message, inquire about data requirements, and update directory entries, the bus load problem caused by non-exclusive cache line write operations is resolved, efficient cache consistency maintenance is achieved, and the execution efficiency of write-after-read operations is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2026-03-24
- Publication Date
- 2026-06-12
AI Technical Summary
In shared memory systems such as multi-core processors and multi-way servers, non-exclusive cache lines need to initiate a mutual exclusion read request before performing a write operation, resulting in invalid data transmission, increased bus load and communication latency, and significantly reduced write operation efficiency, especially in large-scale multi-node concurrent write scenarios.
After receiving an invalid cache consistency write operation request, the master node first returns a response message. Without waiting for data to be retrieved, it initiates an invalidation listening request to the other nodes to inquire about data needs, updates directory entries, accurately senses node needs, and sends a completion response after receiving the data to be written, distributing data only to nodes that have data needs.
It effectively reduces bus communication overhead, simplifies the write-after-read operation process, reduces operation latency, improves the write-after-read operation efficiency of multi-node systems, and ensures cache data consistency.
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Figure CN121901296B_ABST