A cache consistency maintenance method, apparatus, device, medium and program product

By having the master node in a multi-core processor system return a response message, inquire about data requirements, and update directory entries, the bus load problem caused by non-exclusive cache line write operations is resolved, efficient cache consistency maintenance is achieved, and the execution efficiency of write-after-read operations is improved.

CN121901296BActive Publication Date: 2026-06-12SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
Filing Date
2026-03-24
Publication Date
2026-06-12

AI Technical Summary

Technical Problem

In shared memory systems such as multi-core processors and multi-way servers, non-exclusive cache lines need to initiate a mutual exclusion read request before performing a write operation, resulting in invalid data transmission, increased bus load and communication latency, and significantly reduced write operation efficiency, especially in large-scale multi-node concurrent write scenarios.

Method used

After receiving an invalid cache consistency write operation request, the master node first returns a response message. Without waiting for data to be retrieved, it initiates an invalidation listening request to the other nodes to inquire about data needs, updates directory entries, accurately senses node needs, and sends a completion response after receiving the data to be written, distributing data only to nodes that have data needs.

🎯Benefits of technology

It effectively reduces bus communication overhead, simplifies the write-after-read operation process, reduces operation latency, improves the write-after-read operation efficiency of multi-node systems, and ensures cache data consistency.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN121901296B_ABST
    Figure CN121901296B_ABST
Patent Text Reader

Abstract

The application discloses a cache consistency maintenance method and device, equipment, medium and program product, relates to the computer technical field, and the main node is after receiving the cache consistency write operation request of the first request node of the initial state being invalid state, first returns a response message, then initiates the invalidation monitoring request carrying the target cache line data demand inquiry to the rest request node, and receives the monitoring response carrying the data demand information of each node, accurately perceives and records the actual data demand of each node, avoids the problem of increasing bus load; based on the updated directory entry, only the target cache line data is distributed to the node with data demand, without waiting for the data demand node to reinitiate the read data operation, which can effectively reduce the bus communication overhead, simplify the process of the read-after-write operation of the multi-core system, reduce the operation delay, ensure the cache data consistency among the multiple nodes, and significantly improve the execution efficiency of the read-after-write operation in the shared memory system.
Need to check novelty before this filing date? Find Prior Art