System, method and apparatus for calculating loss function in quantum linear system

Abstract

The embodiment of the invention discloses a system, method and device for calculating a loss function in a quantum linear system.The system comprises classic hardware and quantum hardware which are in communication connection, and the classic hardware is used for vectorizing the Hamiltonian of the quantum linear system to obtain the loss function; according to the vectorized Hamiltonian, constructing an SWAP test circuit used for calculating a loss function in the quantum linear system, and sending the SWAP test circuit to the quantum hardware; the quantum hardware is used for operating the SWAP test circuit; and the classical hardware is used for measuring auxiliary bits in the SWAP test circuit to obtain a value of a loss function. According to the embodiment of the application, the matrix-vector multiplication in the loss function is mapped into the inner product of the vector, so that the requirement on explicit matrix operation is eliminated, and the quantum calculation of the loss function is realized by using the SWAP test circuit, so that the quantum circuit only needs to be executed once in each loss function evaluation, the execution complexity of the quantum circuit can be reduced, and the quantum calculation efficiency is improved. Therefore, consumption of quantum hardware resources is reduced.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a system, method, and apparatus for calculating loss functions in quantum linear systems. Background Technology

[0002] Variational quantum algorithms (VQA) are a class of hybrid algorithms combining classical optimization and quantum computing, widely used in recent medium-scale quantum devices with noise. Their core idea is to prepare quantum states using a parameterized quantum circuit and then adjust the circuit parameters using a classical optimizer to minimize the loss function. VQA is used to solve linear systems. When this is the case, it is usually called a Variational Quantum Linear Solver (VQLS), where, The coefficient matrix, The unknown quantity to be solved is... This is the right-hand vector. VQLS defines the following loss function: Since quantum computing only supports unitary operators, the coefficient matrix in the loss function... It needs to be decomposed into a linear combination of unitary operators, that is ,in It is a unitary matrix. It is a coefficient. This is the total number of terms in the unitary matrix after decomposition. The loss function takes the following form: .

[0003] Based on the loss function described above, VQLS uses a classical optimizer (such as gradient descent) to iteratively update the parameters of the quantum circuit. To minimize the loss function Continue until the convergence condition is met, and an optimal set of results is obtained. This is approximately a normalized solution to the system of equations. The number of quantum circuits required for each evaluation of the above loss function increases with the number of unitary matrix terms in the coefficient matrix decomposition. It grows quadratically, meaning the quantum circuit execution complexity for each loss function calculation is O(n log n). The execution of quantum circuits requires configuration and conversion into analog signals using a classical computer. The quadratic increase in the number of quantum circuits leads to a quadratic increase in the consumption of quantum hardware resources. Summary of the Invention

[0004] Based on the above-mentioned technical problems, this application provides a system, method, and apparatus for calculating the loss function in a quantum linear system. By mapping the matrix-vector multiplication in the loss function to the inner product of vectors, the need for explicit matrix operations is eliminated. The quantum computation of the loss function is realized using a SWAP test circuit, so that the quantum circuit only needs to be executed once for each loss function evaluation, which can reduce the execution complexity of the quantum circuit and thus reduce the consumption of quantum hardware resources.

[0005] A first aspect of this application provides a system for calculating a loss function in a quantum linear system, comprising classical hardware and quantum hardware connected by communication, wherein: Classical hardware is used to vectorize the Hamiltonian of the quantum linear system, construct a SWAP test circuit based on the vectorized Hamiltonian for calculating the loss function in the quantum linear system, and send the SWAP test circuit to the quantum hardware. Quantum hardware for running the SWAP test circuit; Classical hardware is used to measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function.

[0006] Optionally, the classical hardware is also used to update the parameters of the SWAP test circuit using gradient descent based on the value of the loss function, and send the updated SWAP test circuit to the quantum hardware.

[0007] Optionally, the SWAP test circuit includes a quantum logic gate for preparing the vectorized Hamiltonian to a first quantum state and a parametric quantum logic gate for preparing a second quantum state.

[0008] Optionally, measuring the auxiliary bits in the SWAP test circuit to obtain the value of the loss function includes: The auxiliary bit in the SWAP test circuit is measured to determine the probability of the auxiliary bit in the ground state. The difference between twice the probability of the auxiliary bit in the ground state and 1 is determined as the similarity between the first quantum state and the second quantum state; The product of the square root of the similarity between the first quantum state and the second quantum state and the second norm of the Hamiltonian is determined as the value of the loss function.

[0009] Optionally, the first quantum state is as follows: , in, It is the first quantum state. For Hamiltonian, For vectorized Hamiltonians, The second norm of the Hamiltonian, The first matrix corresponding to the Hamiltonian Line number Column elements, This represents the number of rows and columns.

[0010] Optionally, the quantum linear system uses Indicate, then ,in, The coefficient matrix, The unknown quantity to be solved is... This is the vector on the right side.

[0011] A second aspect of this application provides a method for calculating a loss function in a quantum linear system, the method comprising: The Hamiltonian of the quantum linear system is vectorized, and a SWAP test circuit for calculating the loss function in the quantum linear system is constructed based on the vectorized Hamiltonian. Run the SWAP test circuit; The value of the loss function is obtained by measuring the auxiliary bits in the SWAP test circuit.

[0012] A third aspect of this application provides an apparatus for calculating a loss function in a quantum linear system, the apparatus comprising: A classical computing unit is used to vectorize the Hamiltonian of the quantum linear system and to construct a SWAP test circuit for calculating the loss function of the quantum linear system based on the vectorized Hamiltonian. A quantum computing unit is used to run the SWAP test circuit. The classical computing unit is also used to measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function.

[0013] A fourth aspect of this application provides an electronic device, including: a processor and a memory; The processor is connected to a memory, wherein the memory is used to store computer programs and the processor is used to invoke the computer programs to execute the methods as described in the second aspect of the embodiments of this application.

[0014] The fifth aspect of this application provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, perform the method as described in the second aspect of this application.

[0015] This application provides a system for calculating the loss function in a quantum linear system, comprising classical hardware and quantum hardware connected by communication. The classical hardware is used to vectorize the Hamiltonian of the quantum linear system, construct a SWAP test circuit for calculating the loss function based on the vectorized Hamiltonian, and send the SWAP test circuit to the quantum hardware. The quantum hardware is used to run the SWAP test circuit. The classical hardware is used to measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function. It can be seen that in this embodiment, by mapping the matrix-vector multiplication in the loss function to the inner product of vectors, the need for explicit matrix operations is eliminated. The quantum computation of the loss function is achieved using the SWAP test circuit, so that each loss function evaluation only requires the execution of the quantum circuit once, reducing the execution complexity of the quantum circuit and thus reducing the consumption of quantum hardware resources. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 An example system block diagram for calculating the loss function in a quantum linear system, according to an embodiment of this application, is shown. Figure 2 A schematic diagram of the structure of a SWAP test circuit provided in one embodiment of this application is shown; Figure 3 This invention provides a schematic diagram of the structure of a SWAP test circuit for calculating the loss function in a quantum linear system according to an embodiment of the present application. Figure 4 A flowchart illustrating a method for calculating a loss function in a quantum linear system according to an embodiment of this application is shown. Figure 5 A schematic diagram of a device for calculating the loss function in a quantum linear system according to an embodiment of this application is shown. Figure 6 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0020] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A single qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, then... A quantum state can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement, where the state of one qubit (whether 1, 0, or both) depends on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0021] Please refer to Figure 1 This illustrates an example system block diagram for computing loss functions in a quantum linear system, provided in one embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1 In the example shown, system 100 may include quantum hardware 110 and classical hardware 120. In one implementation, quantum hardware 110 and classical hardware 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). Quantum hardware 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. Classical hardware 120 may be electronically integrated with quantum hardware 110 via any suitable wired and / or wireless electronic connection.

[0022] exist Figure 1 In the example shown, quantum hardware 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1 In the illustrated example embodiment, quantum hardware 110 may include a measurement and control unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control unit 111, interface 112, and quantum chip 113 may be located in a cryogenic environment to facilitate the performance of quantum operations. Quantum chip 113 may be any hardware capable of processing information using quantum states. This hardware may include multiple qubits and means for coupling or entanglement of the qubits to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on the qubits stored in a quantum register. Quantum gates may include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0023] The measurement and control unit 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in conjunction with interface 112. This digital computing device may include a digital processor and memory for storing and executing quantum instructions using interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the performed quantum computing to a classical computer. Additionally, the digital computing device may include a communication interface with interface 112. In one embodiment, the measurement and control unit 111 may be configured to receive classical instructions (e.g., from classical hardware 120) and convert these classical instructions into measurement and control instructions for interface 112. The measurement and control instructions provided by the measurement and control unit 111 to interface 112 may be, for example, digital signals indicating which quantum gates in a quantum gate array need to be applied to the qubits to perform a specific function. Interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which can be used to apply quantum gates to the qubits to manipulate the interactions between the qubits.

[0024] Interface 112 may be a classical-quantum interface, comprising a combination of devices capable of receiving instructions from the integrated measurement and control unit 111 and converting those instructions into a means for implementing quantum operations. In one embodiment, interface 112 may convert instructions from the integrated measurement and control unit 111 into drive signals capable of driving or manipulating qubits, and / or applying quantum gates to qubits. Additionally, interface 112 may be configured to convert signals received from the quantum chip 113 into digital signals capable of being processed and transmitted by the integrated measurement and control unit 111. Devices included in interface 112 may include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 may further include circuitry configured to measure multiple qubits after the application of quantum gates, wherein the measurements may produce results represented in classical bits. Each measurement performed by interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The multiple measurement results provided by interface 112 may represent probabilistic results.

[0025] Classical hardware 120 can include hardware components such as a processor and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, classical hardware 120 can be configured to provide quantum hardware 110 with various control signals, instructions, and data encoded in classical bits. Furthermore, the quantum state measured by quantum hardware 110 can be read out by classical computer 120, and classical hardware 120 can store the measured quantum state as classical bits in classical registers.

[0026] In one embodiment, classical hardware 120 can be any suitable combination of computer-executable hardware and / or computer-executable software capable of executing preparation module 121 to perform quantum computing using data stored in data storage module 122 as part of the construction and computation. Data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and the results of that analysis. Preparation module 121 can be a program or module capable of preparing classical data from data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as a function call to an application programming interface (API), or by resolving hybrid classical-quantum computing into aspects of quantum and classical computing. For example, preparation module 121 can generate instructions for creating quantum circuits using quantum gates. In an embodiment, such instructions can be stored by measurement and control unit 111 and can be instantiated by components of interface 112 to execute, such that quantum operations of quantum gates can be performed on quantum chip 113.

[0027] Classic hardware 120 can be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, classic hardware 120 can also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). Classic hardware 120 can also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0028] When the above system is used to calculate the loss function in a quantum linear system: Classical hardware is used to vectorize the Hamiltonian of the quantum linear system, construct a SWAP test circuit based on the vectorized Hamiltonian for calculating the loss function in the quantum linear system, and send the SWAP test circuit to the quantum hardware. Quantum hardware for running the SWAP test circuit; Classical hardware is used to measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function.

[0029] I. The vector dot product mapping theorem for matrix-vector multiplication states: For any matrix... ,vector x ,have , in, For matrix The vectorization, i.e.: , The standard basis vector representation is as follows: .

[0030] In this application, the quantum linear system is used... Indicate, then ,in, The coefficient matrix, The unknown quantity to be solved is... This is the vector on the right side.

[0031] According to the vector inner product mapping theorem of matrix-vector multiplication, the Hamiltonian can be vectorized as follows: , in, It is the first quantum state. For Hamiltonian, For vectorized Hamiltonians, The second norm of the Hamiltonian, The first matrix corresponding to the Hamiltonian Line number Column elements, This represents the number of rows and columns.

[0032] Based on the vectorized Hamiltonian, the loss function can be rewritten as: .

[0033] II. SWAP Test Circuit Please refer to Figure 2 The diagram shows a schematic of the structure of a SWAP test circuit provided in one embodiment of this application. and They are respectively in The quantum states prepared on each qubit are used by the SWAP test circuit to calculate the inner square product. The time complexity is The specific principle is as follows: The initial quantum state is ， application Gate to auxiliary qubit, there are .

[0034] In two Controlled swapping gates are applied between bit registers: .

[0035] application Gate to auxiliary qubit, there are .

[0036] Measuring the auxiliary qubit to obtain the ground state The probability is , Therefore: .

[0037] Based on the above, the loss function can be... middle The item is obtained through the SWAP test circuit, that is, the SWAP test circuit mentioned above. and Replace with and ,in, Initial state preparation is performed using amplitude encoding or sparse state preparation algorithms.

[0038] Please refer to Figure 3This illustration shows a schematic diagram of a SWAP test circuit for calculating the loss function in a quantum linear system according to an embodiment of this application, requiring a number of qubits. As shown in the figure, the SWAP test circuit includes a quantum logic gate for preparing the vectorized Hamiltonian to a first quantum state and a parametric quantum logic gate for preparing a second quantum state. The gate for preparing the vectorized Hamiltonian to the first quantum state... Quantum logic gates act on two Bit registers are used to prepare the second quantum state. The parametric quantum logic gate includes two identical hypothetical circuits. , These are the parameters of the parameterized quantum logic gate. The rest of the circuit is connected to... Figure 2 The SWAP test circuit shown is consistent.

[0039] Specifically, measuring the auxiliary bits in the SWAP test circuit to obtain the value of the loss function includes: The auxiliary bit in the SWAP test circuit is measured to determine the probability of the auxiliary bit in the ground state. The difference between twice the probability of the auxiliary bit in the ground state and 1 is determined as the similarity between the first quantum state and the second quantum state; The product of the square root of the similarity between the first quantum state and the second quantum state and the second norm of the Hamiltonian is determined as the value of the loss function.

[0040] Or as Figure 3 As shown, the auxiliary bit in the SWAP test circuit is measured to determine the auxiliary bit in the ground state. The probability of time ,Will Determined as and The similarity between the first and second quantum states. The square root of the similarity between the first and second quantum states. The second norm of Hamiltonian The product is determined as the loss function. The value of .

[0041] Furthermore, the classical hardware is also used to update the parameters of the SWAP test circuit using gradient descent based on the value of the loss function, and then send the updated SWAP test circuit to the quantum hardware.

[0042] For Hamiltonian Obviously, if and only if hour, VQLS uses parametric simulation circuits. structure ,have ,in These are circuit parameters. Therefore, the goal of VQLS is to continuously train the parameterized circuit until it achieves... Thus we obtain Gradient descent is used to optimize the parameters. Optimize and update the parameters to minimize the loss function. The specific parameter update formula is as follows: , in, For learning rate, For about The gradient of the loss function, This represents the number of training iterations.

[0043] For example, the gradient of the loss function can be calculated based on the parameter drift method and the value of the loss function. Then, the updated parameters are calculated based on the parameter update formula described above. ,Will Replace the SWAP test circuit in the previous training iteration step The updated parameters of the SWAP test circuit are obtained and sent to the quantum hardware. As mentioned in the discussion of continuous training and iteration... The value will approach 0, and then the optimized proposed parameters can be obtained, denoted as... ,Will The prepared quantum state is converted into classical data to determine the unknowns to be solved. .

[0044] This application provides a system for calculating the loss function in a quantum linear system, comprising classical hardware and quantum hardware connected by communication. The classical hardware is used to vectorize the Hamiltonian of the quantum linear system, construct a SWAP test circuit for calculating the loss function based on the vectorized Hamiltonian, and send the SWAP test circuit to the quantum hardware. The quantum hardware is used to run the SWAP test circuit. The classical hardware is used to measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function. It can be seen that in this embodiment, by mapping the matrix-vector multiplication in the loss function to the inner product of vectors, the need for explicit matrix operations is eliminated. The quantum computation of the loss function is achieved using the SWAP test circuit, so that each loss function evaluation only requires the execution of the quantum circuit once, reducing the execution complexity of the quantum circuit and thus reducing the consumption of quantum hardware resources.

[0045] Please refer to Figure 4 This illustration shows a flowchart of a method for calculating a loss function in a quantum linear system according to an embodiment of this application. The method can be applied to... Figure 1 Quantum systems in the universe. This method may include the following steps: Step 401: Vectorize the Hamiltonian of the quantum linear system, and construct a SWAP test circuit for calculating the loss function of the quantum linear system based on the vectorized Hamiltonian.

[0046] Step 402: Run the SWAP test circuit.

[0047] Step 403: Measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function.

[0048] Figure 5 A schematic diagram of a device for calculating the loss function in a quantum linear system, according to an embodiment of this application, is shown. The device includes: Classical computing unit 501 is used to vectorize the Hamiltonian of the quantum linear system and construct a SWAP test circuit for calculating the loss function of the quantum linear system based on the vectorized Hamiltonian. Quantum computing unit 502 is used to run the SWAP test circuit; The classical computing unit 501 is also used to measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function.

[0049] It should be noted that the specific implementation methods of the method-side and device-side embodiments can be found in the system-side embodiments, and will not be repeated here.

[0050] In one specific embodiment provided in this application, the above-described system-side, method-side, and device-side embodiments can be applied to electromagnetic transient simulation to determine the instantaneous voltages across circuit components. In electromagnetic transient simulation, the circuit's balance equations can be used... It means that, among them, Represents all equivalent admittances The admittance matrix formed by superposition, , Represents all historical current sources The current vector formed by superposition, , Indicates that both ends of the component are Instantaneous voltage at time t, For different components, , Different values. Resistor. middle, , ;inductance middle, , ;capacitance middle, , ,in, For time step, , By order Through continuous training and iteration, the instantaneous voltage across the circuit components is determined.

[0051] Figure 6 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system for calculating the loss function in a quantum linear system as described in any of the above embodiments.

[0052] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system for calculating the loss function in a quantum linear system as described in any of the above embodiments.

[0053] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system for calculating the loss function in a quantum linear system as described in any of the above embodiments.

[0054] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0055] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0056] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0057] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0058] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0059] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0060] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0061] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0062] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0063] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0064] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0065] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0066] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A system for calculating the loss function in a quantum linear system, comprising classical hardware and quantum hardware with communication connections, characterized in that, in: Classical hardware is used to vectorize the Hamiltonian of the quantum linear system, construct a SWAP test circuit based on the vectorized Hamiltonian for calculating the loss function in the quantum linear system, and send the SWAP test circuit to the quantum hardware. Quantum hardware for running the SWAP test circuit; Classical hardware is used to measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function.

2. The system according to claim 1, characterized in that, in: Classical hardware is used to update the parameters of the SWAP test circuit using gradient descent based on the value of the loss function, and then sends the updated SWAP test circuit to the quantum hardware.

3. The system according to claim 1 or 2, characterized in that, The SWAP test circuit includes a quantum logic gate for preparing the vectorized Hamiltonian to a first quantum state and a parametric quantum logic gate for preparing a second quantum state.

4. The system according to claim 3, characterized in that, The measurement of the auxiliary bits in the SWAP test circuit to obtain the value of the loss function includes: The auxiliary bit in the SWAP test circuit is measured to determine the probability of the auxiliary bit in the ground state. The difference between twice the probability of the auxiliary bit in the ground state and 1 is determined as the similarity between the first quantum state and the second quantum state; The product of the square root of the similarity between the first quantum state and the second quantum state and the second norm of the Hamiltonian is determined as the value of the loss function.

5. The system according to claim 3, characterized in that, The first quantum state is as follows: ， in, It is the first quantum state. For Hamiltonian, For vectorized Hamiltonians, The second norm of the Hamiltonian, The first matrix corresponding to the Hamiltonian Line number Column elements, This represents the number of rows and columns.

6. The system according to claim 5, characterized in that, The quantum linear system is used Indicate, then ,in, The coefficient matrix, The unknown quantity to be solved is... This is the vector on the right side.

7. A method for calculating the loss function in a quantum linear system, characterized in that, The method includes: The Hamiltonian of the quantum linear system is vectorized, and a SWAP test circuit for calculating the loss function in the quantum linear system is constructed based on the vectorized Hamiltonian. Run the SWAP test circuit; The value of the loss function is obtained by measuring the auxiliary bits in the SWAP test circuit.

8. An apparatus for calculating the loss function in a quantum linear system, characterized in that, The device includes: A classical computing unit is used to vectorize the Hamiltonian of the quantum linear system and to construct a SWAP test circuit for calculating the loss function of the quantum linear system based on the vectorized Hamiltonian. A quantum computing unit is used to run the SWAP test circuit. The classical computing unit is also used to measure the auxiliary bits in the SWAP test circuit to obtain the value of the loss function.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claim 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claim 7.

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