Communication method and device based on FPGA
By integrating IGMP and ICMP modules into the FPGA kernel module, multicast communication and PING probing are realized, solving the compatibility issues of rate and maintenance efficiency in the implementation of advanced functions of communication equipment, and improving the integration and maintenance efficiency of communication equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING RUNKE GENERAL TECH
- Filing Date
- 2026-01-04
- Publication Date
- 2026-04-21
AI Technical Summary
Existing communication equipment cannot simultaneously achieve both high communication speeds and high maintenance efficiency, especially in the implementation of advanced Ethernet functions, where hardware integration is low and maintenance efficiency is low.
By integrating IGMP and ICMP modules into the FPGA kernel module, multicast communication and PING probing are implemented in hardware, improving communication speed and maintenance efficiency through the integration of the FPGA kernel module.
It achieves compatibility between high communication speed and high maintenance efficiency, improves the integration of FPGA boards, and enhances the maintenance efficiency of communication equipment.
Smart Images
Figure CN121907736A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of communication technology, and in particular relates to a communication method and device based on FPGA. Background Technology
[0002] Ethernet technology is a flexible, universal, reliable, and highly scalable technology for data transmission between devices. Due to its hierarchical nature, it supports a wide range of application scenarios with different media and different needs, and has been developed and applied extensively over a long period of time.
[0003] With the development of the information age, the amount of data is growing exponentially, leading to a continuous increase in the demand for higher transmission rates and more complex network architectures for Ethernet. This has resulted in advanced functions such as PING (Packet Internet Groper) and multicast, which are implemented based on Ethernet upper-layer protocols. Due to the high algorithmic complexity of these functions, they are usually implemented in software programs at the terminal. However, limited by CPU efficiency and network card specifications, these advanced functions can usually only be implemented in low-speed networks, thus reducing communication speed.
[0004] In addition, the aforementioned advanced functions can also be implemented through hardware in related technologies. Although this method can improve the communication rate, each function usually requires a separate module, resulting in low integration of hardware boards and low maintenance efficiency of communication equipment.
[0005] This shows that communication equipment in related technologies cannot simultaneously achieve both communication speed and maintenance efficiency. Summary of the Invention
[0006] This application provides an FPGA-based communication method and apparatus, which can simultaneously improve the communication speed and maintenance efficiency of communication devices that use FPGA boards for communication.
[0007] In a first aspect, embodiments of this application provide a communication method based on an FPGA, applied in a programmable gate array (FPGA). The FPGA includes at least one FPGA core module, and each FPGA core module deploys multiple communication modules, including an Internet Group Management Protocol (IGMP) module and an Internet Control Message Protocol (ICMP) module. The method includes: responding to a communication command input by a user; determining a target communication type matching the communication command from multiple communication types, wherein the multiple communication types include at least multicast communication implemented by the IGMP module, probe communication implemented by the ICMP module, and unicast communication; determining a target communication module corresponding to the target communication type from the multiple communication modules; converting the format of the communication address of the destination host receiving the data to be transmitted through the target communication module to obtain a target message; and transmitting the data to be transmitted to the destination host corresponding to the target message.
[0008] Secondly, embodiments of this application provide an FPGA-based communication device applied in a programmable gate array (FPGA). The FPGA includes at least one FPGA core module, and each FPGA core module deploys multiple communication modules, including an Internet Group Management Protocol (IGMP) module and an Internet Control Message Protocol (ICMP) module. The device includes: a type determination module, used to determine a target communication type matching the communication command from multiple communication types in response to a user-input communication command, wherein the multiple communication types include at least multicast communication implemented by the IGMP module, probe communication implemented by the ICMP module, and unicast communication; a communication determination module, used to determine a target communication module corresponding to the target communication type from the multiple communication modules; a format conversion module, used to perform format conversion on the communication address of the destination host receiving the data to be transmitted through the target communication module to obtain a target message; and a communication module, used to transmit the data to be transmitted to the destination host corresponding to the target message.
[0009] Thirdly, embodiments of this application provide an electronic device, which includes: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, it implements the FPGA-based communication method as described in the first aspect.
[0010] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the FPGA-based communication method as described in the first aspect.
[0011] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform the FPGA-based communication method as described in the first aspect.
[0012] As described above, in this embodiment, an FPGA kernel module is set on the FPGA chip, and each FPGA kernel module is equipped with an IGMP module for multicast communication and an ICMP module for PING probing. This hardware-based implementation of multicast and probing communication (i.e., PING-based network probing) improves the communication rate of multicast and probing communication. Furthermore, in this embodiment, the IGMP and ICMP modules are integrated into the FPGA kernel module, meaning that multicast and probing communication can be implemented through the FPGA kernel module. This increases the integration level of the FPGA board, thereby improving the integration level of the communication equipment using the FPGA board and ultimately enhancing the maintenance efficiency of the communication equipment.
[0013] Therefore, it can be seen that the solution provided by the embodiments of this application can simultaneously achieve both communication speed and maintenance efficiency. Attached Figure Description
[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 This is a schematic diagram of communication between an FPGA and a switch provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of an FPGA kernel module provided in one embodiment of this application; Figure 3 This is a flowchart illustrating an embodiment of the FPGA-based communication method provided in this application. Figure 4 This is a schematic diagram of the structure of an FPGA-based communication device provided in another embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation
[0016] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.
[0017] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.
[0018] As described in the background section of this application, in related technologies, the algorithms for advanced functions such as PING and multicast, which are based on Ethernet upper-layer protocols, are highly complex and are usually implemented in software programs at the terminal. However, due to limitations in CPU efficiency and network card specifications, PING and multicast can usually only be implemented in networks with low speeds. Therefore, users urgently need a high-speed, highly integrated, and user-friendly Ethernet transmission solution.
[0019] To address the aforementioned issues, this application provides an FPGA-based communication method and apparatus. Specifically, this application implements a multi-channel, multi-functional UDP protocol stack design supporting 10 Gigabit Ethernet links on an FPGA using Verilog HDL. Through programmable hardware, it endows high-speed networks with advanced functions such as dynamic multicast configuration, multicast transmission, and PING response, significantly improving network speed, efficiency, and maintainability. Furthermore, the solution is economical, simple to manufacture, and highly flexible and scalable, making it extremely valuable as a high-speed network terminal or auxiliary acceleration hardware.
[0020] The method provided in this application embodiment can be applied to FPGA (Field Programmable Gate Array). The FPGA includes at least one FPGA core module, and each FPGA core module is equipped with multiple communication modules, including IGMP (Internet Group Management Protocol) module and ICMP (Internet Control Message Protocol) module.
[0021] As an example, Figure 1 A schematic diagram of the communication between the FPGA and the switch is shown. Figure 1 As can be seen, in this embodiment of the application, a UDP (User Datagram Protocol) data generation module, a data transmission module, an FPGA kernel module, and a data forwarding module are deployed in the FPGA.
[0022] The UDP data generation module generates the data payload for UDP packets. After starting, it automatically sends UDP data to the data transmission module. For example, in... Figure 1 In this embodiment, after the UDP data generation module starts, its data sending interface tx is enabled. At this time, the UDP data generation module can transmit UDP data to the data transmission module through this interface. It should be noted that in this embodiment, the UDP data can be data directly input by the user, or data obtained after processing the user-input data.
[0023] The data transmission module processes the UDP data transmitted by the UDP data generation module, performing actions such as data fragmentation, buffering, and format conversion. Figure 1 In this embodiment, three data transmission modules (trans_64x) are deployed in the FPGA, each connected to an FPGA kernel module. Each data transmission module performs the same processing on the data transmitted by the UDP data generation module and transmits the processed UDP data to the corresponding FPGA kernel module through its output interface. For example, in... Figure 1 In this design, three FPGA core modules, namely netcore1, netcore2, and netcore3, are deployed on the FPGA and interface with three data transmission modules, respectively. The interfaces of the three data transmission modules are u1_tx, u2_tx, and u3_tx, respectively, and these three interfaces are connected to the data receiving ports of the three FPGA core modules.
[0024] In this embodiment, the multiple FPGA kernel modules deployed on the FPGA are independent yet functionally identical modules, capable of bidirectional conversion between user data and MAC (Media Access Control Address) layer data frames. In this embodiment, the FPGA kernel modules internally implement UDP, IP, IGMP, ICMP, and ARP (Address Resolution Protocol), and provide external interfaces to support corresponding configurations. Figure 1 In the middle, the external interface module on the left can receive user-configured IGMP, IP, and MAC information via virtual input / output interfaces (VIO) and / or DSP (Digital Signal Processing) interfaces. As an example, Figure 2 A schematic diagram of the FPGA kernel module is shown, as follows: Figure 2 As shown, unlike the prior art, in this embodiment of the application, the FPGA core module integrates an IGMP module that implements the IGMP protocol, an ICMP module that implements the ICMP protocol, an IP module that implements the IP protocol, and a UDP module that implements the UDP protocol.
[0025] Additionally, the FPGA kernel module can also receive data sent by the destination host and forward it, for example, in Figure 1 In the output, netcore1, netcore2, and netcore3 respectively output the data rx1_data, rx2_data, and rx3_data sent by the destination host.
[0026] The data forwarding module can forward data from the Ethernet link layer to the physical layer, allowing the switch to forward the data to the corresponding host. Simultaneously, this module can also forward data sent by the host from the physical layer to the Ethernet link layer, where it is processed by the FPGA core module and output. Figure 1 The data in the file are rx1_data, rx2_data, and rx3_data.
[0027] In this embodiment of the application, the data forwarding module (i.e. Figure 1 The bd_10g_pcs_pma_wrapper module in the document instantiates the official XILINX 10G Ethernet PCS / PMA IP, enabling data conversion between link layer data frames and physical layer GT high-speed serial signals, as well as anomaly control.
[0028] It should be noted that, Figure 1 The environment shown is XILINX Vivado 2017.4, using a board equipped with a Virtex-7690T FPGA and an optical module, connected to a 10 Gigabit switch via fiber optic cable, and accessed into a high-speed network. In practical applications, other environments and boards can be used depending on the requirements, which will not be illustrated here.
[0029] The structure of the FPGA in the embodiments of this application has been described above. The following explains how to use the FPGA to implement the communication method provided in the embodiments of this application.
[0030] Figure 3 A schematic flowchart of an FPGA-based communication method according to an embodiment of this application is shown. Figure 3 As shown, the method may include the following steps: Step S301: In response to the communication command input by the user, determine the target communication type that matches the communication command from multiple communication types.
[0031] In step S301, the multiple communication types include at least multicast communication implemented by the IGMP module, probe communication implemented by the ICMP module, and unicast communication.
[0032] As an example, users can... Figure 1 The external interface module on the left is used to input communication commands to instruct the FPGA to perform multicast, unicast, or probe communication. These communication commands contain fields indicating the communication type; parsing these commands determines the communication method used by the user to transmit data.
[0033] It should be noted that in this embodiment, the IGMP module is used to implement the IGMP protocol, which is a protocol in the TCP / IP protocol suite responsible for managing IPv4 multicast members. Key information in the IGMP protocol includes the address of the multicast group, as well as information about the creation / joining / leaving of the multicast group. When a multicast group exists in the network, data can be sent to the group rather than a single address as the receiving target. The network's switching devices will copy and distribute the multicast data to every member within the group. In contrast, if unicast is used to achieve one-to-many transmission, it can only be achieved by the sending end repeatedly transmitting the data. Therefore, using IGMP multicast can significantly improve the efficiency of data distribution.
[0034] The ICMP module implements the ICMP protocol, which is used to send control messages in TCP (Transmission Control Protocol) / IP (Internet Protocol) networks. It provides feedback on various problems that may occur in the communication environment, allowing network administrators to diagnose these issues. The PING (Packet Internet Groper) command is a common application of the ICMP protocol, consisting of ICMP request and response packets of a specific format, and is often used to determine network connectivity.
[0035] Step S302: Determine the target communication module corresponding to the target communication type from multiple communication modules.
[0036] It should be noted that, in the embodiments of this application, the multiple communication modules include an IGMP module, an ICMP module, and may also include a unicast module that implements unicast functionality. The unicast module may be located in the FPGA kernel module or outside the FPGA kernel module.
[0037] After determining the target communication type through step S301, the target communication module can be determined from multiple communication modules. For example, if the target communication type is multicast communication, then the target communication module is a multicast module; or if the target communication type is unicast communication, then the target communication module is a unicast module.
[0038] Step S303: The target communication module converts the communication address of the destination host receiving the data to be transmitted into a format to obtain the target message.
[0039] It should be noted that different communication types require different formats for the communication address of the destination host receiving the data to be transmitted. For example, in multicast communication, the destination host's communication address is in IGMP format, and the corresponding target message is an IGMP message; while in probe communication, the destination host's communication address is in ICMP format, and the corresponding target message is an ICMP message. Therefore, to ensure that the data to be transmitted can be transmitted to the destination host under different communication types, the communication address of the destination host needs to be formatted by the target communication module corresponding to the target communication type. The process of formatting the communication address is essentially the process of generating the target message.
[0040] Furthermore, it should be noted that in step S303, the data to be transmitted can be probe data used to probe the communication connection, or it can be UDP data. The data to be transmitted can be... Figure 1 It is obtained from the UDP data generation module.
[0041] Step S304: Transmit the data to be transmitted to the destination host corresponding to the target message.
[0042] As an example, after the target message is determined, the data to be transmitted can be encapsulated into a message and forwarded to the link layer, and then forwarded to the external module (e.g., the destination host) corresponding to the target message.
[0043] Based on the scheme defined in steps S301 to S304 above, it can be understood that in this embodiment, the FPGA is used as a network device to realize data transmission. An FPGA kernel module is set on the FPGA chip, and each FPGA kernel module deploys an IGMP module for multicast communication and an ICMP module for PING probing, thereby implementing multicast communication and probing communication (i.e., PING-based network probing) in hardware, thus improving the communication rate of multicast and probing communication. Furthermore, in this embodiment, the IGMP module and ICMP module are integrated into the FPGA kernel module, meaning that multicast communication and probing communication can be realized through the FPGA kernel module, improving the integration of the FPGA board, thereby improving the integration of the communication device using the FPGA board, and ultimately improving the maintenance efficiency of the communication device.
[0044] Therefore, it can be seen that the solution provided by the embodiments of this application can simultaneously achieve both communication speed and maintenance efficiency.
[0045] The following combination Figure 2 The steps of the method provided in the embodiments of this application will be explained in detail.
[0046] When the target communication module is an IGMP module, i.e., in a scenario where the user wants to perform multicast communication, the IGMP module is first put into an active state and the multicast address input by the user is obtained. Then, the IGMP module constructs an IGMP message containing the multicast address. After obtaining the IGMP message, the FPGA transmits the data to be transmitted to the multicast group corresponding to the IGMP message, so that the destination host located in the multicast group can obtain the data to be transmitted.
[0047] In the above embodiments, the multicast address includes the communication address of the destination host. As can be seen from the above embodiments, the solution provided in this application can implement multicast communication via FPGA. Compared with related technologies that implement multicast communication using software programs, the method provided in this application is not limited by CPU efficiency, network card rules, etc., thereby improving network transmission speed to a certain extent. Furthermore, in this application embodiment, the IGMP module enables dynamic configuration of multicast groups within the network, thereby supporting one-to-many simultaneous multicast transmission. Compared with unicast, this reduces the overhead of repetitive data transmission and improves network transmission efficiency.
[0048] As an example, the meaning of each field in the IGMP protocol corresponding to the IGMP module is shown in Figure 1: Table 1
[0049] As shown in Table 1, the input to the IGMP module is the user's command to join or leave the multicast group. For example, if the input signal to the IGMP module is a rising edge signal, it indicates that the user is transmitting data in multicast format. Additionally, the IGMP module can convert the multicast address corresponding to the multicast group into IGMP format.
[0050] It should be noted that, in the embodiments of this application, the UDP, IP and ARP protocols in the FPGA are implemented based on existing mature modules, and the IGMP and ICMP protocols are implemented through the IGMP module and ICMP module respectively. Multiple communication modules can be combined and nested to form a multifunctional FPGA core module, which can be used as a unicast / multicast sender / receiver and can respond to PING messages.
[0051] As an example, Table 2 shows the input / output ports that users need to be aware of and pay attention to in the FPGA core module: Table 2
[0052] After identifying the IGMP message, the FPGA can transmit the data to be transmitted to the destination host of the multicast group corresponding to the IGMP message.
[0053] Specifically, the multicast command input by the user to the IGMP module is first obtained. If the multicast command is a group join command, a multicast group corresponding to the communication address is constructed, and a group join message for joining the multicast group is constructed through the IGMP module. For example, if the igmp_report signal of the IGMP module is valid, it is determined that the multicast command is a group join command. At this time, the FPGA transmits the data to be transmitted to the multicast group via multicast.
[0054] When the multicast command is a group leave command, a group leave message is generated to prevent the data to be transmitted from being transmitted to the multicast group in a multicast manner. For example, if the igmp_leave signal of the IGMP module is valid, the multicast command is determined to be a group leave command, and the FPGA will no longer transmit data to the multicast group via multicast.
[0055] When the igmp_report or igmp_leave signal is active, the IGMP module uses the data from the input igmp_group signal as the address of the multicast group and outputs it via the m_igmp_group signal. Simultaneously, it generates the corresponding IGMP-type field, representing multicast group operations such as joining or leaving the group. The m_igmp_valid and m_igmp_ready signals are used to inform the FPGA kernel module to receive the data and perform subsequent processing.
[0056] It should be noted that, in the embodiments of this application, only one of igmp_report and igmp_leave is valid at the same time.
[0057] like Figure 2 As shown in this embodiment, the FPGA kernel module further includes a User Datagram Protocol (UDP) module for receiving user-inputted data to be transmitted. During the process of sending the data to be transmitted to a multicast group via multicast, the port configuration information corresponding to the multicast group input by the user is first obtained. Then, the validity of the data to be transmitted is checked through the UDP module to obtain the check result. If the check result indicates that the data to be transmitted is valid, the data to be transmitted and the port configuration information are encapsulated through the UDP module to obtain a message to be transmitted. The message to be transmitted is then sent via multicast to the multicast group corresponding to the IGMP message, so that the destination host located in the multicast group receives the message to be transmitted.
[0058] It should be noted that in the above embodiments, the data to be transmitted obtained by the UDP module comes from the data transmission module. Additionally, the port configuration information may include, but is not limited to, IP address, port number, etc., and the port configuration information can be packaged together with the data to be transmitted to obtain the message to be transmitted.
[0059] Furthermore, it should be noted that to ensure valid data transmission, the validity of the data to be transmitted must be checked before encapsulation. For example, the validity of the data to be transmitted can be determined by checking the header corresponding to the data to be transmitted, as shown in the `tx_udp_hdr_valid` field in Table 2. If the data to be transmitted is found to be valid, the UDP module outputs a signal indicating that the data to be transmitted is valid, as shown in `rx_tvalid` in Table 2. Figure 2 The IP selection module in the middle can output the data to be transmitted to the network layer (such as...) Figure 2 The IP module in the link layer forwards the data to the link layer eth_to_gmii, and finally outputs it to the external module through the link layer eth_to_gmii.
[0060] Before the UDP module encapsulates the data to be transmitted and the port configuration information, that is, after the data transmission module obtains the data to be transmitted, it checks whether the data length of the data to be transmitted is greater than the preset data length. If the data length of the data to be transmitted is greater than the preset data length, the data transmission module performs fragmentation processing on the data to be transmitted to obtain multiple data fragments. Then, the multiple data fragments are transmitted to the UDP module in a preset order so that the UDP module encapsulates each data fragment and the port configuration information to obtain the message to be transmitted corresponding to each data fragment.
[0061] It should be noted that when the data to be transmitted is large, in order to ensure the efficiency of data transmission, the data to be transmitted is fragmented and sent to the UDP module in a certain order, so that the UDP module can encapsulate each data fragment into a message, while the unsent data fragments are buffered in the data transmission module.
[0062] In addition, it should be noted that, in order to meet the requirements of subsequent Ethernet modules and links, the data transmission module also performs status detection and traffic statistics.
[0063] In addition, Figure 1 The system is configured with three data transmission modules. The data transmitted by the UDP data generation module to the three data transmission modules can be the same or different.
[0064] When the target communication module is an ICMP module, the ICMP module is controlled to enter an active state and the probe address input by the user to the ICMP module is obtained; an ICMP message containing the probe address is then constructed through the ICMP module. After this, as... Figure 2As shown, ICMP can send probe packets (i.e., PING packets) to the IP selection module, which then determines whether to output probe packets, data packets from the IGMP module, or UDP data from the UDP module based on routing rules (e.g., the priority of different communication methods). Simultaneously, the network layer can also transmit data returned by the destination host to the UDP module, ICMP module, and IGMP module.
[0065] In one embodiment, the multiple communication modules may further include a unicast module. When the target communication module is a unicast module, the unicast module is controlled to enter an active state and the target communication address input by the user to the unicast module is obtained. Then, the data to be transmitted is transmitted to the destination host corresponding to the target communication address.
[0066] It should be noted that the process of implementing unicast communication on an FPGA is similar to the process of implementing multicast communication described above, and will not be described in detail here.
[0067] The above method yields the target communication address, allowing data to be transmitted to the destination host corresponding to that address. Specifically, the subnet mask of the communication address is used to determine the subnet number; then, the MAC address corresponding to the subnet number is determined using the mapping between Internet Protocol (IP) addresses and Media Access Control (MAC) addresses; finally, the data is transmitted to the destination host that matches the MAC address.
[0068] As described above, this application relates to the design of a multi-UDP protocol transceiver terminal that supports dynamic Ethernet multicast and PING response, and can support a transmission rate of 10 Gigabit (10Gbps). This method is implemented using HDL code and runs on an FPGA chip on a board. During high-speed UDP data transmission, it also supports IGMP protocol communication with network switches to achieve dynamic configuration of multicast groups within the network, thereby supporting one-to-many simultaneous multicast transmission. Furthermore, it can implement PING message responses, enabling multicast group configuration and multicast data distribution across multiple terminals and multicast groups. This technology can be applied in various FPGAs / ASICs (Application Specific Integrated Circuits) connected to 10 Gigabit high-speed networks.
[0069] This application also provides an FPGA-based communication device applied in a programmable gate array (FPGA). The FPGA includes at least one FPGA core module, and each FPGA core module deploys multiple communication modules, including an Internet Group Management Protocol (IGMP) module and an Internet Control Message Protocol (ICMP) module. Figure 4 As shown, the device 400 includes: a type determination module 401, a communication determination module 402, a format conversion module 403, and a communication module 404.
[0070] The type determination module 401 is used to determine the target communication type that matches the communication command from multiple communication types in response to the communication command input by the user. The multiple communication types include at least multicast communication implemented by the IGMP module, probe communication implemented by the ICMP module, and unicast communication. The communication determination module 402 is used to determine the target communication module corresponding to the target communication type from multiple communication modules; The format conversion module 403 is used to convert the communication address of the destination host receiving the data to be transmitted through the target communication module to obtain the target message; The communication module 404 is used to transmit the data to be transmitted to the destination host corresponding to the target message.
[0071] In one example, the target message includes an IGMP message. Specifically, the format conversion module is used to control the IGMP module to enter an active state when the target communication module is an IGMP module, and to obtain the multicast address input by the user to the IGMP module, wherein the multicast address includes the communication address of the destination host; and to construct an IGMP message containing the multicast address through the IGMP module.
[0072] In one example, the communication module is specifically used to obtain multicast instructions input by the user to the IGMP module; when the multicast instruction is a group join instruction, it constructs a multicast group corresponding to the communication address, and constructs a group join message for joining the multicast group through the IGMP module.
[0073] In one example, the FPGA-based communication device further includes a group leave module for generating a group leave message when the multicast instruction is a group leave instruction, so as to prevent the data to be transmitted from being transmitted to the multicast group in the form of multicast.
[0074] In one example, the FPGA kernel module also includes a User Datagram Protocol (UDP) module for receiving user input data to be transmitted, wherein the communication module includes: an information acquisition module, a message encapsulation module, and a multicast module.
[0075] The information acquisition module is used to acquire the port configuration information corresponding to the multicast group input by the user; it performs validity verification on the data to be transmitted through the UDP module and obtains the verification result; the message encapsulation module is used to encapsulate the data to be transmitted and the port configuration information through the UDP module to obtain the message to be transmitted if the verification result indicates that the data to be transmitted is valid; the multicast module is used to send the message to be transmitted to the multicast group corresponding to the IGMP message in a multicast manner, so that the destination host located in the multicast group can receive the message to be transmitted.
[0076] In one example, the FPGA-based communication device also includes a message encapsulation module, which is specifically used to detect whether the data length of the data to be transmitted is greater than a preset data length; if the data length of the data to be transmitted is greater than the preset data length, the data transmission module performs fragmentation processing on the data to be transmitted to obtain multiple data fragments; the multiple data fragments are transmitted to the UDP module in a preset order so that the UDP module encapsulates each data fragment and port configuration information to obtain the message to be transmitted corresponding to each data fragment.
[0077] In one example, the target message includes an ICMP message. The format conversion module is also used to control the ICMP module to enter an active state when the target communication module is an ICMP module, and to obtain the probe address input by the user to the ICMP module; and to construct an ICMP message containing the probe address through the ICMP module.
[0078] In one example, the multiple communication modules also include a unicast module. The FPGA-based communication device further includes: a unicast communication module, used to control the unicast module to enter an active state and obtain the target communication address input by the user to the unicast module; and to transmit the data to be transmitted to the destination host corresponding to the target communication address.
[0079] In one example, the FPGA-based communication device further includes: a mapping module, used to determine the subnet mask of the target communication address corresponding to the data to be transmitted, and obtain the subnet number corresponding to the target communication address; determine the MAC address corresponding to the subnet number through the mapping relationship between Internet Protocol IP address and Media Access Control MAC address; and transmit the data to be transmitted to the destination host that matches the MAC address.
[0080] The FPGA-based communication device provided in this application embodiment can implement the various processes implemented in the aforementioned method embodiments. To avoid repetition, it will not be described again here.
[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0082] Figure 5 A schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application is shown.
[0083] The electronic device may include a processor 501 and a memory 502 storing computer program instructions.
[0084] Specifically, the processor 501 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.
[0085] Memory 502 may include mass storage for data or instructions. For example, and not limitingly, memory 502 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 502 may include removable or non-removable (or fixed) media. Where appropriate, memory 502 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 502 is non-volatile solid-state memory.
[0086] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods according to one aspect of this disclosure.
[0087] The processor 501 reads and executes computer program instructions stored in the memory 502 to implement any of the FPGA-based communication methods described in the above embodiments.
[0088] In one example, the electronic device may also include a communication interface 503 and a bus 510. For example, Figure 5 As shown, the processor 501, memory 502, and communication interface 503 are connected through bus 510 and complete communication with each other.
[0089] The communication interface 503 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.
[0090] Bus 510 includes hardware, software, or both, that couples components of an electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 510 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.
[0091] Furthermore, in conjunction with the FPGA-based communication methods in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. This computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the FPGA-based communication methods in the above embodiments.
[0092] Furthermore, in conjunction with the FPGA-based communication methods described in the above embodiments, this application can provide a computer program product for implementation. When the instructions in this computer program product are executed by the processor of an electronic device, the electronic device performs any of the FPGA-based communication methods described in the above embodiments.
[0093] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.
[0094] The functional modules shown in the above-described block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.
[0095] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.
[0096] The foregoing flowcharts and / or block diagrams of the FPGA-based communication method and apparatus according to embodiments of the present disclosure have described various aspects of the present disclosure. It should be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by dedicated hardware performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.
[0097] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.
Claims
1. A communication method based on FPGA, characterized in that, The method, applied in a Field-Programmable Gate Array (FPGA), includes at least one FPGA core module, each of which deploys multiple communication modules, including an Internet Group Management Protocol (IGMP) module and an Internet Control Message Protocol (ICMP) module. In response to a communication command input by a user, a target communication type matching the communication command is determined from a plurality of communication types, wherein the plurality of communication types include at least multicast communication implemented by the IGMP module, probe communication implemented by the ICMP module, and unicast communication; Determine the target communication module corresponding to the target communication type from the plurality of communication modules; The target communication module converts the format of the communication address of the destination host receiving the data to be transmitted to obtain the target message. The data to be transmitted is sent to the destination host corresponding to the target message.
2. The method according to claim 1, characterized in that, The target message includes an IGMP message, wherein the target communication module performs format conversion on the communication address of the destination host receiving the data to be transmitted to obtain the target message, which includes: When the target communication module is the IGMP module, the IGMP module is controlled to enter an active state, and the multicast address input by the user to the IGMP module is obtained, wherein the multicast address includes the communication address of the destination host; The IGMP module constructs an IGMP message containing the multicast address.
3. The method according to claim 2, characterized in that, The IGMP module constructs an IGMP message containing the multicast address, including: Obtain multicast commands input by the user into the IGMP module; When the multicast instruction is a group join instruction, a multicast group corresponding to the communication address is constructed, and a group join message for joining the multicast group is constructed through the IGMP module.
4. The method according to claim 3, characterized in that, After obtaining the multicast command input by the user to the IGMP module, the method further includes: If the multicast instruction is a group leave instruction, a group leave message is generated to prevent the data to be transmitted from being transmitted to the multicast group in a multicast manner.
5. The method according to claim 3, characterized in that, The FPGA kernel module further includes a User Datagram Protocol (UDP) module for receiving user-input data to be transmitted, wherein transmitting the data to be transmitted to the destination host corresponding to the target message includes: Obtain the port configuration information corresponding to the multicast group input by the user; The validity of the data to be transmitted is verified using the UDP module, and the verification result is obtained. If the test result indicates that the data to be transmitted is valid, the data to be transmitted and the port configuration information are encapsulated by the UDP module to obtain the message to be transmitted. The message to be transmitted is sent in a multicast manner to the multicast group corresponding to the IGMP message, so that the destination host located in the multicast group can receive the message to be transmitted.
6. The method according to claim 5, characterized in that, The FPGA further includes a data transmission module, wherein, before encapsulating the data to be transmitted and the port configuration information through the UDP module to obtain the message to be transmitted, the method further includes: Detect whether the length of the data to be transmitted is greater than the preset data length; If the length of the data to be transmitted is greater than the preset data length, the data to be transmitted is segmented by the data transmission module to obtain multiple data segments. The multiple data fragments are transmitted to the UDP module in a preset order, so that the UDP module encapsulates each data fragment and the port configuration information to obtain the message to be transmitted corresponding to each data fragment.
7. The method according to claim 1, characterized in that, The target message includes an ICMP message, wherein the target communication module performs format conversion on the communication address of the destination host receiving the data to be transmitted to obtain the target message, which includes: When the target communication module is the ICMP module, the ICMP module is controlled to enter an active state, and the probe address input by the user to the ICMP module is obtained; The ICMP module constructs an ICMP message containing the probe address.
8. The method according to claim 1, characterized in that, The plurality of communication modules further includes a unicast module, and when the target communication module is the unicast module, the method further includes: The unicast module is controlled to enter an active state, and the target communication address input by the user to the unicast module is obtained; The data to be transmitted is sent to the destination host corresponding to the target communication address.
9. The method according to any one of claims 1 to 8, characterized in that, After converting the format of the communication address of the destination host receiving the data to be transmitted through the target communication module to obtain the target message, the method further includes: The subnet number mask is determined by analyzing the communication address to obtain the subnet number corresponding to the communication address; The MAC address corresponding to the sub-network number is determined by the mapping relationship between Internet Protocol (IP) addresses and Media Access Control (MAC) addresses. The data to be transmitted is sent to the destination host that matches the MAC address.
10. A communication device based on FPGA, characterized in that, The device is applied in a programmable gate array (FPGA), wherein the FPGA includes at least one FPGA core module, and each FPGA core module deploys multiple communication modules, the multiple communication modules including an Internet Group Management Protocol (IGMP) module and an Internet Control Message Protocol (ICMP) module, the device comprising: A type determination module is used to determine a target communication type that matches a communication command from a plurality of communication types in response to a communication command input by a user. The plurality of communication types include at least multicast communication implemented by the IGMP module, probe communication implemented by the ICMP module, and unicast communication. A communication determination module is used to determine, from the plurality of communication modules, a target communication module corresponding to the target communication type; The format conversion module is used to convert the communication address of the destination host receiving the data to be transmitted through the target communication module to obtain the target message; A communication module is used to transmit the data to be transmitted to the destination host corresponding to the target message.