Pixel structure, manufacturing method thereof and display device

Abstract

The invention provides a pixel structure, a manufacturing method thereof and a display device, a plurality of pixels used for LED display are arranged, and the pixels comprise a first sub-pixel, a second sub-pixel and a third sub-pixel which can emit light of three different colors and are separated from one another; the second sub-pixel is located on the right side of the first sub-pixel along the first direction line; the third sub-pixel is located below the first sub-pixel along a second direction line, and the first direction line intersects with the second direction line; or, the two first sub-pixels are located on the third direction line and symmetrically distributed on the two sides of the intersection point, the two second sub-pixels are located on the fourth direction line and symmetrically distributed on the two sides of the intersection point, and the two third sub-pixels are located on the fifth direction line and symmetrically distributed on the two sides of the intersection point; the third direction line, the fourth direction line and the fifth direction line intersect at the same point to obtain an intersection point; wherein the current pixel and the adjacent pixel share part of the sub-pixels, and specifically, the pixel density is remarkably improved by sharing part of the sub-pixels.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronics technology, and specifically relates to a pixel structure, its manufacturing method, and a display device. Background Technology

[0002] As the core of next-generation display technology, Micro / Mini LED has become a focus of attention in academia and industry, alongside the rapid maturation of artificial intelligence and image recognition technologies, and the rapid development of augmented reality (AR), virtual reality (VR) technologies, and other new display technologies. One of the core challenges of Micro / Mini LED lies in full-color technology, which has become a key requirement. There are two main solutions for full-color Micro / Mini LED: mass transfer of RGB three-primary-color Micro / Mini LED chips and blue Micro / Mini LED combined with color conversion technology.

[0003] The RGB three-primary-color transfer scheme requires the precise transfer of thousands or even millions of individual tiny Micro / Mini LED chips onto a circuit board to achieve full-color display for a single pixel. However, this process not only demands extremely high manufacturing precision, but the tiny size of the chips makes loss rate and cost control during the transfer process exceptionally difficult, posing significant technical challenges for mass production.

[0004] In Micro / Mini LED full-color solutions, epitaxial stacking or chip stacking can avoid or reduce the difficulty of mass transfer. In the epitaxial stacking technology route, the tunnel junction epitaxial three-color stacking scheme can overlap the emitting areas of the three colors to achieve higher pixel density integration. However, this scheme suffers from the problem of difficulty in activating deeply buried P-type GaN. Therefore, another approach is to use non-tunnel junction three-color stacked epitaxy, where the three colors are arranged in a flat pattern. This occupies a larger area and makes it difficult to achieve higher pixel density integration. Summary of the Invention

[0005] Based on this, the present invention provides a pixel structure and its manufacturing method, as well as a display device, which aims to improve the pixel density of the non-tunnel nodal epitaxial three-color stacking scheme.

[0006] A first aspect of the present invention provides a pixel structure, the pixel structure comprising: Multiple pixels for LED display, each pixel comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel that are capable of emitting three different colors of light and are separated from each other; The second sub-pixel is located to the right of the first sub-pixel along the first direction line; the third sub-pixel is located below the first sub-pixel along the second direction line, and the first direction line intersects the second direction line; or, Two first sub-pixels are located on a third direction line and symmetrically distributed on both sides of the intersection point; two second sub-pixels are located on a fourth direction line and symmetrically distributed on both sides of the intersection point; two third sub-pixels are located on a fifth direction line and symmetrically distributed on both sides of the intersection point; the third direction line, the fourth direction line, and the fifth direction line intersect at the same point, which is the intersection point. In this context, the current pixel shares some sub-pixels with its neighboring pixels.

[0007] Furthermore, the pixel is the smallest unit capable of forming a repeating periodic arrangement.

[0008] Furthermore, the angle between the first direction line and the second direction line is 70°~110°.

[0009] Furthermore, the ratio of the total luminous area of ​​the first sub-pixel to the total luminous area of ​​the third sub-pixel is 1.5 to 7, and the ratio of the total luminous area of ​​the second sub-pixel to the total luminous area of ​​the third sub-pixel is 0.5 to 1.5.

[0010] Furthermore, by rotating or symmetrically manipulating the pixels, a new sub-pixel arrangement can be obtained.

[0011] A second aspect of this invention provides a method for preparing a pixel structure, used to prepare the pixel structure described in the first aspect, the method comprising: A three-in-one epitaxial wafer is provided, consisting of a first light-emitting layer, a second light-emitting layer, a third light-emitting layer, and a substrate, from top to bottom; The three-in-one epitaxial wafer was etched using an inductively coupled plasma etching machine to expose part of the surface of the second and third light-emitting layers. Etching is used to form the first sub-pixel by forming the first light-emitting layer, the second light-emitting layer by forming the second sub-pixel, and the third light-emitting layer by forming the third sub-pixel; Electrons are fabricated on each sub-pixel using electron beam evaporation; The substrate is thinned by using a laser dicing machine to cut the substrate between different sub-pixels.

[0012] A third aspect of the present invention provides a driving substrate, including the pixel structure as described in the first aspect, wherein the pixel grid is arranged on the driving substrate.

[0013] Furthermore, grid arrangement refers to the distribution of elements in the vertical and horizontal directions according to a preset spacing rule, with the angle between the vertical and horizontal directions being 90°.

[0014] A fourth aspect of the present invention provides a display device including a driving substrate as described in the third aspect.

[0015] This invention provides a pixel structure, its manufacturing method, and a display device. By setting multiple pixels for LED display, each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit three different colors of light and are separated from each other. The second sub-pixel is located to the right of the first sub-pixel along a first direction line; the third sub-pixel is located below the first sub-pixel along a second direction line, where the first and second direction lines intersect. Alternatively, two first sub-pixels are located on a third direction line and symmetrically distributed on both sides of the intersection point; two second sub-pixels are located on a fourth direction line and symmetrically distributed on both sides of the intersection point; two third sub-pixels are located on a fifth direction line and symmetrically distributed on both sides of the intersection point. The third, fourth, and fifth direction lines intersect at the same point. Specifically, the current pixel shares some sub-pixels with adjacent pixels. By designing the pixel arrangement prepared by non-tunnel nodal epitaxial three-color stacking, the smallest unit forming the periodic arrangement shares some pixels with adjacent units, thereby increasing the pixel density of the display screen in the horizontal and vertical directions. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a single pixel; Figure 2 A schematic diagram of a periodically arranged pixel array; Figure 3 This is a schematic diagram of the structure of another single pixel; Figure 4 This is a schematic diagram of another periodically arranged pixel array; Figure 5 This is a schematic diagram of the structure of a three-in-one epitaxial wafer; Figure 6 This is a schematic diagram of the structure of the three-in-one epitaxial wafer after etching. Detailed Implementation

[0017] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0018] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0020] Example 1 Embodiment 1 of the present invention provides a pixel structure, please refer to... Figure 1 The diagram shows the structure of a single pixel. L1 refers to the first direction line and L2 refers to the second direction line. This pixel includes a first sub-pixel 201, a second sub-pixel 202, and a third sub-pixel 203 that emit three different colors of light and are separated from each other. The first sub-pixel 201, the second sub-pixel 202, and the third sub-pixel 203 can be composed of x LEDs, where x ranges from 1 to 10. The second sub-pixel 202 is located to the right of the first sub-pixel 201 along the first direction line L1. The third sub-pixel 203 is located below the first sub-pixel 201 along the second direction line L2. The first direction line L1 intersects the second direction line L2.

[0021] It should be noted that the angle between the first direction line L1 and the second direction line L2 is 70°~110°. For example, the angle between the first direction line L1 and the second direction line L2 is 70°, 80°, 90°, 100° or 110°, etc., but it is not limited to this. In the embodiment of the present invention, the angle between the first direction line L1 and the second direction line L2 is 90°.

[0022] Specifically, the ratio of the total luminous area of ​​the first sub-pixel to the total luminous area of ​​the third sub-pixel is 1.5 to 7, and the ratio of the total luminous area of ​​the second sub-pixel to the total luminous area of ​​the third sub-pixel is 0.5 to 1.5. It should be noted that for small-sized (<300μm) LEDs, pixels of different wavelengths have different luminous efficiencies, requiring the design of different luminous areas to balance the light intensity.

[0023] More specifically, a first sub-pixel 201 with a length of 90μm and a width of 90μm is located along the first direction line L1, and a second sub-pixel 202 with a length of 30μm and a width of 90μm is located 30μm to the right of the first sub-pixel 201. A third sub-pixel 203 with a length of 30μm and a width of 90μm is located along the second direction line L2, and a third sub-pixel 203 with a length of 30μm and a width of 90μm is located 30μm below the first sub-pixel 201.

[0024] Please see Figure 2 This is a schematic diagram of a periodically arranged pixel array. It can be understood that... Figure 1 The pixels shown are transferred to the driving substrate. During this transfer process, the pixels are mirror-aligned (because the electrodes are plated on the surface, the pixels need to be flipped and bonded to the driving substrate), resulting in... Figure 2 The smallest unit shown can form a repeating periodic arrangement, that is, the smallest unit is arranged into a 4×4 array. There is one pixel in box a1, one pixel in box b1, and one pixel in box c1. Then, it can be concluded that there are 7 pixels in the horizontal direction and 7 pixels in the vertical direction. The original 4×4 pixels (existing technology) form a 7×7 pixel array by sharing pixels. That is, by sharing sub-pixels, the original M×N real pixels can be transformed into (2M-1)×(2N-1) virtual pixels.

[0025] Example 2 Embodiment 2 of the present invention provides a pixel structure, please refer to... Figure 3 The diagram shows the structure of another single pixel, where S1 refers to the third direction line, S2 refers to the fourth direction line, and S3 refers to the fifth direction line. This pixel contains a first sub-pixel 201, a second sub-pixel 202, and a third sub-pixel 203 that emit three different colors of light and are separated from each other. The first sub-pixel 201, the second sub-pixel 202, and the third sub-pixel 203 can be composed of x LEDs, where x ranges from 1 to 10. Two first sub-pixels 201 are located on the third direction line S1 and are symmetrically distributed on both sides of the intersection point A. Two second sub-pixels 202 are located on the fourth direction line S2 and are symmetrically distributed on both sides of the intersection point A. Two third sub-pixels 203 are located on the fifth direction line S3 and are symmetrically distributed on both sides of the intersection point A. The third direction line S1, the fourth direction line S2, and the fifth direction line S3 intersect at the same point, which is the intersection point A.

[0026] Specifically, the ratio of the total luminous area of ​​the first sub-pixel to the total luminous area of ​​the third sub-pixel is 1.5 to 7, and the ratio of the total luminous area of ​​the second sub-pixel to the total luminous area of ​​the third sub-pixel is 0.5 to 1.5. It should be noted that for small-sized (<300μm) LEDs, pixels of different wavelengths have different luminous efficiencies, requiring the design of different luminous areas to balance the light intensity.

[0027] More specifically, two first sub-pixels 201, each 90μm long and 90μm wide, are located on the first direction line S1 and symmetrically distributed on both sides of the intersection point A. Two second sub-pixels 202, each 30μm long and 90μm wide, are located on the second direction line S2 and symmetrically distributed on both sides of the intersection point A. Two third sub-pixels 203, each 30μm long and 90μm wide, are located on the third direction line S3 and symmetrically distributed on both sides of the intersection point A.

[0028] Please see Figure 4 This is a schematic diagram of another periodically arranged pixel array. It can be understood that... Figure 3 The pixels shown are transferred to the driving substrate to obtain Figure 4 The smallest unit shown can form a repeating periodic arrangement, that is, the smallest unit is arranged into a 4×4 array. There are 0.5 pixels in box a2, 0.5 pixels in box b2, 0.5 pixels in box c2, and 0.5 pixels in box d2. Then, we can conclude that there are 7×0.5 pixels in the first horizontal row and 8×0.5 pixels in the first horizontal gap row. The original 4×4 pixels (existing technology) form a (7×8+8×7)×0.5 pixel array by sharing sub-pixels. That is, by sharing sub-pixels, the original M×N real pixels can be transformed into M(2N-1)+(2M-1)N virtual pixels.

[0029] Example 3 Embodiment 3 of the present invention provides a method for preparing a pixel structure, used to prepare the pixel structure in Embodiment 1 of the present invention, including steps S01 to S05, specifically: Step S01: Provide a three-in-one epitaxial wafer, which consists of a first light-emitting layer, a second light-emitting layer, a third light-emitting layer, and a substrate, from top to bottom.

[0030] Please see Figure 5 This is a schematic diagram of the structure of a three-in-one epitaxial wafer, wherein the substrate is a sapphire substrate 104, and the third light-emitting layer 103, the second light-emitting layer 102 and the first light-emitting layer 101 are sequentially deposited on the sapphire substrate 104.

[0031] Step S02: Use an inductively coupled plasma etching machine to etch the three-in-one epitaxial wafer, exposing part of the surface of the second and third light-emitting layers.

[0032] Please see Figure 6 This is a schematic diagram of the structure of the three-in-one epitaxial wafer after etching.

[0033] Step S03: Etching is performed to form a first sub-pixel from a first light-emitting layer, a second sub-pixel from a second light-emitting layer, and a third sub-pixel from a third light-emitting layer.

[0034] Please see Figure 1Specifically, a first sub-pixel 201 with a length of 90μm and a width of 90μm is located along the first direction line L1. A second sub-pixel 202 with a length of 30μm and a width of 90μm is located 30μm to the right of the first sub-pixel 201. A third sub-pixel 203 with a length of 30μm and a width of 90μm is located 30μm below the first sub-pixel 201 along the second direction line L2. The angle between the first direction line L1 and the second direction line L2 is 90°.

[0035] Step S04: Electrodes are fabricated on each sub-pixel using electron beam evaporation.

[0036] Step S05: Thin the substrate by using a laser dicing machine to cut the substrate between different sub-pixels.

[0037] The sapphire substrate is thinned to 104 to 150 μm.

[0038] Furthermore, solder paste is applied to the driving substrate, and a die bonder is used to pick up the pixels and attach them to the driving substrate. The process is then completed by annealing at 230°C to solder the solder paste, arranging them into a periodically arranged pixel array, such as... Figure 2 As shown.

[0039] Example 4 Embodiment 4 of the present invention provides a method for preparing a pixel structure, used to prepare the pixel structure in Embodiment 2 of the present invention, including steps S11 to S15, specifically: Step S11: Provide a three-in-one epitaxial wafer, which consists of a first light-emitting layer, a second light-emitting layer, a third light-emitting layer, and a substrate, from top to bottom.

[0040] Please see Figure 5 This is a schematic diagram of the structure of a three-in-one epitaxial wafer, wherein the substrate is a sapphire substrate 104, and the third light-emitting layer 103, the second light-emitting layer 102 and the first light-emitting layer 101 are sequentially deposited on the sapphire substrate.

[0041] Step S12: Use an inductively coupled plasma etching machine to etch the three-in-one epitaxial wafer, exposing part of the surface of the second and third light-emitting layers.

[0042] Please see Figure 6 This is a schematic diagram of the structure of the three-in-one epitaxial wafer after etching.

[0043] Step S13: Etching is performed to form a first sub-pixel from a first light-emitting layer, a second sub-pixel from a second light-emitting layer, and a third sub-pixel from a third light-emitting layer.

[0044] Please see Figure 3Specifically, two first sub-pixels 201, each 90μm long and 90μm wide, are located on the first direction line S1 and symmetrically distributed on both sides of the intersection point A. Two second sub-pixels 202, each 30μm long and 90μm wide, are located on the second direction line S2 and symmetrically distributed on both sides of the intersection point A. Two third sub-pixels 203, each 30μm long and 90μm wide, are located on the third direction line S3 and symmetrically distributed on both sides of the intersection point A.

[0045] Step S14: Electrodes are fabricated on each sub-pixel using electron beam evaporation.

[0046] In this process, an 800 nm thick Au electrode is fabricated on each sub-pixel, and the three-in-one epitaxial layer is bonded to the driving substrate using an Au-Au electrode under conditions of 320℃, 90 Kg pressure for 20 min using a wafer bonding machine.

[0047] Step S15: Thin the substrate by using a laser dicing machine to cut the substrate between different sub-pixels.

[0048] In this process, the sapphire substrate is thinned to 104 to 150 μm, and then the sapphire substrate 104 is peeled off using a laser to form a periodically arranged pixel array, such as... Figure 4 As shown.

[0049] The present invention also provides a driving substrate, the driving substrate including the pixel structure as described above, wherein the pixel grid is arranged on the driving substrate. Specifically, the pixels are fixed on the driving substrate by bonding to form a periodically arranged pixel array. In addition, the grid arrangement refers to the distribution of pixels in the longitudinal and transverse directions according to a preset spacing rule, with the included angle between the longitudinal and transverse directions being 90°.

[0050] The present invention also provides a display device, the display device comprising the driving substrate described above.

[0051] In summary, the pixel structure, manufacturing method, and display device in the embodiments of the present invention, by setting multiple pixels for LED display, each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that can emit three different colors of light and are separated from each other; the second sub-pixel is located to the right of the first sub-pixel along a first direction line; the third sub-pixel is located below the first sub-pixel along a second direction line, and the first direction line intersects the second direction line; or, two first sub-pixels are located on a third direction line and symmetrically distributed on both sides of the intersection point, two second sub-pixels are located on a fourth direction line and symmetrically distributed on both sides of the intersection point, and two third sub-pixels are located on a fifth direction line and symmetrically distributed on both sides of the intersection point, and the third, fourth, and fifth direction lines intersect at the same point to obtain the intersection point; wherein, the current pixel shares some sub-pixels with adjacent pixels. Specifically, by designing the pixel arrangement prepared by non-tunnel nodal epitaxial three-color stacking, the smallest unit forming the periodic arrangement shares some pixels with adjacent units, thereby increasing the pixel density of the display screen in the horizontal and vertical directions.

[0052] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A pixel structure, characterized in that, The pixel structure includes: Multiple pixels for LED display, each pixel comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel that are capable of emitting three different colors of light and are separated from each other; The second sub-pixel is located to the right of the first sub-pixel along the first direction line; the third sub-pixel is located below the first sub-pixel along the second direction line, and the first direction line intersects the second direction line; or, Two first sub-pixels are located on a third direction line and symmetrically distributed on both sides of the intersection point; two second sub-pixels are located on a fourth direction line and symmetrically distributed on both sides of the intersection point; two third sub-pixels are located on a fifth direction line and symmetrically distributed on both sides of the intersection point; the third direction line, the fourth direction line, and the fifth direction line intersect at the same point, which is the intersection point. In this context, the current pixel shares some sub-pixels with its neighboring pixels.

2. The pixel structure according to claim 1, characterized in that, The pixel is the smallest unit capable of forming a repeating periodic arrangement.

3. The pixel structure according to claim 1, characterized in that, The angle between the first direction line and the second direction line is 70°~110°.

4. The pixel structure according to claim 1, characterized in that, The ratio of the total luminous area of ​​the first sub-pixel to the total luminous area of ​​the third sub-pixel is 1.5 to 7, and the ratio of the total luminous area of ​​the second sub-pixel to the total luminous area of ​​the third sub-pixel is 0.5 to 1.

5.

5. The pixel structure according to claim 1, characterized in that, By rotating or symmetrically manipulating the pixels, a new sub-pixel arrangement can be obtained.

6. A method for fabricating a pixel structure, characterized in that, The method for preparing the pixel structure as described in any one of claims 1-5 comprises: A three-in-one epitaxial wafer is provided, consisting of a first light-emitting layer, a second light-emitting layer, a third light-emitting layer, and a substrate, from top to bottom; The three-in-one epitaxial wafer was etched using an inductively coupled plasma etching machine to expose part of the surface of the second and third light-emitting layers. Etching is used to form the first sub-pixel by forming the first light-emitting layer, the second light-emitting layer by forming the second sub-pixel, and the third light-emitting layer by forming the third sub-pixel; Electrons are fabricated on each sub-pixel using electron beam evaporation; The substrate is thinned by using a laser dicing machine to cut the substrate between different sub-pixels.

7. A driving substrate, characterized in that, Includes the pixel structure as described in any one of claims 1-5, wherein the pixel grid is arranged on a driving substrate.

8. The driving substrate according to claim 7, characterized in that, Grid arrangement refers to the arrangement of elements in the vertical and horizontal directions according to a preset spacing rule, with the angle between the vertical and horizontal directions being 90°.

9. A display device, characterized in that, The display device includes the driving substrate as described in any one of claims 7-8.

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