Semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of increasing the effective area of a semiconductor device and reducing the delay of a gate signal. A semiconductor device (100) is provided with: a semiconductor substrate (1) in which an active region (2) and a terminal region (3), which is a region outside the active region, are defined; a first gate pad (4) disposed in the center of the first side of the active region; a first gate wiring (5) connected to the first gate pad and extending in the first direction; a first gate signal line connected to the first gate pad or the first gate wiring and extending in the second direction; a second gate pad (14) disposed at a corner of the first side of the active region; a second gate wiring (15) connected to the second gate pad and having a portion extending in the first direction; and a second gate signal line connected to the second gate pad or the second gate wiring and extending in the second direction. The second gate wiring extends along the boundary between the active region and the termination region.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] For example, in conventional semiconductor devices described in Patent Document 1, a semiconductor substrate is defined with an active region on which a semiconductor element is formed, a gate pad configuration region formed adjacent to the active region, and a terminal region serving as the outer region of both the active region and the gate pad configuration region. A first gate pad is disposed at one end of the gate pad configuration region in a first direction, and a first gate wiring extending in a second direction intersecting the first direction is connected to the first gate pad. Furthermore, a second gate pad is disposed at the other end of the gate pad configuration region in the first direction, and a second gate wiring extending in the second direction is connected to the second gate pad. A first gate signal line extending in the first direction is connected to the first gate wiring, and a second gate signal line extending in the first direction is connected to the second gate wiring.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2010-109545

[0004] However, in conventional semiconductor devices, the gate pad configuration area does not have the first and second gate signal lines, so no output current flows through it, making the gate pad configuration area an ineffective region. Therefore, due to the small effective area of ​​conventional semiconductor devices, there is a problem of increased on-resistance and high conduction losses.

[0005] Furthermore, the first and second gate pads, the first and second gate wirings, and the first and second gate signal lines appear comb-like when viewed from above. The first and second gate signal lines extend from one end to the other in the first direction within the active region, thereby increasing the gate resistance of the first and second gate signal lines. As a result, there is a problem of large delays in the respective gate signals from the first and second gate pads to the ends of the first and second gate signal lines. Summary of the Invention

[0006] Therefore, the purpose of this disclosure is to provide a technique that can increase the effective area of ​​a semiconductor device and reduce the delay of the gate signal.

[0007] The semiconductor device disclosed herein comprises: a semiconductor substrate having an active region on which semiconductor elements are formed and which has a quadrilateral shape when viewed from above, and a terminal region being an outer region of the active region; a first gate pad disposed at the center of a first side of the active region; a first gate wiring connected to the first gate pad and extending along a first direction; a first gate signal line connected to the first gate pad or the first gate wiring and extending along a second direction intersecting the first direction; a second gate pad disposed at a corner of the first side of the active region; a second gate wiring connected to the second gate pad and having a portion extending along the first direction; and a second gate signal line connected to the second gate pad or the second gate wiring and extending along the second direction, the second gate wiring extending along the boundary between the active region and the terminal region.

[0008] According to this disclosure, first and second gate pads are disposed in the active region, and first and second gate signal lines are also disposed between the first and second gate pads. Therefore, output current also flows between the first and second gate pads, thereby making the region between the first and second gate pads an effective region as well. Thus, the effective region of the semiconductor device is expanded.

[0009] Furthermore, since the first gate pad is disposed at the center of the first side of the active region and the second gate pad is disposed at the corner of the first side of the active region, the length of the first and second gate signal lines disposed between the first and second gate pads is shorter than when the first and second gate signal lines extend from one end to the other in the first direction of the active region. As a result, the gate resistance of the first and second gate signal lines is reduced, which can reduce the delay of the respective gate signals from the first and second gate pads to the ends of the first and second gate signal lines. Attached Figure Description

[0010] Figure 1 This is a schematic top view used to illustrate the various regions defined in the semiconductor substrate of the semiconductor device according to Embodiment 1.

[0011] Figure 2 This is a schematic top view of the semiconductor device according to Embodiment 1.

[0012] Figure 3 It is a variation of implementation method 1. Figure 2 The magnified view corresponding to region A.

[0013] Figure 4 yes Figure 2 A magnified view of region B.

[0014] Figure 5 This is a schematic top view of the semiconductor device involved in Embodiment 2.

[0015] Figure 6 yes Figure 5 A magnified view of region C.

[0016] Figure 7 This is a schematic top view of a semiconductor device involved in a variation of Embodiment 2.

[0017] Figure 8 It is a schematic top view of the semiconductor device involved in the related technology.

[0018] Explanation of reference numerals in the attached figures

[0019] 1... Semiconductor substrate; 2... Active region; 3... Termination region; 4... First gate pad; 5... First gate wiring; 6, 7... First gate signal line; 14... Second gate pad; 15... Second gate wiring; 16, 17... Second gate signal line; 27... Dummy gate signal line; 100, 100A... Semiconductor device. Detailed Implementation

[0020] <Implementation Method 1>

[0021] Hereinafter, Embodiment 1 will be described using the accompanying drawings. Figure 1 This is a schematic top view used to illustrate the various regions defined in the semiconductor substrate 1 of the semiconductor device 100 according to Embodiment 1.

[0022] exist Figure 1 In the diagram below, the X, Y, and Z directions are orthogonal to each other. The X, Y, and Z directions shown in the diagram below are also orthogonal to each other. Hereinafter, the direction encompassing the X direction and its opposite direction, the -X direction, will also be referred to as the "X-axis direction." Similarly, the direction encompassing the Y direction and its opposite direction, the -Y direction, will also be referred to as the "Y-axis direction." Finally, the direction encompassing the Z direction and its opposite direction, the -Z direction, will also be referred to as the "Z-axis direction."

[0023] like Figure 1As shown, the semiconductor device 100 includes a semiconductor substrate 1. An active region 2 and a terminal region 3 are defined on the semiconductor substrate 1. The active region 2 is the region where a semiconductor element (not shown) is formed. When viewed from above, the active region 2 is formed in a quadrilateral shape, and its outline includes a side in the -Y direction (corresponding to the first side), a side in the Y direction (corresponding to the second side), a side in the -X direction (corresponding to the third side), and a side in the X direction (corresponding to the fourth side). The terminal region 3 is the region outside the active region 2; in other words, it is the region outside the first, second, third, and fourth sides, and is formed in a frame shape.

[0024] Here, semiconductor devices are IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), etc.

[0025] Next, the details of the semiconductor device 100 will be explained. Figure 2 This is a schematic top view of the semiconductor device 100 according to Embodiment 1. Figure 2 As shown, the semiconductor device 100 also includes a first gate pad 4, a first gate wiring 5, first gate signal lines 6 and 7, a second gate pad 14, a second gate wiring 15, and second gate signal lines 16 and 17.

[0026] The first gate pad 4 is disposed at the center of the edge in the Y direction of the active region 2. The first gate wiring 5 is connected to the first gate pad 4 and extends from the first gate pad 4 along the Y-axis direction (corresponding to the first direction) to the vicinity of the edge in the Y direction of the active region 2. The first gate signal line 6 is connected to the first gate pad 4 and extends along the direction intersecting the Y direction, i.e., the X-axis direction (corresponding to the second direction). The first gate signal line 7 is connected to the first gate wiring 5 and extends along the X-axis direction.

[0027] The second gate pad 14 is disposed at the corner of the edge in the -Y direction of the active region 2. The corner of the edge in the -Y direction of the active region 2 refers to the connection point between the edge in the -Y direction of the active region 2 and the edge in the -X direction or the edge in the X direction. Although in Figure 2In this configuration, the second gate pad 14 is disposed at a corner in the -X direction, but it can also be disposed at a corner in the X direction. The second gate wiring 15 is connected to the second gate pad 14 and has a portion extending along the Y-axis direction, extending along the boundary between the active region 2 and the terminal region 3. In other words, the second gate wiring 15 extends along the edges in the -X direction, Y direction, X direction, and -Y direction of the active region 2. The second gate signal line 16 is connected to the second gate pad 14 and extends along the X-axis direction. The second gate signal line 17 is connected to the second gate wiring 15 and extends along the X-axis direction.

[0028] The first gate pad 4, the first gate wiring 5, the second gate pad 14, and the second gate wiring 15 are all made of polysilicon thin film and metal thin film. According to this structure, the gate resistance connecting the first gate pad 4 and the first gate wiring 5, and the second gate pad 14 and the second gate wiring 15, can be reduced. Alternatively, although not shown, gate resistors can also be integrated between the first gate pad 4 and the first gate wiring 5, and between the second gate pad 14 and the second gate wiring 15.

[0029] The first gate signal line 6 and the second gate signal line 16 are alternately arranged in the Y-axis direction between the first gate pad 4 and the second gate pad 14, and between the first gate pad 4 and the second gate wiring 15. In addition, the first gate signal line 7 and the second gate signal line 17 are alternately arranged in the Y-axis direction between the portion of the second gate wiring 15 extending along the -X direction and the first gate wiring 5.

[0030] Figure 3 It is a variation of implementation method 1. Figure 2 The magnified view corresponding to region A. For example... Figure 3 As shown, a dummy gate signal line 27 may also be configured between the first gate signal line 7 and the second gate signal line 17 between the portion extending along the -X direction in the second gate wiring 15 and the first gate wiring 5. The dummy gate signal line 27 is connected to an emitter electrode (ground potential) not shown.

[0031] Figure 4 yes Figure 2 A magnified view of region B. (See image below.) Figure 4 As shown, the spacing A2 between the first gate pad 4 and the second gate wiring 15 is 10 μm or more. This is to suppress interference between the gate signal flowing in the first gate pad 4 and the gate signal flowing in the second gate wiring 15.

[0032] Next, the function and effect of Implementation Method 1 will be explained by comparing it with the situation of related technologies. Figure 8 This is a schematic top view of the semiconductor device 101 involved in the related technology.

[0033] like Figure 8 As shown, in the semiconductor device 101 according to the related art, an active region 2, a gate pad configuration region 10 formed adjacent to the active region 2, and a terminal region 3 serving as the outer region of the active region 2 and the gate pad configuration region 10 are defined on the semiconductor substrate 1. A first gate pad 4 is disposed at the X-direction end of the gate pad configuration region 10, and a first gate wiring 5 extending along the Y-axis direction is connected to the first gate pad 4. In addition, a second gate pad 14 is disposed at the X-direction end of the gate pad configuration region 10, and a second gate wiring 15 extending along the Y-axis direction is connected to the second gate pad 14. Furthermore, a first gate signal line 7 extending along the X-axis direction is connected to the first gate wiring 5, and a second gate signal line 17 extending along the X-axis direction is connected to the second gate wiring 15.

[0034] Since the first and second gate signal lines 7 and 17 are not configured in the gate pad configuration area 10, no output current flows, and therefore the gate pad configuration area 10 becomes an invalid area. Therefore, there is a problem that the small effective area of ​​the semiconductor device 101 leads to increased on-resistance and high conduction loss.

[0035] In contrast, such as Figure 2 As shown, in Embodiment 1, the semiconductor device 100 includes: a semiconductor substrate 1, defining an active region 2 on which semiconductor elements are formed and which has a quadrilateral shape when viewed from above, and a terminal region 3 serving as the outer region of the active region 2; a first gate pad 4 disposed at the center of the edge of the active region 2 in the Y direction; a first gate wiring 5 connected to the first gate pad 4 and extending along the Y-axis direction; first gate signal lines 6 and 7 connected to the first gate pad 4 or the first gate wiring 5 and extending along the X-axis direction, which intersects the Y-axis direction; a second gate pad 14 disposed at the corner of the edge of the active region 2 in the Y direction; a second gate wiring 15 connected to the second gate pad 14 and having a portion extending along the Y-axis direction; and second gate signal lines 16 and 17 connected to the second gate pad 14 or the second gate wiring 15 and extending along the X-axis direction. The second gate wiring 15 extends along the boundary between the active region 2 and the terminal region 3.

[0036] Therefore, since the first and second gate pads 4 and 14 are arranged in the active region 2, and the first and second gate signal lines 6 and 16 are also arranged between the first gate pad 4 and the second gate pad 14, a cell structure for arranging semiconductor elements can be configured in the region where the first and second gate signal lines 6 and 16 are arranged, thereby allowing output current to flow between the first gate pad 4 and the second gate pad 14. As a result, the region between the first gate pad 4 and the second gate pad 14 also becomes an effective region. Therefore, the effective region of the semiconductor device 100 is expanded. By expanding the effective region of the semiconductor device 100, the on-state voltage of the semiconductor element under the same output current is reduced, thereby reducing conduction losses.

[0037] Next, the effect of reducing gate signal delay will be explained. A trench is formed in the active region 2. In the case of a trench IGBT as the semiconductor element, the first and second gate wirings 5 ​​and 15 are made of polysilicon thin films. Alternatively, the first and second gate wirings 5 ​​and 15 may also be made of a combination of polysilicon thin films and metal thin films.

[0038] On the other hand, the first and second gate signal lines 6, 7, 16, and 17 are composed of a polysilicon thin film buried in the trench. However, when a dummy gate signal line 27 is provided, the dummy gate signal line 27 is also composed of a polysilicon thin film buried in the trench. The polysilicon thin films constituting the first and second gate wirings 5 ​​and 15 and the polysilicon thin films constituting the first and second gate signal lines 6, 7, 16, and 17 are formed by the same polysilicon deposition process and have the same resistivity. The cross-sectional area of ​​the polysilicon thin film constituting the first and second gate wirings 5 ​​and 15 is much larger than that of the polysilicon thin films constituting the first and second gate signal lines 6, 7, 16, and 17, therefore the resistance per unit length of the first and second gate wirings 5 ​​and 15 is small. The cross-sectional area of ​​a typical gate wiring is 10. 2 μm 2 The typical cross-sectional area of ​​a gate signal line is 5μm. 2 Above and 6μm 2 the following.

[0039] Furthermore, when the first and second gate wirings 5 ​​and 15 are composed of polysilicon thin films and metal thin films, the resistance is further reduced. That is, relative to the gate signal delay, the resistance components of the first and second gate signal lines 6, 7, 16, and 17 are more dominant than the resistance components of the first and second gate wirings 5 ​​and 15. Additionally, as... Figure 2As shown, although the second gate wiring 15 has a closed-loop shape, even if the second gate wiring 15 did not have a closed-loop shape, the resistance component of the second gate wiring 15 would be relatively small. Therefore, as mentioned above, the resistance components of the first and second gate signal lines 6, 7, 16, and 17 are dominant. Therefore, when studying the following delays, only the first and second gate signal lines 6, 7, 16, and 17 are approximately considered.

[0040] like Figure 8 As shown, in the semiconductor device 101 according to the related art, the first and second gate pads 4 and 14, the first and second gate wirings 5 ​​and 15, and the first and second gate signal lines 7 and 17 are comb-shaped when viewed from above. The first and second gate signal lines 7 and 17 extend from one end to the other in the X-axis direction of the active region 2, thereby increasing the gate resistance of the first and second gate signal lines 7 and 17. As a result, the delay of the respective gate signal from the first and second gate pads 4 and 14 to the ends of the first and second gate signal lines 7 and 17 is large. That is, this is a delay difference on the same gate signal line. Furthermore, due to this delay on the gate signal line, a gate signal delay difference is also generated between the first gate signal line 7 near the first gate wiring 5 and the second gate signal line 17 near the second gate wiring 15. That is, this is a delay difference between the first gate signal line 7 and the second gate signal line 17.

[0041] In contrast, such as Figure 2 As shown, in the semiconductor device 100 according to Embodiment 1, the first gate pad 4 is disposed at the center of the edge in the -Y direction of the active region 2, and the second gate pad 14 is disposed at the corner of the edge in the -Y direction of the active region 2. Therefore, the lengths of the first and second gate signal lines 6 and 16 disposed between the first gate pad 4 and the second gate pad 14 are shorter than when the first and second gate signal lines 6 and 16 extend from one end to the other in the X-axis direction of the active region 2. As a result, the gate resistance of the first and second gate signal lines 6 and 16 is reduced, and the delay of the respective gate signal from the first and second gate pads 4 and 14 to the ends of the first and second gate signal lines 6 and 16 can be reduced. With this structure, not only the delay difference on the same gate signal line can be reduced, but also the delay difference between the first gate signal line 6 and the second gate signal line 16 can be reduced.

[0042] Furthermore, since the first gate signal lines 6 and 7 and the second gate signal lines 16 and 17 are alternately arranged in the Y-axis direction, the carrier concentration control effect caused by the dual-gate operation can be made uniform.

[0043] Furthermore, when a dummy gate signal line 27 is disposed between the first gate signal line 7 and the second gate signal line 17, the output current of the semiconductor device 100 can be suppressed because no current flows in the region where the dummy gate signal line 27 is disposed.

[0044] In addition, the first gate pad 4, the first gate wiring 5, the second gate pad 14 and the second gate wiring 15 are all made of polysilicon thin film and metal thin film, which can reduce the gate resistance between the first gate pad 4 and the first gate wiring 5 and between the second gate pad 14 and the second gate wiring 15.

[0045] <Implementation Method 2>

[0046] Next, implementation method 2 will be described. Figure 5 This is a schematic top view of the semiconductor device 100A according to Embodiment 2. Furthermore, in Embodiment 2, the same reference numerals are used for the same constituent elements as those described in Embodiment 1, and descriptions are omitted.

[0047] like Figure 5 As shown, in Embodiment 2, the configuration position of the second gate pad 14 and the shape of the first gate wiring 5 are different from those in Embodiment 1.

[0048] The first gate pad 4 is disposed at the center of the edge in the -Y direction of the active region 2. The second gate pad 14 is disposed at the center of the edge in the -Y direction of the active region 2, adjacent to the first gate pad 4. Although in Figure 5 In this configuration, the second gate pad 14 is disposed in the -X direction of the first gate pad 4, but it can also be disposed in the X direction of the first gate pad 4.

[0049] The first gate wiring 5 has: a portion connected to the first gate pad 4 and extending from the first gate pad 4 along the Y-axis direction to near the edge of the active region 2 in the Y direction; and a portion partially surrounding the outer periphery of the second gate pad 14 in the Y direction and the -X direction. The first gate signal line 6 is connected to the first gate pad 4 and extends in a direction intersecting the Y-axis direction, i.e., the X-axis direction. The first gate signal line 7 is connected to the first gate wiring 5 and extends in the X-axis direction.

[0050] The second gate wiring 15 is connected to the second gate pad 14 and has a portion extending along the Y-axis direction, extending along the boundary between the active region 2 and the terminal region 3. In other words, the second gate wiring 15 extends along the edge in the -X direction, the edge in the Y direction, the edge in the X direction, and the edge in the -Y direction of the active region 2. The second gate signal line 17 is connected to the second gate wiring 15 and extends along the X-axis direction. Furthermore, in Embodiment 2, the second gate signal line 16 connected to the second gate pad 14 is not configured.

[0051] Figure 6 yes Figure 5 A magnified view of region C. (See image below.) Figure 6 As shown, the spacing A1 between the first gate pad 4 and the second gate pad 14, the spacing A2 between the first gate pad 4 and the second gate wiring 15, the spacing B1 between the second gate pad 14 and the first gate wiring 5, and the spacing C1 between the first gate wiring 5 and the second gate wiring 15 are all 10 μm or more. This is to suppress interference between the gate signals flowing in each part. Furthermore, although no other spacings are mentioned except for spacing A2 in Embodiment 1, in Embodiment 1, spacings A1, B1, and C1 are also 10 μm or more.

[0052] Next, a variation of Implementation Method 2 will be described. Figure 7 This is a schematic top view of the semiconductor device 100A according to a variation of Embodiment 2.

[0053] like Figure 7 As shown, the first gate wiring 5 branches off from the first gate pad 4 in both the X and -X directions, and then extends in the Y direction. That is, it has a portion branching off from the first gate pad 4 in the X direction and a portion branching off from the first gate pad 4 in the -X direction. The second gate wiring 15 is connected to the second gate pad 14 and extends along the boundary between the active region 2 and the terminal region 3. Furthermore, the second gate wiring 15 has a portion extending in the -Y direction from the edge of the active region 2 between the portion branching off from the first gate pad 4 in the X direction and the portion branching off from the first gate pad 4 in the -X direction.

[0054] Here, in a variation of Embodiment 2, the intervals A1, A2, B1, and C1 are 10 μm or more.

[0055] Next, the function and effects of Embodiment 2 and its variations will be explained. Embodiment 2 and its variations include: a semiconductor substrate 1, defining an active region 2 on which semiconductor elements are formed and which has a quadrilateral shape when viewed from above, and a terminal region 3 serving as the outer region of the active region 2; a first gate pad 4 disposed at the center of the edge of the active region 2 in the -Y direction; a first gate wiring 5 connected to the first gate pad 4 and having a portion extending along the Y-axis direction; first gate signal lines 6 and 7 connected to the first gate pad 4 or the first gate wiring 5 and extending along a direction intersecting the Y-axis direction, i.e., the X-axis direction; a second gate pad 14 disposed at the center of the edge of the active region 2 in the -Y direction, adjacent to the first gate pad 4; a second gate wiring 15 connected to the second gate pad 14 and having a portion extending along the Y-axis direction; and a second gate signal line 17 connected to the second gate wiring 15 and extending along the X-axis direction. The second gate wiring 15 extends along the boundary between the active region 2 and the terminal region 3. A portion of the first gate wiring 5 partially surrounds the outer periphery of the second gate pad 14.

[0056] Therefore, similar to Embodiment 1, the effective area of ​​the semiconductor device 100A is expanded. By expanding the effective area of ​​the semiconductor device 100A, the on-state voltage of the semiconductor element at the same output current is reduced, thereby reducing conduction losses.

[0057] And, as Figure 5 and Figure 7 As shown, in the semiconductor device 100A according to Embodiment 2 and its variations, the first gate pad 4 is disposed at the center of the edge in the -Y direction of the active region 2, and the second gate pad 14 is disposed at the center of the edge in the -Y direction of the active region 2, adjacent to the first gate pad 4. Therefore, the lengths of the first and second gate signal lines 6, 7, 17 disposed between the first and second gate pads 4, 14 and the second gate wiring 15 are shorter than when the first and second gate signal lines 6, 7, 17 extend from one end to the other in the X-axis direction of the active region 2. As a result, the gate resistance of the first and second gate signal lines 6, 7, 17 is reduced, and the delay of the respective gate signal from the first and second gate pads 4, 14 to the ends of the first and second gate signal lines 6, 7, 17 can be reduced. This structure not only reduces the delay difference on the same gate signal lines, but also reduces the delay difference between the first gate signal lines 6 and 7 and the second gate signal line 17.

[0058] Next, the interference suppression effect on the gate signal will be explained. When different gate signals are input to the first gate pad 4 and the second gate pad 14, if the spacing between the first and second gate pads 4 and 14, and the spacing between the first and second gate wirings 5 ​​and 15, are too close, gate signal interference may occur due to the parasitic capacitance of the interlayer film between the first and second gate wirings 5 ​​and 15. When gate signal interference occurs, the semiconductor device may malfunction and be damaged.

[0059] like Figure 6 As shown, in the semiconductor device 100A according to Embodiment 2 and its modifications, the spacing A1 between the first gate pad 4 and the second gate pad 14, the spacing A2 between the first gate pad 4 and the second gate wiring 15, the spacing B1 between the second gate pad 14 and the first gate wiring 5, and the spacing C1 between the first gate wiring 5 and the second gate wiring 15 are all 10 μm or more, thus suppressing interference with the gate signal. Furthermore, since the same structure is also present in Embodiment 1, the same effect is obtained.

[0060] Furthermore, the various implementation methods can be freely combined, or appropriately modified or omitted.

[0061] The various forms disclosed herein will be recorded hereafter as appendices.

[0062] (Note 1) A semiconductor device, wherein,

[0063] The aforementioned semiconductor device includes:

[0064] A semiconductor substrate is defined as having an active region on which semiconductor elements are formed and which has a quadrilateral shape when viewed from above, and a terminal region that is the outer region of the active region.

[0065] The first gate pad is disposed at the center of the first side of the active region;

[0066] The first gate wiring is connected to the first gate pad and extends along the first direction;

[0067] The first gate signal line is connected to the first gate pad or the first gate wiring described above, and extends in the direction that intersects with the first direction, i.e., the second direction.

[0068] The second gate pad is disposed at the corner of the first side of the active region;

[0069] The second gate wiring is connected to the second gate pad and has a portion extending along the first direction; and

[0070] The second gate signal line is connected to the second gate pad or the second gate wiring, and extends along the second direction.

[0071] The second gate wiring extends along the boundary between the active region and the terminal region.

[0072] (Appendix 2) A semiconductor device, wherein,

[0073] The aforementioned semiconductor device includes:

[0074] A semiconductor substrate is defined as having an active region on which semiconductor elements are formed and which has a quadrilateral shape when viewed from above, and a terminal region that is the outer region of the active region.

[0075] The first gate pad is disposed at the center of the first side of the active region;

[0076] The first gate wiring is connected to the first gate pad and has a portion extending along the first direction;

[0077] The first gate signal line is connected to the first gate pad or the first gate wiring described above, and extends in the direction that intersects with the first direction, i.e., the second direction.

[0078] The second gate pad is disposed at the center of the first side of the active region, adjacent to the first gate pad.

[0079] The second gate wiring is connected to the second gate pad and has a portion extending along the first direction; and

[0080] The second gate signal line is connected to the second gate wiring described above and extends along the second direction described above.

[0081] The second gate wiring extends along the boundary between the active region and the termination region.

[0082] A portion of the first gate wiring partially surrounds the outer periphery of the second gate pad.

[0083] (Note 3) The semiconductor device according to Note 1 or 2, wherein,

[0084] The first gate signal line and the second gate signal line are alternately arranged in the first direction.

[0085] (Note 4) The semiconductor device according to Note 3, wherein,

[0086] A dummy gate signal line is provided between the first gate signal line and the second gate signal line.

[0087] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, wherein,

[0088] The spacing between the first gate pad and the second gate pad, the spacing between the first gate pad and the second gate wiring, the spacing between the second gate pad and the first gate wiring, and the spacing between the first gate wiring and the second gate wiring are all 10 μm or more.

[0089] (Appendix 6) The semiconductor device according to any one of Appendices 1 to 5, wherein,

[0090] The first gate pad, the first gate wiring, the second gate pad, and the second gate wiring are all made of polysilicon thin film and metal thin film.

[0091] (Note 7) The semiconductor device according to any one of Notes 1 to 6, wherein,

[0092] A gate resistor is built into both the first gate pad and the first gate wiring and the second gate pad and the second gate wiring.

[0093] (Note 8) The semiconductor device according to Note 4, wherein,

[0094] It also has grooves formed in the aforementioned active regions.

[0095] The first gate signal line, the second gate signal line, and the dummy gate signal line are buried in the trench and are made of polysilicon thin film.

Claims

1. A semiconductor device, wherein, The semiconductor device includes: A semiconductor substrate is defined as an active region on which semiconductor elements are formed and which has a quadrilateral shape when viewed from above, and a terminal region that is the outer region of the active region. The first gate pad is disposed at the center of the first side of the active region; The first gate wiring is connected to the first gate pad and extends along the first direction; The first gate signal line is connected to the first gate pad or the first gate wiring and extends in the direction that intersects the first direction, i.e., the second direction. The second gate pad is disposed at the corner of the first side of the active region; The second gate wiring is connected to the second gate pad and has a portion extending along the first direction; as well as The second gate signal line is connected to the second gate pad or the second gate wiring and extends along the second direction. The second gate wiring extends along the boundary between the active region and the terminal region.

2. A semiconductor device, wherein, The semiconductor device includes: A semiconductor substrate is defined as an active region on which semiconductor elements are formed and which has a quadrilateral shape when viewed from above, and a terminal region that is the outer region of the active region. The first gate pad is disposed at the center of the first side of the active region; The first gate wiring is connected to the first gate pad and has a portion extending along the first direction; The first gate signal line is connected to the first gate pad or the first gate wiring and extends in the direction that intersects the first direction, i.e., the second direction. The second gate pad is disposed at the center of the first side of the active region, adjacent to the first gate pad; The second gate wiring is connected to the second gate pad and has a portion extending along the first direction; as well as The second gate signal line is connected to the second gate wiring and extends along the second direction. The second gate wiring extends along the boundary between the active region and the termination region. A portion of the first gate wiring partially surrounds the outer periphery of the second gate pad.

3. The semiconductor device according to claim 1 or 2, wherein, The first gate signal line and the second gate signal line are alternately arranged in the first direction.

4. The semiconductor device according to claim 3, wherein, A dummy gate signal line is configured between the first gate signal line and the second gate signal line.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The spacing between the first gate pad and the second gate pad, the spacing between the first gate pad and the second gate wiring, the spacing between the second gate pad and the first gate wiring, and the spacing between the first gate wiring and the second gate wiring are all greater than 10 μm.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The first gate pad, the first gate wiring, the second gate pad, and the second gate wiring are all composed of polysilicon thin film and metal thin film.

7. The semiconductor device according to any one of claims 1 to 6, wherein, A gate resistor is built into both the first gate pad and the first gate wiring, and between the second gate pad and the second gate wiring.

8. The semiconductor device according to claim 4, wherein, It also has grooves formed in the active region. The first gate signal line, the second gate signal line, and the dummy gate signal line are buried in the trench and are made of a polysilicon thin film.

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