Driving substrate, electronic paper display module and display device

Abstract

A driving substrate, an electronic paper display module and a display device, belonging to the technical field of display, the driving substrate can be applied to electronic paper, and the driving substrate comprises: a substrate (13) comprising a display area (1) and a peripheral area (4) surrounding the display area (1); a plurality of sub-pixels (111) located in the display area (1); and at least one hole digging region (2), the plurality of sub-pixels (111) surrounding the hole digging region (2); wherein the orthographic projection of the hole digging area (2) on the substrate (13) is located in a fitting area (2 ') of the display area (1), the fitting area (2') is an area defined by a regular graph obtained after fitting is conducted on the edge of the display area (1), and all or part of the fitting area (2 ') is the display area (1).

Description

Driving substrate, electronic paper display module and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a driving substrate, an electronic paper display module and a display device. BACKGROUND

[0002] Electronic paper (E-Paper) is also called digital paper, which is a product combining the display information characteristics of ordinary paper with the characteristics of computer display screens. Electronic paper can reflect the display characteristics of paper and can be reused. At present, electronic paper screens are increasingly used to display information in more and more scenarios, such as being widely used in the fields of electronic price tags, electronic books, billboards, etc.

[0003] Electronic paper is mainly assembled by a TFT substrate, a paper film and an encapsulation glue encapsulating the TFT substrate and the paper film. In practice, the manufacturing cost of electronic paper needs to be considered.

[0004] SUMMARY

[0005] In a first aspect, the present disclosure provides a driving substrate, wherein the driving substrate comprises:

[0006] a substrate comprising a display area and a peripheral area surrounding the display area;

[0007] a plurality of sub-pixels located in the display area; and

[0008] at least one cutout area, the plurality of sub-pixels bypassing the cutout area.

[0009] The orthographic projection of the cutout area on the substrate is located in a fitting area of the display area, the fitting area is an area enclosed by a regular figure after fitting the edges of the display area, and all or part of the fitting area is the display area.

[0010] Exemplarily, the driving substrate comprises a first cutout area and / or a second cutout area, the first cutout area is located in the display area, and the second cutout area is located outside the display area.

[0011] The display area has a notch area inwardly recessed at at least one edge of the display area, and the second cutout area is located in the notch area.

[0012] Exemplarily, the display area comprises a first sub-display area and a second sub-display area at least partially surrounding the first sub-display area, and the plurality of sub-pixels are located in the first sub-display area.

[0013] The fitting area is an area enclosed by a regular figure after fitting the edges of the second sub-display area.

[0014] Exemplarily, the display panel further comprises a third cutout region located between the first sub-display region and the second sub-display region.

[0015] Exemplarily, the fitting region is a regular polygon, and the cutout region is arranged at at least one end point of the fitting region; and / or, the cutout region is arranged at at least one edge of the fitting region.

[0016] Exemplarily, one side of the substrate further comprises a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines cross to define a plurality of sub-pixel regions.

[0017] The common electrode line is arranged in the same layer as the gate line or the data line; and / or, the common electrode line is arranged in a different layer from the gate line and the data line.

[0018] Exemplarily, one side of the substrate further comprises a plurality of common electrode lines; the cutout region exposes the common electrode line, or the cutout region is spaced apart from the common electrode line by at least one film layer.

[0019] Exemplarily, the aperture of the cutout region is 2mm-3mm.

[0020] Exemplarily, the display panel comprises a plurality of cutout regions and a plurality of common electrode lines, and different cutout regions correspond to different common electrode lines on the substrate.

[0021] Exemplarily, one side of the substrate further comprises a plurality of signal lines, and the plurality of signal lines comprise the gate lines, the data lines, and the common electrode lines, and the gate lines and the data lines cross to define a plurality of sub-pixel regions.

[0022] At least one of the signal lines is routed around the perimeter direction of the cutout region at the position of the cutout region.

[0023] Exemplarily, at least one of the signal lines is routed in a circular arc and / or a polyline around the cutout region at the position of the cutout region.

[0024] Exemplarily, the line shape of at least one of the signal lines at the position of the cutout region is conformal to the edge of the cutout region.

[0025] Exemplarily, the cutout region is located in the display region, and a plurality of the signal lines are routed around the perimeter direction of the cutout region at different positions of the cutout region.

[0026] Exemplarily, the cutout region is located outside the display region and close to the edge of the display region, and a plurality of the signal lines are routed around the perimeter direction of the cutout region on the side of the cutout region close to the display region.

[0027] Exemplarily, among the plurality of signal lines located at the hole digging area, two adjacent signal lines are located at different film layers respectively.

[0028] Exemplarily, one side of the substrate further comprises a plurality of gate line leads and a plurality of data leads, the gate line leads and the data leads are routed at the peripheral area;

[0029] Among them, one of the gate line leads is connected with two adjacent rows of the sub-pixels, one column of the sub-pixels corresponds to two adjacent first data leads and second data leads respectively, among any two adjacent sub-pixels located in the same column, one of the sub-pixels is connected with the first data lead, and the other sub-pixel is connected with the second data lead.

[0030] Exemplarily, there is an inter-row gap between two adjacent rows of the sub-pixels, a plurality of gate lines are included in the display area, and the orthogonal projection of the plurality of gate lines on the substrate is located in different inter-row gaps;

[0031] Among them, two adjacent gate lines are connected with two adjacent rows of the sub-pixels respectively, and the two adjacent gate lines are connected with the same gate line lead.

[0032] Exemplarily, there is an inter-row gap between two adjacent rows of the sub-pixels, a plurality of gate lines are included in the display area, and the plurality of gate lines are connected with the plurality of gate line leads respectively;

[0033] Among them, one of the gate lines is connected with two adjacent rows of the sub-pixels.

[0034] Exemplarily, the sub-pixel comprises a thin film transistor;

[0035] Among the first sub-pixel and the second sub-pixel connected with the same gate line lead and adjacent in the column direction, the orthogonal projection of the thin film transistor of the first sub-pixel on the substrate is a mirror image of the orthogonal projection of the thin film transistor of the second sub-pixel on the substrate.

[0036] The second aspect of the present disclosure provides an electronic paper display module, wherein the electronic paper display module comprises the driving substrate of any one of the exemplary embodiments of the first aspect; and

[0037] A paper film is packaged with the driving substrate, and the paper film comprises a common electrode layer;

[0038] A conductive object is located in the hole digging area of the driving substrate;

[0039] Among them, the common electrode layer is connected with the common electrode line on the driving substrate through the conductive object.

[0040] In a third aspect, the present disclosure provides a display device, comprising the electronic paper display module of any one of the second aspect.

[0041] In an example, the display device further comprises:

[0042] a display lamp located on a side of the paper film away from the driving substrate;

[0043] The display lamp has an orthogonal projection on the substrate that overlaps the orthogonal projection of the cutout region on the substrate.

[0044] In an example, the display device further comprises:

[0045] a cover plate located on a side of the electronic paper display module;

[0046] The cover plate comprises an open hole region, and the display lamp is located in the open hole region.

[0047] In an embodiment of the present disclosure, an electronic paper is provided with a driving substrate, which comprises: a substrate, a display region and a peripheral region surrounding the display region are arranged on the substrate; a plurality of sub-pixels are arranged in the display region; and at least one cutout region, and the plurality of sub-pixels bypass the cutout region; wherein the orthogonal projection of the cutout region on the substrate is located in a fitting region of the display region, the fitting region is a region enclosed by a regular pattern after fitting the edges of the display region, and all or part of the fitting region is the display region. Since the cutout region is located in the fitting region of the display region, and the fitting region is a region enclosed by a regular pattern after fitting the edges of the display region, the display region and the cutout region are both in the regular region where the display region is located, so that the union of the display region and the cutout region can form a regular pattern, so that the area occupied by the display region and the cutout region on the substrate is a regular area, thereby making the cutout region and the display region form a more compact pattern, avoiding the increase of the frame length of the electronic paper due to the formation of a special-shaped pattern by the position of the cutout region and the display region, and reducing the waste of materials such as paper film, protective film of the driving substrate and the like of the electronic paper, thereby reducing the production cost of the electronic paper.

[0048] The above description is only a summary of the technical solutions of the present disclosure. In order to more clearly understand the technical means of the present disclosure, the specific embodiments of the present disclosure can be implemented in accordance with the content of the description, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following specific embodiments of the present disclosure are described.

[0049] Brief Description of Drawings

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description are some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor. It should be noted that the ratio in the drawings is only used as an illustration and does not represent the actual ratio.

[0051] FIGS. 1-2 respectively show top view schematic diagrams of several driving substrates in the embodiments of the present disclosure;

[0052] FIG. 3 shows a cross-sectional structure schematic diagram of a driving substrate in the embodiments of the present disclosure;

[0053] FIG. 4 shows an enlarged schematic diagram of the vicinity of the lower left corner hole area in (b) of FIG. 1;

[0054] FIG. 5 shows an enlarged schematic diagram of the vicinity of the upper left corner hole area in (a) of FIG. 1;

[0055] FIGS. 6 and 7 respectively show top view schematic diagrams of two driving substrates;

[0056] FIGS. 8-10 respectively show schematic diagrams of position settings of various hole areas;

[0057] FIG. 11 shows a schematic diagram of signal line routing inside a driving substrate;

[0058] FIGS. 12-16 respectively show cross-sectional structure schematic diagrams of several driving substrates;

[0059] FIGS. 17 and 18 respectively show schematic diagrams of common electrode line routing on a driving substrate;

[0060] FIG. 19 shows a schematic diagram of routing on a driving substrate;

[0061] FIG. 20 shows a schematic diagram of routing at the position of the lower left corner hole area 2 in (b) of FIG. 1;

[0062] FIG. 21 shows a schematic diagram of routing at the hole area of (a) of FIG. 7;

[0063] FIG. 22 shows a schematic diagram of cross-sectional structure related to routing at the hole area;

[0064] FIGS. 23 and 24 respectively show two schematic diagrams of routing of a driving substrate;

[0065] FIG. 25 shows a schematic diagram of sub-pixel design of the driving substrate of FIG. 23;

[0066] FIG. 26 shows a schematic diagram of sub-pixel design of the driving substrate of FIG. 24;

[0067] Fig. 27 shows a structural schematic diagram of a driving substrate in the present example;

[0068] Fig. 28 shows a cross-sectional structural schematic diagram of an electronic paper display module;

[0069] Fig. 29 shows an exploded structural schematic diagram of a display device;

[0070] Fig. 30 shows a top view schematic diagram of several display devices.

[0071] Reference signs: 10, driving substrate; 20, paper film; 30, protective film; 1, display area; 2, hole area; 21, first hole area; 2', fitting area; 22, second hole area; 23, third hole area; 24, via hole; 3, notch area; 4, peripheral area; 5, driving chip; 6, flexible circuit board; 7, water-blocking glue; 8, white glue; 9, display lamp; 13, substrate; 14, first interlayer dielectric layer; 15, thin film transistor; 16, second interlayer dielectric layer; 17, encapsulation layer; 18, pixel electrode; 151, drain area; 152, drain electrode; 153, gate insulating layer; 154, gate; 155, channel area; 156, source area; 157, source electrode; 18, pixel electrode; 111, sub-pixel; 31, reserved area; VD, data line; VG, gate line; Vcom, common electrode line; C1, first common electrode line; C2, second common electrode line; G1, gate line lead; D1, data lead; 1C1, opening area; 1C, cover plate; 1B, printed circuit board; 1A, electronic paper display module.

[0072] Detailed description

[0073] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0074] In the related art, the electronic paper includes a driving substrate and a paper film, wherein an electric field is formed between the driving substrate and the paper film FPL, so as to drive the medium (black and white particles) on the paper film to move, so as to display an image. Generally, a common electrode layer is arranged on the paper film, so that the common electrode layer on the FPL is driven, and a part of the area on the FPL needs to be extended outward for reserving an ear hole, and an electric connection point (such as silver glue) is arranged at the position of the ear hole, and then the electrode (such as the common electrode) on the TFT substrate is connected with the common electrode layer on the FPL through the electric connection point. However, due to the existence of the ear hole, the FPL and the protective film (for preventing glare and preventing water vapor from entering the FPL) attached to the FPL are irregular patterns, which brings an increase in the size of the FPL, the PS (protective film) and the TFT, such as increasing the frame of the TFT, so that the number of cuts of the electronic paper screen is reduced, and the manufacturing cost of the electronic paper is increased.

[0075] Among them, the number of cuts is a measure of the number of large pieces of electronic paper film being cut, and the larger the number of cuts, the more the large pieces of electronic paper film are cut into small pieces of paper film, and each small piece of paper film is used for an electronic paper screen. Because of the existence of the ear hole, when cutting, a frame area needs to be reserved for the ear hole, so as to increase the size of each small piece of electronic paper film, so that the number of cuts of the large piece of electronic paper film is reduced, and a larger size of the large piece of electronic paper film is needed to meet the production of a predetermined number of electronic paper screens.

[0076] Similarly, not only for the paper film, but also for the driving substrate (TFT substrate) matched with the paper film, the protective film of the driving substrate, and the glue material for sealing the driving and the edge of the electronic paper, more are needed, thereby causing waste of these materials, so that the production cost of the electronic paper screen is increased synchronously.

[0077] Therefore, the present disclosure proposes a driving substrate, which is used to fill the area composed of the dug hole area 2 of the silver glue and the display area, and the area is a regular area, and the area can be a regular pattern fitted by the display area. Thus, the problem of increasing the frame size and increasing the cost caused by the dug hole area 2 protruding outside the display area can be avoided.

[0078] The regular pattern in the embodiment refers to a pattern with a clear name and fixed characteristics, such as a square, a rectangle, a ball, a circle, a triangle, a semicircle, and the like. The circle can be an ellipse or a perfect circle. These patterns have clear definitions and properties in geometry, such as side length, angle, volume, or curvature, and the like. The regular pattern has consistent number and relationship of points, lines, and angles. For example, a triangle has three sides and three angles, a square has four sides and four right angles, and a parallelogram has two opposite sides that are parallel and have the same length. Since the embodiment is applied to the display field, the regular pattern can also refer to a pattern with symmetry characteristics, such as a pattern having both axial symmetry and central symmetry. Compared with an irregular pattern, the regular pattern has a fixed shape and can be directly classified into common geometric patterns.

[0079] Specifically, the cutout area 2 of the driving substrate in the embodiment can be located in the display area, or can also be located outside the display area. When located outside the display area, the cutout area 2 and the display area can be spliced into a regular pattern. For example, there is a notch in the display area, and the cutout area 2 is located in the notch, so that the cutout area 2 and the display area form a regular pattern area.

[0080] Please refer to FIGS. 1-3, FIGS. 1-2 respectively show top view schematic diagrams of several driving substrates in the embodiment of the disclosure, and FIG. 3 shows a cross-sectional structure schematic diagram of the driving substrate. As shown in FIGS. 1-3, the driving substrate can be applied to electronic paper, and the driving substrate can also be referred to as a TFT substrate.

[0081] Specifically, the driving substrate can include:

[0082] a substrate 13 including a display area 1 and a peripheral area 4 surrounding the display area 1;

[0083] a plurality of sub-pixels 111 located in the display area 1; and

[0084] at least one cutout area 2, and the plurality of sub-pixels 111 bypass the cutout area 2.

[0085] The orthogonal projection of the cutout area 2 on the substrate 13 is located in a fitting area 2' of the display area 1. The fitting area 2' is a region enclosed by a regular pattern after the edges of the display area 1 are fitted. All or part of the fitting area 2' is the display area 1.

[0086] In the embodiment, the sub-pixels 111 are connected with the common electrode lines arranged on the substrate 13, and the cutout area 2 is used to fill a conductive object to connect the conductive object with the common electrode lines.

[0087] In the embodiment, the driving substrate includes a substrate 13, which can be a flexible substrate 13 or a non-flexible substrate 13. In the case of the flexible substrate 13, the substrate 13 can be a silicon-based substrate 13. In the case of the non-flexible substrate 13, the substrate 13 can be a glass substrate 13. The driving substrate can include a display area 1 and a peripheral area 4 surrounding the display area 1. The display area 1 can have a circular, rectangular, elliptical, regular polygonal or other regular shape. The peripheral area 4 can have a corresponding circular ring shape, frame shape, elliptical ring shape, or regular polygonal frame shape. The shape of the peripheral area 4 can be adapted to the shape of the display area 1. For example, the display area 1 can be circular, and the peripheral area 4 can be a circular ring. Alternatively, the display area 1 can be elliptical, and the peripheral area 4 can be an elliptical ring. Alternatively, the shape of the peripheral area 4 can be different from the shape of the display area 1. For example, the display area 1 can be circular, and the peripheral area 4 can be a frame shape or an elliptical ring. Alternatively, the display area 1 can be rectangular, and the peripheral area 4 can be a circular ring or an elliptical ring.

[0088] In the embodiment, the display area 1 can include a plurality of sub-pixels 111. Each sub-pixel 111 can include a pixel driving circuit for driving the sub-pixel 111. The pixel driving circuit can include a thin film transistor 15, which can include a gate, a source and a drain. For example, as shown in FIG. 3, the thin film transistor 15 can have a bottom gate structure or a top gate structure. Taking the bottom gate structure as an example, the thin film transistor 15 can include the following structure.

[0089] A gate 154 located on one side of the substrate 13;

[0090] A gate insulating layer 153 located on the side of the gate 154 away from the substrate 13;

[0091] An active layer located on the side of the gate insulating layer away from the substrate 13. The active layer includes a channel region 155, an active region 151 and a drain region 156. The channel region 155 has an overlapping projection on the substrate 13 with the projection of the gate on the substrate 13;

[0092] A source / drain electrode located on the side of the active layer away from the substrate 13. The source / drain electrode includes a source electrode 157 and a drain electrode 152. The source electrode 157 and the drain electrode 152 are overlapped with the active layer. The drain electrode is connected with a pixel electrode 18.

[0093] The substrate 13 further includes a plurality of gate lines and a plurality of data lines on one side thereof, the plurality of gate lines and the plurality of data lines cross to define a plurality of sub-pixel regions, the sub-pixel regions are regions where the sub-pixels 111 are located, each sub-pixel 111 is connected to a corresponding gate line and a corresponding data line, the gate line can be connected to the gate electrode of the thin film transistor 15, the data line can be connected to the source electrode 157 of the thin film transistor 15, the driving signal on the gate line can control the turn-off and turn-on of the thin film transistor 15, when the thin film transistor 15 is turned on, the driving signal on the data line reaches the thin film transistor 15, and then an electric field is formed at the pixel electrode 18, thereby driving the sub-pixel 111 to display the corresponding color. For example, in the electronic paper in the embodiment, when the driving signal on the data line reaches the thin film transistor 15, an electric field is formed between the common electrode layer on the paper film and the driving substrate, thereby driving the ink on the paper film to move, and then displaying the corresponding color, such as white, black or red.

[0094] The driving substrate further includes a common electrode line, which can include a plurality of common electrode lines, or can include one common electrode line, the common electrode line can be connected to the plurality of sub-pixels 111 respectively, and in the pixel driving circuit, the common electrode line can provide a common voltage. It should be noted that the connection of the common electrode line to the sub-pixel 111 can mean that the common electrode line is connected to the driving circuit of the sub-pixel 111, and is used to provide a common voltage to the driving circuit.

[0095] In the embodiment, the driving substrate can include at least one hole region 2, the hole region 2 can be used to fill a conductive material, which can be silver glue or other conductive glue, the filled conductive material can be connected to the common electrode line on the driving substrate, after the driving substrate is connected to the paper film in a sandwich manner, the conductive material in the hole region 2 can be connected to the common electrode layer on the paper film, thereby connecting the common electrode layer on the paper film to the common electrode line on the driving substrate, so that the driving substrate can provide a common voltage to the common electrode layer on the paper film.

[0096] In some examples, the orthographic projection of the position of one hole region 2 on the substrate 13 can overlap with the orthographic projection of any common electrode line on the substrate 13, thereby the conductive material in the hole region 2 can be directly lapped on the common electrode line, thereby reducing the wiring distance between the conductive material and the common electrode line. In yet some examples, the orthographic projection of the position of one hole region 2 on the substrate 13 can not overlap with the orthographic projection of the common electrode line on the substrate 13, when connecting the conductive material and the common electrode line, the electrical connection between the two can be realized by a via hole opened between the hole region 2 and the common electrode line.

[0097] In this embodiment, the shape of the punch-hole area 2 can include a circle, an ellipse, a rectangle, or a polygon. Specifically, it can be determined based on the shape of the display area 1 or the shape of the surrounding area 4. In one example, the shape of the punch-hole area 2 can be adapted to the shape of the surrounding area 4. For example, if the surrounding area 4 is an annular shape, then the punch-hole area 2 can be circular; or, for another example, if the surrounding area 4 is a rectangular frame, then the punch-hole area 2 can be rectangular. In yet another example, the shape of the punch-hole area 2 can be the same as the shape of the display area 1. For example, if the display area 1 is circular, then the punch-hole area 2 can be circular; or, for another example, if the display area 1 is a rectangular frame, then the punch-hole area 2 can be rectangular.

[0098] Among them, multiple sub-pixels 111 can be set around the punch-hole area 2. This can be understood as not setting sub-pixels 111 in the punch-hole area 2. Specifically, it can mean that the orthographic projection of the punch-hole area 2 on the substrate 13 does not overlap with the orthographic projection of the thin film transistor 15 in the sub-pixel 111 on the substrate 13.

[0099] In this embodiment, the punch-hole area 2 can be located inside or outside the display area 1. Regardless of whether it is located inside or outside the display area 1, the orthogonal projection of the punch-hole area 2 on the substrate 13 is within the area enclosed by a regular pattern fitted to the edge of the display area 1. This can be understood as the union of the display area 1 and the punch-hole area 2 forming a regular pattern with rounded edges, so that the punch-hole area 2 does not protrude outside the display area 1.

[0100] For example, as shown in Figure 1(a) and Figures 2(b), (c), and (d), the cutout area 2 can be located outside the display area 1 and close to the peripheral area 4. The shape of the display area 1 can be irregular, meaning that the edges of the display area 1 are irregular. In this case, fitting the edges of the display area 1 can refer to fitting along the extension direction of the edges of the display area 1, fitting the display area 1 into a regular shape. For example, as shown in Figure 1(a), most of the edges of the display area 1 are straight lines. Fitting along the extension direction of its edges can fit it into a rectangle. The dashed line in Figure 1(a) shows the fitted edge, and the cutout area 2 is located within the fitted rectangular area. As another example, as shown in Figure 2(b), most of the edges of the display area 1 are arcs. Fitting along the extension direction of its edges can fit it into a circle. The dashed line in Figure 2(b) shows the fitted edge, and the cutout area 2 is located within the fitted circular area. Thus, when the punch-hole area 2 is located outside the display area 1, it can be understood that the display area 1 has a notch 3 for setting the punch-hole area 2, and the punch-hole area 2 is set in the notch 3. Therefore, the punch-hole area 2 and the display area 1 can be located in a regular area that is mainly fitted by the display area 1, so that the punch-hole area 2 and the display area 1 can form a more compact shape, avoiding the increase in the border length of the electronic paper due to the irregular shape formed by the location of the punch-hole area 2 and the display area 1.

[0101] For example, as shown in (b) of FIG. 1 and (a) of FIG. 2, the cutout area 2 can be located in the display area 1 and close to the peripheral area 4, and the display area 1 can have a regular shape, that is, the edges of the display area 1 are regular edges. In this case, the area fitted to the edges of the display area 1 can be the original area of the display area 1, and the cutout area 2 is located in the original area. For example, as shown in (b) of FIG. 1, the display area 1 is a rectangle, and the cutout area 2 is located in the rectangular area. For another example, as shown in (a) of FIG. 2, the display area 1 is a circle, and the cutout area 2 is located in the circular area. In this way, when the cutout area 2 is located in the display area 1, it can be understood that the cutout is made inside the display area 1. By locating the cutout area 2 inside the display area 1, the problem of increasing the size of the frame caused by cutting out outside the display area 1 can be avoided.

[0102] It should be noted that, since the sub-pixels 111 of the display area 1 are arranged around the cutout area 2, when the cutout area 2 is located inside the display area 1, a plurality of sub-pixels 111 can be arranged in the area outside the cutout area 2, and the plurality of sub-pixels 111 can all be regular-shaped sub-pixels 111. For example, as shown in FIG. 4, which shows an enlarged view of the area near the lower left corner cutout area 2 in (b) of FIG. 1, the plurality of sub-pixels 111 are regular-shaped and arranged around the cutout area 2. When the cutout area 2 is located outside the display area 1, the sub-pixels 111 near the cutout area 2 can be arranged as irregular-shaped sub-pixels 111. For example, as shown in FIG. 5, which shows an enlarged view of the area near the upper left corner cutout area 2 in (a) of FIG. 1, the sub-pixels 111 in the display area 1 can include first sub-pixels 11a and second sub-pixels 11b. The second sub-pixels 11b near the edges of the cutout area 2 in the display area 1 can be conformal to the edges of the cutout area 2, and the first sub-pixels 11a are regular-shaped. Thus, irregular-shaped sub-pixels 11b can exist in the display area 1. In this way, the display area 1 can be fully utilized, the light-emitting area of the peripheral area 4 of the cutout area 2 can be increased, and the display quality can be ensured.

[0103] In this embodiment, the shape of the sub-pixel 111 can refer to the shape of the opening area of the sub-pixel 111, and the opening area refers to the area not blocked by the black matrix. Specifically, in some embodiments, whether the shape of the sub-pixel 111 around the cutout area is regular or not can depend on the resolution of the electronic paper. In the case of high resolution, the sub-pixels 111 around the cutout area can all be regular-shaped, as shown in FIG. 4. In the case of low resolution, the sub-pixels 111 around the cutout area can be irregular-shaped, as shown in FIG. 5, that is, the opening area of the sub-pixel 111 is blocked by the black matrix to form an irregular opening area, thereby avoiding the problem of jagged display edges around the cutout area in the case of low resolution.

[0104] In some embodiments, the first cutout region 21 in the display region 1 can be included, and / or the second cutout region 22 outside the display region 1 can be included, wherein at least one edge of the display region 1 has a notch region that is inwardly recessed into the display region 1, and the second cutout region 22 can be located in the notch region.

[0105] In the embodiment, in the case of including one cutout region 2, the cutout region 2 can be the first cutout region 21 located in the display region 1, or can be the second cutout region 22 located outside the display region 1; in the case of including multiple cutout regions 2, the multiple cutout regions 2 can all be the first cutout region 21 located in the display region 1, as shown in (b) of FIG. 1, or the multiple cutout regions 2 can all be the second cutout region 22 located outside the display region 1, as shown in (a) of FIG. 1.

[0106] Alternatively, in some examples, the multiple cutout regions 2 can include both the first cutout region 21 located in the display region 1 and the second cutout region 22 located outside the display region 1.

[0107] In the case of including the second cutout region 22, the union of the second cutout region 22 and the display region 1 constitutes a regular pattern, for example, the display region 1 is an irregular pattern, the fitting pattern of the edge of the display region 1 is a regular pattern, and the second cutout region 22 is located in the area where the regular pattern is located. As described in the above embodiment, the display region 1 can predefine a notch region for the second cutout region 22, as shown in FIG. 1(a) and FIG. 2(b), the display region 1 includes a notch region for the second cutout region 22, and the second cutout region 22 is arranged in the notch region.

[0108] In the embodiment, the notch region can be understood as a notch at the edge region or the endpoint region of the display region, for example, the display region is a rectangle, and the notch region can refer to a notch dug at the edge position of the rectangle, or can refer to a notch dug at the endpoint position of the rectangle, and the sub-pixels can not be arranged in the notch region, wherein the edge of the notch region can be conformal with the edge of the cutout region, for example, the cutout region is a circle, and the edge of the notch region can include a circular arc segment, as shown in (a) of FIG. 1, for example, the cutout region is a rectangle, and the edge of the notch region can include two mutually orthogonal edges to match the rectangular cutout region.

[0109] The driving substrate of the embodiment can be opened in the display region 1 or outside the display region 1, and no matter where the opening is made, the display region 1 and the area where the cutout region 2 is located can constitute a regular pattern area, avoiding that the cutout region 2 occupies too much frame space.

[0110] In some embodiments, the display area 1 can be divided into a first sub-display area 11 and a second sub-display area 12 surrounding the first sub-display area 11 at least partially, the first sub-display area 11 includes a plurality of sub-pixels 111, and the second sub-display area 12 can be regarded as a border display area of the first sub-display area 11, wherein the fitting area 2' of the display area 1 can be an area surrounded by a regular pattern fitted to the edge of the second sub-display area 12.

[0111] Please refer to FIG. 6 and FIG. 7, which respectively show the top view schematic diagrams of two driving substrates. As shown in FIG. 6 and FIG. 7, the display area 1 includes a first sub-display area 11 and a second sub-display area 12 surrounding the first sub-display area 11. Specifically, the second sub-display area 12 can surround the first sub-display area 11 completely or partially. FIG. 6 and FIG. 7 show the case that the second sub-display area 12 surrounds the first sub-display area 11 completely. The second sub-display area 12 can be regarded as the boundary of the first sub-display area 11, and can be used to distinguish the peripheral area 4 from the display area 1. The second sub-display area 12 can display color or not. When displaying color, the same color is displayed in one driving display period, for example, white, black or red.

[0112] In combination with the above embodiments, when the first cutout area 21 is located in the display area 1, the first cutout area 21 can be arranged on the side of the first sub-display area 11 away from the second sub-display area 12. When the second cutout area 22 is located outside the display area 1, the second cutout area 22 can be arranged on the side of the second sub-display area 12 away from the first sub-display area 11.

[0113] Since the second sub-display area 12 can be regarded as the boundary of the first sub-display area 11, the fitting area 2' of the display area 1 can be an area surrounded by a regular pattern fitted to the edge of the second sub-display area 12.

[0114] In the present embodiment, when the second sub-display area 12 surrounds the first sub-display area 11, the second sub-display area 12 can be a regular pattern or an irregular pattern. When the second sub-display area 12 is a regular pattern, such as a circle or a rectangle, the first sub-display area 11 can be an irregular pattern, and the first cutout area 21 is located in the first sub-display area 11. Alternatively, the first sub-display area 11 can also be a regular pattern, and the first cutout area 21 can be located in the second sub-display area 12 or the peripheral area 4.

[0115] In the embodiment, since the display region 1 includes the first sub-display region 11 and the second sub-display region 12, the display region 1 and the peripheral region 4 can be distinguished by the second sub-display region 12, so that there is a transition display region 1 between the display region 1 where the sub-pixel 111 is located and the peripheral region 4, and thus the ink at the first sub-display region 11 can be electrically field isolated by the electric field at the second sub-display region 12, so as to avoid crosstalk of the ink at the edge of the first sub-display region 11, thereby clearly displaying the boundary and improving the display quality.

[0116] Please continue to refer to (a) in FIG. 6, for the cutout region 2 located in the display region 1, the cutout region 2 can be located between the first sub-display region 11 and the second sub-display region 12, and specifically, the cutout region 2 arranged between the first sub-display region 11 and the second sub-display region 12 is referred to as a third cutout region 23.

[0117] In an example of the embodiment, the third cutout region 23 can be a region obtained after the first sub-display region 11 is punched, as shown in (b) in FIG. 6, the first sub-display region 11 can be directly punched, and the entire region punched can be the third cutout region 23, that is, the region enclosed by the second sub-display region 12 can be a region spliced by the first sub-display region 11 and the third cutout region 23; or in another example, as shown in (a) in FIG. 6, a region can be reserved in the first sub-display region 11, which can be referred to as a reserved region 31, and can be the notch region in the above example, and then the reserved region 31 can be punched to obtain the third cutout region 23, in this case, the third cutout region 23 can occupy part of the reserved region, and thus the region enclosed by the second sub-display region 12 can be a region spliced by the third cutout region 23, the reserved region and the first sub-display region 11.

[0118] In another example of the embodiment, in the case of including the first sub-display region 11 and the second sub-display region 12, the second cutout region 22 can be included, that is, the cutout region 2 located outside the display region 1, in this case, the second cutout region 22 is located on the side of the second sub-display region 12 away from the first sub-display region 11, and the second sub-display region 12 can enclose the first sub-display region 11, or the second sub-display region 12 can partially enclose the first sub-display region 11, for example, the second sub-display region 12 can enclose the first sub-display region 11 by avoiding the position where the second cutout region 22 is located (not shown in the figure). Specifically, as shown in (a) in FIG. 7, the fitting shape of the second sub-display region 12 can be a rectangular frame, and thus the fitting region 2' of the display region 1 can be a rectangular region, and the second cutout region 22 is located in the rectangular region.

[0119] For example, the second cutout area 22 can fill the gap area 3 of the display area 1, for example, as shown in (b) of FIG. 7, the second cutout area 22 fills the area between the fitting pattern of the second sub-display area 12 and the second sub-display area 12, so that the second cutout area 22 and the display area 1 can be spliced into a regular area. For another example, the second cutout area 22 can fill part of the gap area 3 of the display area 1, as shown in (a) of FIG. 7, the second cutout area 22 does not fill the area between the fitting pattern of the second sub-display area 12 and the second sub-display area 12 (i.e. the gap area 3), so that although the second cutout area 22 and the display area 1 are spliced into an irregular area, the second cutout area 22 is in the fitting area 2' of the display area 1 with a regular pattern.

[0120] In the case that the second cutout area 22 does not fill the area between the fitting pattern of the second sub-display area 12 and the second sub-display area 12, that is, in the case that the second cutout area 22 does not completely fill the gap area 3, the difficulty of cutting can be reduced.

[0121] In some embodiments, for the position setting of the cutout area 2, it can be determined according to the area shape of the display area 1, for example, in the case that the display area 1 is a polygon, the fitting area 2' of the display area 1 can be a regular polygon, then the cutout area 2 can be set at at least one endpoint of the fitting area 2', and / or at least one edge of the fitting area 2'.

[0122] In the embodiments, please refer to FIGS. 8-10, which respectively show various position setting diagrams of the cutout area 2, as shown in FIG. 9, in the case that one cutout area 2 is included, the cutout area 2 can be located at any one endpoint of the fitting area 2', or at any one edge of the fitting area 2'. Please refer to FIG. 1, in the case that multiple cutout areas 2 are included, the multiple cutout areas 2 can be respectively located at different endpoints, or respectively located at multiple edges of the fitting area 2'. Or, in the case that multiple cutout areas 2 are included, the multiple cutout areas 2 can include a cutout area 2 located at an endpoint of the fitting area 2', and a cutout area 2 located at an edge of the fitting area 2' (not shown in the figure).

[0123] For example, as shown in FIG. 1, the fitting area 2' is a rectangle, no matter whether the cutout area 2 is set outside the display area 1 or inside the display area 1, then one cutout area 2 can be set at each endpoint of the fitting area 2', or as shown in FIG. 9, a cutout area 2 can be set at any one endpoint of the fitting area 2'. In the case that the cutout area 2 is located outside the display area 1, that is, for the second cutout area 22, it can be regarded as that the display area 1 has a gap area at the corner, then the second cutout area 22 is located in the gap area at the corner.

[0124] Exemplarily, as shown in FIG. 1, the fitting region 2' is rectangular, and one hole region 2 can be arranged at each end point of the fitting region 2', or one hole region 2 can be arranged at any end point of the fitting region 2', regardless of whether the hole region 2 is arranged outside or inside the display region 1. As shown in FIG. 1(a), in the case where the hole region 2 is located outside the display region 1, that is, for the second hole region 22, it can be regarded that there is a notch region at the corner of the display region 1, and the second hole region 22 is located in the notch region at the corner.

[0125] Exemplarily, as shown in FIGS. 8-10, in the case where one hole region 2 is included and the hole region 2 is located at any edge of the display region 1, the hole region 2 can be located at the upper edge, the lower edge, the left edge or the right edge of the display region 1. Exemplarily, as shown in FIG. 9, in the case where one hole region 2 is included and the hole region 2 can be located at any end point of the display region 1, the hole region 2 can be located at the upper left corner, the lower left corner, the upper right corner or the lower right corner of the display region 1.

[0126] In some embodiments, the shape of the orthographic projection of the hole region 2 on the substrate 13 includes at least one of a circle, a polygon, an ellipse and an irregular shape. As shown in FIG. 10, the hole region 2 can be located at the lower edge of the fitting region 2' of the display region 1, and the splicing pattern of the hole region 2 and the first sub-display region 11 can be a region enclosed by the second sub-display region 12. The hole region 2 can be a triangle, a rectangle, a semicircle, a square, etc.

[0127] As shown in FIG. 2, in the case where the fitting region 2' of the display region 1 is a circular arc region such as a circle or an ellipse, the hole region 2 can be located at any position of the edge of the fitting region 2'.

[0128] In the embodiment, the hole region 2 can not penetrate the substrate 13, and a plurality of common electrode lines are arranged on the substrate 13. Since the conductive object in the hole region 2 needs to be connected to the common electrode lines, according to the position of the common electrode lines or according to the position of the metal film layer on the substrate 13, the hole region 2 can penetrate to the film layer where the common electrode lines are located, or penetrate to the film layer where any of the plurality of metal film layers is located. Specifically, the substrate 13 further includes a plurality of thin film transistors 15 connected to a plurality of sub-pixels 111 on one side of the substrate 13, and the thin film transistor 15 includes a gate electrode, a gate insulating layer, an active layer and a source-drain electrode 152 arranged in sequence in the thickness direction of the substrate 13; and the bottom of the hole region 2 is located at any one of the layers of the gate electrode, the gate insulating layer, the active layer, the source-drain electrode 152 and the film layer where the common electrode lines are located.

[0129] Please continue to combine Figure 3, the thin film transistor 15 can be a bottom gate type thin film transistor 15, which includes a gate, a gate insulating layer, an active layer and a source-drain electrode 152 in the thickness direction of the substrate 13; wherein one side of the substrate 13 includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines intersect to define a plurality of sub-pixel regions, the gate lines can be disposed in the same layer or different layers with the gate and connected with the gate, or the gate lines can be disposed in different layers with the gate and connected with the gate through a via in the film layer.

[0130] Wherein the data line can be disposed in the same layer or different layers with the source electrode 157 and connected with the source electrode 157, or the data line can be disposed in different layers with the source electrode 157 and connected with the source electrode 157 through a via in the film layer.

[0131] Wherein the common electrode line can be in the same layer with the gate line or the data line, for example, can be disposed in the same layer with the gate line, and for example, can be disposed in the same layer with the data line. Further, in an example, the common electrode line can be disposed in the same layer with the gate or in the same layer with the source-drain electrode 152, so that the common electrode line and the gate, the gate line (or the source-drain electrode 152 and the data line) can be formed in the same process, thereby improving the manufacturing efficiency.

[0132] Wherein the common electrode line can also be disposed in different layers with the gate line and the data line, so that the risk of short circuit between the common electrode line and the gate line and the data line can be reduced, and further, in this example, the common electrode line can be disposed in the same layer with the gate insulating layer, or in different layers with the gate and the source-drain electrode 152, so that the common electrode line and the gate and the source-drain electrode 152 can also be separated by an insulating film layer, thereby avoiding the short circuit between the common electrode line and the gate and the source-drain electrode 152.

[0133] In some embodiments, the data line and the gate line are disposed in different layers, and a metal layer is provided on the second sub-display area 12, the metal layer of the second sub-display area 12 is disposed in different layers with the gate line and the data line, specifically, referring to Figure 11, Figure 11 shows a schematic diagram of the signal line inside the driving substrate, as shown in Figure 1, the data line and the gate line are disposed in different layers, and the distance between the gate lines and the distance between the data lines can be different.

[0134] In an embodiment, the bottom of the hole digging area 2 exposes the common electrode line, or the bottom of the hole digging area 2 is spaced apart from the common electrode line by at least one film layer.

[0135] In the embodiment, the projection of the hole digging area 2 on the substrate 13 can overlap the common electrode line, the bottom of the hole digging area 2 can be exposed to the common electrode line, or not exposed to the common electrode line. In the case of exposing the common electrode line, part of the common electrode line is exposed in the hole digging area 2, so that the conductive material filled in the hole digging area 2 can realize the connection with the common electrode line; in the case of not exposing the common electrode line, the bottom of the hole digging area 2 is spaced from the common electrode line by at least one film layer, which can be a film layer with insulating properties, so that when the hole digging area 2 is filled with conductive material, the conductive material can be connected with the common electrode line through the via on the spaced film layer.

[0136] In the embodiment, the exposure can mean that the common electrode line can be observed through the hole digging area without filling material, and the conductive material can be in direct contact with the common electrode line in the hole digging area with filling material, such as conductive material.

[0137] In the embodiment, please refer to the cross-sectional structure schematic diagrams of the driving substrate shown in FIGS. 12-15. As shown in FIGS. 12-15, the driving substrate can include a substrate 13, a gate electrode disposed on one side of the substrate 13, a gate insulating layer disposed on the side of the gate electrode away from the substrate 13, a first interlayer dielectric layer 14 disposed on the side of the gate insulating layer away from the substrate 13, an active layer disposed on the side of the first interlayer dielectric layer 14 away from the substrate 13, a source electrode 157 and a drain electrode 152 disposed on the side of the active layer away from the substrate 13, a second interlayer dielectric layer 16 disposed on the side of the source-drain electrode 152 away from the substrate 13, and a pixel electrode connected with the drain electrode 152 disposed on the side of the second interlayer dielectric layer 16, and an encapsulation layer 17 disposed on the side of the pixel electrode away from the substrate 13.

[0138] In the embodiment, the hole digging area 2 can be opened from the encapsulation layer 17, and further penetrate the film layers below the encapsulation layer 17 (close to the substrate 13 side), but not penetrate the substrate 13. Specifically, the bottom of the hole digging area 2 can be located in any one of the film layers of the gate electrode, the gate insulating layer, the active layer, the source-drain electrode 152, and the common electrode line.

[0139] For example, as shown in FIG. 12, the common electrode line can be in the same layer as the gate electrode, the gate line is also in the same layer as the gate electrode and electrically connected with the gate electrode, the data line and the gate line are disposed in different layers, the data line is disposed in the same layer as the source electrode 157 and connected with the source electrode 157, wherein the common electrode line is spaced from the gate line and the gate electrode, the hole digging area 2 can penetrate the first interlayer dielectric layer 14 and can expose the common electrode line, or can not expose the common electrode line.

[0140] As another example, as shown in FIG. 13, the common electrode line can be in the same layer as the data line, the data line is also in the same layer as the source-drain electrode 152 and is electrically connected to the source electrode 157, the data line and the gate line are arranged in different layers, the data line is arranged in the same layer as the source electrode 157 and is connected to the source electrode 157, wherein the common electrode line has a spacing between the data line and the source-drain electrode 152, the hole digging area 2 can penetrate to the second interlayer dielectric layer 16 and can expose the common electrode line, or can not expose the common electrode line.

[0141] As another example, as shown in FIG. 14, the gate insulating layer can cover the substrate 13, the common electrode line is arranged in different layers from the gate line and the data line, and the data line and the gate line are arranged in different layers, the data line is arranged in the same layer as the source electrode 157 and is connected to the source electrode 157, specifically, the common electrode line can be located on the side of the gate insulating layer away from the substrate 13, the hole digging area 2 can penetrate to the first interlayer dielectric layer 14 and does not penetrate the gate insulating layer, similarly, the hole digging area 2 can expose the common electrode line, or can not expose the common electrode line.

[0142] As another example, as shown in FIG. 15, the common electrode line is arranged in different layers from the gate line and the data line, and the data line and the gate line are arranged in different layers, the data line is arranged in the same layer as the source electrode 157 and is connected to the source electrode 157, specifically, the common electrode line can be located on the side of the second interlayer dielectric layer 16 away from the substrate 13 and is covered by the packaging layer 17, then the hole digging area 2 can penetrate to the packaging layer 17 and does not penetrate the second interlayer dielectric layer 16, the hole digging area 2 can expose the common electrode line, or can not expose the common electrode line.

[0143] Of course, the above four examples only exemplarily show the setting of the hole digging area 2, and for any of the examples of FIGS. 12-15, the hole digging area 2 can also not penetrate to the film layer where the common electrode line is located, the bottom of the hole digging area 2 can be located on the side of the common electrode line away from the substrate 13, and there are other film layers between the bottom of the hole digging area 2 and the film layer where the common electrode line is located. In this way, when connecting between the common electrode line and the conductive object in the hole digging area 2, a via hole 24 can also be formed in the hole digging area 2, so that the conductive object can be connected with the common electrode line through the via hole 24. For example, referring to FIG. 16, which is a variant example of the driving substrate of FIG. 15, as shown in FIG. 16, the common electrode line can be in the same layer as the gate electrode, the gate line is also in the same layer as the gate electrode and is electrically connected with the gate electrode, and the common electrode line has a spacing with the gate line and the gate electrode. The hole digging area 2 penetrates to the second interlayer dielectric layer 16, the bottom is located in the first interlayer dielectric layer 14, and does not penetrate the first interlayer dielectric layer 14. When connecting the conductive object and the common electrode line, a hole can be further formed in the hole digging area 2 to obtain a via hole 22, through which the conductive object and the common electrode line can be overlapped to realize electrical connection between them. When this example is used, a larger hole digging area 2 can be formed first, and then a smaller via hole can be formed in the larger hole digging area 2. In this way, the depth of the hole digging area 2 can be prevented from being too deep, and the risk of lateral over-etching to the thin film transistor 15 can be avoided, thereby ensuring the device yield.

[0144] In an embodiment, one hole digging area 2 or multiple hole digging areas 2 can be included, and in the case of multiple hole digging areas 2, different hole digging areas 2 can be located at different positions of the display area 1, and the driving substrate can also include multiple common electrode lines, and the orthographic projections of the multiple hole digging areas 2 on the substrate 13 can not overlap each other.

[0145] In the embodiment, different hole digging areas 2 can correspond to the same common electrode line. For example, the conductive objects in the multiple hole digging areas 2 can be electrically connected with the same common electrode line. For example, referring to FIG. 17, which shows a wiring diagram on the driving substrate, as shown in FIG. 17, the common electrode line can include a first common electrode line C2 arranged around the display area 1, and multiple second common electrode lines C2 arranged in the first direction of the display area 1, the multiple second common electrode lines C2 are connected with the first common electrode line C1, then the multiple hole digging areas 2 can correspond to the first common electrode line C1, specifically, the conductive objects in the multiple hole digging areas 2 can be electrically connected with the first common electrode line C1, and the second common electrode lines C2 located in the display area 1 can bypass the hole digging area 2, as shown in FIG. 17, the second common electrode line C2 can be routed around the hole digging area 2 at the hole digging area 2, specifically, the wire can be routed in the gap between the hole digging area 2 and the second sub-display area 12, or the wire can be routed in the gap between the hole digging area 2 and the first sub-display area 11.

[0146] In yet another example of the present embodiment, different hole digging areas 2 can correspond to different common electrode lines, and further, the orthographic projections of different hole digging areas 2 on the substrate 13 can overlap with different common electrode lines. For example, referring to FIG. 18, FIG. 18 shows another wiring diagram on the driving substrate. As shown in FIG. 18, the common electrode lines can include a first common electrode line arranged around the display area 1, and a plurality of second common electrode lines arranged in a first direction of the display area 1, the plurality of second common electrode lines being connected with the first common electrode line, and the plurality of hole digging areas 2 can correspond to different second common electrode lines, specifically, the orthographic projections of the plurality of hole digging areas 2 on the substrate 13 can overlap with or not overlap with different second common electrode lines, and the conductive objects in the plurality of hole digging areas 2 can be electrically connected with different second common electrode lines.

[0147] In this embodiment, the plurality of common electrode lines on the driving substrate can be connected with the common electrode lines at different positions on the driving substrate, and the plurality of hole digging areas 2 can be connected with the common electrode layer on the paper film, thereby providing balanced common voltage for the common electrode layer on the paper film, so as to improve the uniformity of the electric field between the driving substrate and the paper film, so that the luminance of the electronic paper at different positions can be kept balanced, thereby improving the display quality.

[0148] In some embodiments, the aperture of the hole digging area 2 can be 2-3 mm, which can refer to the size of the hole digging area 2 in the planar direction of the substrate 13. Specifically, since the hole digging area 2 has a certain depth, the aperture of the hole digging area 2 at different depths can have differences. In the present embodiment, the aperture of the hole digging area 2 can refer to the average aperture of the hole digging area 2.

[0149] Specifically, the aperture of the hole digging area 2 can be 2 mm, 2.2 mm, 2.23 mm, 2.4 mm, 2.5 mm, 2.8 mm, or 3 mm.

[0150] In some embodiments, a plurality of signal lines can be arranged on the driving substrate, and the plurality of signal lines can include data lines, gate lines, and common electrode lines. In the case of arranging the hole digging area 2 in the display area 1 and outside the display area 1, the plurality of signal lines can bypass the hole digging area 2. Specifically, the substrate 13 further includes a plurality of signal lines on one side, and the plurality of signal lines include gate lines and data lines, and the gate lines and the data lines cross to define a plurality of sub-pixel regions; at least one signal line bypasses the perimeter of the hole digging area 2 at the position of the hole digging area 2.

[0151] In the present embodiment, the signal line bypassing the perimeter of the hole digging area 2 at the position of the hole digging area 2 can be understood as the signal line bypassing the edge of the hole digging area 2 at the position of the hole digging area 2.

[0152] Specifically, one side of the substrate 13 includes a plurality of gate lines and a plurality of data lines, the gate lines can run along a first direction x of the substrate 13, the data lines can run along a second direction y of the substrate 13, the first direction and the second direction are orthogonal, then according to the spacing between the gate lines, the spacing between the data lines, at least one gate line needs to run at the position of the hole digging area 2, due to the existence of the hole digging area 2, the gate line needs to run around the hole digging area 2; or, at least one data line needs to run at the position of the hole digging area 2, so that the data line needs to run around the hole digging area 2. Or, at least one gate line and at least one data line need to run around the hole digging area 2.

[0153] Exemplarily, please refer to FIG. 19, FIG. 19 shows a wiring diagram of a driving substrate, as shown in FIG. 19, one side of the driving substrate includes a plurality of gate lines arranged along a first direction x, and a plurality of data lines arranged along a second direction y, wherein, a hole digging area 2 is included, a gate line and a data line near the hole digging area 2 both need to run around the hole digging area 2.

[0154] Of course, in some examples, the plurality of signal lines can also include a common electrode line, then the signal line running around the hole digging area 2 can also include the common electrode line, as shown in FIG. 19 and FIG. 17, in one of the examples, if the hole digging area 2 is connected with the first common electrode line surrounding the periphery of the display area 1, and does not overlap with the second common electrode line in the display area 1, then there is also a common electrode line running around the hole digging area 2.

[0155] In some embodiments, the signal line running around the hole digging area 2 can be determined according to the film layer penetrated by the hole digging area 2. Exemplarily, in combination with FIG. 12-FIG. 16, if the hole digging area 2 penetrates the film layer above the gate line and the data line, please refer to FIG. 12, then the gate line and the data line at the hole digging area 2 both need to run around the hole digging area 2. If the hole digging area 2 does not penetrate the film layer above the gate line (the first interlayer dielectric layer 14 or the gate insulating layer), as shown in FIG. 14 and FIG. 13, then the gate line is protected by the insulating film layer between the gate line and the hole digging area 2, so the gate line can not need to run around the hole digging area 2, the data line and the common electrode line at the hole digging area 2 can run around the hole digging area 2. If the data line and the gate line are both located between the hole digging area 2 and the substrate 13, such as the hole digging area 2 penetrating the encapsulation layer 17, as shown in FIG. 15, then the data line and the gate line can not need to run around the hole digging area 2, while the common electrode line at the hole digging area 2 can run around the hole digging area 2.

[0156] In some embodiments, for the signal line that needs to be routed around the hole region, the signal line can be routed in an arc shape around the hole region 2 and / or in a zigzag shape at the position of the hole region 2. As described in the above embodiments, the orthographic projection of the hole region 2 on the substrate 13 can be a circle, an ellipse or a polygon, and the signal line routed around the hole region 2 can have the same shape as the edge of the hole region 2 or a different shape. For example, if the hole region 2 is a circle, the signal line routed around the hole region 2 can be routed in an arc shape around the hole region 2, or in a zigzag shape, or first in an arc shape and then in a zigzag shape, or first in a zigzag shape and then in an arc shape.

[0157] In this way, for the same signal line routed around the hole region 2, the signal line can be routed in an arc shape around the hole region 2, or in a zigzag shape, or in a combination of an arc shape and a zigzag shape.

[0158] It should be noted that for the signal line routed around the hole region 2, after being routed around the hole region 2 at the hole region 2, the part of the signal line not located at the hole region 2 can be routed in a straight line. For example, after being routed around the hole region 2 at the hole region 2, the gate line can be routed in the first direction x. For another example, after being routed around the hole region 2 at the hole region 2, the data line can be routed in the second direction y.

[0159] In some embodiments, if there are multiple signal lines that need to be routed around the hole region 2, the shapes of the multiple signal lines routed around the hole region 2 can be the same or different. For example, the multiple signal lines can all be routed in an arc shape around the hole region 2, or all be routed in a zigzag shape, or some of the signal lines are routed in an arc shape around the hole region 2 and the remaining signal lines are routed in a zigzag shape around the hole region 2. For example, as shown in FIG. 19, the gate line, the data line and the common electrode line are routed around the hole region 2 at the hole region 2, and specifically, the gate line, the data line and the common electrode line are all routed in an arc shape around the hole region 2 at the hole region 2.

[0160] In some other embodiments, if there are multiple signal lines that need to be routed around the hole region 2, the multiple signal lines can be routed around the hole region 2 at different positions of the hole region 2.

[0161] In the embodiments, as shown in FIG. 19, the multiple signal lines routed around the hole region 2 can include multiple signal lines, and the multiple signal lines can be routed in the same direction, such as in the first direction x or in the second direction y. Alternatively, the multiple signal lines can include the gate line and the data line routed in different directions, and the multiple signal lines can be routed around the hole region 2 at different positions of the hole region 2. The different positions of the hole region 2 can refer to different positions of the edge of the hole region 2. For example, if the hole region 2 is a circle, the different positions of the hole region 2 can refer to different arc segments of the circle.

[0162] For example, referring to FIG. 20, which shows a wiring schematic of the lower left corner of the hole-digging area 2 in (b) of FIG. 1, as shown in FIG. 20, the data lines and the gate lines are routed around the hole-digging area 2 at the hole-digging area 2, wherein the gate lines are routed on the upper arc segment of the hole-digging area 2, and the data lines are routed on the right arc segment of the hole-digging area 2.

[0163] For example, referring to FIG. 20, which shows a wiring schematic of the lower left corner of the hole-digging area 2 in (b) of FIG. 1, as shown in FIG. 20, the data lines and the gate lines are routed around the hole-digging area 2 at the hole-digging area 2, wherein the gate lines are routed on the upper arc segment of the hole-digging area 2, and the data lines are routed on the right arc segment of the hole-digging area 2.

[0164] In the present embodiment, the different sides of the hole-digging area can include the opposite sides of the hole-digging area in the extension direction of the gate lines, and the opposite sides of the hole-digging area in the extension direction of the data lines. Of course, in practice, it is not limited to this, for example, if the hole-digging area is circular, then the opposite sides of any one diameter of the circle are also referred to as different sides of the hole-digging area.

[0165] For example, referring to FIG. 20, which shows a wiring schematic of the lower left corner of the hole-digging area 2 in (b) of FIG. 1, as shown in FIG. 20, the data lines and the gate lines are routed around the hole-digging area 2 at the hole-digging area 2, wherein the gate lines are routed on the upper arc segment of the hole-digging area 2, and the data lines are routed on the right arc segment of the hole-digging area 2.

[0166] With such a routing design of the signal lines, the space near the hole-digging area 2 can be fully utilized, so that the plurality of signal lines routed around the hole-digging area 2 can be more evenly distributed around the hole-digging area 2.

[0167] In some embodiments, for the signal lines routed around the hole-digging area 2 at the hole-digging area 2, if there are a plurality of signal lines, then the routing line shape of the plurality of signal lines at the position of the hole-digging area 2 can be conformal to the edge of the hole-digging area 2.

[0168] In the present embodiment, the conformality can mean that the routing of the signal lines at the position of the hole-digging area 2 is substantially parallel to the edge of the hole-digging area 2, so that the routing linearity of the signal lines at the position of the hole-digging area 2 is substantially the same as the shape of the edge of the hole-digging area 2. Wherein, the substantially parallel can mean that the intersection angle between the routing of the signal lines at the hole-digging area 2 and the edge of the hole-digging area 2 is 0-3 degrees.

[0169] In a further example, for the plurality of signal lines conforming to the edge of the hole digging area 2 at the position of the hole digging area 2, the plurality of signal lines can be routed in the same direction, such as being routed in the first direction x or being routed in the second direction y, so that, in the case that the routing line shape of the signal lines at the position of the hole digging area 2 conforms to the edge of the hole digging area 2, the plurality of signal lines routed in the same direction can be kept in a balanced spacing, thereby avoiding short circuit between the signal lines.

[0170] In some embodiments, the routing of the signal lines at the hole digging area 2 can also be determined according to the position of the hole digging area 2. For example, when the hole digging area 2 is arranged in the display area 1, if the plurality of signal lines need to be routed around the hole digging area 2, the plurality of signal lines can be routed around the hole digging area 2 at different positions of the hole digging area 2. For another example, when the hole digging area 2 is arranged close to the peripheral area 4, if the plurality of signal lines need to be routed around the hole digging area 2, the plurality of signal lines can be routed around the hole digging area 2 at the same position of the hole digging area 2.

[0171] Specifically, in the case that the hole digging area 2 is located on the side of the display area 1 close to the peripheral area 4, the plurality of signal lines can be routed around the hole digging area 2 in the circumferential direction of the hole digging area 2 on the side of the hole digging area 2 close to the display area 1.

[0172] In the embodiments, the case that the hole digging area 2 is located on the side of the display area 1 close to the peripheral area 4 can include the case that the hole digging area 2 is located outside the display area 1, such as shown in FIG. 7, in which the hole digging area 2 is located outside the display area 1, and can include the case that the hole digging area 2 is located inside the display area 1 and on the edge of the display area 1. For example, as shown in FIG. 8, the hole digging area 2 is located inside the display area 1, but the hole digging area 2 is located on the edge of the display area 1.

[0173] In the embodiments, when the hole digging area 2 is arranged close to the peripheral area 4, the signal lines need to be arranged close to the display area 1, and the plurality of signal lines can be routed around the hole digging area 2 in the circumferential direction of the hole digging area 2 on the side of the hole digging area 2 close to the display area 1, which can also be understood as that the plurality of signal lines are routed on the same side of the hole digging area 2. In combination with the above embodiments, in the case that the plurality of signal lines are routed around the hole digging area 2, the routing of the plurality of signal lines at the hole digging area 2 can be circular arc routing and / or polyline routing, and in the embodiments, the plurality of signal lines can be circular arc routed and / or polyline routed around the hole digging area 2 on the same side of the hole digging area 2, wherein the routing of the plurality of signal lines at the hole digging area 2 can be substantially parallel.

[0174] For example, please refer to FIG. 21, which shows a schematic diagram of the routing at the hole digging area 2 of FIG. 7(a), as shown in FIG. 21, the hole digging area 2 is located outside the second sub-display area 12, and the plurality of gate lines and the plurality of data lines are routed at the hole digging area 2, wherein the gate lines and the data lines can be polyline routed at the position of the hole digging area 2.

[0175] More specifically, in some embodiments, the cutout region is located outside the display region and close to one side of the display region, and the plurality of signal lines are routed along the circumferential direction of the cutout region close to the one side of the display region. As shown in FIG. 21, the cutout region 2 is located outside the second sub-display region 12 and close to the display region. Here, close to the display region can mean that the cutout region is close to the edge of the display region, such as immediately adjacent to the edge of the display region, or that the cutout region is close to the end corner of the display region, such as immediately adjacent to the end corner region of the display region. Specifically, there can be a gap between the cutout region and the display region, or there can be no gap, for example, as shown in FIG. 21, there is a gap between the cutout region and the second sub-display region 12 in the display region, and of course, in other examples, there can be no gap between the edge of the cutout region and the display region. Here, the gap refers to a region located in the peripheral region and between the edge of the cutout region and the display region, and there can be signal line routing or no signal line routing in the gap.

[0176] In this embodiment, the plurality of signal lines can be routed on the same side of the cutout region 2, and specifically, as shown in FIG. 21, the plurality of signal lines are routed on the side of the cutout region 2 close to the display region, and there is no signal line routing on the side of the cutout region 2 away from the display region. In this example, the plurality of signal lines can include data lines, gate lines, and common electrode lines, and these signal lines can be routed in the form of zigzag lines, arc lines, etc. on the side of the cutout region close to the display region.

[0177] In some embodiments, the data lines, the gate lines, and the common electrode lines can be located in different film layers, and in this case, even if the data lines, the gate lines, and the common electrode lines are all routed around the cutout region 2 at the cutout region 2, the data lines, the gate lines, and the common electrode lines will not be short-circuited.

[0178] In some embodiments, as shown in FIG. 21, when the plurality of signal lines are routed around the cutout region 2 at the position of the cutout region 2, the routing space is small, and for the same type of signal lines, such as two gate lines or two data lines, there is a risk of short-circuiting. To avoid short-circuiting between the plurality of signal lines, adjacent two signal lines among the plurality of signal lines at the cutout region 2 can be located in different film layers.

[0179] In one example of the embodiment, for the plurality of signal lines around the hole digging area 2 at the hole digging area 2, each two adjacent signal lines can be located in different film layers. For example, as shown in FIG. 21, two adjacent gate lines are around the hole digging area 2 at the hole digging area 2, then the gate line VG1 and the gate line VG2 among the two gate lines can be located in different film layers at the hole digging area 2, and the gate line VG1 and the gate line VG2 can be located in the same film layer in the area away from the hole digging area 2. For another example, as shown in FIG. 22, two adjacent data lines are around the hole digging area 2 at the hole digging area 2, then the data line VD1 and the data line VD2 among the two data lines can be located in different film layers at the hole digging area 2, and the data line VD1 and the data line VD2 can be located in the same film layer in the area away from the hole digging area 2.

[0180] In a further example of the embodiment, for two adjacent signal lines transmitting the same type of signal, they can be arranged in the same layer in the area away from the hole digging area 2, and can be arranged in different layers at the position of the hole digging area 2.

[0181] For example, referring to FIG. 22, FIG. 22 shows a schematic diagram of the cross-sectional structure related to the wiring at the hole digging area 2. As shown in FIG. 22, the data lines and the gate lines are in different layers, and both the two data lines and the two gate lines need to be around the hole digging area 2 at the hole digging area 2. For the two adjacent data lines, they are located in different film layers at the hole digging area 2, and can be arranged in the same layer in the area away from the hole digging area 2. For the two adjacent gate lines, they are located in different film layers at the hole digging area 2, and can be arranged in the same layer in the area away from the hole digging area 2.

[0182] In combination with the above embodiment, at least one signal line is around the hole digging area 2 at the hole digging area 2, then there is at least one signal line with special-shaped wiring on the driving substrate. In this way, the wiring distance of the signal line around the hole digging area 2 is increased, which can cause the impedance to change. In the case that there are more signal lines around the hole digging area 2, the spacing between the signal lines is small and can be non-uniform, and the problem of signal crosstalk can occur. In a further example of the embodiment, the connection relationship between the gate lines, the data lines and the sub-pixels 111 can be improved, so that the sub-pixels 111 controlled by the signal lines (the gate lines and the data lines) with special-shaped wiring are uniformly distributed in the picture, thereby avoiding the problem of display quality decline caused by the impedance change and the signal crosstalk.

[0183] In specific implementation, the number of gate lines can be reduced and the number of data lines can be increased. Specifically, a plurality of gate line leads and a plurality of data line leads can be included, and the plurality of gate line leads and the plurality of data line leads can be routed in the peripheral area. One gate line lead is connected to two adjacent rows of sub-pixels 111, one column of sub-pixels 111 is respectively connected to two adjacent first data line leads and second data line leads, and in any two adjacent sub-pixels 111 in the same column, one sub-pixel 111 is connected to the first data line lead and the other sub-pixel 111 is connected to the second data line lead.

[0184] In this embodiment, the data line of each sub-pixel 111 can be increased, so that one data line controls two sub-pixels 111 that are spaced apart. Since the resolution of the display screen of the electronic paper is not high, the pixels controlled by the special-shaped lines are uniformly distributed in the screen, and the human eye intuitively feels that this is not obvious, so that the electronic paper screen displays normally, and the side bezel can be reduced.

[0185] Please refer to FIGS. 23-26, FIGS. 23 and 24 respectively show two wiring diagrams of the driving substrate, FIG. 25 shows a sub-pixel 111 design diagram of the driving substrate of FIG. 23, and FIG. 26 shows a sub-pixel 111 design diagram of the driving substrate of FIG. 24. Next, the wiring of the driving substrate and the design of the sub-pixel 111 will be described by way of example with reference to FIGS. 23-26.

[0186] As shown in FIGS. 19, 23 and 24, the driving substrate includes a driving chip 5 and a flexible circuit board 6. The plurality of gate line leads G1 and the plurality of data line leads D1 are connected to the driving chip 5. The driving chip 5 outputs a scanning signal to the plurality of gate line leads and outputs a data signal to the data line leads. The plurality of gate line leads are routed in the peripheral area 4, for example, on the left and right sides of the display area 1, and need to occupy the peripheral area 4 on the left and right sides of the display area 1. The data line leads can be routed in the display area 1 after being routed in the fan-out area of the peripheral area 4, and do not need to occupy the peripheral area 4 on the left and right sides of the display area 1. One gate line lead is used to transmit a scanning signal to the sub-pixels 111 in the display area 1, and one data line lead is used to transmit a data signal to the sub-pixels 111 in the display area 1. Specifically, one end of the data line lead is connected to the driving chip 5, and the other end can be connected to one column of sub-pixels 111 in the display area 1. One end of the gate line lead is connected to the driving chip 5, and the other end can be connected to two adjacent rows of sub-pixels 111 in the display area 1.

[0187] Specifically, the gate line lead is connected to one pin of the driving chip 5, and the data line lead is connected to one pin of the driving chip 5.

[0188] As shown in FIG. 19, the gate line leads are routed from the left and right peripheral areas 4, and as shown in FIG. 19, one data lead is connected to each column of sub-pixels 111, and one gate line lead is connected to each row of sub-pixels 111. Among them, the frame of the electronic paper design is closely related to the resolution, for example, for a product with a resolution of N*M, the space used by the single-side gate line is N / 2 gate lines, and the space required by the single-side frame is calculated by the formula:

[0189] X = p * (N / 2) + K,

[0190] X: space required by the side frame

[0191] P: pitch of each Gate line

[0192] N: Gate resolution

[0193] K: width required by other designs

[0194] Therefore, the larger the resolution N is, the larger the frame K required is. In the case of resolution improvement, the consequence is that the frame distance required by the design side becomes larger. The product with a large frame not only increases the cost, but also affects the overall design of the product.

[0195] In this embodiment, in order to reduce the frame size and avoid the problem of display quality degradation caused by impedance change and signal crosstalk, the number of gate line leads routed in the peripheral area 4 can be reduced. In this way, one pin of the driving chip 5 is connected to one gate line lead and controls two adjacent rows of sub-pixels 111, and the data lead can be doubled. Thus, the number of gate line leads required to be routed in the peripheral area 4 is reduced, thereby reducing the frame size.

[0196] Specifically, as shown in FIGS. 23 and 24, each row of gate line signals is output from the driving chip 5 to control two rows of sub-pixels 111. For example, each gate line lead is routed on the left and right sides of the display area 1 and then connected to the adjacent two rows of sub-pixels 111. In this way, the single-side frame is X1 = p * (N / 4) + K, and the space required by the signal line is X1 = 0.5X, which is half of the design in FIG. 19. The frame can be reduced by 50% compared with the conventional design.

[0197] When using such a driving substrate, as shown in FIGS. 25 and 26, the scanning signal output on one gate line lead can control the thin film transistors 15 of two rows of sub-pixels 111 to be turned on, for example, the thin film transistors 15 of the i-th row of sub-pixels 111 and the i+1-th row of sub-pixels 111 are controlled to be turned on. Since each column of sub-pixels 111 is connected to two data lines, the two data lines respectively input data signals to the i-th row of sub-pixels 111 and the i+1-th row of sub-pixels 111 located in the same column, thereby controlling the i-th row of sub-pixels 111 and the i+1-th row of sub-pixels 111 in the same column to be lit. By analogy, two rows of sub-pixels 111 can be lit at a time.

[0198] Since one gate line lead corresponds to two rows of adjacent sub-pixels 111, in some embodiments, a plurality of gate lines VG are included in the display area 1, and the plurality of gate lines VG run along the first direction x, then one gate line lead G1 can connect two gate lines VG to connect two rows of adjacent sub-pixels 111, or one gate line lead G1 can connect one gate line VG to connect two rows of adjacent sub-pixels 111.

[0199] Please refer to FIG. 23, which shows a case where one gate line lead G1 can connect two gate lines VG to connect two rows of adjacent sub-pixels 111, specifically, there are inter-row gaps between adjacent two rows of sub-pixels 111, and the display area 1 includes a plurality of gate lines, and the orthogonal projections of the plurality of gate lines on the substrate 13 are located in different inter-row gaps; wherein, adjacent two gate lines are connected with adjacent two rows of sub-pixels 111 respectively, and the adjacent two gate lines are connected with the same gate line lead.

[0200] In this embodiment, the inter-row gap can refer to the gap between the orthogonal projections of adjacent two rows of sub-pixels 111 on the substrate.

[0201] As shown in FIG. 23, in this example, one end of the gate line lead is connected with the driving chip 5, and the other end runs along the left and right sides of the display area 1 and the binding area, and then is connected with two gate lines running along the first direction x, and the two gate lines connected with the same gate line lead are connected with adjacent two rows of sub-pixels 111 respectively, and the two gate lines can be located in different inter-row gaps, so that the spacing between the gate lines can be increased. In this way, the number of gate lines in the display area 1 can be the same as the number of rows of sub-pixels 111, for example, including N rows of sub-pixels 111, then the display area 1 can include N gate lines, but the peripheral area 4 includes N / 2 gate line leads.

[0202] In this way, in the display area 1, each row of sub-pixels 111 has a gate line connected with it, please refer to FIG. 25, then in the corresponding sub-pixel 111 design, the thin film transistors 15 of different rows of sub-pixels 111 can be located in different inter-row gaps, and this design can reduce the wiring difficulty of the gate lines and the thin film transistors 15 of the sub-pixels 111.

[0203] Please refer to FIG. 24, which shows a case where one gate line lead G1 can connect one gate line VG, and one gate line VG is connected with two rows of adjacent sub-pixels 111, specifically, there are inter-row gaps between adjacent two rows of sub-pixels 111, and the display area 1 includes a plurality of gate lines, and the orthogonal projections of the plurality of gate lines on the substrate 13 are located in different inter-row gaps; wherein, different gate lines in the display area 1 are connected with different gate line leads, and one gate line is connected with the gate electrodes of the thin film transistors 15 of two rows of sub-pixels 111 simultaneously.

[0204] Thus, in the display area 1, the thin film transistors 15 of the two adjacent rows of sub-pixels 111 are connected to one gate line, as shown in FIG. 26, and in the corresponding sub-pixel 111 design, the thin film transistors 15 of the two adjacent rows of sub-pixels 111 can be located in the same inter-row gap. With this design, the number of gate lines in the display area 1 can be reduced, thereby reducing the occupation of the wiring space of the display area 1 by the gate lines, and thus reducing the number of signal lines that need to be routed through the cutout area 2. As a result, the sub-pixels 111 controlled by the signal lines (gate lines and data lines) of the irregular shape can be uniformly distributed in the picture, thereby avoiding the problem of display quality degradation caused by impedance variation and signal crosstalk.

[0205] Please continue to refer to FIGS. 25 and 26, in some embodiments, the connection of the gate line and the data line to the sub-pixel 111 can mean that the gate line is connected to the gate electrode of the thin film transistor 15 of the sub-pixel 111, and the data line is connected to the source electrode 157 of the thin film transistor 15 of the sub-pixel 111. In the case where one gate line lead is connected to two adjacent rows of sub-pixels 111, the gate line lead can be connected to the gate electrodes of the thin film transistors 15 of the two adjacent rows of sub-pixels 111, and the thin film transistors 15 of the two adjacent rows of sub-pixels 111 can be mirror-imaged.

[0206] Specifically, in the first sub-pixel 111 and the second sub-pixel 111 connected to the same gate line lead and adjacent in the column direction, the orthographic projection of the thin film transistor 15 of the first sub-pixel 111 on the substrate 13 is a mirror image of the orthographic projection of the thin film transistor 15 of the second sub-pixel 111 on the substrate 13.

[0207] In this embodiment, the first sub-pixel 111 and the second sub-pixel 111 are sub-pixels 111 located in the same column and in adjacent rows, and the orthographic projection of the thin film transistor 15 of the first sub-pixel 111 on the substrate 13 is a mirror image of the orthographic projection of the thin film transistor 15 of the second sub-pixel 111 on the substrate 13.

[0208] For example, as shown in FIGS. 23 and 25, in the case where the first sub-pixel 111 and the second sub-pixel 111 are connected to two gate lines in the display area 1, i.e., two adjacent gate lines are connected to two adjacent rows of sub-pixels 111, and the two adjacent gate lines are connected to the same gate line lead, the thin film transistors 15 of the first sub-pixel 111 and the second sub-pixel 111 can be located in different inter-row gaps, respectively, and the orthographic projection of the thin film transistors 15 of the first sub-pixel 111 and the second sub-pixel 111 on the substrate 13 is mirror-symmetric about the direction of the data line.

[0209] For another example, referring to FIGS. 24 and 26, in the case where the first sub-pixel 111 and the second sub-pixel 111 are connected to one gate line in the display area 1, i.e., one gate line is connected to two adjacent rows of sub-pixels 111 respectively, and a plurality of gate lines are connected to a plurality of different gate line leads, the thin film transistor 15 of the first sub-pixel 111 and the thin film transistor 15 of the second sub-pixel 111 can be located in the same row gap, and the orthographic projection of the thin film transistor 15 of the first sub-pixel 111 and the thin film transistor 15 of the second sub-pixel 111 on the substrate 13 can be mirror-symmetrical about the direction of the gate line.

[0210] With such a mirror-symmetrical arrangement of the thin film transistor 15, the film layers on the driving substrate can be shifted left and right or obliquely, and the Cgs between the first sub-pixel 111 and the second sub-pixel 111 can remain horizontally consistent, where the Cgs can refer to the capacitance formed between the gate line and the pixel electrode of the thin film transistor 15.

[0211] Next, the driving substrate of the present disclosure is exemplarily described in combination with two examples. Referring to FIG. 27, FIG. 27 shows a structural schematic diagram of the driving substrate in the present example.

[0212] Example A, referring to FIGS. 27 and 12, the driving substrate of the present example A comprises:

[0213] The substrate 13 is a glass substrate 13;

[0214] The display area 1 and the peripheral area 4 surrounding the display area 1 are included on one side of the substrate 13, where the display area 1 comprises a first sub-display area 11 and a second sub-display area 12, the first sub-display area 11 comprises a plurality of sub-pixels 111, and the second sub-display area 12 surrounds the first sub-display area 11 as the boundary between the display area 1 and the peripheral area 4, where the second sub-display area 12 is provided with a metal layer.

[0215] The sub-pixel 111 comprises a thin film transistor 15, and the thin film transistor 15 comprises:

[0216] A gate electrode located on one side of the substrate 13;

[0217] A gate insulating layer located on the side of the gate electrode away from the substrate 13;

[0218] An active layer located on the side of the gate insulating layer away from the substrate 13, the active layer comprises a channel region, and the orthographic projection of the channel region on the substrate 13 overlaps with the orthographic projection of the gate electrode on the substrate 13;

[0219] A source / drain electrode located on the side of the active layer away from the substrate 13, where the source / drain electrode comprises a source electrode 157 and a drain electrode 152, and the source electrode 157 and the drain electrode 152 are overlapped with the active layer.

[0220] The hole digging area 2 is arranged in the display area 1 and between the first sub display area 11 and the second sub display area 12, and the hole digging area 2 can be arranged at the end corner of the second sub display area 12, and the orthographic projection of the hole digging area 2 on the substrate 13 is a circle.

[0221] A plurality of gate lines and a plurality of data lines are arranged in the display area 1, and the plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions, each of which is provided with a sub-pixel, the sub-pixel comprising a thin film transistor as described above, and a pixel electrode connected to the drain of the thin film transistor, wherein the gate line is connected to the gate of the thin film transistor, and the data line is connected to the source of the thin film transistor.

[0222] The gate line and the data line at the hole digging area 2 are arranged around the hole digging area 2, specifically, the gate line and the data line at the hole digging area 2 can be circularly arranged at different sides of the hole digging area 2, and the gate line and the data line are arranged in different layers.

[0223] The driving chip 5 and the flexible circuit board are arranged in the peripheral area 4, wherein the driving chip 5 is connected to the flexible circuit board, the driving chip 5 is connected to the plurality of gate lines and the plurality of data lines, specifically, referring to FIG. 24, the driving chip 5 is connected to a plurality of gate line leads, each of which is arranged in the peripheral area 4 and connected to the plurality of gate lines in the display area 1, one gate line lead is connected to one gate line, one gate line is connected to the gate of the thin film transistor 15 of the sub-pixel 111 in two adjacent rows, and one column of sub-pixels 111 is connected to two data lines, that is, the first sub-pixel 111 in one column of sub-pixels 111 is connected to one data line, and the second sub-pixel 111 is connected to another data line.

[0224] For the two adjacent rows of sub-pixels 111, the orthographic projection of the thin film transistor 15 of the first sub-pixel 111 in the same column on the substrate 13 is a mirror image of the orthographic projection of the thin film transistor 15 of the second sub-pixel 111 in the same column on the substrate 13, as shown in FIG. 26, the orthographic projection of the thin film transistor 15 of the first sub-pixel 111 and the thin film transistor 15 of the second sub-pixel 111 on the substrate 13 is mirror symmetric along the first direction x.

[0225] The common electrode line includes a first common electrode line and a second common electrode line, the first common electrode line is connected to the flexible circuit board and is arranged around the peripheral area, and the plurality of second common electrode lines can be arranged along the first direction x or the second direction y, and the plurality of second common electrode lines pass through the display area.

[0226] The short-circuit ring line SR can be located on the left and right sides of the display area 1, and is connected with the gate line lead through an ESD to collect static electricity on the driving substrate to avoid signal crosstalk caused by static electricity.

[0227] The detection line PB is arranged around the display area 1, and the detection line PB is connected with the driving chip 5, and the driving chip 5 is used to output a test signal to the detection line PB to detect whether the edge of the driving substrate is damaged.

[0228] In example B, as shown in FIG. 27 and FIG. 20, the driving substrate of example B is different from the driving substrate of example A in that the cutout area 2 is located outside the display area 1, specifically, on the side of the second sub-display area 12 away from the first sub-display area 11, and the second sub-display area 12 has a notch area, and the cutout area 2 is located in the notch area. The gate line and the data line are folded and routed around the cutout area 2 on the side of the cutout area 2 close to the display area 1.

[0229] In example C, as shown in FIG. 27 and FIG. 23, the driving substrate of example C is different from the driving substrate of example A in that each gate line lead is routed in the peripheral area 4 and connected with a plurality of gate lines in the display area 1. One gate line lead connects two gate lines. One gate line is connected with the gate electrode of the thin film transistor 15 of one row of sub-pixels 111. One column of sub-pixels 111 is cross-connected with two data lines, that is, the first sub-pixel 111 in one column of sub-pixels 111 is connected with one data line, and the second sub-pixel 111 is connected with another data line. For the adjacent two rows of sub-pixels 111, the orthographic projection of the thin film transistor 15 of the first sub-pixel 111 located in the same column on the substrate 13 is a mirror image of the orthographic projection of the thin film transistor 15 of the second sub-pixel 111 located in the same column on the substrate 13. As shown in FIG. 25, the orthographic projection of the thin film transistor 15 of the first sub-pixel 111 and the orthographic projection of the thin film transistor 15 of the second sub-pixel 111 on the substrate 13 are mirror symmetrical along the second direction y.

[0230] Based on the same inventive concept, the disclosure also provides an electronic paper display module, which comprises the driving substrate of any of the above-mentioned embodiments.

[0231] A paper film is packaged with the driving substrate, and the paper film comprises a common electrode layer.

[0232] A conductive object is located in the cutout area 2 of the driving substrate.

[0233] The common electrode layer is connected with the common electrode line on the driving substrate through the conductive object.

[0234] Please refer to FIG. 28, which shows a cross-sectional structure diagram of the electronic paper display module. As shown in FIG. 28, the electronic paper display module includes a driving substrate 10, a paper film 20 attached to one side of the driving substrate 10, and a protective film 30 attached to the side of the paper film 20 away from the driving substrate. The two sides of the protective film, the driving substrate, and the paper film can be filled with a water-blocking glue to prevent water vapor from entering the driving substrate and the paper film. The driving chip 5 and the flexible circuit board are bound to the peripheral area 4 of the driving substrate. The flexible circuit board and the driving chip 5 are filled with white glue to achieve insulation performance and protect the flexible circuit board and the driving chip 5 from water erosion.

[0235] In the case where the display area 1 of the driving substrate includes the first sub-display area 11 and the second sub-display area 12, the paper film can cover the first sub-display area 11 and the second sub-display area 12.

[0236] In this embodiment, the paper film is provided with a common electrode layer. The common electrode layer can be electrically connected to the common electrode line on the driving substrate through a conductive object in the hole area 2. The conductive object can be silver glue.

[0237] The electronic paper display module using this embodiment has a regular area occupied by the display area and the hole area on the substrate. Therefore, the hole area and the display area can form a more compact pattern, avoiding the situation that the hole area and the display area form a special-shaped pattern, which increases the frame length of the electronic paper and causes waste of materials such as the paper film, the protective film of the driving substrate, and the like, thereby reducing the production cost of the electronic paper.

[0238] Based on the same inventive concept, a display device is also provided. Please refer to FIG. 29, which shows an exploded structure diagram of the display device. As shown in FIG. 29, the display device can include the electronic paper display module of the above-mentioned embodiments, a cover plate, and a printed circuit board. The printed circuit board is connected to the flexible circuit board FPC of the electronic paper display module.

[0239] The size of the printed circuit board can be less than or equal to the size of the driving substrate. The printed circuit board can be the control circuit board of the entire display device.

[0240] In some embodiments, the display device can further include a display lamp 9, which can be located on the side of the paper film away from the driving substrate. The orthogonal projection of the display lamp on the substrate overlaps with the orthogonal projection of the hole area on the substrate. Specifically, since the hole area can be in the display area, the display lamp can cover the hole area, thereby covering the conductive object in the hole area. That is, the position of the display lamp is at least partially vertically above the silver paste point, thereby improving the aesthetics of the display module.

[0241] As shown in FIG. 30, the display module can be in various positions. For example, as shown in FIG. 30(c), the display lamp can be partially overlapped with the edge of the display area and located at the edge of the display area. For example, as shown in FIG. 30(b), the display lamp can be located at the end of the display area. For example, as shown in FIG. 30(a), the display lamp can be located in the display area and at the edge of the display area.

[0242] The display lamp can be an LED lamp, and the color of the LED lamp can be one of red R, green G, blue B, multi-color, and mixed color. The display lamp can be connected to the control chip or connected to the flexible circuit board. In this way, the display lamp can be connected to the printed circuit board through the flexible circuit board, so as to be controlled by the processor on the printed circuit board. The display lamp is arranged above the cover plate of the paper film, and the cover plate is used to encapsulate the electronic paper display module.

[0243] In some embodiments, the cover plate 1C of the display device includes an opening area 1C1, and the display lamp is located in the opening area. Specifically, the orthographic projection of the opening area on the substrate can cover the orthographic projection of the hole area on the substrate, and the display lamp can be located in the opening area and cover the hole area.

[0244] In some embodiments, the display device can be an electronic nameplate, an electronic doorplate, an electronic paper reader, or other EPD (Electronic Paper Display) products.

[0245] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0246] Finally, it should be noted that, in this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, product or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, product or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, product or equipment including the element.

[0247] The driving substrate, the electronic paper display module and the display device provided by the present disclosure are described in detail above, the principles and implementation manners of the present disclosure are described by applying specific examples in the present document, and the above description of the embodiments is only used to help understand the method of the present disclosure and the core idea thereof; meanwhile, for those skilled in the art, according to the idea of the present disclosure, the specific implementation manners and application ranges can be changed, and the above description of the present specification should not be understood as a limitation of the present disclosure.

[0248] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure as come within known or customary practice in the art to which the present disclosure pertains. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0249] It should be understood that the present disclosure is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made to the embodiments thereof without departing from the scope thereof. The scope of the present disclosure is limited only by the claims that follow.

[0250] As used herein, the terms “one embodiment”, “an embodiment” or “one or more embodiments” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

[0251] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been described in detail in order not to obscure the understanding of this description.

[0252] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim. The word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. The disclosure can be implemented by means of both hardware and software, and any combination thereof. In a unit claim, several elements can be presented in a dependent manner, connected with the conjunction “and” or “or”. Any of such conjunctions shall not be construed as limiting the scope of the claims. The word “first”, “second”, “third”, etc. do not denote any order. The mere fact that an element is recited as a means for performing a specified operation does not preclude other structure considered by those of ordinary skill to also perform that operation in conjunction with other operations.

[0253] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A drive substrate, wherein, The driving substrate comprises: a substrate comprising a display area and a peripheral area surrounding the display area; a plurality of sub-pixels located in the display area; and at least one cutout area, the plurality of sub-pixels bypassing the cutout area; wherein a normal projection of the cutout area on the substrate is located in a fitting area of the display area, the fitting area being an area enclosed by a regular figure after fitting edges of the display area, and all or part of the fitting area is the display area.

2. The drive substrate according to claim 1, wherein The display area comprises a first cutout area and / or a second cutout area, the first cutout area being located in the display area, and the second cutout area being located outside the display area; wherein at least one edge of the display area has a notch area that is recessed into the display area, and the second cutout area is located in the notch area.

3. The drive substrate according to claim 1 or 2, wherein The display area comprises a first sub-display area and a second sub-display area at least partially surrounding the first sub-display area, and a plurality of sub-pixels are located in the first sub-display area; wherein the fitting area is an area enclosed by a regular figure after fitting edges of the second sub-display area.

4. The drive substrate according to claim 3, wherein The display area comprises a third cutout area, and the third cutout area is located between the first sub-display area and the second sub-display area.

5. The drive substrate according to claim 1, wherein The fitting area is a regular polygon, and the cutout area is arranged at at least one end point of the fitting area; and / or, the cutout area is arranged at at least one edge of the fitting area.

6. The drive substrate according to claim 1, wherein One side of the substrate further comprises a plurality of common electrode lines, a plurality of gate lines and a plurality of data lines, the gate lines and the data lines intersecting to define a plurality of sub-pixel areas; wherein the common electrode lines are arranged in the same layer as the gate lines or the data lines; and / or, the common electrode lines are arranged in different layers from the gate lines and the data lines.

7. The drive substrate according to claim 1, wherein One side of the substrate further comprises a plurality of common electrode lines; the cutout area exposes the common electrode lines, or the cutout area is spaced apart from the common electrode lines by at least one film layer.

8. The drive substrate according to claim 1, wherein One side of the substrate further comprises a plurality of common electrode lines, and comprises a plurality of cutout areas; wherein different cutout areas correspond to different common electrode lines on the substrate.

9. The drive substrate according to claim 1, wherein One side of the substrate further comprises a plurality of signal lines, and the plurality of signal lines comprise gate lines, data lines and common electrode lines, the gate lines and the data lines intersecting to define a plurality of sub-pixel areas; wherein at least one of the signal lines is routed along the perimeter direction of the cutout area at the position of the cutout area.

10. The drive substrate according to claim 9, wherein The routing shape of at least one of the signal lines at the position of the cutout area is conformal to the edge of the cutout area.

11. The drive substrate according to claim 9, wherein The cutout area is located in the display area, and the plurality of signal lines are routed along the perimeter direction of the cutout area at different positions of the cutout area.

12. The drive substrate according to claim 9, wherein, The cutout area is located outside the display area and close to the edge of the display area, and the plurality of signal lines are routed along the perimeter direction of the cutout area on the side of the cutout area close to the display area.

13. The drive substrate according to any one of claims 9 to 12, wherein Among the plurality of signal lines located at the cutout area, two adjacent signal lines are located in different film layers, respectively.

14. The drive substrate according to claim 1, wherein One side of the substrate further comprises a plurality of gate line leads and a plurality of data line leads, and the gate line leads and the data line leads are routed in the peripheral area; One of the gate lines is electrically connected with two adjacent rows of the sub-pixels.

15. The drive substrate according to claim 14, wherein, The display area includes a plurality of gate lines, and the projections of the plurality of gate lines on the substrate are located in different inter-row gaps. Two adjacent gate lines are connected with two adjacent rows of the sub-pixels, and the two adjacent gate lines are connected with the same gate line lead.

16. The drive substrate of claim 14, wherein, The display area includes a plurality of gate lines, and the plurality of gate lines are connected with the plurality of gate line leads. One of the gate lines is connected with two adjacent rows of the sub-pixels.

17. The drive substrate according to any one of claims 14-16, wherein, The sub-pixels include thin film transistors. In first and second sub-pixels connected with the same gate line lead and adjacent in the column direction, the projection of the thin film transistor of the first sub-pixel on the substrate is a mirror image of the projection of the thin film transistor of the second sub-pixel on the substrate.

18. An electronic paper display module, wherein, The display device includes the driving substrate of any one of claims 1-17; and A paper film encapsulating the driving substrate, the paper film including a common electrode layer; A conductive object located in the hole region of the driving substrate; The common electrode layer is connected with the common electrode line on the driving substrate through the conductive object.

19. A display device comprising: The electronic paper display module includes the display device of claim 18. 20.The electronic paper display module of claim 19, wherein, The display device further includes: A display lamp located on the side of the paper film away from the driving substrate; The projection of the display lamp on the substrate overlaps with the projection of the hole region on the substrate.

21. The display device of claim 20, wherein, The display device further includes: A cover plate located on one side of the electronic paper display module; The cover plate includes an opening region, and the display lamp is located in the opening region.

Images