Inter-core communication method and device, storage medium, component and chip

Abstract

The invention discloses an inter-core communication method and device, a storage medium, a component and a chip, and relates to the technical field of chips, a first communication system comprises at least one first processor and a first inter-core communication component, and the first inter-core communication component responds to an access request of a target processor in a second communication system for target data in the first communication system. Filling the target data in a memory block corresponding to a target descriptor in the first inter-core communication component through the at least one first processor; the at least one first processor writes the target descriptor into the first inter-core communication component; and the first inter-core communication component sends the target data in the memory block to the second communication system based on the target descriptor. Compared with the prior art, the method does not need to depend on a processor in the system for control, simplifies the control task of the processor, and improves the data interaction efficiency between different communication systems.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an inter-core communication method, device, storage medium, component and chip. Background Technology

[0002] The inter-core communication methods of related technologies cannot meet the performance requirements of inter-core communication between the physical layer system and the protocol stack system in 5G scenarios, resulting in low communication efficiency between the physical layer system and the protocol stack system. Summary of the Invention

[0003] In view of this, this application provides an inter-core communication method, apparatus, storage medium, component, and chip.

[0004] In a first aspect, this application provides an inter-core communication method, executed by a first communication system, the first communication system including at least one first processor and a first inter-core communication component, the method comprising: In response to a target processor in the second communication system requesting access to target data in the first communication system, the target data is filled into the memory block corresponding to the target descriptor in the first inter-core communication component by the at least one first processor. The at least one first processor writes the target descriptor into the first inter-core communication component; The first inter-core communication component sends the target data in the memory block to the second communication system based on the target descriptor.

[0005] Optionally, based on the target descriptor, sending the target data in the memory block to the second communication system includes: Determine the transmission queue in the transmission channel of the target descriptor written by the at least one first processor in the first inter-core communication component; The target data is sent to the direct memory access module through the sending queue, so as to send the target data to the second communication system through the direct memory access module.

[0006] Optionally, sending the target data to the direct memory access module through the sending queue includes: Based on the queue priority information of the sending queue and the write time of the target descriptor in the sending queue, the processing priority corresponding to the target descriptor is determined; The target descriptor in the sending queue is sent to the direct memory access module according to the processing priority.

[0007] Optionally, sending the target descriptor in the sending queue to the direct memory access module according to the processing priority includes: The target descriptor in the sending queue is parsed according to the processing priority to determine the source data information corresponding to the target data. The source data information includes the source data address and the source data length. The source data and the target data are added to the access list of the direct memory access module, which is used by the direct memory access module for data transmission.

[0008] Optionally, after parsing the target descriptor in the sending queue according to the processing priority to determine the source data information corresponding to the target data, the method further includes: The first inter-core communication component updates the pointer position of the write pointer of the target processor according to the length of the source data; Add the updated first pointer position to the access list.

[0009] Optionally, updating the write pointer of the target processor based on the source data length includes: Based on the second pointer position of the write pointer before the update, the remaining length in the data buffer area corresponding to the target processor is determined, and the remaining length is the data length between the second pointer position in the data buffer area and the end position of the data buffer area. If the remaining length is less than the length of the source data, the starting position of the data buffer area is determined as the first pointer position.

[0010] Optionally, determining the starting position of the data buffer area as the first pointer position includes: Determine the position of the third pointer corresponding to the read pointer of the target processor; If the interval between the starting position and the third pointer position is greater than the length of the source data, the starting position of the data buffer area is determined as the first pointer position.

[0011] Optionally, after determining the position of the third pointer corresponding to the read pointer of the target processor, the method further includes: If the interval length is less than or equal to the source data length, wait for the read pointer to be updated and enter the wait-update timer. If the waiting time for the update reaches the target duration, an abnormal alarm message is generated.

[0012] Optionally, after sending the target descriptor to the target processor, the method further includes: The first inter-core communication component receives the updated position of the read pointer of the target processor and updates the position of the third pointer according to the updated position.

[0013] Optionally, after determining the starting position of the data buffer area as the first pointer position, the method further includes: The pointer data of the wraparound pointer of the target processor is updated, and the wraparound pointer is used to indicate the pointer position before the write pointer is updated when the remaining length is less than the source data length; Add the updated wraparound pointer data to the access list.

[0014] Optionally, before writing the target descriptor to the first inter-core communication component, the method further includes: The first inter-core communication component determines the target memory block corresponding to the target data from the storage pool based on the memory block acquisition request of the at least one first processor.

[0015] Optionally, after sending the target data to the direct memory access module through the sending queue, the method further includes: The first inter-core communication component stores the target descriptor in the storage pool.

[0016] Optionally, the first communication system and the second communication system are integrated in the same chip; and / or the first communication system and the second communication system are a physical layer system and a protocol stack system.

[0017] Secondly, this application provides an inter-core communication method, executed by a second communication system, the second communication system including at least one second processor and a second inter-core communication component, the method comprising: The second inter-core communication component receives target data sent by the first communication system, wherein the target data is data in the first communication system that the second inter-core communication component requests to access; The target processor in at least one of the second processors reads the target data from the second inter-core communication component.

[0018] Optionally, the second inter-core communication component receives target data sent by the first communication system, including: The direct memory access module receives the target data and the first update information of the write pointer and / or the second update information of the wraparound pointer in the target processor. The write pointer and / or the wraparound pointer are updated based on the first update information and / or the second update information.

[0019] Optionally, after the target processor reads the target data from the second inter-core communication component, the method further includes: The target processor updates the read pointer corresponding to the target processor based on the target data.

[0020] Thirdly, this application provides an inter-core communication method, executed by a first inter-core communication component in a first communication system, wherein the first communication system further includes at least one first processor, and the method includes: In response to a target processor in the second communication system's access request for target data in the first communication system, the target data stored in the memory block corresponding to the target data is sent to the second communication system based on the target descriptor corresponding to the target data. The target descriptor is written into the first inter-core communication component by the at least one first processor after filling the memory block with the target data.

[0021] Fourthly, this application provides a communication system, comprising: At least one first processor is configured to, in response to a target processor in a second communication system requesting access to target data in the first communication system, populate the target data in a memory block corresponding to a target descriptor in the first inter-core communication component via the at least one first processor. At least one first processor is also configured to write the target descriptor into the first inter-core communication component; A first inter-core communication component is configured to send the target data in the memory block to the second communication system based on the target descriptor.

[0022] Fifthly, this application provides a communication system, comprising: The second inter-core communication component is configured to receive target data sent by the first communication system, wherein the target data is data in the first communication system that the second inter-core communication component requests to access. The target processor is configured to read the target data from the second inter-core communication component.

[0023] In a sixth aspect, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the inter-core communication method described in the first or second aspect.

[0024] In a seventh aspect, this application provides a system comprising: A first communication system is used to execute the inter-nuclear communication method described in the first aspect; A second communication system is used to perform the inter-nuclear communication method described in the second aspect; A direct memory access module is used for data transmission between the first communication system and the second communication system.

[0025] Eighthly, this application provides a chip that includes the system described in the seventh aspect.

[0026] By utilizing the above technical solutions, this application provides an inter-core communication method, apparatus, storage medium, component, and chip. Compared with related technologies, this application adds an inter-core communication component to the communication system. This allows the processor in the system to store the target data that other systems need to access in the memory block corresponding to the descriptor when other communication systems are accessing data. The processor in the system then writes the descriptor into the inter-core communication component, thereby enabling the target data in the memory block to be sent based on the descriptor. This allows data interaction with other communication systems to be performed through the inter-core communication component without relying on the processor in the system for control, simplifying the processor's control tasks and improving the data interaction efficiency between different communication systems.

[0027] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A flowchart illustrating an inter-core communication method provided in an embodiment of this application is shown; Figure 2 A flowchart illustrating an example provided in an embodiment of this application is shown; Figure 3 This illustration shows a structural diagram of an example provided in an embodiment of this application; Figure 4A flowchart illustrating an example provided in an embodiment of this application is shown; Figure 5 This illustration shows a structural diagram of an example provided in an embodiment of this application; Figure 6 A flowchart illustrating an inter-core communication method provided in an embodiment of this application is shown; Figure 7 A flowchart illustrating an inter-core communication method provided in an embodiment of this application is shown; Figure 8 This paper shows a schematic diagram of the structure of a first communication system provided in an embodiment of this application; Figure 9 A schematic diagram of the structure of a second communication system provided in an embodiment of this application is shown. Detailed Implementation

[0031] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0032] To address the technical problem of low communication efficiency between physical layer systems and protocol stack systems caused by the inability of current inter-core communication methods to meet performance requirements, this embodiment provides an inter-core communication method executed by a first communication system. The first communication system includes at least one first processor and a first inter-core communication component, such as... Figure 1 As shown, the method includes: Step 101: In response to the target processor in the second communication system's access request for target data in the first communication system, the target data is filled into the memory block corresponding to the target descriptor in the first inter-core communication component by at least one first processor.

[0033] Optionally, the first communication system and the second communication system are integrated in the same chip, and / or the first communication system and the second communication system are a physical layer system and a protocol stack system.

[0034] In the embodiments of this application, the first communication system and the second communication system can be communication systems in the chip. Specifically, the first communication system and the second communication system can be physical layer system and protocol stack system in the chip. When the first communication system is physical layer system in the chip, the second communication system can be protocol stack system in the chip. When the first communication system is protocol stack system in the chip, the second communication system can be physical layer system in the chip.

[0035] In some examples, the first communication system can be a single-core processing system or a multi-core processing system, and correspondingly, the second communication system can also be a single-core processing system or a multi-core processing system. That is, the first communication system may include at least one first processor, and the second communication system may include at least one second processor.

[0036] In this embodiment, the inter-core communication component can be a component used to implement data communication in different systems of the chip. Specifically, an inter-core communication component needs to be integrated in each communication system. For example, the first inter-core communication component can be a component integrated in the first communication system for at least one first processor to implement data transmission and reception.

[0037] In this embodiment of the application, the access request for the target data can specifically be an access request in the form of an interrupt message, and correspondingly, at least one first processor is a processor with interrupt response function.

[0038] For example, the target processor in the second communication system can send an access request for target data to at least one first processor in the first communication system through a hardware notification mechanism, such as a mailbox. Specifically, the target processor in the second communication system can send an access request to at least one processor in the first processor that stores the target data. The processor in the at least one first processor that stores the target data can be one processor or multiple processors, which is not specifically limited in this embodiment.

[0039] For example, when at least one first processor receives a request from the target processor in the second communication system to access target data, the target data can be filled into the memory block corresponding to the target descriptor, so that the target data can be read from the memory block during the transmission of the target data.

[0040] It should be noted that the descriptor corresponding to the target data can be a descriptor that corresponds to the target data, determined based on the size of the target data.

[0041] For example, if the processor storing the target data in at least one first processor is a central processing unit (CPU) 1, and if CPU 1 receives an access request for the target data from the target processor in the second communication system, CPU 1 can respond to the access request for the target data and fill the target data in the memory block corresponding to the target descriptor.

[0042] For example, if CPU1 and CPU2 are the processors storing the target data in at least one first processor, and if CPU1 and CPU2 receive an access request for the target data from the target processor in the second communication system, then CPU1 and CPU2 can respond to the access request for the target data and fill the target data in the memory block corresponding to the target descriptor.

[0043] Step 102: At least one first processor writes the target descriptor into the first inter-core communication component.

[0044] In this embodiment, the first inter-core communication component can send data based on the descriptor when the descriptor is written. Therefore, in this embodiment, after at least one first processor fills the target data in the memory block corresponding to the target descriptor, the target descriptor is written into the first inter-core communication component, so that the target data in the memory block can be sent through the first inter-core communication component.

[0045] For example, if the processor storing the target data in at least one first processor is a central processing unit (CPU) 1 and the first inter-core communication component is HIPC 1, if CPU 1 receives an access request for the target data from the target processor in the second communication system, CPU 1 can respond to the access request for the target data, fill the target data in the memory block corresponding to the target descriptor, and then CPU 1 can write the target descriptor into HIPC 1.

[0046] For example, if CPU1 and CPU2 are processors storing target data in at least one first processor and HIPC1 is the first inter-core communication component, if CPU1 and CPU2 receive a target processor in the second communication system requesting access to the target data, then CPU1 and CPU2 can respond to the access request by filling the target data in the memory block corresponding to the target descriptor, and then CPU1 and CPU2 can write the target descriptor into HIPC1.

[0047] Optionally, before executing "writing the target descriptor to the first inter-core communication component", the following methods may be used, but not limited to: the first inter-core communication component determines the target memory block corresponding to the target data from the storage pool based on a memory block acquisition request from at least one first processor.

[0048] In this embodiment, the first inter-core communication component can support multiple hardware memory pools (e.g., 16). In the initial state, at least one first processor will fill a fixed number of memory blocks into each hardware memory pool, specifically in the form of descriptors. Each hardware memory pool maintains memory blocks of the same size. Figure 2As shown, taking one memory pool and one hardware channel as an example, it can be the interaction flowchart of at least one first processor and one first core communication component. It should be noted that if the first core communication component can support 16 hardware memory pools, then 16 memory pools require 16 sets of identical hardware instances.

[0049] For example, such as Figure 2 As shown, the first inter-core communication component can maintain memory blocks. When at least one first processor receives a request from the target processor in the second communication system to access target data, it can request a memory block from the memory pool of the first inter-core communication component. After filling the target data, it rewrites the target descriptor corresponding to the memory block into the first inter-core communication component. Then, after the first inter-core communication component sends out the target data, it reclaims the target descriptor corresponding to the memory block into the corresponding memory pool according to the fields in the descriptor.

[0050] As an alternative approach, the first inter-core communication component in this application can be divided into multiple functional modules, including but not limited to a memory management module, a data transmission module, and a pointer maintenance module. When at least one first processor receives a request from the target processor in the second communication system for access to target data, it can request a memory block from the memory pool of the memory management module in the first inter-core communication component. After filling the memory block with target data, the target descriptor corresponding to the memory block is written into the data transmission module in the first inter-core communication component. Then, after the data transmission module sends out the target data, the target descriptor corresponding to the target memory block is recycled back to the memory pool corresponding to the memory management module according to the fields in the descriptor.

[0051] For example, if the processor storing the target data in at least one first processor is a central processing unit (CPU) 1 and the first inter-core communication component is HIPC 1, if CPU 1 receives an access request for the target data from the target processor in the second communication system, CPU 1 can respond to the access request for the target data, apply for a memory block from the memory pool of the memory management module in HIPC 1, and after filling the target data, write the target descriptor corresponding to the memory block into the data sending module in HIPC 1. Then, after the data sending module sends the target data, the target descriptor corresponding to the target memory block is recycled to the memory pool corresponding to the memory management module in HIPC 1 according to the fields in the descriptor.

[0052] For example, if CPU1 and CPU2 are processors storing target data in at least one first processor and HIPC1 is the first inter-core communication component, if CPU1 and CPU2 receive a target processor in the second communication system requesting access to the target data, CPU1 and CPU2 can respond to the access request by requesting a memory block from the memory pool of the memory management module in HIPC1, and after filling the target data, write the target descriptor corresponding to the memory block into the data sending module in HIPC1. Then, after the data sending module sends the target data, the target descriptor corresponding to the target memory block is recycled to the memory pool corresponding to the memory management module in HIPC1 according to the fields in the descriptor.

[0053] Step 103: The first inter-core communication component sends the target data in the memory block to the second communication system based on the target descriptor.

[0054] In this embodiment of the application, after the first inter-core communication component is written to the target descriptor, it can send the target data in the memory block to the second communication system based on the target descriptor.

[0055] Optionally, when performing "sending target data in a memory block to a second communication system based on a target descriptor", the following methods may be used, but are not limited to: determining a transmission queue in a transmission channel in which at least one first processor writes a target descriptor in a first inter-core communication component; sending the target data to a direct memory access module through the transmission queue, so as to send the target data to the second communication system through the direct memory access module.

[0056] In this embodiment of the application, the first inter-core communication component is configured with multiple data transmission channels, each data transmission channel having a data transmission queue. For example, the first inter-core communication component can support multiple channels (e.g., 8 channels) working in parallel at the same time, that is, the transmission queues in the multiple channels (e.g., 8 channels) can transmit data in parallel.

[0057] For example, during the process of at least one first processor writing a target descriptor into the first inter-core communication component, the data transmission channel corresponding to the target processor requesting access to the target data can be determined, and the target descriptor can be written into the data transmission channel corresponding to the target processor in the first inter-core communication component. This allows the first inter-core communication component to send the target data to the direct memory access module through the transmission queue in the data transmission channel corresponding to the target processor, and then send the target data to the second communication system through the direct memory access module.

[0058] In some examples, a Direct Memory Access (DMA) module is a dedicated hardware module used to enable high-speed data transfer between peripherals and memory, or between memory modules, without consuming CPU resources; for example, such as Figure 3 As shown, in this embodiment of the application, data transmission between the first communication system and the second communication system can be achieved through DMA.

[0059] For example, such as Figure 4 As shown, after at least one first processor writes the target descriptor into the first inter-core communication component, the first inter-core communication component can perform cyclic redundancy check on the target descriptor. If the cyclic redundancy check fails, the target descriptor will not enter the transmission queue; correspondingly, if the cyclic redundancy check passes, the target descriptor can be sent into the first-in-first-out (FIFO) transmission queue, i.e., the transmission queue in the embodiments of this application.

[0060] For example, if the processor storing the target data in at least one first processor is a central processing unit (CPU) 1 and the first inter-core communication component is HIPC 1, if CPU 1 receives an access request for the target data from the target processor in the second communication system, CPU 1 can respond to the access request for the target data, fill in the target data, and write the target descriptor corresponding to the memory block into the transmission queue in the transmission channel corresponding to the target processor in HIPC 1. Then, HIPC 1 can send the target data to the DMA module through the transmission queue in the transmission channel corresponding to the target processor, thereby sending the target data to the second communication system through the DMA module.

[0061] For example, if CPU1 and CPU2 are processors storing target data in at least one first processor and HIPC1 is the first inter-core communication component, if CPU1 and CPU2 receive a target data access request from the target processor in the second communication system, CPU1 and CPU2 can respond to the target data access request, fill in the target data, and write the target descriptor corresponding to the memory block into the transmission queue in the transmission channel corresponding to the target processor in HIPC1. Then, HIPC1 can send the target data to the DMA module through the transmission queue in the transmission channel corresponding to the target processor, thereby sending the target data to the second communication system through the DMA module.

[0062] Optionally, when executing "sending target data to the direct memory access module via the send queue", the following methods can be used, but are not limited to: determining the processing priority corresponding to the target descriptor based on the queue priority information of the send queue and the write time of the target descriptor in the send queue; and sending the target descriptor in the send queue to the direct memory access module according to the processing priority.

[0063] In this embodiment, since the first inter-core communication component can support multiple channels (e.g., 8 channels) working in parallel, that is, the sending queues in multiple channels (e.g., 8 channels) can send data in parallel, multiple channels (e.g., 8 channels) can be set to different priorities, and the hardware determines the data packet transmission order (i.e., the processing priority in this embodiment) according to the channel priority and sequence.

[0064] In some examples, the data sending module in the first inter-core communication component can determine the processing priority of the target descriptor based on the time when the target descriptor enters the sending FIFO (i.e., the sending queue in this embodiment) (i.e., the write time in this embodiment) and the priority of the sending FIFO (i.e., the sending queue in this embodiment) in multiple channels (e.g., up to 8 channels) (i.e., the queue priority information in this embodiment). The processor priority can determine when the target descriptor is parsed and processed.

[0065] For example, if the processor storing the target data in at least one first processor is a central processing unit (CPU) 1 and the first inter-core communication component is HIPC 1, if CPU 1 receives an access request for the target data from the target processor in the second communication system, CPU 1 can respond to the access request for the target data, fill in the target data, and write the target descriptor corresponding to the memory block into the transmission queue in the transmission channel corresponding to the target processor in HIPC 1. Then, the processing priority of the target data can be determined according to the write time of the transmission queue and the priority information of the transmission queue. Thus, HIPC 1 can send the target data to the DMA module through the transmission queue in the transmission channel corresponding to the target processor according to the processing priority, and then send the target data to the second communication system through the DMA module.

[0066] For example, if CPU1 and CPU2 are processors storing target data in at least one first processor and HIPC1 is the first inter-core communication component, if CPU1 and CPU2 receive a target data access request from the target processor in the second communication system, CPU1 and CPU2 can respond to the target data access request, fill in the target data, and write the target descriptor corresponding to the memory block into the transmission queue in the transmission channel corresponding to the target processor in HIPC1. Then, the processing priority of the target data can be determined according to the write time and priority information of the transmission queue. Thus, HIPC1 can send the target data to the DMA module according to the processing priority in the transmission queue of the transmission channel corresponding to the target processor, and then send the target data to the second communication system through the DMA module.

[0067] Optionally, when executing "sending the target descriptors in the sending queue to the direct memory access module according to the processing priority", the following methods can be used, but are not limited to: parsing the target descriptors in the sending queue according to the processing priority to determine the source data information corresponding to the target data, the source data information including the source data address and the source data length; adding the source data information and the target data to the access list of the direct memory access module, the access list being used by the direct memory access module for data transmission.

[0068] In this embodiment, the first inter-core communication component can parse the target descriptor, thereby writing the target data into the source address and length of the DMA, and adding the target data to the DMA linked list (LinkList) according to the source address and length, i.e., the access linked list in this embodiment. If there is still data to be sent in the transmit FIFO where the target data is located, it can also be added to the DMA linked list (i.e., the access linked list in this embodiment).

[0069] It should be noted that the source data information in the embodiments of this application can be carried by the target descriptor and obtained during the process of parsing the target descriptor by the first inter-core communication component.

[0070] Optionally, after executing "parse the target descriptor in the sending queue according to the processing priority to determine the source data information corresponding to the target data", the following methods can be used, but not limited to these, including: the first inter-core communication component updates the pointer position of the write pointer of the target processor according to the length of the source data; and adds the updated first pointer position to the access list.

[0071] In this embodiment, the write pointer can be the write pointer of the target processor maintained by the first inter-core communication component. The position of the write pointer can determine the writing position of the target data in the ring buffer (i.e., the data buffer area in this embodiment) of the second inter-core communication component.

[0072] For example, such as Figure 5 As shown, if the write pointer of the target processor is at the 80th bit in the RingBuffer (i.e., the data buffer area in this embodiment) before data transmission, and the target data is determined to be 20 bits based on the length of the source data, then the write pointer can be updated to the position in the RingBuffer (i.e., the data buffer area in this embodiment) after the target data is written, which can be the 100th bit. The 100th bit is the position of the updated write pointer (i.e., the first pointer position in this embodiment).

[0073] It should be noted that, in this embodiment of the application, the write pointer of the target processor maintained by the first inter-core communication component enables the first inter-core communication component to determine the write status of the circular buffer (i.e., the data buffer area in this embodiment of the application) in the second inter-core communication component. After updating the write pointer, the updated first pointer position can be added to the access list, so that the DMA can send the updated first pointer position and the target data together to the second communication system, so that the second communication system can update the write status of the circular buffer (i.e., the data buffer area in this embodiment of the application).

[0074] Optionally, when performing "updating the write pointer of the target processor based on the length of the source data", the following methods can be used, but are not limited to: determining the remaining length in the data buffer area corresponding to the target processor based on the second pointer position of the write pointer before the update, wherein the remaining length is the data length between the second pointer position and the end position of the data buffer area; and determining the starting position of the data buffer area as the first pointer position if the remaining length is less than the length of the source data.

[0075] In this embodiment, if the difference between the write pointer and the Buffer End (i.e., the end position of the data buffer area in this embodiment) is insufficient to write a new piece of data, the hardware will abandon this memory and reset the write pointer to the beginning position of the Buffer (i.e., the beginning position in this embodiment).

[0076] For example, if the write pointer of the target processor is at the 80th bit (i.e., the second pointer position in this embodiment) of the Ring Buffer (i.e., the data buffer area in this embodiment) before data transmission, the target data can be determined to be 20 bits based on the length of the source data. If the end position of the Ring Buffer (i.e., the data buffer area in this embodiment) is the 99th bit, it can be determined that the remaining length (19 bits) in the data buffer area is less than the length of the source data (20 bits). Then the write pointer can be updated and reset to the starting position of the Buffer (i.e., the starting position in this embodiment), which is the 1st bit. The 1st bit is the position of the updated write pointer (i.e., the first pointer position in this embodiment).

[0077] Optionally, when executing "determine the starting position of the data buffer area as the first pointer position", the following methods can be used, but are not limited to: determining the third pointer position corresponding to the read pointer of the target processor; and determining the starting position of the data buffer area as the first pointer position if the interval length between the starting position and the third pointer position is greater than the length of the source data.

[0078] In this embodiment, the read pointer can indicate the position where the target processor reads data from the data buffer area. For example, if the read pointer is the 20th bit, it means that the target processor has read the data from the data buffer area up to the 20th bit position. If the read pointer is the 30th bit, it means that the target processor has read the data from the data buffer area up to the 30th bit position, and so on. No further examples will be given here.

[0079] In this embodiment, if the difference between the write pointer and the Buffer End (i.e., the end point of the data buffer area in this embodiment) is insufficient to write the target data, it is also necessary to determine the position corresponding to the read pointer of the target processor (i.e., the third pointer position in this embodiment). Based on the position corresponding to the read pointer (i.e., the third pointer position in this embodiment), the interval length between the read pointer position and the starting position is determined. Then, if the interval length is greater than the length of the source data, the starting position of the data buffer area is determined as the first pointer position.

[0080] For example, if the write pointer of the target processor is at bit 80 (i.e., the second pointer position in this embodiment) of the Ring Buffer (i.e., the data buffer area in this embodiment) before data transmission, the target data can be determined to be 20 bits based on the length of the source data. If the end position of the Ring Buffer (i.e., the data buffer area in this embodiment) is bit 99, it can be determined that the remaining length (19 bits) in the data buffer area is less than the length of the source data (20 bits). The read pointer position can then be further determined. If the read pointer position is bit 25, it can be determined that the interval length (25 bits) between the read pointer position and the start position is greater than the length of the source data (20 bits). The write pointer can then be updated and reset to the start position of the Buffer (i.e., the start position in this embodiment), i.e., bit 1. Bit 1 is the updated write pointer position (i.e., the first pointer position in this embodiment).

[0081] Optionally, after executing "determine the position of the third pointer corresponding to the read pointer of the target processor", the following methods can be used, but not limited to these, including: if the interval length is less than or equal to the source data length, wait for the read pointer position to be updated and enter the waiting update timer; if the waiting update timer reaches the target duration, generate an abnormal alarm message.

[0082] For example, if the write pointer of the target processor is at bit 80 (i.e., the second pointer position in this embodiment) of the Ring Buffer (i.e., the data buffer area in this embodiment) before data transmission, the target data can be determined to be 20 bits based on the source data length. If the end position of the Ring Buffer (i.e., the data buffer area in this embodiment) is bit 99, it can be determined that the remaining length (19 bits) in the data buffer area is less than the source data length (20 bits). The read pointer position can then be further determined. If the read pointer position is bit 18, it can be determined that the interval length (18 bits) between the read pointer position and the start position is less than the source data length (20 bits). Then, the first inter-core communication component needs to enter the waiting update timer. If the interval length between the read pointer position and the start position is still less than or equal to the source data length when the waiting update timer reaches the target duration, an abnormal alarm message can be generated.

[0083] It should be noted that the target duration in this embodiment can be set according to the read data situation of the target processor. Specifically, it can be set to a duration much longer than the read data interval of the target processor, so as to ensure that when the waiting time for the update reaches the target duration, there is an abnormality in the read pointer of the target processor, thereby generating an abnormal alarm message.

[0084] Optionally, after executing "send target descriptor to target processor", the following methods may be used, but not limited to: the first inter-core communication component receives the updated position of the target processor's read pointer and updates the third pointer position according to the updated position.

[0085] In this embodiment of the application, the read pointer can be a pointer maintained by the target processor. For example, in this embodiment of the application, the first inter-core communication component can receive the updated position of the read pointer sent by the second communication system when the target processor reads data in the data buffer area, thereby realizing that the read pointer positions of the target processor in the first communication system and the second communication system are synchronized.

[0086] Optionally, after executing "determine the starting position of the data buffer area as the first pointer position", the following methods can be used, but not limited to these, including: updating the pointer data of the wraparound pointer of the target processor, the wraparound pointer being used to indicate the pointer position before the write pointer is updated when the remaining length is less than the length of the source data; and adding the updated pointer data of the wraparound pointer to the access list.

[0087] In this embodiment, if the difference between the write pointer and the Buffer End (i.e., the end position of the data buffer area in this embodiment) is insufficient to write a new piece of data, the hardware will abandon this memory and reset the write pointer to the Buffer start position (i.e., the start position in this embodiment). This process can be determined as a pointer wrap-around process, so that the pointer position of the wrap-around pointer of the target processor can be updated based on the position of the write pointer before wrap-around.

[0088] For example, if the pointer position of the write pointer of the target processor is the 80th bit (i.e., the second pointer position in this embodiment) in the Ring Buffer (i.e., the data buffer area in this embodiment) before data transmission, the target data can be determined to be 20 bits based on the length of the source data. If the end position of the Ring Buffer (i.e., the data buffer area in this embodiment) is the 99th bit, it can be determined that the remaining length (19 bits) in the data buffer area is less than the length of the source data (20 bits). The write pointer can then be updated and reset to the starting position of the Buffer (i.e., the starting position in this embodiment), which is the 1st bit. The 1st bit is the position of the updated write pointer (i.e., the first pointer position in this embodiment). Then, the pointer position of the wraparound pointer of the target processor can be updated based on the position of the write pointer before wraparound (the 80th bit).

[0089] Optionally, after executing "sending target data to the direct memory access module via the send queue", the following methods may be used, but not limited to: the first inter-core communication component stores the target descriptor in the storage pool.

[0090] It should be noted that, in the embodiments of this application, the target descriptor can be reclaimed by the first inter-core communication component after the target data is written to the DMA chain. That is, after the target data is written to the DMA chain, the target descriptor will be stored again in the storage block of the storage pool.

[0091] In related technologies, inter-core data is managed in shared memory. The communication system sending data uses a hardware notification mechanism, such as a mailbox, to notify the communication system receiving data to retrieve the data. This means that most of the logic for inter-core communication is implemented in software, and both the data sending and receiving systems need to access the shared memory area across systems, which cannot meet the requirements for high-performance inter-core communication. This application's embodiment can harden the inter-core communication mechanism. The data sending communication system (i.e., the first communication system in this application embodiment) and the data receiving communication system (i.e., the second communication system in this application embodiment) use DMA to transfer data. The main communication logic is offloaded from the CPU to the hardware. Based on the inherent advantages of DMA transfer, CPU data access does not cross systems, thereby improving inter-core communication performance and meeting the inter-core communication requirements in 5G high-speed, low-latency scenarios.

[0092] Compared with related technologies, this embodiment adds an inter-core communication component to the communication system. This allows the processor in the system to store the target data that other systems need to access in the memory block corresponding to the descriptor when other communication systems are accessing data. The processor in the system then writes the descriptor into the inter-core communication component, so that the target data in the memory block can be sent based on the descriptor. This enables data interaction with other communication systems through the inter-core communication component without relying on the processor in the system for control, simplifying the processor's control tasks and improving the efficiency of data interaction between different communication systems.

[0093] To illustrate the execution process of the second communication system, embodiments of this application also provide an inter-core communication method, executed by the second communication system. The second communication system includes at least one second processor and a second inter-core communication component, such as... Figure 6 As shown, it includes: Step 201: The second inter-core communication component receives the target data sent by the first communication system.

[0094] The target data is the data in the first communication system that the second inter-core communication component requests to access.

[0095] In the embodiments of this application, the first communication system and the second communication system can be communication systems in the chip. Specifically, the first communication system and the second communication system can be physical layer system and protocol stack system in the chip. When the first communication system is physical layer system in the chip, the second communication system can be protocol stack system in the chip. When the first communication system is protocol stack system in the chip, the second communication system can be physical layer system in the chip.

[0096] In some examples, the first communication system can be a single-core processing system or a multi-core processing system, and correspondingly, the second communication system can also be a single-core processing system or a multi-core processing system. That is, the first communication system may include at least one first processor, and the second communication system may include at least one second processor.

[0097] In this embodiment, the inter-core communication component can be a component used to implement data communication in different systems of the chip. Specifically, an inter-core communication component needs to be integrated in each communication system. For example, the second inter-core communication component can be a component integrated in the first communication system for at least one second processor to implement data transmission and reception.

[0098] For example, the target processor in the second communication system can send an access request for target data to at least one first processor in the first communication system through a hardware notification mechanism, such as a mailbox. Specifically, the target processor in the second communication system can send an access request to at least one processor in the first processor that stores the target data, and then receive the target data through the second inter-core communication component. The processor in the at least one first processor that stores the target data can be one processor or multiple processors, which is not specifically limited in this embodiment.

[0099] For example, when at least one first processor receives a request from the target processor in the second communication system to access target data, the target data can be filled into the memory block corresponding to the target descriptor, so that the target data can be read from the memory block during the transmission of the target data.

[0100] Optionally, when executing "the second inter-core communication component receives the target data sent by the first communication system", the following methods may be used, but not limited to these, including: receiving the target data and the first update information of the write pointer and / or the second update information of the wraparound pointer in the target processor through the direct memory access module; updating the write pointer and / or the wraparound pointer based on the first update information and / or the second update information.

[0101] For example, in the embodiments of this application, when the second inter-core communication component receives the target data, it can simultaneously receive the first update information of the write pointer in the target processor, so that the write pointer in the target processor can be updated in the second inter-core communication component.

[0102] As an alternative approach, in the case of updating the wraparound pointer by the first inter-core communication component in this application embodiment, if target data is received, the first update information of the write pointer and the second update information of the wraparound pointer in the target processor can be received simultaneously, so that the write pointer and the wraparound pointer in the target processor can be updated in the second inter-core communication component.

[0103] Step 202: The target processor in at least one of the second processors reads the target data from the second inter-core communication component.

[0104] Optionally, after executing "at least one target processor in the second processor reads target data from the second inter-core communication component", the following methods may be used, but not limited to: the target processor updates the read pointer corresponding to the target processor based on the target data.

[0105] In this embodiment of the application, the read pointer can be a pointer maintained by the target processor. For example, in this embodiment of the application, the second inter-core communication component can send the updated position of the read pointer to the first communication system after the target processor reads the data in the data buffer area, thereby synchronizing the read pointer positions of the target processor in the first communication system and the second communication system.

[0106] Compared with related technologies, this embodiment adds an inter-core communication component to the communication system. This allows the processor in the system to store the target data that other systems need to access in a descriptor when other communication systems are accessing data. The processor in the system then writes the descriptor containing the target data into the inter-core communication component. This enables data interaction with other communication systems through the inter-core communication component without relying on the processor in the system for control. This simplifies the processor's control tasks and improves the efficiency of data interaction between different communication systems.

[0107] To illustrate the execution process of the first inter-core communication component, embodiments of this application also provide an inter-core communication method, executed by the first inter-core communication component in a first communication system. The first communication system further includes at least one first processor, such as... Figure 7 As shown, it includes: Step 301: In response to the target processor in the second communication system's access request for target data in the first communication system, the target data stored in the memory block corresponding to the target descriptor is sent to the second communication system according to the target descriptor corresponding to the target data.

[0108] The target descriptor is written into the first inter-core communication component by at least one first processor after the target data is filled in a memory block.

[0109] In the embodiments of this application, the first communication system and the second communication system can be communication systems in the chip. Specifically, the first communication system and the second communication system can be physical layer system and protocol stack system in the chip. When the first communication system is physical layer system in the chip, the second communication system can be protocol stack system in the chip. When the first communication system is protocol stack system in the chip, the second communication system can be physical layer system in the chip.

[0110] In some examples, the first communication system can be a single-core processing system or a multi-core processing system, and correspondingly, the second communication system can also be a single-core processing system or a multi-core processing system. That is, the first communication system may include at least one first processor, and the second communication system may include at least one second processor.

[0111] In this embodiment, the inter-core communication component can be a component used to implement data communication in different systems of the chip. Specifically, an inter-core communication component needs to be integrated in each communication system. For example, the first inter-core communication component can be a component integrated in the first communication system for at least one first processor to implement data transmission and reception.

[0112] In this embodiment of the application, the access request for the target data can specifically be an access request in the form of an interrupt message, and correspondingly, at least one first processor is a processor with interrupt response function.

[0113] For example, the target processor in the second communication system can send an access request for target data to at least one first processor in the first communication system through a hardware notification mechanism, such as a mailbox. Specifically, the target processor in the second communication system can send an access request to at least one processor in the first processor that stores the target data. The processor in the at least one first processor that stores the target data can be one processor or multiple processors, which is not specifically limited in this embodiment.

[0114] For example, when at least one first processor receives a request from a target processor in the second communication system to access target data, the target data can be populated in the target descriptor so that the target data can be read from the memory block during the transmission of the target data.

[0115] It should be noted that the descriptor corresponding to the target data can be a descriptor that corresponds to the target data, determined based on the size of the target data.

[0116] For example, if the processor storing the target data in at least one first processor is a central processing unit (CPU) 1, and if CPU 1 receives an access request for the target data from the target processor in the second communication system, CPU 1 can respond to the access request for the target data and fill the target data in the memory block corresponding to the target descriptor.

[0117] For example, if CPU1 and CPU2 are the processors storing the target data in at least one first processor, and if CPU1 and CPU2 receive an access request for the target data from the target processor in the second communication system, then CPU1 and CPU2 can respond to the access request for the target data and fill the target data in the memory block corresponding to the target descriptor.

[0118] In this embodiment, the first inter-core communication component can send data based on the descriptor when the descriptor is filled with data. Therefore, this embodiment requires that after at least one first processor fills the target data in the memory block corresponding to the target descriptor, the target descriptor is written into the first inter-core communication component, and then the target data can be sent through the first inter-core communication component.

[0119] For example, if the processor storing the target data in at least one first processor is a central processing unit (CPU) 1 and the first inter-core communication component is HIPC 1, if CPU 1 receives an access request for the target data from the target processor in the second communication system, CPU 1 can respond to the access request for the target data, fill the target data in the memory block corresponding to the target descriptor, and then CPU 1 can write the target descriptor into HIPC 1.

[0120] For example, if CPU1 and CPU2 are processors storing target data in at least one first processor and HIPC1 is the first inter-core communication component, if CPU1 and CPU2 receive a target processor in the second communication system requesting access to the target data, then CPU1 and CPU2 can respond to the access request by filling the target data in the memory block corresponding to the target descriptor, and then CPU1 and CPU2 can write the target descriptor into HIPC1.

[0121] In this embodiment of the application, after the first inter-core communication component is written to the target descriptor, it can send the target data in the memory block to the second communication system based on the target descriptor.

[0122] Compared with related technologies, this embodiment adds an inter-core communication component to the communication system. This allows the processor in the system to store the target data that other systems need to access in the memory block corresponding to the descriptor when other communication systems are accessing data. The processor in the system then writes the descriptor into the inter-core communication component, so that the target data in the memory block can be sent based on the descriptor. This enables data interaction with other communication systems through the inter-core communication component without relying on the processor in the system for control, simplifying the processor's control tasks and improving the efficiency of data interaction between different communication systems.

[0123] Furthermore, as Figure 1 The specific implementation of the method shown in this embodiment provides a communication system, such as... Figure 8 As shown, it includes: at least one first processor 41 and a first inter-core communication component 42; At least one first processor 41 is configured to, in response to a target processor in the second communication system's request to access target data in the first communication system, populate the target data in a memory block corresponding to a target descriptor in the first inter-core communication component via the at least one first processor. At least one first processor 41 is also configured to write the target descriptor into the first inter-core communication component; The first inter-core communication component 42 is configured to send the target data in the memory block to the second communication system based on the target descriptor.

[0124] In some examples of this embodiment, the first inter-core communication component 42 is specifically configured to determine a transmission queue in the transmission channel where the at least one first processor writes the target descriptor in the first inter-core communication component; and to send the target data to the direct memory access module through the transmission queue, so as to send the target data to the second communication system through the direct memory access module.

[0125] In some examples of this embodiment, the first inter-core communication component 42 is further configured to determine the processing priority corresponding to the target descriptor based on the queue priority information of the sending queue and the write time of the target descriptor in the sending queue; and send the target descriptor in the sending queue to the direct memory access module according to the processing priority.

[0126] In some examples of this embodiment, the first inter-core communication component 42 is further configured to parse the target descriptor in the sending queue according to the processing priority, determine the source data information corresponding to the target data, the source data information including the source data address and the source data length; and add the source data information and the target data to the access list of the direct memory access module, the access list being used by the direct memory access module for data transmission.

[0127] In some examples of this embodiment, the first inter-core communication component 42 is further configured to update the pointer position of the write pointer of the target processor according to the length of the source data; and add the updated first pointer position to the access list.

[0128] In some examples of this embodiment, the first inter-core communication component 42 is further configured to determine the remaining length in the data buffer area corresponding to the target processor based on the second pointer position of the write pointer before the update, wherein the remaining length is the data length between the second pointer position in the data buffer area and the end position of the data buffer area; and if the remaining length is less than the source data length, the starting position of the data buffer area is determined as the first pointer position.

[0129] In some examples of this embodiment, the first inter-core communication component 42 is further configured to determine the third pointer position corresponding to the read pointer of the target processor; and when the interval length between the starting position and the third pointer position is greater than the length of the source data, the starting position of the data buffer area is determined as the first pointer position.

[0130] In some examples of this embodiment, the first inter-core communication component 42 is further configured to wait for the read pointer to be updated and enter a waiting update timer when the interval length is less than or equal to the source data length; and to generate an abnormal alarm message when the waiting update timer reaches the target duration.

[0131] In some examples of this embodiment, the first inter-core communication component 42 is further configured to receive the updated position of the read pointer of the target processor and update the third pointer position according to the updated position.

[0132] In some examples of this embodiment, the first inter-core communication component 42 is further configured to update the pointer data of the wraparound pointer of the target processor, wherein the wraparound pointer is used to indicate the pointer position before the write pointer is updated when the remaining length is less than the source data length; and to add the updated pointer data of the wraparound pointer to the access list.

[0133] In some examples of this embodiment, at least one first processor 41 is specifically configured to determine the target memory block corresponding to the target data from the storage pool based on the memory block acquisition request of the at least one first processor.

[0134] In some examples of this embodiment, the first inter-core communication component 42 is further configured to store the target descriptor in the storage pool.

[0135] It should be noted that other corresponding descriptions of the functional units involved in the communication system provided in this embodiment can be found in [reference needed]. Figure 1 The corresponding descriptions in [the document] will not be repeated here.

[0136] Furthermore, as Figure 6 The specific implementation of the method shown in this embodiment provides a communication system, such as... Figure 9 As shown, it includes: a second inter-core communication component 51, and at least one second processor 52; The second inter-core communication component 51 is configured to receive target data sent by the first communication system, wherein the target data is data in the first communication system that the second inter-core communication component requests to access. At least one second processor 52, wherein the target processor in the at least one second processor 52 is configured to read the target data from the second inter-core communication component.

[0137] In some examples of this embodiment, the second inter-core communication component 51 receives the target data and the first update information of the write pointer and / or the second update information of the wraparound pointer in the target processor through the direct memory access module; and updates the write pointer and / or the wraparound pointer based on the first update information and / or the second update information.

[0138] In some examples of this embodiment, the target processor in the at least one second processor 52 is further configured to update the read pointer corresponding to the target processor based on the target data.

[0139] It should be noted that other corresponding descriptions of the functional units involved in the communication system provided in this embodiment can be found in [reference needed]. Figure 6 The corresponding descriptions in [the document] will not be repeated here.

[0140] Based on the above, Figure 1 or Figure 6 or Figure 7 Accordingly, this embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. Figure 1 or Figure 6or Figure 7 The method shown.

[0141] Based on this understanding, the technical solution of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of this application.

[0142] Based on the above, Figure 1 or Figure 6 or Figure 7 The method shown, and Figure 8 or Figure 9 To achieve the above objectives, the present application also provides a system comprising a first communication system, a second communication system, and a direct memory access module, as shown in the virtual device embodiment. The first communication system is used to execute a computer program to achieve the above-mentioned... Figure 1 The method shown includes a second communication system for executing computer programs to achieve the above-described... Figure 3 The method shown uses a direct memory access module to execute computer programs to enable data transfer between a first communication system and a second communication system.

[0143] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0144] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0145] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the aforementioned physical device, supporting the operation of information processing programs and other software and / or programs. The network communication module is used to enable communication between the various components within the storage medium, as well as communication with other hardware and software in the information processing physical device.

[0146] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. By applying the solution of this embodiment, compared with related technologies, this embodiment adds an inter-core communication component to the communication system, so that when other communication systems access data, the processor in the system can store the target data that other systems need to access in the memory block corresponding to the descriptor, and the processor in the system writes the descriptor into the inter-core communication component. Thus, the target data in the memory block can be sent based on the descriptor, enabling data interaction with other communication systems through the inter-core communication component without relying on the processor in the system for control, simplifying the processor's control tasks and improving the data interaction efficiency between different communication systems.

[0147] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0148] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for inter-core communication, characterized in that, Performed by a first communication system, the first communication system including at least one first processor and a first inter-core communication component, the method includes: In response to a target processor in the second communication system requesting access to target data in the first communication system, the target data is filled into the memory block corresponding to the target descriptor in the first inter-core communication component by the at least one first processor. The at least one first processor writes the target descriptor into the first inter-core communication component; The first inter-core communication component sends the target data in the memory block to the second communication system based on the target descriptor.

2. The method according to claim 1, characterized in that, Based on the target descriptor, sending the target data in the memory block to the second communication system includes: Determine the transmission queue in the transmission channel of the target descriptor written by the at least one first processor in the first inter-core communication component; The target data is sent to the direct memory access module through the sending queue, so as to send the target data to the second communication system through the direct memory access module.

3. The method according to claim 2, characterized in that, Sending the target data to the direct memory access module through the sending queue includes: Based on the queue priority information of the sending queue and the write time of the target descriptor in the sending queue, the processing priority corresponding to the target descriptor is determined; The target descriptor in the sending queue is sent to the direct memory access module according to the processing priority.

4. The method according to claim 3, characterized in that, Sending the target descriptor in the sending queue to the direct memory access module according to the processing priority includes: The target descriptor in the sending queue is parsed according to the processing priority to determine the source data information corresponding to the target data. The source data information includes the source data address and the source data length. The source data and the target data are added to the access list of the direct memory access module, which is used by the direct memory access module for data transmission.

5. The method according to claim 4, characterized in that, After parsing the target descriptor in the sending queue according to the processing priority to determine the source data information corresponding to the target data, the method further includes: The first inter-core communication component updates the pointer position of the write pointer of the target processor according to the length of the source data; Add the updated first pointer position to the access list.

6. The method according to claim 5, characterized in that, The step of updating the write pointer of the target processor based on the length of the source data includes: Based on the second pointer position of the write pointer before the update, the remaining length in the data buffer area corresponding to the target processor is determined, and the remaining length is the data length between the second pointer position in the data buffer area and the end position of the data buffer area. If the remaining length is less than the length of the source data, the starting position of the data buffer area is determined as the first pointer position.

7. The method according to claim 6, characterized in that, Determining the starting position of the data buffer area as the first pointer position includes: Determine the position of the third pointer corresponding to the read pointer of the target processor; If the interval between the starting position and the third pointer position is greater than the length of the source data, the starting position of the data buffer area is determined as the first pointer position.

8. The method according to claim 7, characterized in that, After determining the position of the third pointer corresponding to the read pointer of the target processor, the method further includes: If the interval length is less than or equal to the source data length, wait for the read pointer to be updated and enter the wait-update timer. If the waiting time for the update reaches the target duration, an abnormal alarm message is generated.

9. The method according to claim 7, characterized in that, After sending the target descriptor to the target processor, the method further includes: The first inter-core communication component receives the updated position of the read pointer of the target processor and updates the position of the third pointer according to the updated position.

10. The method according to claim 6, characterized in that, After determining the starting position of the data buffer area as the first pointer position, the method further includes: The pointer data of the wraparound pointer of the target processor is updated, and the wraparound pointer is used to indicate the pointer position before the write pointer is updated when the remaining length is less than the source data length; Add the updated wraparound pointer data to the access list.

11. The method according to claim 2, characterized in that, Before writing the target descriptor to the first inter-core communication component, the method further includes: The first inter-core communication component determines the target memory block corresponding to the target data from the storage pool based on the memory block acquisition request of the at least one first processor.

12. The method according to claim 11, characterized in that, After sending the target data to the direct memory access module via the sending queue, the method further includes: The first inter-core communication component stores the target descriptor in the storage pool.

13. The method according to any one of claims 1 to 12, characterized in that, The first communication system and the second communication system are integrated in the same chip, and / or the first communication system and the second communication system are a physical layer system and a protocol stack system.

14. A method for inter-core communication, characterized in that, Performed by a second communication system, the second communication system including at least one second processor and a second core inter-core communication component, the method includes: The second inter-core communication component receives target data sent by the first communication system, wherein the target data is data in the first communication system that the second inter-core communication component requests to access; The target processor in at least one of the second processors reads the target data from the second inter-core communication component.

15. The method according to claim 14, characterized in that, The second inter-core communication component receives target data sent by the first communication system, including: The target data and the first update information of the write pointer and / or the second update information of the wraparound pointer in the target processor are received through the direct memory access module. The write pointer and / or the wraparound pointer are updated based on the first update information and / or the second update information.

16. The method according to claim 14, characterized in that, After the target processor reads the target data from the second inter-core communication component, the method further includes: The target processor updates the read pointer corresponding to the target processor based on the target data.

17. A method for inter-core communication, characterized in that, Performed by a first inter-core communication component in a first communication system, the first communication system further comprising at least one first processor, the method includes: In response to a target processor in the second communication system's access request for target data in the first communication system, the target data stored in the memory block corresponding to the target data is sent to the second communication system based on the target descriptor corresponding to the target data. The target descriptor is written into the first inter-core communication component by the at least one first processor after filling the memory block with the target data.

18. A communication system, characterized in that, include: At least one first processor is configured to, in response to a target processor in a second communication system requesting access to target data in the first communication system, populate the target data in a memory block corresponding to a target descriptor in the first inter-core communication component via the at least one first processor. At least one first processor is also configured to write the target descriptor into the first inter-core communication component; A first inter-core communication component is configured to send the target data in the memory block to the second communication system based on the target descriptor.

19. A communication system, characterized in that, include: The second inter-core communication component is configured to receive target data sent by the first communication system, wherein the target data is data in the first communication system that the second inter-core communication component requests to access. At least one second processor, wherein the target processor in the at least one second processor is configured to read the target data from the second inter-core communication component.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 17.

21. A system, characterized in that, include: A first communication system is used to perform the method according to any one of claims 1 to 13; A second communication system is used to perform the method according to any one of claims 14 to 16; A direct memory access module is used for data transmission between the first communication system and the second communication system.

22. A chip, characterized in that, Includes the system described in claim 21.

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