Pixel driving circuit, electronic device including same, and method of driving electronic device

Abstract

A method for driving an electronic device, an electronic device, and a pixel driving circuit are provided. The electronic device includes a display panel operating in a first luminance characteristic and a second luminance characteristic, the display panel including a pixel driving circuit and a light emitting element, the pixel driving circuit including a driving transistor and a switching transistor for receiving a data voltage. The method comprises the following steps: determining an initialization voltage corresponding to a first brightness characteristic; determining a first initialization voltage to be supplied to a gate electrode of the driving transistor in a first luminance characteristic by compensating the initialization voltage based on the margin voltage; determining a second initialization voltage to be supplied to the light emitting element in the first luminance characteristic based on the first initialization voltage and the driving condition; and providing the first initialization voltage and the second initialization voltage to the display panel.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0152554, filed on October 31, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to a pixel driving circuit capable of preventing display quality degradation, an electronic device including the pixel driving circuit, and a method for driving the electronic device. Background Technology

[0004] Organic light-emitting diodes (OLEDs) in display devices can display images by using organic light-emitting diodes (OLEDs) that generate light through the recombination of electrons and holes. OLEDs offer fast response times and low power consumption.

[0005] Organic light-emitting display devices may include pixels connected to data lines and scan lines. Each pixel may generally include an organic light-emitting diode (OLED) and a circuit unit that controls the amount of current flowing to the OLED. The OLED can produce light with a specific brightness corresponding to the amount of current received from the circuit unit. Summary of the Invention

[0006] Embodiments of this disclosure provide a pixel driving circuit capable of preventing display quality degradation, an electronic device including the pixel driving circuit, and a method for driving the electronic device.

[0007] According to an exemplary embodiment of the present disclosure, a method for driving an electronic device is provided. The electronic device includes a display panel, the display panel including a pixel driving circuit and a light-emitting element, the pixel driving circuit including a driving transistor and a switching transistor for receiving a data voltage. The method includes: determining an initialization voltage corresponding to a first brightness characteristic; determining a first initialization voltage to be provided to the gate electrode of the driving transistor in the first brightness characteristic by compensating the initialization voltage based on a margin voltage; determining a second initialization voltage to be provided to the light-emitting element in the first brightness characteristic based on the first initialization voltage and driving conditions; and providing the first initialization voltage and the second initialization voltage to the display panel.

[0008] According to an exemplary embodiment of the present disclosure, an electronic device is provided, comprising: a display panel including a plurality of pixels, wherein at least one of the plurality of pixels includes: a light-emitting element; and a pixel driving circuit connected to the light-emitting element, wherein the pixel driving circuit includes: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line providing a first driving voltage, and a second electrode connected to a second node; a second transistor including a gate electrode connected to a first scan line providing a first scan signal, a first electrode connected to a data line, and a second electrode connected to the first node; a first capacitor connected between the first node and a second node; and a second capacitor connected between the first power line and the second node. The third transistor includes a gate electrode connected to a second scan line providing a second scan signal different from the first scan signal, a first electrode connected to a first voltage line providing a first initialization voltage, and a second electrode connected to a first node; and the fourth transistor includes a gate electrode connected to a third scan line providing a third scan signal different from the first scan signal and the second scan signal, a first electrode connected to a light-emitting element, and a second electrode connected to a second voltage line providing a second initialization voltage, wherein the first initialization voltage is determined by compensating for a voltage level determined with respect to the minimum brightness for rendering black in the first brightness characteristic based on a margin voltage, and wherein the second initialization voltage is determined based on the first initialization voltage and driving conditions.

[0009] According to an exemplary embodiment of the present disclosure, a pixel driving circuit is provided, comprising: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line providing a first driving voltage, and a second electrode connected to a second node; a second transistor including a gate electrode connected to a first scan line providing a first scan signal, a first electrode connected to a data line, and a second electrode connected to the first node; a first capacitor connected between the first node and the second node; a second capacitor connected between the first power line and the second node; a third transistor including a gate electrode connected to a second scan line providing a second scan signal different from the first scan signal, a first electrode connected to a first voltage line providing a first initialization voltage, and a second electrode connected to the first node; and a fourth transistor including a gate electrode connected to a third scan line providing a third scan signal different from the first scan signal and the second scan signal, a first electrode connected to a third node, and a second electrode connected to a second voltage line providing a second initialization voltage, wherein the first initialization voltage is determined by compensating for a voltage level determined with respect to a minimum brightness for rendering black based on a margin voltage, and wherein the second initialization voltage is determined based on the first initialization voltage and driving conditions. Attached Figure Description

[0010] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0012] Figure 2 This is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0013] Figure 3 This is a rear perspective view showing an electronic device according to an embodiment of the present disclosure.

[0014] Figure 4 This is a perspective view showing an electronic device according to an embodiment of the present disclosure.

[0015] Figure 5 This is a perspective view showing an electronic device according to an embodiment of the present disclosure.

[0016] Figure 6 This is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0017] Figure 7 This is a cross-sectional view of the display layer according to an embodiment of the present disclosure.

[0018] Figure 8 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0019] Figure 9 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0020] Figure 10 This is a timing diagram of signals used to describe the operation of pixels according to embodiments of the present disclosure.

[0021] Figure 11 This is a flowchart illustrating a method for operating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0022] Various embodiments will be described in detail below with reference to the accompanying drawings.

[0023] The following detailed description is provided to aid the reader in fully understanding the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent after understanding the disclosure of this application. For example, the order of operations described herein is merely illustrative and is not limited to those set forth herein, but may be obviously changed after understanding the disclosure of this application (except that the operations must occur in a specific order). Furthermore, descriptions of features known after understanding the disclosure of this application may be omitted to improve clarity and conciseness.

[0024] The features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways in which the methods, apparatus, and / or systems described herein will become apparent upon understanding the disclosure of this application.

[0025] In the specification, the description of a first component (or area, layer or part) being "on", "connected to" or "linked to" a second component means that the first component is directly on, directly connected to or directly linked to the second component, or that a third component is inserted between them.

[0026] The same reference numerals will be assigned to the same components. Furthermore, in the drawings, the thickness, scale, and dimensions of components may be exaggerated to effectively describe technical features. The term "and / or" includes any and all combinations of one or more of the related components. As used herein, the expression "at least one of..." following an element in a list modifies the entire list of elements and does not modify any individual element in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0027] Although the terms "first" or "second" can be used to describe various components, the components should not be construed as being limited by the terms. The terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. The singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0028] Furthermore, the terms "below," "at the lower part," "above," and "at the upper part" are used to describe the relationships between the components shown in the accompanying drawings. The terms are relative and will be described with reference to the directions shown in the accompanying drawings.

[0029] It will also be understood that the terms “comprise,” “include,” or “including,” or “have,” or “having” specify the presence of the said feature, quantity, step, operation, component, part, or combination thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof.

[0030] The terms "part" and "unit" refer to software or hardware components used to perform a specific function. Hardware components may include field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). Software components may refer to executable code in addressable storage media and / or data used by the executable code. Therefore, software components can be, for example, object-oriented software components, class components, and task components, and may include processes, functions, attributes, procedures, subroutines, program code segments, driver data, firmware, microcode, circuits, data, databases, data structures, tables, arrangements, or variables.

[0031] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0032] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0033] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0034] refer to Figure 1 According to an embodiment, the electronic device 101 may include a processor 110, a memory 120, an input module 130, a display module 140, a power module 150, an embedded module 160, and an external module 170. The electronic device 101 can output various information through the display module 140 in the operating system. When the processor 110 executes an application stored in the memory 120, the display module 140 can provide application information to the user through the display panel 141.

[0035] Processor 110 can obtain external input through input module 130 or sensor module 161 and execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 141, processor 110 can obtain user input through input sensor 161-2 and activate camera module 171. Processor 110 can then transmit image data corresponding to the captured (e.g., photographed) image obtained through camera module 171 to display module 140. Display module 140 can display the image corresponding to the captured image through display panel 141.

[0036] As another example, when authentication of personal information is performed in display module 140, fingerprint sensor 161-1 can obtain input fingerprint information as input data. Processor 110 can compare the input data obtained by fingerprint sensor 161-1 with authentication data stored in memory 120 and execute the application based on the comparison result. Display module 140 can display information executed according to the application logic via display panel 141.

[0037] As another example, when a user selects a music stream icon displayed on display module 140, processor 110 can obtain user input via input sensor 161-2 and activate the music stream application stored in memory 120. When a music playback command is input to the music stream application, processor 110 can activate sound output module 163 and provide the user with sound information corresponding to the music playback command.

[0038] The operation of electronic device 101 has been briefly described above. The configuration of electronic device 101 will now be described in detail. Some of the components of electronic device 101 may be implemented as a single component, and a single component may be divided into two or more components. According to embodiments, electronic device 101 may not include at least one of the aforementioned components and / or may further include at least one different component. According to embodiments, some of the above components (e.g., sensor module 161, antenna module 162, or sound output module 163) may be integrated into any other component (e.g., display module 140).

[0039] Electronic device 101 can communicate with external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network).

[0040] The processor 110 can execute software to control at least one component (e.g., a hardware or software component) of the electronic device 101 connected to the processor 110, and can perform various data processing or operations. According to embodiments, as at least part of the data processing or operation, the processor 110 can store commands or data received from any other component (e.g., input module 130, sensor module 161, or communication module 173) in volatile memory 121, can process the commands or data stored in volatile memory 121, and can store the processed data in non-volatile memory 122.

[0041] Processor 110 may include a main processor 111 and an auxiliary processor 112. Main processor 111 may include at least one of a central processing unit (CPU) 111-1 and an application processor (AP). Main processor 111 may also include at least one of a graphics processing unit (GPU) 111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 111 may also include a neural processing unit (NPU) 111-3. Neural processing unit 111-3 may be a processor specifically designed for processing artificial intelligence models, and the artificial intelligence models may be created through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may include one of deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), restricted Boltzmann machines (RBM), deep belief networks (DBN), bidirectional recurrent deep neural networks (BRDNN), deep Q-networks, and combinations of at least two of these, but this disclosure is not limited thereto. Additionally or alternatively, the artificial intelligence model may include software structures in addition to hardware structures. At least two of the above processing units and processors can be integrated into a single component (e.g., a single chip), or each of the above processing units and processors can be implemented as an independent component (e.g., multiple chips).

[0042] The auxiliary processor 112 may include a controller 112-1. The controller 112-1 may include interface conversion circuitry and timing control circuitry. The controller 112-1 can receive image signals from the main processor 111 and output image data obtained by converting the data format of the image signals to conform to the specifications of the interface of the display module 140. The controller 112-1 can output various types of control signals for driving the display module 140.

[0043] The auxiliary processor 112 may further include a data conversion circuit 112-2, a gamma correction circuit 112-3, and a rendering circuit 112-4. The data conversion circuit 112-2 can receive image data from the controller 112-1 and can compensate the image data to display an image at a desired brightness according to the characteristics of the electronic device 101 or user settings, or can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit 112-3 can convert the image data or a gamma reference voltage so that the image displayed on the electronic device 101 has desired gamma characteristics. The rendering circuit 112-4 can receive image data from the controller 112-1 and can render the image data taking into account the pixel arrangement of the display panel 141 of the electronic device 101. At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into any other component (e.g., the main processor 111 or the controller 112-1). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into the data driver 143, which will be described later.

[0044] The memory 120 may store various data used by at least one component of the electronic device 101 (e.g., processor 110 or sensor module 161), as well as input or output data for commands associated therewith. The memory 120 may include at least one of volatile memory 121 and non-volatile memory 122.

[0045] The input module 130 can receive commands or data from outside the electronic device 101 (e.g., from a user or external electronic device 102) to be used by components of the electronic device 101 (e.g., processor 110, sensor module 161, or sound output module 163).

[0046] Input module 130 may include a first input module 131 for receiving commands or data from a user and a second input module 132 for receiving command or data input from an external electronic device 102. The first input module 131 may include, for example, (but not limited to) a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 132 may support specified protocols enabling wired and / or wireless connection to the external electronic device 102. Depending on the implementation, the second input module 132 may include, for example, (but not limited to) a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital Card (SD) card interface, or an audio interface. The second input module 132 may include connectors capable of physically connecting to the external electronic device 102, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0047] Display module 140 can visually provide information to the user. Display module 140 may include display panel 141, scan driver 142, and data driver 143. Display module 140 may also include a window, chassis, and bracket to protect display panel 141.

[0048] The display panel 141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of display panel 141 is not particularly limited. The display panel 141 may be of a rigid type or a flexible type that can be rolled or folded. The display module 140 may also include a support member, bracket, or heat dissipation member that supports the display panel 141.

[0049] The scan driver 142, used as a driving chip, can be mounted on the display panel 141. Alternatively, the scan driver 142 can be integrated into the display panel 141. For example, the scan driver 142 may include an amorphous silicon TFT gate (ASG) driver circuit, a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor (OSG) TFT gate driver circuit disposed in the display panel 141. The scan driver 142 can receive control signals from the controller 112-1 and output scan signals to the display panel 141 in response to the control signals.

[0050] The display panel 141 may also include a light-emitting driver. The light-emitting driver can output a light-emitting control signal to the display panel 141 in response to a control signal received from the controller 112-1. The light-emitting driver may be formed separately from the scan driver 142, or it may be integrated into the scan driver 142.

[0051] The data driver 143 can receive data control signals from the controller 112-1. After converting image data into an analog voltage (e.g., data voltage) in response to the data control signals, the data driver 143 can output the converted analog voltage to the display panel 141.

[0052] The data driver 143 can be integrated into another component (e.g., controller 112-1). The functions of the interface conversion circuit and timing control circuit of the controller 112-1 can be integrated into the data driver 143.

[0053] The display module 140 may also include a light-emitting driver and a voltage generating circuit. The voltage generating circuit can output various types of voltages for driving the display panel 141.

[0054] Power module 150 can provide power to components of electronic device 101. Power module 150 may include a battery charged with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 150 may include a power management integrated circuit (PMIC). The PMIC can provide optimized power for each of the modules described above and below. Power module 150 may include wireless power transmission / reception components electrically connected to the battery. The wireless power transmission / reception components may include multiple antenna radiators in the form of coils.

[0055] The electronic device 101 may also include an embedded module 160 and an external module 170. The embedded module 160 may include a sensor module 161, an antenna module 162, and a sound output module 163. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0056] The sensor module 161 can sense input from the user's body or a pen in the first input module 131, and can generate an electrical signal or data value corresponding to the input. The sensor module 161 may include at least one of a fingerprint sensor 161-1, an input sensor 161-2, and a digitizer 161-3.

[0057] The fingerprint sensor 161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 161-1 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0058] Input sensor 161-2 can generate data values ​​corresponding to the coordinate information of input from the user's body or a pen. Input sensor 161-2 can generate capacitance changes caused by input in the form of data values. Input sensor 161-2 can sense input from a passive pen or exchange data with an active pen.

[0059] Input sensor 161-2 can measure biometric signals such as blood pressure, humidity, or body fat. For example, when a user's body part touches the sensor layer or sensing panel and remains stationary for a specific period of time, input sensor 161-2 can sense the biometric signal based on changes in the electric field caused by the body part and can output information about the sensed biometric signal to display module 140.

[0060] The digitizer 161-3 can generate data values ​​corresponding to the coordinate information input by the user or pen. The digitizer 161-3 can generate electromagnetic changes caused by the input in the form of data values. The digitizer 161-3 can sense input from a passive pen or exchange data with an active pen.

[0061] At least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be implemented as a sensor layer formed on the display panel 141 by subsequent processes. The fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be disposed above / on the display panel 141. In an embodiment, at least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 (e.g., digitizer 161-3) can be disposed below / under the display panel 141.

[0062] At least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be integrally formed in the form of a single sensing panel using the same process. When at least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 are integrally formed in the form of a single sensing panel, the sensing panel can be disposed between the display panel 141 and a window disposed above / on the display panel 141. According to one embodiment, the sensing panel can be disposed on the window, and the position of the sensing panel is not particularly limited.

[0063] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be embedded in the display panel 141. In other words, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be formed simultaneously with the display panel 141 by a process for forming components (e.g., light-emitting elements and / or transistors) included in the display panel 141.

[0064] In addition, sensor module 161 can generate electrical signals or data values ​​corresponding to the internal or external state of electronic device 101. Sensor module 161 may also include, for example (but not limited to), gesture sensors, gyroscope sensors, pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biometric sensors, temperature sensors, humidity sensors, or illuminance sensors.

[0065] Antenna module 162 may include at least one antenna to transmit and / or receive signals or power from an external source. According to embodiments, communication module 173 may transmit signals to and / or receive signals from external electronic device 102 via an antenna suitable for a communication scheme. The antenna configuration of antenna module 162 may be integrated into a component of display module 140 (e.g., display panel 141) or into input sensors 161-2.

[0066] The sound output module 163 can output sound signals to the outside of the electronic device 101, and may include, for example, a speaker for general purposes (such as multimedia playback or recording playback) and a receiver specifically for receiving calls. Depending on the implementation, the receiver and speaker may be integrated or separate. The sound output mode of the sound output module 163 may be integrated into the display module 140.

[0067] Camera module 171 can capture (e.g., photograph) still images and / or moving images. According to one embodiment, camera module 171 may include at least one lens, image sensor, or image signal processor. Camera module 171 may also include an infrared camera capable of detecting the presence of a user, the user's position, and the user's line of sight.

[0068] The light module 172 can provide light. The light module 172 may include a light-emitting diode or a xenon lamp. The light module 172 can operate together with the camera module 171, or it can operate independently.

[0069] Communication module 173 can establish a wired or wireless communication channel between electronic device 101 and external electronic device 102, and can support communication execution through the established communication channel. Communication module 173 may include at least one of a wireless communication module (such as a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) and a wired communication module (such as a local area network (LAN) communication module or a power line communication module). Communication module 173 can communicate with external electronic device 102 via a short-range communication network such as Bluetooth, Wi-Fi Direct, or Infrared Data Association (IrDA), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN)). The various types of communication modules described above can be implemented as a single chip or as separate chips.

[0070] The input module 130, sensor module 161, and camera module 171 can be used to control the operation of the display module 140 when operating together with the processor 110.

[0071] The processor 110 can output commands or data to the display module 140, the sound output module 163, the camera module 171, or the optical module 172 based on the input data received from the input module 130. For example, the processor 110 can generate image data corresponding to the input data applied by a mouse or active pen, and can output the image data to the display module 140; alternatively, the processor 110 can generate command data corresponding to the input data and can output the command data to the camera module 171 or the optical module 172. When no input data is received from the input module 130 during a specific time period, the processor 110 can switch the operating mode of the electronic device 101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 101.

[0072] The processor 110 can output commands or data to the display module 140, the sound output module 163, the camera module 171, or the optical module 172 based on the sensing data received from the sensor module 161. For example, the processor 110 can compare the authentication data obtained by the fingerprint sensor 161-1 with the authentication data stored in the memory 120, and can execute an application based on the comparison result. The processor 110 can execute commands based on the sensing data sensed by the input sensor 161-2 or the digitizer 161-3, or it can output image data corresponding to the sensing data to the display module 140. When the sensor module 161 includes a temperature sensor, the processor 110 can receive temperature data about the measured temperature from the sensor module 161, and can further correct the brightness of the image data based on the temperature data.

[0073] Processor 110 can receive measurement data from camera module 171 related to the presence of a user, the user's position, and the user's line of sight. Processor 110 can further correct the brightness of image data based on the measurement data. For example, processor 110, which determines the presence of a user based on input from camera module 171, can output image data with brightness corrected by data conversion circuit 112-2 or gamma correction circuit 112-3 to display module 140.

[0074] Some of the components described above can be connected to each other via communication schemes between peripheral devices (e.g., buses, general purpose input / output (GPIO), serial peripheral interfaces (SPI), mobile industrial processor interfaces (MIPI), or ultrapath interconnect (UPI) links) and can exchange signals (e.g., commands or data). Processor 110 can communicate with display module 140 via a specific interface. For example, one of the communication schemes described above can be used, and this disclosure is not limited thereto.

[0075] The electronic device 101 according to various embodiments of the present disclosure can be implemented as various types of devices. The electronic device 101 may include at least one of, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. The electronic device 101 according to embodiments of the present disclosure is not limited to the above-mentioned devices.

[0076] Figure 2 This is a perspective view of an electronic device according to an embodiment of the present disclosure, and Figure 3 This is a rear perspective view of an electronic device according to an embodiment of the present disclosure.

[0077] refer to Figure 2 and Figure 3 The electronic device 1000 can be activated in response to an electrical signal. For example, the electronic device 1000 can display an image.

[0078] The electronic device 1000 may include a first display panel DP1 and a second display panel DP2. The first display panel DP1 and the second display panel DP2 may be separate panels that are independent of each other. The first display panel DP1 may be referred to as the main display panel, and the second display panel DP2 may be an auxiliary display panel or an external display panel.

[0079] The first display panel DP1 may include a first display unit DA1-F, and the second display panel DP2 may include a second display unit DA2-F. The second display panel DP2 may have an area smaller than that of the first display panel DP1. The size of the first display unit DA1-F, corresponding to the size of the first display panel DP1, may be larger than the size of the second display unit DA2-F, corresponding to the size of the second display panel DP2.

[0080] When the electronic device 1000 is unfolded, the first display unit DA1-F may have a plane substantially parallel to the plane defined by the first direction DR1 and the second direction DR2. The thickness direction of the electronic device 1000 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Therefore, the front surface (or top surface / upper surface) and rear surface (or bottom surface / lower surface) of the components included in the electronic device 1000 may be defined based on the third direction DR3.

[0081] The first display panel DP1 or the first display unit DA1-F may include a folded or unfolded folded region FA and a plurality of non-folded regions NFA1 and NFA2 spaced apart from each other, wherein the folded region FA is interposed between the non-folded regions NFA1 and NFA2. The second display panel DP2 may overlap with any one of the plurality of non-folded regions NFA1 and NFA2. For example, the second display panel DP2 may overlap with the first non-folded region NFA1.

[0082] The display orientation of the first image IM1a displayed on a portion of the first display panel DP1 (e.g., the second non-folding region NFA2) may be opposite to the display orientation of the second image IM2a displayed on the second display panel DP2. For example, the first image IM1a may be displayed on a third direction DR3, and the second image IM2a may be displayed on a fourth direction DR4, which is opposite to the third direction DR3.

[0083] According to embodiments of this disclosure, the folding region FA can be bent around a folding axis extending in a direction parallel to the longer side (or edge) of the electronic device 1000 (e.g., parallel to the second direction DR2). When the electronic device 1000 is folded, the folding region FA can have a specific curvature and a specific radius of curvature. When the electronic device 1000 is folded, the first non-folding region NFA1 and the second non-folding region NFA2 can face each other, and the electronic device 1000 can be in an inward folded state, such that the first display unit DA1-F is not exposed to the outside.

[0084] According to embodiments of the present disclosure, when the electronic device 1000 is folded, it can be in an outward-folded state, exposing the first display unit DA1-F to the outside. According to embodiments of the present disclosure, the electronic device 1000 can be in an inward-folded state or an outward-folded state, transitioning from a state in which the electronic device 1000 is unfolded, and the present disclosure is not limited thereto.

[0085] Figure 2 A folding region FA is shown defined (set or included) in electronic device 1000, but this disclosure is not limited thereto. For example, a plurality of folding axes and a plurality of folding regions corresponding to the plurality of folding axes may be defined in electronic device 1000, and electronic device 1000 may be in an inward folding state or an outward folding state in each of the plurality of folding regions.

[0086] Figure 4 This is a perspective view of an electronic device according to an embodiment of the present disclosure, and Figure 5 This is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0087] Figure 4The electronic device 1000-1 shown according to an embodiment is a tablet personal computer, and the electronic device 1000-1 may include a display panel DP. Figure 5 The electronic device 1000-2 shown according to an embodiment is a laptop computer, and the electronic device 1000-2 may include a display panel DP.

[0088] Figure 6 This is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0089] refer to Figure 6 The display panel DP may include a display layer 100. Display layer 100 may be a component that substantially generates an image. Display layer 100 may be a light-emitting display layer. For example, display layer 100 may be an organic light-emitting display layer, an inorganic light-emitting display layer, an organic-inorganic light-emitting display layer, a quantum dot display layer, a micro-light-emitting diode (LED) display layer, or a nano-LED display layer. The display panel DP may include a display area 100A and a peripheral area 100NA adjacent to the display area 100A. The peripheral area 100NA may surround the display area 100A. Display layer 100 may include a base layer 110, a circuit layer 120, a light-emitting element layer 130, and an encapsulation layer 140.

[0090] The base layer 110 may be a component providing a base surface on which the circuit layer 120 is disposed. The base layer 110 may have a multilayer structure or a single-layer structure. The base layer 110 may be implemented using a glass substrate, a metal substrate, a silicon substrate, or a polymer substrate, but this disclosure is not limited thereto.

[0091] Circuit layer 120 may be disposed on base layer 110. Circuit layer 120 may include insulating layer, semiconductor pattern, conductive pattern, and signal lines. The insulating layer, semiconductor layer, and conductive layer may be formed on base layer 110 by coating or deposition processes, and may be selectively patterned by multiple photolithography processes.

[0092] The light-emitting element layer 130 may be disposed on the circuit layer 120. The light-emitting element layer 130 may include light-emitting elements. For example, the light-emitting element layer 130 may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, micro LEDs, or nano LEDs.

[0093] An encapsulation layer 140 may be disposed on the light-emitting element layer 130. The encapsulation layer 140 can protect the light-emitting element layer 130 from moisture, oxygen and foreign matter such as dust particles.

[0094] Figure 7 This is a cross-sectional view of a display layer according to an embodiment of the present disclosure. See the following references. Figure 7 In the description, refer to Figure 6The components described are given the same reference numerals, and their details will be omitted.

[0095] refer to Figure 7 At least one buffer layer BFL may be formed on the top surface of the base layer 110. The buffer layer BFL can improve the adhesion between the base layer 110 and the semiconductor pattern. The buffer layer BFL can be formed as a multilayer structure. Alternatively, the display layer 100 may also include a barrier layer. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are stacked alternately.

[0096] Semiconductor patterns SC, AL, DR, and SCL can be disposed on the buffer layer BFL. The semiconductor patterns SC, AL, DR, and SCL can comprise polycrystalline silicon. However, this disclosure is not limited thereto. For example, the semiconductor patterns SC, AL, DR, and SCL can comprise amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductor.

[0097] Figure 7 Only a portion of the semiconductor patterns SC, AL, DR, and SCL are shown, and these patterns can be further disposed in any other regions. The semiconductor patterns SC, AL, DR, and SCL can be arranged across pixels according to specific rules. Depending on the doping state, the semiconductor patterns SC, AL, DR, and SCL can have various electrical properties. The semiconductor patterns SC, AL, DR, and SCL may include a first region SC, DR, and SCL with higher conductivity and a second region AL with lower conductivity. The first regions SC, DR, and SCL can be doped with N-type or P-type dopant. A P-type transistor may include a region doped with P-type dopant, and an N-type transistor may include a region doped with N-type dopant. The second region AL may be an undoped region or a region doped at a concentration lower than that of the first regions SC, DR, and SCL.

[0098] The conductivity of the first regions SC, DR, and SCL can be greater than that of the second region AL, and can be substantially used as electrodes or signal lines. The second region AL can substantially correspond to the active region AL (or channel) of transistor 100PC. In other words, a portion AL of the semiconductor patterns SC, AL, DR, and SCL can be the active region AL of transistor 100PC, another portion SC and DR of the semiconductor patterns SC, AL, DR, and SCL can be the source region SC or drain region DR of transistor 100PC, and yet another portion SCL of the semiconductor patterns SC, AL, DR, and SCL can be a connecting electrode or a connecting signal line SCL.

[0099] Each pixel may have an equivalent circuit comprising multiple transistors, at least one capacitor and at least one light-emitting element, and the equivalent circuit of a pixel may be modified in various forms. Figure 7 The pixel shown includes a transistor 100PC and a light-emitting element 100PE.

[0100] The source region SC, active region AL, and drain region DR of transistor 100PC can be formed by semiconductor patterns SC, AL, DR, and SCL. When viewed in a cross-sectional view, the source region SC and drain region DR can extend from the active region AL in opposite directions to each other. Figure 7 A portion of the connection signal line SCL, formed by semiconductor patterns SC, AL, DR, and SCL, is shown. Although not shown separately, when viewed in a plan view, the connection signal line SCL can be connected to the drain region DR of transistor 100PC.

[0101] A first insulating layer 10 may be disposed on a buffer layer BFL. The first insulating layer 10 may overlap with multiple pixels to cover semiconductor patterns SC, AL, DR, and SCL. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include, for example (but not limited to), at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. According to an embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. In addition to the first insulating layer 10, the insulating layer of the circuit layer 120, which will be described later, may also be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the materials described above, and this disclosure is not limited thereto.

[0102] The gate GT of transistor 100PC can be disposed on the first insulating layer 10. The gate GT can be part of a metal pattern. The gate GT can overlap with the active region AL. In the process of doping or reducing semiconductor patterns SC, AL, DR, and SCL, the gate GT can be used as a mask.

[0103] A second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate GT. The second insulating layer 20 may overlap with the pixel in a common ground. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. The second insulating layer 20 may include, for example, (but not limited to) at least one of silicon oxide, silicon nitride, and silicon oxynitride. According to an embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0104] The third insulating layer 30 may be disposed on the second insulating layer 20. The third insulating layer 30 may have a single-layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0105] The first connection electrode CNE1 can be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the connection signal line SCL through the contact hole CNT-1 formed through the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30.

[0106] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single layer of silicon oxide. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0107] The second connecting electrode CNE2 can be disposed on the fifth insulating layer 50. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the contact hole CNT-2 formed through the fourth insulating layer 40 and the fifth insulating layer 50.

[0108] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0109] The light-emitting element layer 130 may be disposed on the circuit layer 120. The light-emitting element layer 130 may include a light-emitting element 100PE. For example, the light-emitting element layer 130 may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, microLEDs, or nanoLEDs. The following description of the light-emitting element 100PE as an organic light-emitting element will be given by way of example, but this disclosure is not specifically limited thereto.

[0110] The light-emitting element 100PE may include a first electrode AE, a light-emitting layer EL, and a second electrode CE.

[0111] The first electrode AE ​​can be disposed on the sixth insulating layer 60. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through the contact hole CNT-3 formed through the sixth insulating layer 60. The first electrode AE ​​can be referred to as the anode AE.

[0112] A pixel defining layer 70 may be disposed on the sixth insulating layer 60 to cover a portion of the first electrode AE. An opening 70-OP may be defined in the pixel defining layer 70. The opening 70-OP in the pixel defining layer 70 may expose at least a portion of the first electrode AE.

[0113] First display unit DA1-F (see...) Figure 2The electrode may include an emitting region PXA and a non-emitting region NPXA adjacent to the emitting region PXA. The non-emitting region NPXA may surround the emitting region PXA. According to an embodiment, the emitting region PXA may be defined to correspond to a portion of the first electrode AE ​​exposed by the opening 70-OP.

[0114] The light-emitting layer EL can be disposed on the first electrode AE. The light-emitting layer EL can be disposed in the region corresponding to the opening 70-OP. Although Figure 7 The illustration shows an emitting layer EL disposed in an opening 70-OP, but the present disclosure is not limited thereto. For example, the emitting layer EL may extend to cover a portion of the side surface and the top surface of the pixel defining layer 70 defining the opening 70-OP.

[0115] According to embodiments of this disclosure, the light-emitting layer (EL) can be formed independently for each pixel. When the light-emitting layer (EL) is formed independently for each pixel, each of the ELs can emit light having at least one color selected from blue, red, and green. However, this disclosure is not limited thereto. For example, the ELs can be commonly included in the pixel. In this case, the ELs can provide blue light or can provide white light.

[0116] The second electrode CE can be disposed on the light-emitting layer EL. The second electrode CE can have a monolithic shape and can be commonly included in multiple pixels. The second electrode CE can be referred to as the cathode CE.

[0117] According to embodiments of this disclosure, a hole control layer can be interposed between a first electrode AE ​​and a light-emitting layer EL. The hole control layer can be commonly disposed in the emitting region PXA and the non-emitting region NPXA. The hole control layer may include a hole transport layer and may also include a hole injection layer. An electronic control layer can be interposed between the light-emitting layer EL and the second electrode CE. The electronic control layer may include an electron transport layer and may also include an electron injection layer. The hole control layer and the electronic control layer can be commonly formed in multiple pixels using an aperture mask or an inkjet process.

[0118] An encapsulation layer 140 may be disposed on the light-emitting element layer 130. The encapsulation layer 140 may include sequentially stacked inorganic layers, organic layers, and inorganic layers, and the layers included in the encapsulation layer 140 are not limited thereto. The inorganic layer may protect the light-emitting element layer 130 from moisture and oxygen, and the organic layer may protect the light-emitting element layer 130 from foreign matter such as dust particles. The inorganic layer may include, for example, (but not limited to) a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an acrylic-based organic layer, but this disclosure is not limited thereto.

[0119] Figure 8This is a block diagram of an electronic device according to embodiments of the present disclosure.

[0120] refer to Figure 8 The electronic device 1000 may include a display panel DP and a drive controller DC.

[0121] The drive controller DC may include a timing controller TC, a scan drive circuit SDC, and a data drive circuit DDC.

[0122] The timing controller TC can receive image and control signals from an external source. The timing controller TC can generate image data (D-RGB) by converting the image signal data format to meet the interface specifications with the data drive circuit (DDC). The timing controller TC can convert control signals to generate scan control signals (SCS) and data control signals (DCS). The timing controller TC can output image data (D-RGB), data control signals (DCS), and scan control signals (SCS).

[0123] The scan driver circuit SDC can receive scan control signals SCS from the timing controller TC. The scan control signals SCS may include a vertical start signal to initiate the operation of the scan driver circuit SDC and a clock signal to determine the output timing of the signals. The scan driver circuit SDC can generate multiple first scan signals, multiple second scan signals, and multiple third scan signals. The scan driver circuit SDC can output multiple first scan signals to multiple first scan lines GWL1 to GWLn, multiple second scan signals to multiple second scan lines GIL1 to GILn, and multiple third scan signals to multiple third scan lines GRL1 to GRLn.

[0124] Furthermore, the scan drive circuit SDC can generate multiple first light emission control signals and multiple second light emission control signals in response to the scan control signal SCS. The scan drive circuit SDC can output multiple first light emission control signals to multiple first light emission lines EML1 to EMLn, and output multiple second light emission control signals to multiple second light emission lines EMBL1 to EMBLn.

[0125] although Figure 8The illustration shows multiple first scan signals to multiple third scan signals, as well as multiple first light emission control signals and multiple second light emission control signals, output from a scan driver circuit SDC; however, this disclosure is not limited thereto. According to embodiments of this disclosure, the drive controller DC may include multiple scan driver circuits SDC. The multiple scan driver circuits SDC can respectively output multiple first scan signals to multiple third scan signals, as well as multiple first light emission control signals and multiple second light emission control signals. Furthermore, according to embodiments of this disclosure, the scan driver circuit SDC may include a drive circuit that generates and outputs multiple first scan signals to multiple third scan signals, and a drive circuit that generates and outputs multiple first light emission control signals and multiple second light emission control signals.

[0126] The data drive circuit DDC receives the data control signal DCS and image data D-RGB from the timing controller TC. The data drive circuit DDC converts the image data D-RGB into a data voltage and outputs the data voltage to multiple data lines DL1 to DLm, which will be described later. The data voltage can be an analog voltage corresponding to the grayscale values ​​of the image data D-RGB.

[0127] The display panel DP may include multiple first scan lines GWL1 to GWLn, multiple second scan lines GIL1 to GILn, multiple third scan lines GRL1 to GRLn, multiple first light-emitting lines EML1 to EMLn, multiple second light-emitting lines EMBL1 to EMBLn, multiple data lines DL1 to DLm, a first power line PL, a first voltage line VRL, a second voltage line VL, and multiple pixels PX11 to PXnm. The first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, the third scan lines GRL1 to GRLn, the first light-emitting lines EML1 to EMLn, and the second light-emitting lines EMBL1 to EMBLn may extend in a first direction DR1 and may be arranged in a second direction DR2 that intersects the first direction DR1.

[0128] Data lines DL1 to DLm can be insulated from the first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, the third scan lines GRL1 to GRLn, the first light-emitting lines EML1 to EMLn, and the second light-emitting lines EMBL1 to EMBLn, while also intersecting with these lines. Multiple pixels PX11 to PXnm can be connected to corresponding scan lines among GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn. The connection relationships between pixels PX11 to PXnm and scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn can vary depending on the configuration of the driving circuitry for the multiple pixels PX11 to PXnm.

[0129] The first power line PL can receive the first drive voltage ELVDD. The first voltage line VRL can receive the first initialization voltage Vref. The second voltage line VL can receive the second initialization voltage Vaint. The first voltage line VRL can receive the first drive voltage ELVDD. The second initialization voltage Vaint can have a voltage level lower than the voltage level of the first drive voltage ELVDD. The second drive voltage ELVSS can be applied to the display panel DP. The second drive voltage ELVSS can have a voltage level lower than the voltage level of the first drive voltage ELVDD. The first initialization voltage Vref can have a voltage level higher than the voltage level of the second initialization voltage Vaint.

[0130] Although it has been referenced Figure 8 An electronic device 1000 according to an embodiment has been described, but the electronic device 1000 according to the embodiments of this disclosure is not limited thereto. Depending on the pixel configuration, in addition to scan lines GWL1 to GWLn, GIL1 to GILn, and GRL1 to GRLn, the electronic device 1000 may include additional scan lines, or the scan lines GWL1 to GWLn, GIL1 to GILn, and GRL1 to GRLn may be omitted from the electronic device 1000. Furthermore, the connection relationship between pixels PX11 to PXnm and scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn can be changed.

[0131] Multiple pixels from PX11 to PXnm can include OLEDs containing light-emitting elements that emit light of different colors from each other (see [link to OLED]). Figure 9Multiple pixel groups. For example, multiple pixel groups may include red pixels that produce red light, green pixels that produce green light, and blue pixels that produce blue light. The light-emitting elements of the red pixels, the green pixels, and the blue pixels may each include a light-emitting layer containing different materials.

[0132] Each of the multiple pixels PX11 to PXnm may include multiple transistors and at least one capacitor electrically connected to the transistors. Details will be described later. At least one of the scan drive circuit SDC and the data drive circuit DDC may include multiple transistors formed using the same process as that used for the pixel drive circuitry.

[0133] The aforementioned scan lines GWL1 to GWLn, GIL1 to GILn and GRL1 to GRLn, multiple pixels PX11 to PXnm, scan drive circuit SDC and data drive circuit DDC can be formed on the base substrate through multiple photolithography processes.

[0134] Figure 9 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0135] Figure 9 The pixel PXij shown can be Figure 8 An implementation of any one of the plurality of pixels PX11 to PXnm shown.

[0136] refer to Figure 9 Pixel PXij can be connected to the j-th data line (or data line) DLj among data lines DL1 to DLm, the i-th first scan line (or first scan line) GWLi among first scan lines GWL1 to GWLn, the i-th second scan line (or second scan line) GILi among second scan lines GIL1 to GILn, the i-th third scan line (or third scan line) GRLi among third scan lines GRL1 to GRLn, the i-th first light-emitting line (or first light-emitting line) EMLi among first light-emitting lines EML1 to EMLn, and the i-th second light-emitting line (or second light-emitting line) EMBLi among second light-emitting lines EMBL1 to EMBLn. In this case, 'i' and 'j' are positive integers.

[0137] Pixel PXij can be connected to a first scan line GWLi to transmit a first scan signal GW, to a second scan line GILi to transmit a second scan signal GI, to a third scan line GRLi to transmit a third scan signal GR, to a first light-emitting line EMLi to transmit a first light-emitting control signal EM, to a second light-emitting line EMBLi to transmit a second light-emitting control signal EMB, and to a data line DLj to transmit a data voltage Vdata. Furthermore, pixel PXij can be connected to a first power line PL to transmit a first drive voltage ELVDD, to a first voltage line VRL to transmit a first initialization voltage Vref, and to a second voltage line VL to transmit a second initialization voltage Vaint.

[0138] Pixel PXij may include an OLED (Light Emitting Device) and a pixel driving circuit PC. For example, the OLED may be an organic light-emitting element including an organic light-emitting layer. The pixel driving circuit PC may be connected to the OLED to control the amount of current flowing through the OLED, and the OLED may generate light with a specific brightness depending on the amount of current supplied to it.

[0139] According to embodiments of this disclosure, pixel PXij can have a 6T2C structure. That is, pixel PXij can include six transistors and two capacitors.

[0140] Each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may be an N-type transistor having a semiconductor layer including an oxide semiconductor. However, this is provided for illustrative purposes only. For example, the semiconductor layer according to embodiments of this disclosure is not limited thereto and may include amorphous silicon, low-temperature polycrystalline silicon (LTPS), or crystalline silicon. The first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6, implemented as N-type transistors, may have minor changes in device characteristics or minor transient afterimages. However, this is provided for illustrative purposes only. For example, all of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 may be P-type transistors. According to the implementation, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be an N-type transistor, and the remaining transistors of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be P-type transistors.

[0141] A first transistor T1 can be electrically connected between a first power line PL and a second node N2. The first transistor T1 may include a first gate electrode connected to the first node N1, a first electrode electrically connected to the first power line PL to receive a first drive voltage ELVDD, and a second electrode connected to the second node N2. The first electrode can be connected to the first power line PL via a fifth transistor T5. The second electrode can be connected to a third node N3 via a sixth transistor T6. The first transistor T1 may also include a second gate electrode connected to the second node N2. The first and second gate electrodes can be disposed in different layers facing each other. The first transistor T1 can receive a data voltage Vdata according to the switching operation of the second transistor T2 to control the amount of drive current Id flowing through the light-emitting element OLED. The first transistor T1 may be referred to as a drive transistor.

[0142] A second transistor T2 can be connected between the data line DLj and the first node N1. The second transistor T2 may include a gate electrode connected to the first scan line GWLi to receive the first scan signal GW, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 can be turned on in response to the first scan signal GW to electrically connect the data line DLj to the first node N1 and transmit the data voltage Vdata transmitted to the data line DLj to the first node N1. The second transistor T2 can be referred to as a switching transistor.

[0143] A third transistor T3 may be connected between the first gate electrode of the first transistor T1 and the first voltage line VRL. The third transistor T3 may include a gate electrode connected to the third scan line GRLi to receive a third scan signal GR, a first electrode connected to the first voltage line VRL to receive a first initialization voltage Vref, and a second electrode connected to the first node N1. The third transistor T3 may be turned on in response to the third scan signal GR received via the third scan line GRLi to transmit the first initialization voltage Vref received via the first voltage line VRL to the first node N1. The third transistor T3 may be referred to as a reset transistor.

[0144] A fourth transistor T4 may be electrically connected between the second voltage line VL and the third node N3. The fourth transistor T4 may include a gate electrode connected to the second scan line GILi to receive the second scan signal GI, a first electrode connected to the third node N3, and a second electrode connected to the second voltage line VL to receive the second initialization voltage Vaint. The fourth transistor T4 may be turned on in response to the second scan signal GI received through the second scan line GILi to transmit the second initialization voltage Vaint received through the second voltage line VL to the third node N3. The fourth transistor T4 may be referred to as the initialization transistor.

[0145] A fifth transistor T5 can be connected between the first power line PL and the first transistor T1. The fifth transistor T5 may include a gate electrode connected to the first light-emitting line EMLi to receive a first light-emitting control signal EM, a first electrode connected to the first power line PL, and a second electrode connected to the first electrode of the first transistor T1. The fifth transistor T5 can be turned on or off according to the first light-emitting control signal EM received through the first light-emitting line EMLi. The fifth transistor T5 may be referred to as the first light-emitting transistor.

[0146] A sixth transistor T6 can be connected between the first transistor T1 and the light-emitting element OLED. The sixth transistor T6 may include a gate electrode connected to the second light-emitting line EMBLi to receive a second light-emitting control signal EMB, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The sixth transistor T6 can be turned on or off according to the second light-emitting control signal EMB received through the second light-emitting line EMBLi. The sixth transistor T6 may be referred to as the second light-emitting transistor.

[0147] A first capacitor C1 can be connected between a first node N1 and a second node N2. The first capacitor C1 may include a first electrode and a second electrode. The first electrode of the first capacitor C1 can be connected to the first gate electrode of the first transistor T1, and the second electrode of the first capacitor C1 can be connected to the second electrode of the first transistor T1. The first capacitor C1 can store a voltage corresponding to a threshold voltage and a data signal. The first capacitor C1 can be referred to as a storage capacitor.

[0148] A second capacitor C2 can be connected between the first power line PL and the second node N2. The second capacitor C2 may include a first electrode and a second electrode. The first electrode of the second capacitor C2 can be connected to the first power line PL. The second electrode of the second capacitor C2 can be connected to the second gate electrode of the first transistor T1 and the second electrode of the first capacitor C1. The second capacitor C2 may have a capacitance smaller than that of the first capacitor C1. The second capacitor C2 may be referred to as a holding capacitor.

[0149] The light-emitting element OLED can be electrically connected to the first transistor T1. The light-emitting element OLED may include a first electrode AE ​​connected to the third node N3 (see...). Figure 7 ) and facing the first electrode AE ​​(see Figure 7 The second electrode CE (see) Figure 7 Second electrode CE (see) Figure 7 It can receive the second drive voltage ELVSS. The second electrode CE (see...) Figure 7 ) can be for multiple pixels PX11 to PXnm (see Figure 8 ) Public common electrode.

[0150] Figure 10 It is a waveform diagram of signals used to describe the operation of pixels according to embodiments of the present disclosure.

[0151] refer to Figures 8 to 10 The display panel (DP) can operate on a frame-period basis. Pixels (PXij) can operate in the non-emission period (NEP) and the emission period (EP) of each frame period. The non-emission period (NEP) can include a first initialization period (P1), a compensation period (P2), a write period (P3), and a second initialization period (P4).

[0152] Each of the first scan signal GW, the second scan signal GI, the third scan signal GR, the first light emission control signal EM, and the second light emission control signal EMB may have a high-level voltage during some cycles and a low-level voltage during some cycles. In this case, the high-level voltage may be a turn-on voltage for turning on the transistor, and the low-level voltage may be a cut-off voltage for turning off the transistor.

[0153] During the first initialization period P1, a second scan signal GI with an on-state voltage can be provided to the second scan line GILi, a third scan signal GR with an on-state voltage can be provided to the third scan line GRLi, and a second light emission control signal EMB with an on-state voltage can be provided to the second light emission line EMBLi. The first scan signal GW and the first light emission control signal EM can have off-state voltages during the first initialization period P1.

[0154] The fourth transistor T4 can be turned on in response to the second scan signal GI with a turn-on voltage, the third transistor T3 can be turned on in response to the third scan signal GR with a turn-on voltage, and the sixth transistor T6 can be turned on in response to the second light emission control signal EMB with a turn-on voltage.

[0155] The gate electrode of the first transistor T1 can be initialized to the first initialization voltage Vref by the conducting third transistor T3.

[0156] The first electrode AE ​​of the light-emitting element OLED (see Figure 7 The second node N2 can be initialized to the second initialization voltage Vaint by the conducting fourth transistor T4, and the second node N2 can be initialized to the second initialization voltage Vaint by the conducting sixth transistor T6.

[0157] During the compensation period P2, a third scan signal GR with an on-state voltage can be provided to the third scan line GRLi, and a first light emission control signal EM with an on-state voltage can be provided to the first light emission line EMPi. The first scan signal GW, the second scan signal GI, and the second light emission control signal EMB can have off-state voltages during the compensation period P2.

[0158] The third transistor T3 can be turned on in response to the third scan signal GR having a turn-on voltage, and the fifth transistor T5 can be turned on in response to the first light emission control signal EM having a turn-on voltage. The second transistor T2, the fourth transistor T4, and the sixth transistor T6 can be turned off in response to the first scan signal GW, the second scan signal GI, and the second light emission control signal EMB having a cutoff voltage.

[0159] The first initialization voltage Vref can be provided to the first gate electrode of the first transistor T1 through the conducting third transistor T3, and the first drive voltage ELVDD can be provided to the first electrode of the first transistor T1 to turn on the first transistor T1.

[0160] When the voltage across the second electrode of the first transistor T1 drops to the difference (Vref-Vth) between the first initialization voltage Vref and the threshold voltage Vth of the first transistor T1, the first transistor T1 can be turned off. The first capacitor C1 can be charged with a voltage corresponding to the threshold voltage Vth of the first transistor T1 to compensate for the threshold voltage Vth of the first transistor T1.

[0161] In the comparative example, when the sixth transistor T6 is omitted, during the compensation period P2, the current output from the first transistor T1 can flow to the light-emitting element OLED to charge its capacitor. Therefore, during the compensation period P2, variations in impedance due to degradation of the OLED may occur, leading to differences in capacitor charging and / or overall OLED charging. This can result in differences in image brightness, causing image blemishes. However, according to this disclosure, pixel PXij may include the sixth transistor T6. When the sixth transistor T6 is turned off during the compensation period P2, the first transistor T1 can be electrically disconnected from the OLED during P2. Therefore, differences in OLED charging can be prevented during the compensation period P2, thus preventing differences in image brightness. Therefore, an electronic device 1000 with improved display quality can be provided.

[0162] During the write cycle P3, a first scan signal GW with an on-state voltage can be provided to the first scan line GWLi. Each of the second scan signal GI, the third scan signal GR, the first light emission control signal EM, and the second light emission control signal EMB can have an off-state voltage.

[0163] During the write cycle P3, the second transistor T2 can be turned on in response to the first scan signal GW, which has an on-state voltage. The third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned off during the write cycle P3.

[0164] The conducting second transistor T2 can provide the data voltage Vdata received from the data line DLj to the first node N1 (i.e., the first gate electrode of the first transistor T1).

[0165] During the second initialization period P4, a second scan signal GI with an on-state voltage can be provided to the second scan line GILi, and a second light emission control signal EMB with an on-state voltage can be provided to the second light emission line EMBLi. The first scan signal GW, the third scan signal GR, and the first light emission control signal EM can have off-state voltages during the second initialization period P4.

[0166] The sixth transistor T6 can be turned on in response to the second light-emitting control signal EMB having a turn-on voltage, so as to turn on the first electrode AE ​​of the light-emitting element OLED (see Figure 7 The first electrode of the first transistor T1 is connected to the second node N2 (the second electrode of the first transistor T1), and the fourth transistor T4 can be turned on in response to the second scan signal GI with a turn-on voltage, so as to turn on the first electrode AE ​​of the light-emitting element OLED (see Figure 7 Initialize it to the second initial voltage Vaint.

[0167] During the emission cycle EP, the first light emission control signal EM and the second light emission control signal EMB may have on-state voltages, and the first scan signal GW, the second scan signal GI, and the third scan signal GR may have off-state voltages.

[0168] The second transistor T2, the third transistor T3, and the fourth transistor T4 can be turned off in response to the first scan signal GW, the second scan signal GI, and the third scan signal GR, which have cutoff voltages, and the fifth transistor T5 and the sixth transistor T6 can be turned on in response to the first light emission control signal EM and the second light emission control signal EMB, which have turn-on voltages.

[0169] The first transistor T1 can output a drive current Id with an intensity corresponding to the voltage stored in the first capacitor C1. The light-emitting element OLED can emit light with a brightness corresponding to the intensity of the drive current Id, regardless of the threshold voltage Vth of the first transistor T1.

[0170] Figure 11 This is a flowchart illustrating a method for driving an electronic device according to an embodiment of the present disclosure.

[0171] refer to Figures 8 to 11 The display panel (DP) can operate based on multiple brightness characteristics. These multiple brightness characteristics can be defined as the luminous intensity of the display panel (DP) when the data voltage Vdata supplied to pixel PXij corresponds to the maximum grayscale value.

[0172] Multiple brightness characteristics may include a first brightness characteristic and a second brightness characteristic that is different from the first brightness characteristic. The second brightness characteristic may have a lower brightness than the first brightness characteristic at gray levels from 0 to 255.

[0173] For example, the first brightness characteristic can be defined as '100'. This means that the luminous intensity of the display panel DP is 100 nits at a grayscale level of 255. The first brightness characteristic can be referred to as a high display brightness value (DBV). The second brightness characteristic can be defined as '4'. This means that the luminous intensity of the display panel DP is 4 nits at a grayscale level of 255. The second brightness characteristic can be referred to as a low DBV.

[0174] Copy mura (or mura phenomenon) faults in the panel (such as horizontal / vertical stripe stains) can be measured by presenting a specific test pattern of black or white under the second brightness characteristic. Copy mura faults can be caused when the swing of the data voltage Vdata exerts a coupling effect on the first node N1. For example, the coupling effect can increase when the potential difference between the data voltage Vdata and the first initialization voltage Vref increases.

[0175] To improve the display quality of the electronic device 1000, the first initialization voltage Vref needs to be optimized in the second brightness characteristic.

[0176] In addition, temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) can be used as indicators to evaluate the display panel DP in the second luminance characteristic.

[0177] Temperature luminance sensitivity (TLS) can be a metric used to determine whether luminance remains constant even when temperature changes (i.e., whether luminance does not change (or remains substantially unchanged) due to temperature changes), and can be determined by measuring the degree to which the luminance of the panel changes when the temperature changes.

[0178] Temperature color sensitivity (TCS) can be used to determine whether the color remains consistent even when the temperature changes (i.e., whether the color can remain distorted due to temperature changes), and it can be determined by measuring the color change of the panel based on temperature changes.

[0179] In the second brightness characteristic, temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) can be influenced by the first electrode AE ​​used to initialize the OLED light-emitting element (see...). Figure 7 The impact of the second initialization voltage Vaint. To improve the display quality of the electronic device 1000, it is necessary to optimize the second initialization voltage Vaint in the second brightness characteristic.

[0180] In a method for driving an electronic device 1000 according to an embodiment of the present disclosure, a first initialization voltage Vref and a second initialization voltage Vaint can be determined and optimized.

[0181] A method for driving an electronic device 1000 may include: searching and determining an initialization voltage provided to the first gate electrode of the first transistor T1 in a first brightness characteristic (S100); determining a first initialization voltage Vref by compensating the initialization voltage based on a specific margin voltage (S200); determining a second initialization voltage Vaint based on the first initialization voltage Vref and specific driving conditions (S300); and providing the first initialization voltage Vref and the second initialization voltage Vaint to the display panel DP (S400).

[0182] The initialization voltage for a display panel DP manufactured in each of a plurality of cell regions defined in a working substrate can be determined individually by searching (S100). The initialization voltage can be provided via a first voltage line VRL. The initialization voltage can be the voltage used to initialize the first node N1.

[0183] The initialization voltage level can be determined as the voltage level in the first brightness characteristic used to render black by the display panel DP at a specific brightness level. In other words, the initialization voltage can be referred to as the initialization voltage used to ensure black brightness in the first brightness characteristic. For example, black brightness can be less than or equal to 20 micronits (units). In other words, when the luminous brightness of the display panel DP is 100 nits at a gray level of 255, the voltage used to ensure 20 micronits (units) of black brightness to render black can be determined as the initialization voltage. For example, the initialization voltage obtained through a search can be determined to be 0.9V.

[0184] The initialization voltage can be compensated based on a specific margin voltage to determine the first initialization voltage Vref (S200). A specific margin voltage can be determined based on a degradation margin to ensure reliability.

[0185] In other words, the initial voltage Vref, the specific margin voltage, and the initial voltage Vref' can satisfy Equation 1. In this case, the initial voltage can be referred to as "Vref'".

[0186] Equation 1

[0187] The specific margin voltage can be in the range of 0.1V to 0.5V. For example, the margin voltage can be 0.3V.

[0188] For example, the first initialization voltage Vref to be provided to the display panel DP can be determined to be 1.2V, which is obtained by adding a specific margin voltage of 0.3V to an initialization voltage of 0.9V obtained through a search.

[0189] The second initialization voltage Vaint can be determined based on the first initialization voltage Vref and specific driving conditions (S300). The specific driving conditions can have a predetermined voltage (or a predetermined voltage range).

[0190] In other words, the first initialization voltage Vref, the second initialization voltage Vaint, and the specific driving conditions can satisfy the following equation 2.

[0191] Equation 2

[0192] The value (or voltage level) obtained by subtracting the second initialization voltage Vaint from the first initialization voltage Vref must be greater than or equal to the value (or voltage level) based on the driving condition (e.g., a specific value based on a predetermined voltage range of the driving condition). When the value obtained by subtracting the second initialization voltage Vaint from the first initialization voltage Vref is less than the value of the driving condition, the OLED element may not be initialized. The driving condition may have a voltage level in the range of 1.5V to 2.0V. For example, the driving condition may have a voltage level of 1.8V.

[0193] The second initialization voltage Vaint can be predetermined based on temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS).

[0194] When the predetermined first initialization voltage Vref and the second initialization voltage Vaint satisfy Equation 2, the second initialization voltage Vaint can be set to a predetermined value.

[0195] When the predetermined first initialization voltage Vref and the second initialization voltage Vaint do not satisfy Equation 2, the value (or voltage level) obtained by subtracting the value of the driving condition from the first initialization voltage Vref can be determined as the second initialization voltage Vaint. For example, when the first initialization voltage Vref is 1.2V, the second initialization voltage Vaint can be -0.6V.

[0196] In a method for driving an electronic device 1000 according to an embodiment of the present disclosure, the first initialization voltage Vref determined in S200 may have a positive voltage level, and the second initialization voltage Vaint determined in S300 may have a negative voltage level.

[0197] The first initialization voltage Vref and the second initialization voltage Vaint can be provided to the display panel DP (S400).

[0198] Table 1

[0199] Table 1 shows the measured values ​​of temperature luminance sensitivity (TLS), temperature color sensitivity (TCS), and copy non-uniformity according to the comparative examples and embodiments, which were measured in a first luminance characteristic (100 dBV) and a second luminance characteristic (10 dBV). Referring to Table 1, the measured values ​​according to the comparative examples were obtained using a second initialization voltage Vaint determined by prior art methods, and the measured values ​​according to the embodiments of this disclosure were obtained using a second initialization voltage Vaint determined by using a method for driving electronic device 1000.

[0200] Unlike this disclosure, the second initialization voltage Vaint according to the comparative example is predetermined based on temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS), and therefore the second initialization voltage Vaint does not change. For example, in the first luminance characteristic (100 dBV), the second initialization voltage Vaint for the red pixel, green pixel, and blue pixel can be -0.5V / -0.5V / -0.5V, respectively.

[0201] According to the comparative example, the first initialization voltage Vref can be determined to be 1.3V to satisfy the specific driving conditions based on Equation 2. According to the method described in the comparative example, the potential difference between the data voltage Vdata and the first initialization voltage Vref can be relatively increased.

[0202] The first initialization voltage Vref and the second initialization voltage Vaint in the second brightness characteristic (10dBV) can be determined based on the first initialization voltage Vref and the second initialization voltage Vaint determined in the first brightness characteristic (100dBV). Copy unevenness can be exacerbated by the data voltage Vdata and the first initialization voltage Vref having an increased potential difference.

[0203] However, the second initialization voltages Vaint of the red, green, and blue pixels in the first luminance characteristic (100 dBV) determined by the method for driving the electronic device 1000 according to an embodiment of the present disclosure can be -0.6V / -0.6V / -0.6V, respectively, and the first initialization voltage Vref in the first luminance characteristic (100 dBV) can have a (1-1)th voltage level. For example, the first initialization voltage Vref can be determined to be 1.2V.

[0204] In the second luminance characteristic (10dBV), based on the (1-1)th voltage level, the first initialization voltage Vref can be determined to have a (1-2)th voltage level different from the (1-1)th voltage level. In other words, the first initialization voltage Vref and the second initialization voltage Vaint in the second luminance characteristic (10dBV) can be determined based on the first initialization voltage Vref and the second initialization voltage Vaint determined in the first luminance characteristic (100dBV).

[0205] According to comparative examples and embodiments, temperature color sensitivity (TCS) and temperature luminance sensitivity (TLS) can be measured to similar levels. In other words, when the second initialization voltage Vaint in the first luminance characteristic (100 dBV) is determined using the method for driving an electronic device 1000 according to embodiments of the present disclosure, the effect of the second initialization voltage Vaint on temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) may be insignificant.

[0206] Copy unevenness is measured for each of the specific test patterns representing black or white in the first luminance characteristic (100 dBV) and the second luminance characteristic (10 dBV). In this case, a lower measured value of copy unevenness can indicate an improvement in copy unevenness.

[0207] According to this disclosure, the potential difference between the data voltage Vdata and the first initialization voltage Vref can be reduced compared to the comparative example. According to the comparative example and the embodiment, copy non-uniformity can be improved by approximately 0.2%. Therefore, an electronic device 1000 with improved display quality and a method for driving the electronic device 1000 can be provided.

[0208] Furthermore, according to this disclosure, in the method for driving the electronic device 1000, the first initialization voltage Vref can be determined as a value that ensures the black brightness in the first luminance characteristic (100 dBV), and the reliability margin of the first initialization voltage Vref can be ensured based on Equation 1. The second initialization voltage Vaint can be determined based on Equation 2. Therefore, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) can be improved, and the characteristics of copy unevenness in the second luminance characteristic (10 dBV) can be improved. Therefore, an electronic device 1000 with improved display quality and a method for driving the electronic device 1000 can be provided.

[0209] As described above, according to the method for driving an electronic device, the first initialization voltage can be determined as a value that ensures black brightness in the first brightness characteristic, and the reliability margin of the first initialization voltage can be ensured based on a margin voltage. The second initialization voltage can be determined based on driving conditions. Therefore, temperature-sensitive brightness and temperature-sensitive color can be improved, and the characteristics of copy unevenness in the second brightness characteristic can be improved. Thus, an electronic device with improved display quality and a method for driving the electronic device can be provided.

[0210] Although embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications and substitutions are possible without departing from the scope and spirit of this disclosure as disclosed in the appended claims. Therefore, the technical scope of this disclosure is not limited to the detailed description herein, but should be defined by the claims.

[0211] Although this disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A method for driving an electronic device, the electronic device including a display panel, the display panel including a pixel driving circuit and a light-emitting element, the pixel driving circuit including a driving transistor and a switching transistor for receiving a data voltage, the method comprising: Determine the initial voltage corresponding to the first brightness characteristic; The first initialization voltage to be provided to the gate electrode of the driving transistor in the first brightness characteristic is determined by compensating the initialization voltage based on the margin voltage; Based on the first initialization voltage and driving conditions, a second initialization voltage will be provided to the light-emitting element in the first brightness characteristic; as well as The first initialization voltage and the second initialization voltage are provided to the display panel.

2. The method according to claim 1, wherein, Determining the initial voltage includes: The voltage level used to represent black in the first brightness characteristic is determined as the voltage level of the initialization voltage.

3. The method according to claim 1, wherein, The margin voltage is in the range of 0.1V to 0.5V.

4. The method according to claim 1, wherein, Determining the second initialization voltage includes: The voltage level obtained by subtracting the voltage level of the driving condition from the voltage level of the first initialization voltage is determined as the second initialization voltage.

5. The method according to claim 4, wherein, The voltage level of the driving condition is in the range of 1.5V to 2.0V.

6. The method according to claim 1, wherein, The first initialization voltage has a higher voltage level than the second initialization voltage.

7. The method according to claim 6, wherein, In the first brightness characteristic, the first initialization voltage has a positive voltage level, and the second initialization voltage has a negative voltage level.

8. The method according to claim 1, wherein, The first initialization voltage has a first voltage level in the first brightness characteristic, and The method further includes: Based on the first voltage level in the first brightness characteristic, a first initialization voltage with a second voltage level is determined to be provided to the gate electrode of the driving transistor in the second brightness characteristic, the second voltage level being different from the first voltage level, and for the same gray level, the second brightness characteristic having a lower brightness than the first brightness characteristic.

9. Electronic devices, including: The display panel includes multiple pixels. Wherein, at least one pixel among the plurality of pixels includes: Light-emitting elements; and The pixel driving circuit is connected to the light-emitting element. The pixel driving circuit includes: The first transistor includes a gate electrode connected to a first node, a first electrode connected to a first power line providing a first drive voltage, and a second electrode connected to a second node; The second transistor includes a gate electrode connected to a first scan line that provides a first scan signal, a first electrode connected to a data line, and a second electrode connected to the first node. A first capacitor is connected between the first node and the second node; A second capacitor is connected between the first power line and the second node; The third transistor includes a gate electrode connected to a second scan line providing a second scan signal different from the first scan signal, a first electrode connected to a first voltage line providing a first initialization voltage, and a second electrode connected to the first node; and The fourth transistor includes a gate electrode connected to a third scan line providing a third scan signal different from the first and second scan signals, a first electrode connected to the light-emitting element, and a second electrode connected to a second voltage line providing a second initialization voltage. Wherein, the first initialization voltage is determined by compensating for a voltage level determined based on a margin voltage with respect to the minimum brightness used to represent black in the first brightness characteristic, and The second initialization voltage is determined based on the first initialization voltage and the driving conditions.

10. The electronic device according to claim 9, wherein, The margin voltage is in the range of 0.1V to 0.5V.

11. The electronic device according to claim 9, wherein, The second initialization voltage has a voltage level obtained by subtracting the voltage level of the driving condition from the voltage level of the first initialization voltage.

12. The electronic device according to claim 11, wherein, The voltage level of the driving condition is in the range of 1.5V to 2.0V.

13. The electronic device according to claim 9, wherein, The first initialization voltage has a higher voltage level than the second initialization voltage.

14. The electronic device according to claim 9, wherein, In the first brightness characteristic, the first initialization voltage has a positive voltage level, and the second initialization voltage has a negative voltage level.

15. The electronic device according to claim 9, wherein, The first initialization voltage has a first voltage level in the first brightness characteristic, and In the second brightness characteristic, the first initialization voltage has a second voltage level that is different from the first voltage level, and for the same gray level, the second brightness characteristic has a lower brightness than the first brightness characteristic.

16. A pixel driving circuit, comprising: The first transistor includes a gate electrode connected to a first node, a first electrode electrically connected to a first power line providing a first drive voltage, and a second electrode connected to a second node. The second transistor includes a gate electrode connected to a first scan line that provides a first scan signal, a first electrode connected to a data line, and a second electrode connected to the first node. A first capacitor is connected between the first node and the second node; A second capacitor is connected between the first power line and the second node; The third transistor includes a gate electrode connected to a second scan line that provides a second scan signal different from the first scan signal, a first electrode connected to a first voltage line that provides a first initialization voltage, and a second electrode connected to the first node; as well as The fourth transistor includes a gate electrode connected to a third scan line providing a third scan signal different from the first scan signal and the second scan signal, a first electrode connected to a third node, and a second electrode connected to a second voltage line providing a second initialization voltage. Wherein, the first initialization voltage is determined by compensating for a voltage level determined with respect to the minimum luminance required to represent black based on a margin voltage, and The second initialization voltage is determined based on the first initialization voltage and the driving conditions.

17. The pixel driving circuit according to claim 16, wherein, The margin voltage is in the range of 0.1V to 0.5V.

18. The pixel driving circuit according to claim 16, wherein, The second initialization voltage has a voltage level obtained by subtracting the voltage level of the driving condition from the voltage level of the first initialization voltage.

19. The pixel driving circuit according to claim 18, wherein, The voltage level of the driving condition is in the range of 1.5V to 2.0V.

20. The pixel driving circuit according to claim 16, wherein, The first initialization voltage has a higher voltage level than the second initialization voltage.

21. The pixel driving circuit according to claim 16, wherein, The first initialization voltage has a positive voltage level, and the second initialization voltage has a negative voltage level.

22. The pixel driving circuit according to claim 16, wherein, The first initialization voltage has a first voltage level in the first brightness characteristic, and Wherein, the first initialization voltage has a second voltage level in the second brightness characteristic that is different from the first voltage level, and for the same gray level, the second brightness characteristic has a lower brightness than the first brightness characteristic.

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