H-bridge power module control method and system and storage medium

Abstract

The invention relates to an H-bridge power module control method and system and a storage medium, and the method comprises the steps: obtaining the target working condition data of an H-bridge power module, and carrying out the feedback current sampling processing of a load connected with the H-bridge power module, and obtaining a feedback current effective value; and based on the target working condition data and preset data, querying to obtain a voltage feed-forward amplitude under a corresponding condition, and based on the feedback current effective value and the voltage feed-forward amplitude, performing voltage feed-forward compensation to determine an output voltage amplitude. And performing modulation according to the output voltage amplitude and the current output phase, determining an effective duty ratio, outputting a control waveform to a power tube in the H-bridge power module according to the effective duty ratio, and performing on-off control on the power tube. And under the condition of keeping the hardware cost unchanged, the current control precision is remarkably improved.

Description

H-bridge power module control methods, systems, and storage media Technical Field

[0001] This application relates to the field of power electronic control technology, and in particular to an H-bridge power module control method, system and storage medium. Background Technology

[0002] Traditional H-bridge control technology employs a unipolar PWM control mode, which combines fixed conduction with PWM modulation. Specifically, one bridge arm's switching transistors (Q1 / Q2 in Figure 2) are kept constantly on, while the other bridge arm's transistors (Q3 / Q4 in Figure 2) undergo PWM modulation. When Q1 is normally on, adjusting the PWM duty cycle of Q4 enables forward motor drive; similarly, when Q2 is normally on, adjusting the PWM duty cycle of Q3 enables reverse motor drive. This control method results in large load current fluctuations and significant deviations in the effective current value under dynamic conditions, severely impacting the accuracy of motor drive system testing. Improving the current control accuracy of the H-bridge power module is a pressing issue. Summary of the Invention

[0003] Therefore, it is necessary to provide an H-bridge power module control method, system, and storage medium that can improve the current control accuracy in response to the above problems.

[0004] The first aspect of this application provides an H-bridge power module control method, comprising:

[0005] Acquire the target operating condition data of the H-bridge power module, and obtain the effective value of the feedback current by sampling the load connected to the H-bridge power module.

[0006] Based on the target operating condition data and the preset data, the voltage feedforward amplitude under the corresponding conditions is obtained by querying; the preset data represents the correspondence between the target operating condition data and the voltage feedforward amplitude.

[0007] Based on the effective value of the feedback current and the voltage feedforward amplitude, voltage feedforward compensation is performed to determine the output voltage amplitude.

[0008] The effective duty cycle is determined by modulating the output voltage amplitude and the current output phase.

[0009] The control waveform is output to the power transistor in the H-bridge power module according to the effective duty cycle, and the power transistor is controlled to switch on and off.

[0010] In one embodiment, the target operating condition data includes bus voltage, electrical frequency, and target current RMS value.

[0011] In one embodiment, the effective value of the feedback current is calculated by performing root mean square processing on the real-time values ​​of the feedback current collected within a set time period.

[0012] In one embodiment, voltage feedforward compensation is performed based on the effective value of the feedback current and the voltage feedforward amplitude to determine the output voltage amplitude, including:

[0013] Based on the effective value of the feedback current and the set effective value of the target current, the amplitude of the PI-regulated output voltage is calculated.

[0014] The output voltage amplitude is obtained by adding the voltage feedforward amplitude and the PI-regulated output voltage amplitude.

[0015] In one embodiment, the control waveform is a PWM waveform with the pulses aligned in a central manner around the center of the switching cycle.

[0016] In one embodiment, modulating the output voltage amplitude and the current output phase to determine the effective duty cycle includes:

[0017] The modulation ratio is calculated by dividing the output voltage amplitude by the preset maximum allowable output voltage.

[0018] Perform a sine calculation on the current output phase to obtain the sine value of the current output phase; wherein, the current output phase is calculated based on the set current acceleration / deceleration time;

[0019] The effective duty cycle is obtained by multiplying the modulation ratio by the sine value.

[0020] In one embodiment, outputting a control waveform to the power transistor in the H-bridge power module according to the effective duty cycle includes:

[0021] The current direction is determined based on the current output phase. Based on the current direction, the effective duty cycle, and the carrier period, the comparison value of the corresponding power transistor in the H-bridge power module is calculated, thereby outputting the corresponding PWM waveform.

[0022] In one embodiment, before querying the voltage feedforward amplitude under the corresponding conditions based on the target operating condition data and preset data, the method further includes:

[0023] After receiving the calibration mode command from the host computer, the H-bridge power module is configured based on different target operating condition data, and the voltage amplitude output under the corresponding target operating condition data is recorded to obtain preset data that characterizes the correspondence between the target operating condition data and the voltage feedforward amplitude.

[0024] A second aspect of this application provides an H-bridge power module control system, including a host computer and a slave computer. The slave computer is connected to the host computer, the H-bridge power module, and the load connected to the H-bridge power module. The slave computer controls the H-bridge power module according to the method described above.

[0025] A third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0026] The aforementioned H-bridge power module control method, system, and storage medium acquire target operating condition data of the H-bridge power module and the effective value of the feedback current obtained by sampling the feedback current of the load connected to the H-bridge power module. Based on the target operating condition data and preset data, the voltage feedforward amplitude under the corresponding conditions is retrieved. Voltage feedforward compensation is performed based on the effective value of the feedback current and the voltage feedforward amplitude to determine the output voltage amplitude. Modulation is performed based on the output voltage amplitude and the current output phase to determine the effective duty cycle. The control waveform is output to the power transistors in the H-bridge power module according to the effective duty cycle to control the on / off state of the power transistors. This significantly improves current control accuracy while maintaining the same hardware cost. Attached Figure Description

[0027] Figure 1 is a flowchart of an H-bridge power module control method in one embodiment;

[0028] Figure 2 is a topology diagram of the H-bridge power module in one embodiment;

[0029] Figure 3 is a software H-bridge drive control topology diagram in one embodiment;

[0030] Figure 4 is a schematic diagram of the software H-bridge drive control flow in one embodiment;

[0031] Figure 5 is a schematic diagram of the voltage feedforward calibration process in one embodiment;

[0032] Figure 6 shows the PWM control waveform of the H-bridge in the initial state in one embodiment;

[0033] Figure 7 shows the current path diagram of the H-bridge during the positive half-cycle in one embodiment;

[0034] Figure 8 shows the PWM control waveform of the H-bridge during the positive half-cycle in one embodiment;

[0035] Figure 9 shows the negative half-cycle current path of the H-bridge in one embodiment;

[0036] Figure 10 shows the PWM control waveform of the H-bridge during the negative half-cycle in one embodiment;

[0037] Figure 11 is a hardware topology diagram of the H-bridge power module control system in one embodiment. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. It is understood that the term "connection" in the following embodiments, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, should be understood as "electrical connection," "communication connection," etc.

[0040] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0041] Traditional H-bridge control technology uses a unipolar PWM control mode, which has the following technical drawbacks:

[0042] 1. The load current fluctuates significantly, and the effective value of the current deviates significantly under dynamic operating conditions, which seriously affects the testing accuracy of the motor drive system.

[0043] 2. Asymmetric PWM modulation causes a significant difference in switching losses between the upper and lower bridge arm IGBTs. Actual measurement data shows that the temperature rise of the upper bridge tube is much higher than that of the lower bridge tube. This imbalance in losses not only shortens the device lifespan but also leads to insufficient test coverage of normally open tubes.

[0044] 3. Since the H-bridge can only collect single-phase current, its control response has an inherent lag. The delay from current sampling to PI regulation output is relatively long. In contrast, the full-bridge system can achieve real-time regulation through three-phase current vector synthesis. This response gap is particularly prominent when the load changes rapidly, which seriously restricts the dynamic performance of the H-bridge system.

[0045] These technical shortcomings collectively limit the application value of H-bridges in the field of precision control.

[0046] Based on this, this application provides an H-bridge power module control method. By combining current closed-loop control with SPWM (Sine Pulse Width Modulation) modulation technology and employing a three-dimensional lookup table feedforward and phase synchronization adjustment mechanism, the dynamic response accuracy and power transistor utilization of the H-bridge drive system are significantly improved. The core of this scheme lies in calculating the RMS value of the feedback current in real time and performing PI closed-loop adjustment with the target current RMS value. Simultaneously, voltage feedforward compensation and a center-aligned PWM waveform generation strategy are introduced, effectively solving the problems of current control lag and uneven switching losses inherent in traditional H-bridge power modules. This scheme is particularly suitable for scenarios requiring precise current control, such as motor drives, inverters, and DC-DC converters, providing a new technical path for the testing and optimization of power modules.

[0047] In one embodiment, as shown in Figure 1, an H-bridge power module control method is provided, including:

[0048] Step S110: Obtain the target operating condition data of the H-bridge power module, and the effective value of the feedback current obtained by sampling the feedback current of the load connected to the H-bridge power module.

[0049] The target operating condition data may include bus voltage, electrical frequency, and the effective value of the target current. Figure 2 shows the system topology of the H-bridge power module. The power input is a DC power supply, providing the bus voltage. Four power transistors Q1-Q4 (IGBTs) form an "H" shape, connected to an RL load to achieve drive condition testing. The RL load can specifically be a single-phase reactor. The frequency of the current through the RL load is the electrical frequency, and the effective value of the target current through the RL load is the effective value of the target current. The drive condition of the H-bridge power module can be set to SPWM sine wave output mode, using current closed-loop control and SPWM modulation technology to generate a variable frequency / amplitude sine wave signal, which drives the RL load through the H-bridge output sine wave voltage.

[0050] In one embodiment, the effective value of the feedback current is calculated by performing root mean square (RMS) processing on the real-time feedback current values ​​collected within a set time period. As shown in Figure 3, the effective value (RMS) of the feedback current is calculated by collecting the feedback current, recording the real-time current values ​​within a set time period, and combining these real-time current values ​​with the set time period's RMS processing. The set time period is not unique and can be set according to actual needs.

[0051] Step S120: Based on the target operating condition data and preset data, query the voltage feedforward amplitude under the corresponding conditions. The preset data represents the correspondence between the target operating condition data and the voltage feedforward amplitude.

[0052] Specifically, the preset data can be set in the form of a three-dimensional table, representing the correspondence between bus voltage, electrical frequency, target current RMS value and voltage feedforward amplitude. As shown in Figure 4, when the drive condition is started, a three-dimensional lookup table is performed based on the bus voltage, electrical frequency and target current RMS value to be tested to find the voltage feedforward amplitude to be output under the corresponding conditions. Then, the feedback current is collected, and the root mean square (RMS) value of the feedback current is processed in combination with the real-time current value for a set duration to calculate the RMS value of the feedback current.

[0053] Step S130: Perform voltage feedforward compensation based on the effective value of the feedback current and the voltage feedforward amplitude to determine the output voltage amplitude. Specifically, the PI-regulated output voltage amplitude can be calculated first based on the effective value of the feedback current and the set target current effective value. Then, the voltage feedforward amplitude and the PI-regulated output voltage amplitude are added together to obtain the output voltage amplitude.

[0054] Specifically, as shown in Figures 3 and 4, the effective value of the feedback current and the effective value of the target current can be input into the current loop PI control to obtain the corresponding PI-controlled output voltage amplitude. Then, the voltage feedforward amplitude determined by the three-dimensional lookup table is added to the PI-controlled output voltage amplitude to obtain the final output voltage amplitude. Because the calculation of the effective value of single-phase current is limited by the integral constraint of the definition of effective value, there is a lag. Its mathematical definition requires the completion of time-domain integration (square-average-square root process), and at least 1 / 4 cycle (e.g., 5ms for a 50Hz system) of current sampling data is needed to satisfy the thermal equivalence principle. However, because three-phase systems have spatial symmetry (phases are 120° apart and the vector sum is zero), the effective value can be directly synthesized from the three-phase instantaneous current values ​​through Clarke transform. The solution provided in this application establishes a dynamic voltage amplitude feedforward lookup table based on the three-dimensional parameter space of bus voltage, electrical frequency and target current effective value, so as to realize real-time pre-compensation of drive conditions. It does not require waiting for 1 / 4 cycle to complete the time domain integration to obtain the current effective value. Combined with adaptive PI regulator and phase tracking technology, the traditional control delay is greatly compressed and the response speed is significantly improved.

[0055] Step S140: Modulate the output voltage amplitude and the current output phase to determine the effective duty cycle.

[0056] Specifically, as shown in Figures 3 and 4, the modulation ratio can be calculated by dividing the output voltage amplitude by the preset maximum allowable output voltage. A sine wave is then performed on the current output phase to obtain its sine value. The effective duty cycle is obtained by multiplying the modulation ratio by the sine value.

[0057] The current output phase is calculated based on the set current acceleration / deceleration time. The maximum allowable output voltage value is not unique and can be set according to the actual drive conditions. The phase of the current in one electrical frequency cycle is -180° to 180°, and the current output phase θ can be calculated by the phase generation module based on the current acceleration / deceleration time. After calculating the current output phase θ, a sine operation is performed on the current output phase θ to obtain the sine value Sinθ. Then, the modulation ratio is multiplied by the sine value Sinθ to obtain the effective duty cycle. Thus, through the collaborative control architecture of three-dimensional lookup table feedforward and phase synchronization adjustment, a current closed-loop system with fast dynamic response is constructed, and the dynamic response performance is significantly improved. The algorithm of multiplying the space vector modulation ratio and the phase sine value is used to achieve precise synchronization between the duty cycle and the current phase, improving control accuracy.

[0058] Step S150: Output the control waveform according to the effective duty cycle to the power transistor in the H-bridge power module to control the power transistor's on / off state.

[0059] The type of control waveform is not unique. In this embodiment, the control waveform is a PWM waveform with the pulses aligned to the center of the switching cycle. Specifically, the PWM waveform is center-aligned, and the PWM pulses are symmetrical about the center point of the switching cycle. The current direction is determined based on the current output phase. Based on the current direction, effective duty cycle, and carrier cycle, the comparison value of the corresponding power transistors (Q1-Q4) in the H-bridge power module is calculated. The comparison value is the actual counting threshold of the PWM register in the MCU, determined by the system clock frequency and carrier cycle. It is obtained by multiplying the target duty cycle by the period count value (PRD). For example, when the system clock is 100 MHz and the PWM frequency is 8 kHz, PRD = 12,500. The comparison value of the power transistor is then PRD × (0.5 + m•sinθ). This value directly triggers the hardware comparator to flip the output level, achieving precise switching control and outputting the corresponding PWM waveform to control the on / off state of the power transistors.

[0060] By employing center-aligned space vector modulation technology, PWM pulses are generated with the center point of the switching cycle as the axis of symmetry, which significantly improves the loss balance between the upper and lower bridge arms. This effectively addresses the problem of uneven switching losses between the upper and lower bridge arms and increases the test coverage of all power transistors.

[0061] After step S150, the method may further include: determining whether the drive test time has been reached; if the time has not been reached, jumping back to step S110 and continuing to perform a drive test; if the time has been reached, turning off all PWM outputs and ending the test.

[0062] In one embodiment, before step S120, the method may further include: after receiving the calibration mode command from the host computer, configuring the H-bridge power module based on different target operating condition data, and recording the voltage amplitude output under the corresponding target operating condition data, so as to obtain preset data characterizing the correspondence between the target operating condition data and the voltage feedforward amplitude.

[0063] Specifically, as shown in Figure 5, the automatic voltage feedforward calibration process is as follows:

[0064] 1. The host computer sends a calibration mode command to the slave computer, and the slave computer enters calibration mode and disables the feedforward output.

[0065] 2. The host computer determines whether the automatic voltage feedforward calibration is complete. If it is complete, the process ends; otherwise, it proceeds to the next step.

[0066] 3. The host computer looks up the current calibration target (target operating condition data) from the table, including bus voltage, electrical frequency, and target current RMS value.

[0067] 4. The host computer controls the power supply bus voltage to the target bus voltage.

[0068] 5. The host computer sends the calibration targets to the slave computer (bus voltage, electrical frequency, and target current RMS value).

[0069] 6. The lower-level machine uses shielded voltage feedforward and PI control to adjust the effective value of the current to the target effective value of the current.

[0070] 7. The host computer determines whether the calibration target (electrical frequency, target current effective value) has reached the corresponding target value; if it has not reached the target value, it continues to wait until the timeout period expires, then the voltage feedforward calibration fails and the calibration process is exited; if the target value is reached, it proceeds to the next process.

[0071] 8. The host computer sends a voltage feedforward recording command to the slave computer.

[0072] 9. The lower-level computer stores the voltage amplitude output (i.e., voltage feedforward amplitude) corresponding to the current bus voltage, electrical frequency, and target current effective value.

[0073] 10. The host computer calibrates the target quantity by one, proceeds to step 2, and performs calibration again until the voltage feedforward automatic calibration is completed, finally obtaining the preset data that characterizes the correspondence between the target operating condition data and the voltage feedforward amplitude.

[0074] By simplifying the automatic voltage feedforward calibration process and shortening the adaptation time through closed-loop control of the host computer, the testing efficiency under different load conditions is significantly improved, and the system adaptability is enhanced.

[0075] Figure 6 shows the PWM control waveform of the H-bridge in its initial state. By default, all four power transistors output a 50% duty cycle. A high level indicates the corresponding power transistor is on, and a low level indicates it is off. During adjustment, the current does not instantly reach the target current level but rather changes gradually. The current change trend is determined by the duty cycle difference, which is the absolute value of the duty cycle difference between two power transistors located in the same bridge arm, such as |Q1 duty cycle - Q3 duty cycle|, or |Q2 duty cycle - Q4 duty cycle|. During the T0-T1 and T2-T3 periods, power transistors Q1 and Q3 (upper bridge) are off, and during the T1-T2 period, power transistors Q2 and Q4 (lower bridge) are off. At this time, the circuit has no current output.

[0076] At time T0, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0077] At time T1, power transistor Q1 is turned on, power transistor Q2 is turned off, power transistor Q3 is turned on, and power transistor Q4 is turned off.

[0078] At time T2, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0079] At time T3, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0080] Figure 7 shows the current path diagram for the positive half-cycle. The current direction is: positive power supply → power transistor Q1 → RL load → power transistor Q4 → negative power supply. The PWM control waveforms of the four power transistors are shown in Figure 8, with duty cycles of: Q1 = Q4 = 50% + modulation ratio * sinθ, Q2 = Q3 = 50% - modulation ratio * sinθ.

[0081] At time T0, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0082] At time T1, power transistor Q1 is turned on, power transistor Q2 is turned off, power transistor Q3 is turned off, and power transistor Q4 is turned on.

[0083] At time T2, power transistor Q1 is turned on, power transistor Q2 is turned off, power transistor Q3 is turned on, and power transistor Q4 is turned off.

[0084] At time T3, power transistor Q1 is turned on, power transistor Q2 is turned off, power transistor Q3 is turned off, and power transistor Q4 is turned on.

[0085] At time T4, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0086] At time T5, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0087] During the T1-T4 interval, the circuit outputs current. As the duty cycle difference increases, the current continues to increase until the target current is reached.

[0088] Figure 9 shows the current path diagram for the negative half-cycle. The current direction is: positive terminal of power supply → power transistor Q3 → RL load → power transistor Q2 → negative terminal of power supply. The PWM waveforms of the four power transistors are shown in Figure 10, with duty cycles of: Q1 = Q4 = 50% - modulation ratio * sinθ, Q2 = Q3 = 50% + modulation ratio * sinθ.

[0089] At time T0, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0090] At time T1, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is on, and power transistor Q4 is off.

[0091] At time T2, power transistor Q1 is turned on, power transistor Q2 is turned off, power transistor Q3 is turned on, and power transistor Q4 is turned off.

[0092] At time T3, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is on, and power transistor Q4 is off.

[0093] At time T4, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0094] At time T5, power transistor Q1 is off, power transistor Q2 is on, power transistor Q3 is off, and power transistor Q4 is on.

[0095] During the T1-T4 interval, the circuit outputs current. As the duty cycle difference increases, the current continues to increase until the target current is reached.

[0096] The solution provided in this application achieves significantly improved current control accuracy and a marked reduction in power transistor temperature rise differences through deep collaboration between hardware systems and software algorithms, while maintaining the same hardware cost. The specially designed voltage feedforward automatic calibration process, controlled in a closed loop by a host computer, significantly shortens the time required for the system to adapt to different load conditions, greatly improving testing efficiency.

[0097] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0098] In one embodiment, an H-bridge power module control system is also provided, including a host computer and a slave computer. The slave computer is connected to the host computer, the H-bridge power module, and the load connected to the H-bridge power module. The slave computer controls the H-bridge power module according to the method described above. As shown in Figure 11, the slave computer mainly consists of a control board, a driver board, and a probe board. The control logic of the slave computer is implemented by the control board, while the probe board and driver board are used for functions such as feedback current sampling and output control waveforms.

[0099] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the method described above.

[0100] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited thereto.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for controlling an H-bridge power module, characterized in that, include: Acquire the target operating condition data of the H-bridge power module, and obtain the effective value of the feedback current by sampling the load connected to the H-bridge power module. Based on the target operating condition data and preset data, the voltage feedforward amplitude under the corresponding conditions is obtained by querying. The preset data represents the correspondence between the target operating condition data and the voltage feedforward amplitude; Based on the effective value of the feedback current and the voltage feedforward amplitude, voltage feedforward compensation is performed to determine the output voltage amplitude. The effective duty cycle is determined by modulating the output voltage amplitude and the current output phase. The control waveform is output to the power transistor in the H-bridge power module according to the effective duty cycle, and the power transistor is controlled to switch on and off.

2. The method according to claim 1, characterized in that, The target operating condition data includes bus voltage, electrical frequency, and the effective value of the target current.

3. The method according to claim 1, characterized in that, The effective value of the feedback current is calculated by performing root mean square processing on the real-time values ​​of the feedback current collected within a set time period.

4. The method according to claim 1, characterized in that, Voltage feedforward compensation is performed based on the effective value of the feedback current and the voltage feedforward amplitude to determine the output voltage amplitude, including: calculating the PI-regulated output voltage amplitude based on the effective value of the feedback current and the set target effective value of the current; and adding the voltage feedforward amplitude and the PI-regulated output voltage amplitude to obtain the output voltage amplitude.

5. The method according to claim 1, characterized in that, The control waveform is a PWM waveform with the pulses aligned in a central manner around the center of the switching cycle.

6. The method according to claim 1, characterized in that, Modulation is performed based on the output voltage amplitude and the current output phase to determine the effective duty cycle, including: dividing the output voltage amplitude by a preset maximum allowable output voltage to calculate the modulation ratio; performing a sine operation on the current output phase to obtain the sine value of the current output phase; wherein the current output phase is calculated based on the set current acceleration / deceleration time; and multiplying the modulation ratio by the sine value to obtain the effective duty cycle.

7. The method according to claim 1, characterized in that, The control waveform is output to the power transistor in the H-bridge power module according to the effective duty cycle, including: determining the current direction according to the current output phase, calculating the comparison value of the corresponding power transistor in the H-bridge power module based on the current direction, the effective duty cycle and the carrier period, and thus outputting the corresponding PWM waveform.

8. The method according to any one of claims 1 to 7, characterized in that, Before querying the voltage feedforward amplitude under the corresponding conditions based on the target operating condition data and preset data, the method further includes: after receiving the calibration mode command from the host computer, configuring the H-bridge power module based on different target operating condition data, and recording the voltage amplitude output under the corresponding target operating condition data to obtain preset data that characterizes the correspondence between the target operating condition data and the voltage feedforward amplitude.

9. An H-bridge power module control system, characterized in that, It includes a host computer and a slave computer, wherein the slave computer is connected to the host computer, the H-bridge power module and the load connected to the H-bridge power module, and the slave computer controls the H-bridge power module according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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