A high-voltage floating gate pre-drive circuit and its chip

Abstract

This invention discloses a high-voltage floating gate pre-drive circuit and its chip, comprising a high-frequency pulse module, an isolation transmission module, a level conversion module, and a pulse detection module. The high-frequency pulse module converts the high-level portion of the high-side logic control signal into a high-frequency pulse, which is transmitted through the isolation transmission module. The level conversion module amplifies the pulse level, and the pulse detection module detects the pulse portion, outputting a high-voltage control signal to drive the gate of the high-side power device. This invention does not use a commonly used level shifting circuit to achieve the level shifting of the high-side control signal. Instead, it combines high-voltage isolation with level conversion and pulse detection to achieve the level shifting effect. The circuit structure is simple, requires no LDMOS devices, has low device requirements, a small layout area, low process requirements, low cost, and high reliability.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and particularly relates to a high-voltage floating gate pre-drive circuit and its chip. Background Technology

[0002] High-voltage floating gate driver chips are widely used in electronic ballasts, variable frequency motor drives, and various power conversion circuits to drive high-voltage switching devices. The gate potential of these chips floats with the source voltage of the driven power device. The highest voltage of the high-side output signal is tens or even hundreds of volts, while the control signal voltage is below 20V. Because these chips need to provide not only a low-side output signal with a relatively low level of zero volts but also a high-side output signal with a relatively low level of tens or even hundreds of volts, the high-voltage level shifting circuit becomes the core of the floating gate driver chip. It transmits the logic control signal from the low-voltage region of the high-side channel to the high-voltage region to generate the floating gate control signal.

[0003] like Figure 1 The diagram shows one application of a high-voltage floating gate drive circuit, specifically a dual NMOS floating gate drive. The LO drives the low-side power device NM0, and the HO drives the high-side power device NM1. When the low-side power device NM0 is on and the high-side power device NM1 is off, its VS potential is pulled down to ground (i.e., 0V). When the high-side power device NM1 is on and the low-side power device NM0 is off, its VS potential is the power supply voltage VHV of the high-voltage mains line. In other words, the level fluctuation range of the floating ground terminal VS of the chip is 0V to VHV. Depending on the application requirements, the power supply voltage of the high-voltage trunk line can range from tens of volts to hundreds of volts. The chip needs to provide not only a low-side output signal LO with a relatively low level of 0V, but also a high-side output signal HO with a relatively low level of tens or even hundreds of volts. In most applications, although the high-voltage side control voltage swings between the potentials of the two trunk lines (power supply and ground), its gate-source voltage difference VGS should always be maintained at VCC. That is, the gate potential relative to the ground signal floats with the change of the source potential. Therefore, we only need to find a way to superimpose the initial gate control signal onto the VS voltage to become the gate control voltage of the high-voltage side power device.

[0004] like Figure 2The diagram illustrates the conventional approach in existing technology. A typical pre-driver chip uses an LVSFT level shifter circuit to transmit the logic control signal HIN from the low-voltage region of the high-side channel to the high-voltage region, generating the floating gate control signal HO. The dashed box in the diagram represents a traditional level shifter circuit, whose core component is a high-voltage LDMOS device capable of withstanding hundreds of volts. It should be noted that LDMOS stands for Laterally Diffused Metal Oxide Semiconductor. As a high-voltage device for signal transmission, LDMOS transistors have a large layout area, complex fabrication structure, and extremely high process requirements. Summary of the Invention

[0005] Purpose of the invention: In order to solve the problems of high device requirements and large layout area in the existing high voltage floating gate pre-drive circuit, the present invention provides a high voltage floating gate pre-drive circuit and its chip.

[0006] Technical solution: A high-voltage floating grid pre-drive circuit, including a high-side channel, wherein the high-side channel includes: a high-frequency pulse module, an isolation transmission module, a level conversion module and a pulse detection module;

[0007] The high-frequency pulse module receives a high-side logic control signal at its input terminal, which is used to convert the high-level part of the high-side logic control signal into a high-frequency pulse. The output terminal of the high-frequency pulse module is electrically connected to the isolation transmission module.

[0008] The first end of the isolation transmission module is electrically connected to the high-frequency pulse module, and the second end is electrically connected to the level conversion module.

[0009] The level conversion module is used to increase the level of the high-frequency pulse;

[0010] The input terminal of the pulse detection module is electrically connected to the level conversion module, and the output terminal outputs a high-voltage control signal.

[0011] Furthermore, the level conversion module includes a voltage clamping element, one end of which is electrically connected to the source voltage of the high-side power device, and the other end is electrically connected to the second terminal of the isolation transmission module.

[0012] Furthermore, the level conversion module also includes a first comparator, the positive power supply of which is provided by the high voltage of the power supply, and the negative power supply of which is provided by the source voltage of the high-side power device. The isolation transmission module is electrically connected to the input terminal of the first comparator, and the output terminal of the first comparator is connected to the pulse detection module.

[0013] Furthermore, the isolation transmission module includes a first isolation capacitor and a second isolation capacitor. The high-frequency pulse module is used to convert one high-side logic control signal into two high-frequency pulse signals. The pulse portions of the two high-frequency pulse signals are opposite. The two high-frequency pulse signals are electrically connected to the first terminals of the first isolation capacitor and the second isolation capacitor, respectively. The second terminals of the first isolation capacitor and the second isolation capacitor are electrically connected to the first input terminal and the second input terminal of the first comparator, respectively.

[0014] Furthermore, the pulse detection module sequentially includes a capacitor charging and discharging circuit, a charging and discharging capacitor, and a shaping circuit. The input terminal of the capacitor charging and discharging circuit is electrically connected to the output terminal of the level conversion module. The capacitor charging and discharging circuit includes a reference current source, a charging switch, and a discharging switch. The reference current source is electrically connected to the high voltage of the power supply. The charging switch and the discharging switch are both electrically connected to the charging and discharging capacitor. The input terminal of the shaping circuit is connected to the charging and discharging capacitor, and the output terminal of the shaping circuit outputs a high voltage control signal.

[0015] Furthermore, the level conversion module also includes a first comparator and a second comparator. The positive power supply of the first comparator and the second comparator is provided by the high voltage of the power supply, and the negative power supply of the first comparator and the second comparator is provided by the source voltage of the high-side power device. The isolation transmission module includes a first isolation capacitor and a second isolation capacitor. The first input terminal and the second input terminal of the first comparator are respectively connected to the second terminals of the first isolation capacitor and the second isolation capacitor. The first input terminal and the second input terminal of the second comparator are respectively connected to the second isolation capacitor and the second terminal of the first isolation capacitor.

[0016] Furthermore, the pulse detection module includes a logic circuit, the two input terminals of which are respectively connected to the output terminals of the first comparator and the second comparator, and the output terminal of the logic circuit outputs a high-voltage control signal; the logic circuit uses an XOR gate or a combination of logic gates with XOR function equivalent.

[0017] Furthermore, the high-frequency pulse module includes a high-frequency clock generator and a logic AND gate. The first and second input terminals of the logic AND gate are respectively connected to the output terminal of the high-frequency clock generator and the high-side logic control signal. The high-frequency clock generator outputs one high-frequency clock or two opposite high-frequency clocks.

[0018] Furthermore, it also includes an input-level driving module and an output-level driving module. The input terminal of the input-level driving module receives logic control signals, and the output terminal is electrically connected to a high-frequency pulse module. The input terminal of the output-level driving module is electrically connected to a pulse detection module, and the output terminal outputs the gate control signals of the power devices. The isolation transmission module uses silicon dioxide isolated high-voltage resistant capacitors.

[0019] A high-voltage floating gate pre-drive chip includes the high-voltage floating gate pre-drive circuit described above.

[0020] Compared with the prior art, the high-voltage floating gate pre-drive circuit and its chip provided by the present invention have the following beneficial effects:

[0021] 1. This invention utilizes the DC blocking and AC passing characteristics of capacitors, combined with level conversion and pulse detection, to propose a high-voltage isolation method for level shifting, achieving a level shifting effect from low voltage to high voltage. At the same time, the circuit structure is simple, and the isolation capacitor does not require static power consumption.

[0022] 2. The high-voltage isolation level shifting technology proposed in this invention breaks away from the traditional level shifting technology concept. It does not use traditional level shifting circuits, does not require high-voltage LDMOS transistors, has low device requirements, simple process structure, reduces process requirements, has a small layout area, and thus reduces product costs.

[0023] 3. The high-voltage isolation level shifting technology proposed in this invention can use differential signals to eliminate common-mode noise interference and filter invalid pulses, cleverly solving the shortcomings of insufficient anti-interference capability of traditional level shifting circuits and improving reliability. Traditional level shifting circuits cannot use differential methods. It can also cleverly solve the signal attenuation problem by using a comparator, making up for the signal attenuation problem caused by the actual use of isolation capacitors, avoiding pulse loss due to signal attenuation, and improving reliability. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a dual NMOS floating gate drive circuit;

[0025] Figure 2 This is a traditional circuit structure for implementing floating gate pre-drive using existing technology, which employs a level shifting circuit.

[0026] Figure 3 This is a schematic diagram of the high-voltage floating gate pre-drive circuit in Embodiment 1;

[0027] Figure 4 This is a schematic diagram of the high-voltage floating gate pre-drive circuit in Example 2;

[0028] Figure 5 This is a schematic diagram of the high-voltage floating gate pre-drive circuit in Embodiment 3;

[0029] Figure 6 This is a timing diagram of each node in Example 3.

[0030] Figure 7 This is a schematic diagram of the high-voltage floating gate pre-drive circuit in Example 4;

[0031] Figure 8 This is a timing diagram of each node in Example 4.

[0032] Figure 9This is a schematic diagram of the high-voltage floating gate pre-drive circuit in Example 5;

[0033] Figure 10 This is a timing diagram of each node in Example 5. Detailed Implementation

[0034] The present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments.

[0035] Example 1:

[0036] A high-voltage floating gate pre-drive circuit, such as Figure 3 As shown, it typically includes a high-side channel and a low-side channel. The high-side channel includes a high-frequency pulse module, an isolation transmission module, a level conversion module, and a pulse detection module. It may also include an input stage driver module and an output stage driver module. Since this embodiment focuses on improving the high-side channel, the low-side channel is simplified and is not intended to limit the scope of this technical solution.

[0037] The input stage driver circuit module receives the high-side logic control signal HIN and the low-side logic control signal LIN, and shapes them to give them a certain degree of noise immunity. This ensures that the high-side logic control signal HIN and the low-side logic control signal LIN can pass through the input circuit processing, guaranteeing that the output signal of the front-end digital chip can be reliably transmitted to the pre-driver chip. The input stage driver circuit module may also include a dead-time protection circuit DTG to prevent the high-side logic control signal HIN and the low-side logic control signal LIN from being effective simultaneously, avoiding shoot-through of the pre-driver power devices and causing them to burn out. A dead time DT is set, and the high-side output and low-side output of the dead-time protection circuit generate non-overlapping high-side logic control signals and low-side logic control signals, respectively.

[0038] The high-frequency pulse module is located in the transmission path of the high-side channel and is used to convert the high-side logic control signal into a high-frequency pulse. The input terminal of the high-frequency pulse module is electrically connected to the high-side output terminal of the dead-time protection circuit, converting the high-level part of the high-side logic control signal into a high-frequency pulse, while the low level can remain low. The output terminal of the high-frequency pulse module is electrically connected to the isolation transmission module.

[0039] The high-frequency pulse module can be implemented in various ways; this embodiment, for example... Figure 3As shown, the high-frequency pulse module includes an AND gate and a high-frequency clock generator. The high-frequency clock generator is used to generate a high-frequency clock signal. In this embodiment, it outputs one high-frequency clock, but it can also output two opposite high-frequency clocks for use in a differential scheme. The first input of the AND gate is electrically connected to the output of the high-frequency clock generator, and the second input is electrically connected to the high-side logic control signal. This converts the high-level portion of the high-side logic control signal into a high-frequency pulse, while keeping the low level of the high-side logic control signal unchanged, thus obtaining a high-frequency pulse signal.

[0040] The isolation transmission module can be implemented using a high-voltage capacitor with silicon dioxide isolation. The first end of the isolation transmission module is electrically connected to the output of the logic AND gate of the high-frequency pulse module, and the second end is electrically connected to the level conversion module.

[0041] The level conversion module is used to improve the level of the high-frequency pulse signal transmitted through the isolation transmission module. It can be implemented in various ways; for example, the level conversion module may include a voltage clamping element, which is implemented using resistor R1 in this embodiment. Alternatively, a diode can be connected in parallel with resistor R1 for better results. Figure 4 As shown; or other components or circuits that can achieve voltage clamping can be used. One end of resistor R1 is connected to the source voltage VS of the high-side power device, and the other end is connected to the second terminal of the isolation capacitor. The voltage VS is superimposed on the second terminal of the isolation capacitor to increase the level of the high-frequency pulse. VS is a high voltage, typically ranging from tens to hundreds of volts.

[0042] The pulse detection module sequentially includes a capacitor charging / discharging circuit, a charging / discharging capacitor, and a shaping circuit. The input terminal of the capacitor charging / discharging circuit is electrically connected to the output terminal of the level conversion module (in this embodiment, the second terminal of the isolation capacitor). The capacitor charging / discharging circuit includes a reference current source, a charging switch, and a discharging switch. The gates of both the charging and discharging switches are electrically connected to the second terminal of the isolation capacitor module. The source of the charging switch is indirectly connected to the high-voltage power supply VB (typically VS+VCC) via the reference current source. The source of the discharging switch is electrically connected to the source voltage VS of the high-side power device. One end of the charging / discharging capacitor is electrically connected to the source voltage VS of the high-side power device. The drains of both the charging and discharging switches are connected to the other end of the charging / discharging capacitor and the input terminal of the shaping circuit. The shaping circuit is used to shape the high-voltage ramp signal generated by the capacitor charging / discharging circuit to make the pulse signal waveform more stable and output a high-voltage control signal with a low level of VS and a high level of VB. The output stage drive module then enhances the driving capability of the high-voltage control signal and outputs a gate pre-drive signal HO for the high-side power device, used to control the high-side power device.

[0043] In this embodiment, the shaping circuit can be implemented using a Schmitt trigger.

[0044] This embodiment utilizes a high-voltage isolation combined with level conversion to achieve a level shifting effect, eliminating the need for a high-voltage LDMOS device. The logic control signal HIN from the low-voltage region of the high-side channel is superimposed onto the VS voltage. When HIN is high, the high-side power device NM1 is turned on; when HIN is low, the high-side power device NM2 is turned off. Specifically, the high-level portion of the high-side logic control signal is first converted into a high-frequency pulse. Utilizing the characteristic of a capacitor blocking DC and passing AC, the high-frequency pulse is transmitted to the other side of the isolation capacitor. By superimposing the source voltage of the high-side power device on the other side of the isolation capacitor, the voltage on the right side of the diagram is raised, achieving voltage conversion. The AC pulse signal after the voltage increase controls the on-time and off-time of the switch, charging and discharging the capacitor to generate a sawtooth wave. The sawtooth wave is then shaped to recover the high level (VS+VCC). Since the low voltage on the right side of the dashed line is the source voltage VS of the high-side power device, the high-voltage power supply VB is generally VS+VCC, and the VCC level is typically 3.3V, 5V, or 15V, etc. Each device does not need to withstand excessively high voltage, so the requirements for the devices are not high. There is no need to use LDMOS, the layout area is small, the process structure is simple, and the process requirements are not high.

[0045] Example 2:

[0046] The difference between Embodiment 2 and Embodiment 1 is that the level conversion module further includes a first comparator, such as... Figure 4 As shown, the positive power supply of the first comparator is provided by the high voltage VB, and the negative power supply is provided by the source voltage VS of the high-side power device. The isolation transmission module is electrically connected to the input terminal of the first comparator, the other input terminal of the first comparator module is electrically connected to the reference voltage, and the output terminal of the first comparator is electrically connected to the pulse detection module. The reference voltage can be obtained by voltage division of the high voltage VB through resistors, or other forms of bias voltage can be used. Furthermore, in Embodiment 2, a diode is connected in parallel with resistor R1 for better performance.

[0047] Example 2 considers that actual products are affected by various parasitic factors. The amplitude of high-frequency pulse signals attenuates after passing through the isolation capacitor. When the attenuation is significant, the signal amplitude is small, making it undetectable and affecting subsequent control of the power transistor, leading to malfunction. This example addresses this problem by adding a comparator to the level conversion module. Using the first comparator, small high-frequency pulse signals can be amplified to obtain a full-amplitude signal (VB~VS). This allows for better control of the on-time and off-time of the charge / discharge switch in the pulse detection module, resulting in more accurate pulse detection results, ensuring normal control of the power transistor, and improving system reliability.

[0048] Example 3:

[0049] The difference between Example 3 and Example 2 is that Example 3 converts one high-side logic control signal into two high-frequency pulse signals with opposite pulse portions, and then transmits the two inverted high-frequency pulse signals to the high-voltage domain on the right. For example... Figure 5 As shown, in Embodiment 3, the isolation transmission module includes two isolation capacitors: a first isolation capacitor C1 and a second isolation capacitor C2. The high-frequency pulse module converts one high-side logic control signal into two high-frequency pulse signals. These two high-frequency pulse signals are electrically connected to the first terminals of the two isolation capacitors, respectively. The other terminals of the two isolation capacitors are electrically connected to the first and second input terminals of the first comparator, respectively. Under the action of the level conversion module, the two high-frequency pulse signals are converted into low-level VS and high-level VB high-frequency pulse signals. After detection by the pulse detection module, a high-voltage control signal is output.

[0050] The specific implementation is as follows:

[0051] The high-frequency clock generator outputs two opposite high-frequency clock signals, namely a first high-frequency clock signal and a second high-frequency clock signal. These signals are electrically connected to the first input terminals of two AND gates, respectively. Specifically, the first high-frequency clock signal is electrically connected to the first input terminal of the first AND gate, and the second high-frequency clock signal is electrically connected to the first input terminal of the second AND gate. The second input terminal of the first AND gate is electrically connected to the high-side output terminal of the dead-time protection circuit in the input stage driver module, and the second input terminal of the second AND gate is also electrically connected to the high-side output terminal of the dead-time protection circuit in the input stage driver module. The output terminal of the first AND gate is electrically connected to the first terminal of the first isolation capacitor, and the output terminal of the second AND gate is electrically connected to the first terminal of the second isolation capacitor. The second terminals of the two isolation capacitors are connected to a level conversion module, which includes a first comparator, a first clamping element, and a second clamping element. One end of each clamping element is connected to the source voltage of the high-side power device, and the other end is connected to the second terminals of the two isolation capacitors and the two input terminals of the first comparator. The first comparator outputs a level-converted pulse signal for subsequent detection.

[0052] In this embodiment, the high-frequency pulse signal electrically connected to the first input terminal and the second input terminal (which can be interchanged) of the first comparator is a differential signal, which can resist noise interference and thus more sensitively compare signals with smaller amplitudes. Furthermore, by designing and controlling the number and time of filtering invalid pulses (pulse glitches, etc.), the reliability can be improved and the effect is better, making it a preferred embodiment.

[0053] like Figure 6 This is a timing diagram of each important circuit node in the high-voltage floating gate pre-drive circuit of this embodiment.

[0054] Specifically, a circuit node refers to a connection point in a circuit.

[0055] Node a represents the high-side logic control signal obtained after the input signal HIN is shaped by the input stage driver module, and has an initial low level GND and an initial high level VCC;

[0056] Node b and node c are two opposite high-frequency clock signals generated by the high-frequency clock generator.

[0057] Node d is the first high-frequency pulse signal generated by the first logic AND gate between nodes a and b;

[0058] Node e is the second high-frequency pulse signal generated by the second logic AND gate between nodes a and c;

[0059] Node dx is the first high-voltage domain high-frequency pulse signal generated after node d is transmitted through the first isolation capacitor;

[0060] Node ex is the second high-voltage domain high-frequency pulse signal generated after node e is transmitted through the second isolation capacitor;

[0061] Node f is the high-voltage domain full-amplitude high-frequency pulse signal output by comparing nodes dx and ex through the first comparator, which can be used to control the on-time and off-time of capacitor charging and discharging in the pulse detection module.

[0062] Node g is the voltage change signal on the charging and discharging capacitor in the pulse detection module;

[0063] Node h is the high-voltage control signal after the voltage change signal on the charging and discharging capacitor is shaped by the shaping circuit. h is a signal with a high level of VB and a low level of VS.

[0064] Therefore, it can be seen that the shift from a to h realizes the level shift of the high-side logic control signal from the low-voltage domain to the high-voltage domain.

[0065] Example 4:

[0066] The difference between Example 4 and Example 3 lies in the different structures of the level conversion module and the pulse detection module. In Example 3, the level conversion module converts two high-frequency pulses into one high-frequency pulse. In this example, the two high-frequency pulses remain two high-frequency pulse signals after level conversion. Therefore, the level conversion module in this example includes two comparators: a first comparator and a second comparator. The positive power supply for the first and second comparators is provided by the high voltage of the power supply, and the negative power supply is provided by the source voltage of the high-side power device. The isolation transmission module includes a first isolation capacitor and a second isolation capacitor. The first and second input terminals of the first comparator are respectively connected to the second terminals of the first and second isolation capacitors. The first and second input terminals of the second comparator are respectively connected to the second and second terminals of the second and first isolation capacitors. Thus, the pulse portions of the two full-amplitude high-frequency pulse signals output by the two comparators are opposite.

[0067] The structure of the pulse detection module also differs. In embodiment three, a sawtooth wave is generated by charging and discharging a capacitor, and a high-voltage control signal is output after passing through a shaping circuit. In this embodiment, a logic XOR gate is used to convert two high-frequency pulse signals into a high-voltage control signal. For example... Figure 7 As shown, the first input terminal of the logic XOR gate is electrically connected to the output terminal of the first comparator, and the second input terminal of the logic XOR gate is electrically connected to the output terminal of the first comparator. It is used to perform a logic XOR operation between the full-amplitude high-frequency pulse signal output by the first comparator and the full-amplitude high-frequency pulse signal output by the second comparator, maintain the low level of the high-frequency pulse signal as a low level VS, identify the pulse of the high-frequency pulse signal as a high level VB, and then pass the high-frequency pulse signal through the output stage driving module to obtain the high-side logic control pre-drive signal HO of the high-voltage domain.

[0068] Compared with Embodiment 3, this embodiment reduces the use of a reference current source, thereby reducing chip power consumption.

[0069] like Figure 8 This is a timing diagram of the important circuit nodes in the high-voltage floating gate pre-drive circuit of this embodiment. Specifically, a circuit node refers to a connection point in the circuit.

[0070] Node a represents the high-side logic control signal obtained after the input signal HIN is shaped by the input stage driver module, and has an initial low level GND and an initial high level VCC;

[0071] Node b and node c are two opposite high-frequency clock signals generated by the high-frequency clock generator, respectively.

[0072] Node d is the first high-frequency pulse signal generated by the first logic AND gate between nodes a and b;

[0073] Node e is the second high-frequency pulse signal generated by the second logic AND gate between nodes a and c;

[0074] Node dx is the first high-voltage domain high-frequency pulse signal generated after node d is transmitted through the first isolation capacitor;

[0075] Node ex is the second high-voltage domain high-frequency pulse signal generated after node e is transmitted through the second isolation capacitor;

[0076] Node i represents the high-voltage domain full-amplitude high-frequency pulse signal output by nodes dx and ex through the first comparator;

[0077] Node j represents the high-voltage domain full-amplitude high-frequency pulse signal output by the comparison of nodes dx and ex through the second comparator;

[0078] Node k is the high-side logic control signal of the high-voltage domain obtained by logically XORing nodes i and j;

[0079] Therefore, it can be seen that the shift from a to k realizes the level shift of the high-side logic control signal from the low-voltage domain to the high-voltage domain.

[0080] Example 5:

[0081] The difference between Example 5 and Example 4 lies in the structure of the pulse detection module. In this example, the pulse detection module includes two NOT gates and one NAND gate. For example... Figure 9 As shown, the input of the first NOT gate is electrically connected to the output of the first comparator, the output of the first NOT gate is electrically connected to the first input of the AND gate, the input of the second NOT gate is electrically connected to the output of the second comparator, the output of the second NOT gate is electrically connected to the second input of the AND gate, and the output of the AND gate is electrically connected to the output stage driver module.

[0082] The pulse detection module is equivalent to an XOR gate, which is used to pass the full-amplitude high-frequency pulse signal output by the first comparator through a first NOT gate to obtain the opposite signal, and pass the full-amplitude high-frequency pulse signal output by the second comparator through a second NOT gate to obtain the opposite signal. The two inverted full-amplitude high-frequency pulse signals are then passed through a AND gate circuit to keep the non-pulse part of the high-frequency pulse signal at a low level VS and identify the pulse part of the high-frequency pulse signal as a high level VB, thereby obtaining the high-voltage domain high-side logic control pre-drive signal HO.

[0083] Compared with Example 4, this embodiment reduces the delay time of the logic gate circuit, resulting in better performance.

[0084] like Figure 10This is a timing diagram of the important circuit nodes in the high-voltage floating gate pre-drive circuit of this embodiment. Specifically, a circuit node refers to a connection point in the circuit.

[0085] Node a represents the high-side logic control signal obtained after the input signal HIN is shaped by the input stage driver module, and has an initial low level GND and an initial high level VCC;

[0086] Node b and node c are two opposite high-frequency clock signals generated by the high-frequency clock generator.

[0087] Node d is the first high-frequency pulse signal generated by the first logic AND gate between nodes a and b;

[0088] Node e is the second high-frequency pulse signal generated by the second logic AND gate between nodes a and c;

[0089] Node dx is the first high-voltage domain high-frequency pulse signal generated after node d is transmitted through the first isolation capacitor;

[0090] Node ex is the second high-voltage domain high-frequency pulse signal generated after node e is transmitted through the second isolation capacitor;

[0091] Node i represents the high-voltage domain full-amplitude high-frequency pulse signal output by nodes dx and ex through the first comparator;

[0092] Node j represents the high-voltage domain full-amplitude high-frequency pulse signal output by the comparison of nodes dx and ex through the second comparator;

[0093] Node m represents the inverse signal of node i;

[0094] Node n represents the inverse signal of node j;

[0095] Node p is the high-side logic control signal of the high-voltage domain obtained by ANDing and NOTing nodes m and n;

[0096] Therefore, it can be seen that the shift from a to p realizes the level shift of the high-side logic control signal from the low-voltage domain to the high-voltage domain.

[0097] In the several embodiments provided in this application, it should be understood that the disclosed modules and methods can be implemented in other ways. For example, the embodiments described above are merely illustrative, and the division of modules is only a logical functional division; in actual implementation, there may be other division methods. For example, multiple modules can be combined or separately integrated into another system, or some features can be ignored or not executed. In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. Some or all of the modules can be selected to achieve the purpose of the solution in this application according to actual needs. The integrated modules described above can be implemented in hardware or software. Furthermore, the term "electrical connection" should be interpreted broadly. Unless otherwise specified, it should be understood to include both direct electrical connection between two components (i.e., no intermediate element between them) and indirect electrical connection (i.e., electrical conduction is achieved through one or more intermediate elements).

[0098] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A high-voltage floating gate pre-drive circuit, characterized in that, It includes a high-side channel, which comprises a high-frequency pulse module, an isolation transmission module, a level conversion module, and a pulse detection module, but does not contain a high-voltage LDMOS transistor; The high-frequency pulse module receives a high-side logic control signal at its input terminal, which is used to convert the high-level part of the high-side logic control signal into a high-frequency pulse. The output terminal of the high-frequency pulse module is electrically connected to the isolation transmission module. The first end of the isolation transmission module is electrically connected to the high-frequency pulse module, and the second end is electrically connected to the level conversion module. The level conversion module is used to increase the level of the high-frequency pulse. The level conversion module includes a voltage clamping element, one end of which is electrically connected to the source voltage of the high-side power device, and the other end is electrically connected to the second terminal of the isolation transmission module. The input terminal of the pulse detection module is electrically connected to the level conversion module, and the output terminal outputs a high-voltage control signal.

2. The high-voltage floating grid pre-drive circuit according to claim 1, characterized in that, The level conversion module also includes a first comparator. The positive power supply of the first comparator is provided by the high voltage of the power supply, and the negative power supply of the first comparator is provided by the source voltage of the high-side power device. The isolation transmission module is electrically connected to the input terminal of the first comparator, and the output terminal of the first comparator is connected to the pulse detection module.

3. The high-voltage floating grid pre-drive circuit according to claim 2, characterized in that, The isolation transmission module includes a first isolation capacitor and a second isolation capacitor. The high-frequency pulse module is used to convert one high-side logic control signal into two high-frequency pulse signals. The pulse portions of the two high-frequency pulse signals are opposite. The two high-frequency pulse signals are electrically connected to the first terminals of the first isolation capacitor and the second isolation capacitor, respectively. The second terminals of the first isolation capacitor and the second isolation capacitor are electrically connected to the first input terminal and the second input terminal of the first comparator, respectively.

4. The high-voltage floating grid pre-drive circuit according to any one of claims 1 to 3, characterized in that, The pulse detection module includes, in sequence, a capacitor charging and discharging circuit, a charging and discharging capacitor, and a shaping circuit. The input terminal of the capacitor charging and discharging circuit is electrically connected to the output terminal of the level conversion module. The capacitor charging and discharging circuit includes a reference current source, a charging switch, and a discharging switch. The reference current source is electrically connected to the high voltage of the power supply. The charging switch and the discharging switch are both electrically connected to the charging and discharging capacitor. The input terminal of the shaping circuit is connected to the charging and discharging capacitor, and the output terminal of the shaping circuit outputs a high voltage control signal.

5. The high-voltage floating grid pre-drive circuit according to claim 1, characterized in that, The level conversion module further includes a first comparator and a second comparator. The positive power supply of the first comparator and the second comparator is provided by the high voltage of the power supply, and the negative power supply of the first comparator and the second comparator is provided by the source voltage of the high-side power device. The isolation transmission module includes a first isolation capacitor and a second isolation capacitor. The first input terminal and the second input terminal of the first comparator are respectively connected to the second terminals of the first isolation capacitor and the second isolation capacitor. The first input terminal and the second input terminal of the second comparator are respectively connected to the second isolation capacitor and the second terminal of the first isolation capacitor.

6. The high-voltage floating grid pre-drive circuit according to claim 5, characterized in that, The pulse detection module includes a logic circuit. The two input terminals of the logic circuit are respectively connected to the output terminals of the first comparator and the second comparator. The output terminal of the logic circuit outputs a high-voltage control signal. The logic circuit uses an XOR gate or a combination of logic gates with XOR function equivalent.

7. The high-voltage floating grid pre-drive circuit according to any one of claims 1-3, 5, and 6, characterized in that, The high-frequency pulse module includes a high-frequency clock generator and a logic AND gate. The first and second input terminals of the logic AND gate are respectively connected to the output terminal of the high-frequency clock generator and the high-side logic control signal. The high-frequency clock generator outputs one high-frequency clock or two opposite high-frequency clocks.

8. The high-voltage floating grid pre-drive circuit according to any one of claims 1-3, 5, and 6, characterized in that, It also includes an input-level driver module and an output-level driver module. The input terminal of the input-level driver module receives logic control signals, and the output terminal is electrically connected to a high-frequency pulse module. The input terminal of the output-level driver module is electrically connected to a pulse detection module, and the output terminal outputs gate control signals for power devices. The isolation transmission module uses silicon dioxide isolated high-voltage capacitors.

9. A high-voltage floating gate pre-driven chip, characterized in that, It includes the high-voltage floating grid pre-drive circuit as described in any one of claims 1 to 8.

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